Efficient architecture for high-performance DSP-based SERDES

Abstract

The present application relates to an efficient architecture for a high performance DSP based SERDES. A digital signal processing DSP device includes: a first filter for equalizing channel dispersion associated with signal transmission through a medium; a second filter for eliminating channel reflections; and a third filter for at least reducing noise. The DSP device is a receiver DSP of a SERDES.

Description

Technical Field

[0001] The present description relates generally to high speed serial communication links, and in particular to an efficient architecture for a high performance digital signal processing (DSP) based serializer deserializer (SERDES). Background Art

[0002] Serializer deserializers (SERDES) based on high-speed digital signal processing (DSP) require complex algorithms to operate on densely populated and low-cost channels while maintaining high efficiency to reduce power usage and chip area. This is especially true in highly integrated large-scale application-specific integrated circuit (ASIC) applications. Conventional DSP receivers may have a longer feedforward equalizer (FFE) and a shorter 1-2 tap decision feedback equalizer (DFE). The actual channel has reflections that need to be balanced under long delays, which in turn drives the increase in FFE length. The input to the FFE usually has attenuated high-frequency content, requiring more active taps to balance the reflections. These factors will increase the power and area of ​​the DSP. The complexity of these circuits leads to longer delays for obtaining timing-related information (such as received symbols and expected values) for comparison, thereby causing margin loss in a highly integrated environment where jitter tolerance is required. Sometimes, a separate shorter FFE is dedicated to the timing recovery path to achieve reasonable but suboptimal signal quality, which has a lower delay. However, this approach may increase redundancy and complexity. Low bit error rate applications desire a low power, low area architecture with reflection cancellation and fast timing recovery while still retaining FFE-DFE-like noise shaping. Summary of the invention

[0003] In one aspect, the present application provides a DSP device comprising: a first filter configured to equalize channel dispersion associated with signal transmission; a second filter configured to eliminate channel reflections; and a third filter configured to at least filter noise, wherein the DSP device comprises a receiver DSP of a SERDES.

[0004] On the other hand, the present application provides a system comprising: an analog-to-digital converter (ADC) configured to convert an analog signal from an analog front end (AFE) circuit; a first equalizer configured to equalize channel dispersion of a transmission medium coupled to the AFE circuit; a reflection canceller configured to cancel channel reflections associated with the transmission medium; and a second equalizer configured to remove inter-symbol interference (ISI), wherein the AFE circuit is configured to receive an analog signal transmitted by a SERDES transmitter through the transmission medium.

[0005] On the other hand, the present application provides a SERDES receiver comprising: a first FFE configured to equalize channel dispersion associated with a transmission medium; a filter configured to reduce the effects of channel reflections associated with the transmission medium; and a DFE configured to remove inter-symbol interference added by the RX-FFE and generate a DSP output signal with reduced channel dispersion, reflection effects and noise, wherein the transmission medium comprises a SERDES transmission medium. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Certain features of the present technology are set forth in the appended claims. However, for purposes of explanation, several embodiments of the present technology are set forth in the drawings.

[0007] Figure 1 is a block diagram illustrating an example of a high performance digital signal processing (DSP) serializer-deserializer (SERDES) link within which the present techniques are implemented.

[0008] Figure 2 is a block diagram illustrating an example of a high performance DSP system in accordance with various aspects of the present technique.

[0009] Figure 3 is a block diagram illustrating an example of a high performance DSP system in accordance with various aspects of the present technique.

[0010] Figure 4 is a block diagram illustrating an example of a high performance DSP system in accordance with various aspects of the present technique.

[0011] Figure 5 An electronic system in which some aspects of the present technology are implemented. DETAILED DESCRIPTION

[0012] The detailed description set forth below is intended as a description of various configurations of the present technology and is not intended to represent the only configuration with which the present technology can be practiced. The accompanying drawings are incorporated herein and form part of the detailed description, which includes specific details for providing a thorough understanding of the present technology. However, the present technology is not limited to the specific details set forth herein and may be implemented without one or more of the specific details. In some examples, structures and components are shown in block diagram form in order to avoid confusing the concepts of the present technology.

[0013] The present technology relates to an efficient architecture for a serializer deserializer (SERDES) based on high-performance digital signal processing (DSP). The disclosed technology provides a low-power, low-area architecture with reflection elimination and fast timing recovery for low error rate (BER) applications while retaining feed-forward equalizer (FFE) and decision feedback equalizer (DFE) noise shaping. Instead of a single-stage FFE, the disclosed solution implements the FFE as a cascade combination of three filters and an optional interpolator. In some implementations, the three filters include a receive (RX)-FFE filter, a reflection canceller (RC)-finite impulse response (FIR) filter, and a noise shaping programmable response (PR) FIR filter.

[0014] The short RX-FFE filter implemented with low latency targets a unit tap equalization response. The equalization response has a smaller cross-channel dynamic range and allows for a more aggressive reduction in bit width for downstream stages. The short RX-FFE filter output is provided for timing recovery and can be easily divided into expected values ​​of symbols and provides low latency timing errors for clock and delay recovery (CDR) without the implementation delay of long FFE or DFE. The output is also quantized and used as the input of a floating tap structure to eliminate reflections. This signal has been equalized by the RX FFE, resulting in fewer active taps to eliminate reflections. The quantized input has a narrow bit width that leads to a low-cost delay line and a simple multiplier, which brings low total power and chip area. In order to obtain the benefits of noise shaping, the RX FFE output is passed through a noise shaping filter and the DFE repairs inter-symbol interference (ISI). In order to obtain even faster timing recovery, an interpolator can be inserted at the FFE output. The interpolator operates on a well-equalized input, resulting in a cost saving in the bit resolution of the associated multiplier while still retaining all other capabilities.

[0015] Figure 1 1 is a block diagram illustrating an example of a SERDES link 100 of a high performance DSP within which the present technology is implemented. SERDES link 100 includes a transmitter device 110, a transmission medium 115, and a receiver device 120. Transmitter device 110 includes a transmit (TX) data source 112 and a transmitter circuit 114. The TX data source provides data to be transmitted to receiver device 120, such as electrical or optical data. Transmitter circuit 114 includes digital and analog circuitry suitable for processing data, such as amplification and noise cancellation to prepare the data for transmission over transmission medium 115. In some implementations, transmitter circuit 114 may also include electro-optical circuitry. Transmission medium 115 may be an optical transmission medium consisting of optical fibers and optical fiber components, or an electrical transmission medium consisting of twisted pair or coaxial cables and associated circuitry.

[0016] The receiver device 120 includes an analog front end (AFE) circuit 122, an analog / digital converter (ADC) circuit 124, a receiver (RX) DSP block 126, and an RX data processing block 128. The AFE circuit 122 may include a low noise amplifier, a filter, and an adjustable gain amplifier and is responsible for amplification and noise reduction of analog signals received from the transmission medium 115. The ADC circuit 124 converts the analog output signal of the AFE circuit 122 into a digital signal that can be processed by the RX DSP block 126. The last stage is the RX data processing block 128, which further processes the output data from the RX DSP block 126 to recover the original data for presentation on an output device, such as display on a display device. In some implementations, the SERDES link 100 may include an optional forward error correction (FEC) block (not shown for simplicity) that may be implemented in the transmitter device 110 (e.g., in the TX data source 112) or in the receiver device 120 (e.g., the RX data processing block 128). The SERDES link 100 shows TX and RX in only one direction. A similar link may be used in the reverse direction.RX DSP block 126 is the foundation of receiver device 120 for which the present technology provides an efficient implementation architecture, as discussed herein.

[0017] Figure 2 2 is a block diagram illustrating an example of a high performance DSP system 200 according to various aspects of the present technique. The high performance DSP system 200 includes a DSP device 220, an ADC 210, and an ADC clock controller 212. The ADC 210 and Figure 1 The ADC circuit 124 is similar to and can be derived from the AFE circuit (e.g., Figure 1 The ADC 210 receives analog data 202 and converts it into digital data for processing by the DSP system 200. The ADC clock controller 212 provides a clock signal for the ADC 210 and controls the clock signal.

[0018] DSP device 220 includes ADC calibration circuit 222 and FFE circuit 224, interpolator 226, phase detector (PD) 228, CDR circuit 230 and RX FFE circuit 232, delay matching circuit 234, reflection canceller 236, summing circuit 238 and DFE circuit 240. In some implementations, some components of DSP device 220 may be implemented in software and / or firmware. ADC calibration circuit 222 may be a gain skew calibration circuit and is responsible for the calibration of timing offset (skew) and gain error of ADC 210. FFE circuit 224 is used to remove the error associated with the transmission medium (e.g., Figure 1115) associated with the channel dispersion equalizer and may include offset calibration. FFE circuit 224 may be implemented as a symbol-spaced FIR filter to reduce distortion due to, for example, channel loss impairment. In some aspects, FFE circuit 224 may be implemented using a multi-tap filter that creates several delayed versions of the input signal that are added back to the signal with appropriate weights. In some implementations, FFE circuit 224 may include offset calibration to calibrate the timing or voltage offset of the digital signal received from ADC calibration circuit 222. The benefits of the proposed architecture (e.g., where CDR circuit 230 derives its input from FFE226) are: unlike previous solutions that may have a dedicated stage between ADC and (CDR+FFE), timing or voltage offsets may be corrected in both FFE and CDR paths. Interpolator 226 is an important part of DSP device 220 and allows the receiver to use phase adjustment signal 231 to adjust the phase of its sampling clock with very fine increments. Interpolator 226 helps obtain a faster timing recovery loop. Interpolator 226 operates on well-balanced inputs, resulting in cost savings in bit resolution of the associated multiplier while still retaining all other capabilities. In some aspects, interpolator 226 may be a current-controlled phase interpolator or a voltage-controlled phase interpolator. Current-controlled interpolators may be less linear and more difficult to control because they require analog control inputs. Current-controlled interpolators may be larger and consume more power, but use digital control signals and their outputs can be more linear. PD 228 can detect the phase angle of the interpolator output signal and provide it to CDR circuit 230. CDR circuit 230 may include a loop filter and control logic and generate an interpolator phase adjustment signal 231 and a control signal 233 used by ADC clock controller 212.

[0019] The output of interpolator 226 includes the Figure 1 110) plus the original signal transmitted due to the transmission medium (e.g., Figure 1 115) and is ready to be removed by the next stage including RX-FFE 232 and reflection canceller 236. RX-FFE 232 is a short equalizer implemented with low latency and can target a partial response for noise shaping. RX-FFE 232 includes a noise shaping filter that can change the spectral shape of the signal and can be used to generate a noise-shaped signal by comparing it to 1+αD+βD. 2250 . The reflection canceller 236 is characterized by a similar polynomial transfer function, where D is the delay or time delay variable and α and β are the parameters of the transfer function. The value of α is typically between 0 and 1 to implement a low pass filter to reduce noise. The reflection canceller 236 consists of a quantizer (Q) followed by a FIR filter (also known as a Q-FIR filter) with a floating tap structure. The quantized input of the FIR has a narrow bit width resulting in a low cost delay line and a simple multiplier, which results in low overall power usage and chip area. In other words, the use of a Q filter in front of the FIR filter allows the use of an FIR with a lower number of bits, where the possible outputs for different values ​​of the Q bit (2, 3, and 4) are given in Table 250. The reflection canceller 236 can effectively eliminate the effects of channel impairments, such as when there is a large amount of noise along the transmission medium (e.g., Figure 1 115) when transmitting a signal. The output signal from RX-FFE 232 is delayed by delay matching circuit 234 and combined with the signal output of reflection eliminator 236 by adding circuit 238 for timing recovery. Delay matching circuit 234 takes into account the difference between the processing delays of Q / FIR 236 and RX-FFE 232 paths so that the output of adding circuit 238 is correct. The output signal from adding circuit 238 is passed to DFE circuit 240, which is a noise shaping filter for suppressing quantization noise. DFE circuit 240 uses an estimate of the transmitted symbol derived from the signal at its input to subtract the term αD+βD introduced by RX-FFE 2 In this way, the noise shaping benefits of RX-FFE can be achieved without the penalty of the inter-symbol interference it introduces. The DSP output signal 242 is a signal in which the effects of channel dispersion and reflections are removed. The DSP output signal is sent to the RX data processing circuit (e.g., Figure 1 128) to recover the Figure 1 110) transmits the original data.

[0020] Figure 33 is a block diagram illustrating an example of a high performance DSP device 300 according to various aspects of the present technology. The DSP device 300 includes an ADC calibration circuit 310, an FFE circuit 320, a PD 322, a delay matching circuit 330, a reflection canceller 334, an addition circuit 332, an RX-FFE 336, an interpolator 338, and a DFE circuit 340. In some implementations, some components of the DSP device 300 may be implemented in software and / or firmware. The ADC calibration circuit 310 may be a gain skew calibration circuit and is responsible for calibrating the timing offset and gain error of the ADC 210. The FFE circuit 320 is a passive equalizer for removing channel dispersion and may include offset calibration. The FFE circuit 320 may be implemented as a symbol-spaced FIR filter to reduce distortion due to, for example, channel loss impairments. In some aspects, the FFE circuit 320 may be implemented using a multi-tap filter that creates several delayed versions of the input signal that are added back to the signal with appropriate weights. In some implementations, the FFE circuit 320 may include an offset calibration to calibrate the timing offset of the digital signal received from the ADC calibration circuit 310. The PD 322 may detect a phase angle signal 324 associated with the output signal from the FFE circuit 320. The phase angle signal 324 may be provided to a CDR circuit (e.g., Figure 2 230).

[0021] The output of FFE 320 includes the Figure 1 110) plus the original signal transmitted due to the transmission medium (e.g., Figure 1 The reflection canceller 334 is composed of a Q filter followed by an FIR filter with a floating tap structure and is connected to Figure 2 The quantized input to the FIR filter has a narrow bit width resulting in a low cost delay line and simple multipliers, which results in low overall power and chip area. In other words, the use of a Q filter in front of the FIR filter (also referred to as a Q-FIR filter) allows the use of an FIR with a lower number of bits, where the possible outputs for different values ​​of the Q bit (2, 3, and 4) are given in Table 350. Delay matching 330 takes into account the processing delay of the reflection canceller 334 so that the output of the adding circuit 332 is correct. The output of the delay matching circuit 330 is combined with the output of the reflection canceller 334 by the adding circuit 332. The output signal from the adding circuit 332 is passed to the Figure 2 RX-FFE 232 is similar to RX-FFE 336, as discussed above. For example, RX-FFE 336 similarly includes a noise shaping filter that can change the spectral shape of the signal and can be characterized by the following polynomial transfer function: 1+αD+βD 2, where D is the delay or time delay variable and α and β are the parameters of the transfer function. The value of α is typically between 0 and 1 to implement a low pass filter to reduce noise. The output of RX-FFE 336 is passed to interpolator 338, which can help achieve faster timing recovery. Interpolator 338 can use, for example, a CDR circuit (e.g., Figure 2 The output of the interpolator 338 is sent to the DFE circuit 340, which is a noise shaping filter for suppressing quantization noise and has the same Figure 2 The output of the DSP device 300 is a signal in which the effects of channel dispersion and reflection are eliminated and sent to the RX data processing circuit (e.g., Figure 1 128) to recover the Figure 1 110) transmits the original data.

[0022] Figure 4 4 is a block diagram illustrating an example of a high performance DSP according to various aspects of the present technology. The DSP device 400 includes an ADC calibration circuit 410 and an FFE circuit 420, a PD 422, a number (e.g., three) of reflection canceller stages 430 (430-1, 430-2, and 430-3), an RX-FFE circuit 436, an interpolator 438, and a DFE circuit 440. In some implementations, some components of the DSP device 400 may be implemented in software and / or firmware. The ADC calibration circuit 410 may be a gain skew calibration circuit and is responsible for calibrating the ADC (e.g., Figure 2 210). The FFE circuit 420 is a passive equalizer for removing channel dispersion and may include offset calibration. The FFE circuit 420 may be implemented as a symbol-spaced FIR filter to reduce distortion due to, for example, channel loss impairments. In some aspects, the FFE circuit 420 may be implemented using a multi-tap filter that creates several delayed versions of the input signal that are added back to the signal with appropriate weights. In some implementations, the FFE circuit 420 may include offset calibration to calibrate the timing offset of the digital signal received from the ADC calibration circuit 410. The PD 422 may detect a phase angle signal 424 associated with the output signal from the FFE circuit 420. The phase angle signal 424 may be provided to a CDR circuit (e.g., Figure 2 230).

[0023] The output of FFE circuit 420 includes the output of the transmitter device (e.g., Figure 1 110) plus the original signal transmitted due to the transmission medium (e.g., Figure 1The edge reflection effect caused by the 115 of FIG. 1 must be eliminated. The reflection canceller stage 430 can eliminate the edge reflection effect. Each of the reflection canceller stages 430 is composed of a Q-FIR filter 432, a delay match 433, and an adder circuit 434, as described above with respect to FIG. Figure 2 Described. Delay matching 433 takes into account the delay of Q / FIR filter 432 so that the output of reflection canceller stage 430 is correct. The purpose of using multiple reflection canceller stages 430 is to provide an implementation of an iterative reflection cancellation algorithm. In general, the output of the first Q / FIR filter 432 is a coarser reflection estimate, which is used as the input to the second Q / FIR stage. The reflection estimate from the second Q / FIR is expected to be a better reflection estimate (better performance), and so on. There will be a point after which the estimate will not get better or "converge". Three stages are shown as a balance between the quality of the estimate of the reflection and the complexity of the reflection canceller stage 430. More or fewer stages are also possible. The output signal from the reflection canceller stage 430 is passed to Figure 2 RX-FFE circuit 436 is similar to RX-FFE 232, as discussed above. For example, RX-FFE circuit 436 similarly includes a noise shaping filter that can change the spectral shape of the signal and can be characterized by the following polynomial transfer function: 1+αD+βD 2 , where D is the delay or time delay variable and α and β are the parameters of the transfer function. The value of α is typically between 0 and 1 to implement a low pass filter to reduce noise. The output of the RX-FFE circuit 436 is passed to an interpolator 438 which can help implement faster timing recovery. The interpolator 438 can use, for example, a CDR circuit (e.g., Figure 2 The output of the interpolator 438 is sent to the DFE circuit 440, which is a noise shaping filter for suppressing quantization noise and has the same Figure 2 The output of the DSP device 400 is a signal in which the effects of channel dispersion and reflections are eliminated and the signal is sent to the RX data processing circuit (e.g., Figure 1 128) to recover the Figure 1 110) transmits the original data.

[0024] Figure 5500 is an electronic system in which some aspects of the present technology are implemented. Electronic system 500 may be a network switch for a data center or enterprise network and / or may be a part thereof. Electronic system 500 may include various types of computer-readable media and interfaces for various other types of computer-readable media. Electronic system 500 includes bus 508, one or more processing units 512, system memory 504 (and / or buffers), ROM 510, permanent storage 502, input device interface 514, output device interface 506, and one or more network interfaces 516 or subsets and variations thereof.

[0025] The bus 508 collectively represents all system, peripheral, and chipset buses that communicatively connect the numerous internal devices of the electronic system 500. In one or more embodiments, the bus 508 communicatively connects one or more processing units 512 with the ROM 510, the system memory 504, and the permanent storage device 502. The one or more processing units 512 retrieve instructions to be executed and data to be processed from these various memory units in order to perform the processes of the present disclosure. In different embodiments, the one or more processing units 512 can be a single processor or a multi-core processor. In one or more aspects, the one or more processing units 512 can execute software components of the present technology.

[0026] ROM 510 stores static data and instructions required by one or more processing units 512 and other modules of electronic system 500. On the other hand, permanent storage 502 can be a read and write memory device. Permanent storage 502 can be a non-volatile memory unit that stores instructions and data even when electronic system 500 is turned off. In one or more implementations, a mass storage device such as a magnetic or optical disk and its corresponding magnetic disk drive can be used as permanent storage 502.

[0027] In one or more implementations, a removable storage device, such as a floppy disk, a flash drive and its corresponding disk drive, may be used as the permanent storage device 502. Similar to the permanent storage device 502, the system memory 504 may be a read and write memory device. However, unlike the permanent storage device 502, the system memory 504 may be a volatile read and write memory, such as a random access memory (RAM). The system memory 504 may store any of the instructions and data that may be required by the one or more processing units 512 at runtime. In one or more implementations, the processes of the present disclosure are stored in the system memory 504, the permanent storage device 502, and / or the ROM 510. The one or more processing units 512 retrieve instructions to be executed and data to be processed from these various memory units in order to perform the processes of one or more implementations.

[0028] The bus 508 is also connected to input and output device interfaces 514 and 506. The input device interface 514 enables a user to communicate information and selection commands to the electronic system 500. Input devices that can be used with the input device interface 514 can include, for example, an alphanumeric keyboard and a pointing device (also referred to as a "cursor control device"). The output device interface 506 can enable, for example, the display of images generated by the electronic system 500. Output devices that can be used with the output device interface 506 can include, for example, a printer and a display device, such as a liquid crystal display, a light emitting diode display, an organic light emitting diode display, a flexible display, a flat panel display, a solid-state display, a projector, or any other device for outputting information. One or more implementations can include a device that serves as both an input and output device, such as a touch screen. In these implementations, the feedback provided to the user can be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback; and the input from the user can be received in any form, including sound, voice, or tactile input.

[0029] Finally, if Figure 5 , bus 508 also couples electronic system 500 to one or more networks and / or one or more network nodes through one or more network interfaces 516. In this manner, electronic system 500 may be part of a computer network, such as a local area network, a wide area network, an intranet, or a network of networks, such as the Internet. Any or all components of electronic system 500 may be used in conjunction with the present disclosure.

[0030] Implementations within the scope of the present disclosure may be implemented in part or in whole using a tangible computer-readable storage medium (or multiple tangible computer-readable storage media of one or more types) encoding one or more instructions. The tangible computer-readable storage medium may also be non-transitory in nature.

[0031] Computer-readable storage media may be any storage media that can be read, written, or otherwise accessed by a general or special purpose computing device, including any processing electronics and / or processing circuitry capable of executing instructions. For example, but not limited to, computer-readable media may include any volatile semiconductor memory, such as RAM, DRAM, SRAM, T-RAM, Z-RAM, and TTRAM. Computer-readable media may also include any non-volatile semiconductor memory, such as ROM, PROM, EPROM, EEPROM, NVRAM, flash memory, nvSRAM, FeRAM, FeTRAM, MRAM, PRAM, CBRAM, SONOS, RRAM, NRAM, racetrack memory, FJG, and millipede memory.

[0032] Furthermore, the computer-readable storage medium may include any non-semiconductor memory, such as optical disk storage, magnetic disk storage, magnetic tape, other magnetic storage, or any other medium capable of storing one or more instructions. In one or more implementations, the tangible computer-readable storage medium may be directly coupled to the computing device, while in other implementations, the tangible computer-readable storage medium may be indirectly coupled to the computing device, such as via one or more wired indirect connections, one or more wireless connections, or any combination thereof.

[0033] Instructions may be directly executable or may be used to develop executable instructions. For example, instructions may be implemented as executable or non-executable machine code, or as high-level language instructions that may be compiled to produce executable or non-executable machine code. In addition, instructions may also be implemented as or may include data. Computer executable instructions may also be organized in any format, including routines, subroutines, programs, data structures, objects, modules, applications, applets, and functions. As recognized by those skilled in the art, the details of the number, structure, sequence, and organization of instructions, including but not limited to, may vary significantly without changing the underlying logic, functionality, processing, and output.

[0034] Although the above discussion mainly relates to a microprocessor or multi-core processor that executes software, one or more implementations are performed by one or more integrated circuits, such as ASICs or FPGAs. In one or more implementations, such integrated circuits execute instructions stored on the circuit itself.

[0035] It will be appreciated by those skilled in the art that the various illustrative blocks, modules, elements, components, methods, and algorithms described herein may be implemented as electronic hardware, computer software, or a combination of both. To illustrate this interchangeability of hardware and software, various illustrative blocks, modules, elements, components, methods, and algorithms have been described above generally in terms of their functionality. Whether this functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. A skilled person may implement the described functionality in different ways for each specific application. The various components and blocks may be arranged differently (e.g., arranged in different orders, or divided in different ways), all without departing from the scope of the present technology.

[0036] It should be understood that any particular order or hierarchy of blocks in the disclosed process is an illustration of an example method. Based on design preferences, it should be understood that the specific order or hierarchy of blocks in the process may be rearranged, or not all of the illustrated blocks may be executed. Any of the blocks may be executed simultaneously. In one or more embodiments, multitasking and parallel processing may be advantageous. In addition, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems may generally be integrated together in a single software product or packaged into multiple software products.

[0037] As used in this specification and in any claims of this application, the terms "base station", "receiver", "computer", "server", "processor" and "memory" all refer to electronic or other technical devices. These terms do not include people or groups of people. For the purposes of this specification, the term "display" or "displaying" means displaying on an electronic device.

[0038] As used herein, the phrase "at least one of ..." preceding a series of items (where the terms "and" or "or" are used to separate any of the items) modifies the entire list, rather than each member of the list (i.e., each item). The phrase "at least one of ..." does not require selection of at least one of each listed item; rather, the phrase allows for a meaning that includes at least one of any of the items, and / or at least one of any combination of the items, and / or at least one of each of the items. For example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" each refers to only A, only B, or only C; any combination of A, B, and C; and / or at least one of each of A, B, and C.

[0039] The predicates "configured to," "operable to," and "programmed to" do not imply any particular tangible or intangible modification of the subject matter, but are intended to be used interchangeably. In one or more embodiments, a processor configured to monitor and control an operation or component may also represent a processor programmed to monitor and control an operation or a processor operable to monitor and control an operation. Likewise, a processor configured to execute code may be interpreted as a processor programmed to execute code or operable to execute code.

[0040] For example, "on one hand," "the aspect," "on the other hand," "some aspects," "one or more aspects," "an embodiment," "the embodiment," "another embodiment," "some embodiments," "one or more embodiments," "an example," "the example," "another example," "some examples," "one or more examples," "a configuration," "the configuration," "another configuration," "some configurations," "one or more configurations," "the present technology," "the disclosure," "the present disclosure," and other variations thereof are for convenience and do not imply that the disclosure associated with such phrases is essential to the present technology or that the disclosure applies to all configurations of the present technology. The disclosure associated with such phrases may apply to all configurations, or one or more configurations. The disclosure associated with such phrases may provide one or more examples. For example, a phrase of one hand or some aspects may refer to one or more aspects and vice versa, and this applies similarly to the other aforementioned phrases.

[0041] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" or "example" is not necessarily to be construed as preferred or advantageous over other embodiments. Furthermore, to the extent that the terms "including," "having," and the like are used in the description or claims, such terms are intended to be inclusive in a manner similar to the term "comprising," in that "including" should be construed as being used as a transitional word in the claims.

[0042] All structural and functional equivalents of the elements throughout the various aspects described in this disclosure that are known or later become known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, nothing disclosed herein is intended to be dedicated to the public, regardless of whether the disclosure is explicitly recited in the claims. No claim element is to be interpreted under 35 U.S.C. §112(f) unless the element is explicitly recited using the phrase "means for..." or, in the case of a method claim, the element is recited using the phrase "step for..."

[0043] The previous description is provided to enable any technician in the field to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but should conform to the full scope consistent with the claims of the language, wherein reference to an element in the singular is not intended to mean "one and only one", unless specifically stated, but rather means "one or more". Unless otherwise expressly stated, the term "some" refers to one or more. Male pronouns (e.g., his) include female and neutral genders (e.g., her and its) and vice versa. Titles and subtitles (if any) are used only for convenience and do not limit the present disclosure.

Claims

1. A digital signal processing (DSP) device, comprising: Analog / digital converter ADC; and A receiver DSP for a serializer deserializer SERDES, the receiver DSP comprising: a first filter configured to equalize channel dispersion associated with signal transmission; a second filter configured to eliminate channel reflections; and An ADC calibration circuit is configured to calibrate a gain error and a timing offset of the ADC and provide an input signal for the first filter.

2. The DSP device of claim 1, wherein the first filter comprises a first feed-forward equalizer (FFE) with offset calibration, and wherein the first FFE is implemented in hardware.

3. The DSP device of claim 1, wherein the second filter comprises a quantizer and a finite impulse response (Q-FIR) filter, and wherein the Q-FIR filter is implemented in hardware.

4. The DSP device of claim 1 , wherein the receiver DSP further comprises a receive RX-FFE coupled to a delay matching circuit, wherein the RX-FFE and the delay matching circuit are implemented in parallel with the second filter, wherein the RX-FFE is configured to reduce noise in response to being used with a decision feedback equalizer (DFE), and wherein dispersion added by the RX-FFE is tuned to be removed by the DFE.

5. The DSP device of claim 4, wherein the receiver DSP further comprises a summing circuit configured to combine the output of the delay matching circuit and the second filter and generate a first output signal.

6. The DSP device of claim 5, wherein the DFE is a third filter configured to remove inter-symbol interference added by the RX-FFE.

7. The DSP device of claim 1, wherein the receiver DSP further comprises an interpolator configured to adjust a phase of an equalized input from the first filter using a phase adjustment signal.

8. The DSP device of claim 7, wherein the phase adjustment signal is generated by a clock and data recovery (CDR) circuit coupled to a phase detector (PD), wherein the PD is configured to detect a phase angle of an interpolator output signal.

9. The DSP device of claim 1, wherein the second filter comprises a plurality of reflection cancellation stages, and wherein each reflection cancellation stage of the plurality of reflection cancellation stages comprises a Q-FIR filter, a delay matching circuit, and a summing circuit.

10. The DSP device of claim 9, wherein the second filter is coupled to a receive RX-FFE circuit and an interpolator configured to adjust a phase of a RX-FFE output signal.

11. The DSP device of claim 1, wherein the ADC calibration circuit comprises a gain skew calibration circuit.

12. An electronic system comprising: an analog-to-digital converter ADC configured to convert an analog signal from an analog front end AFE circuit; a first equalizer configured to equalize channel dispersion of a transmission medium coupled to the AFE circuit; a reflection canceller configured to cancel channel reflections associated with the transmission medium; and The receiving RX-FFE is coupled to the delay matching circuit, in: The AFE circuit is configured to receive an analog signal transmitted by a serializer deserializer (SERDES) transmitter through the transmission medium, and the RX-FFE and the delay matching circuit are implemented in parallel with the reflection canceller.

13. The electronic system of claim 12, wherein the first equalizer comprises a first feed-forward equalizer (FFE) with offset calibration, and wherein the reflection canceller comprises a quantizer and a finite impulse response (Q-FIR) filter. 14 . The electronic system of claim 12 , further comprising an ADC calibration circuit configured to calibrate a gain error and a timing offset of the ADC to provide a first input signal to the first equalizer.

15. The electronic system of claim 12, wherein the electronic system further comprises a decision feedback equalizer (DFE) configured to remove inter-symbol interference added by the RX-FFE, and wherein the electronic system further comprises an interpolator configured to adjust a phase angle of an output signal of one of the first equalizer or the RX-FFE coupled to the reflection canceller.

16. The electronic system of claim 12, wherein the reflection canceller comprises one or more reflection cancellation stages, and wherein each of the one or more reflection cancellation stages comprises a Q-FIR filter, a delay matching circuit, and a summing circuit.

17. The electronic system of claim 12, wherein the reflection canceller comprises a quantizer and a finite impulse response filter.

18. A serializer deserializer (SERDES) receiver, comprising: a first feed-forward equalizer (FFE) configured to equalize channel dispersion associated with a transmission medium; a filter configured to reduce the effects of channel reflections associated with the transmission medium; a second FFE coupled to the filter; a decision feedback equalizer DFE configured to remove intersymbol interference added by the second FFE; and An interposer coupled to one of the first FFE or the second FFE, wherein the transmission medium comprises a SERDES transmission medium.

19. The SERDES receiver of claim 18, wherein the filter comprises one or more reflection cancellation stages, and wherein each of the one or more reflection cancellation stages comprises a quantizer and a finite impulse response (Q-FIR) filter, a delay matching circuit, and a summing circuit.

20. The SERDES receiver of claim 18, further comprising a phase detector configured to detect a phase angle signal from an output signal of the first FFE.

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