Encoding method, decoding method and related device

Abstract

An encoding method, a decoding method and related apparatus are disclosed for separately performing an encoding process on each of the second data streams of z lanes without performing operations such as deskewing and reordering, which reduces operational complexity and delay. The encoding method includes the steps of obtaining a first data stream of m lanes through m input lanes, where m is a positive integer, processing the first data stream of m lanes to obtain a second data stream of z lanes, where z is a positive integer, separately performing an encoding process on each of the second data streams of z lanes to obtain a third data stream of z lanes, and performing a multiplexing process on the third data stream of z lanes to obtain a fourth data stream of n lanes, where n is a positive integer.

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims priority to Chinese Patent Application No. CN202111127055.5, entitled "ENCODING METHOD, DECODING METHOD, AND RELATED APPARATUS," filed with the State Intellectual Property Office of the People's Republic of China on September 18, 2021, the entire contents of which are incorporated by reference.

[0002] [Technical field] TECHNICAL FIELD Embodiments of this application relate to the field of communication technologies, and in particular to encoding methods, decoding methods and related devices. [Background technology]

[0003] Currently, 5th generation mobile communication technology (5 Applications such as IEEE 802.11b, artificial intelligence, and virtual reality are driving the continuous and rapid growth of data center traffic. Existing 400GE technologies cannot meet the requirements of the interconnection architecture underlying future data centers. Therefore, next-generation Ethernet technologies with throughput greater than 400 Gbps are needed to meet the bandwidth requirements of future data centers. As Ethernet transmission rates increase, the transmission bit error rate also increases. Forward error correction (FEC) has become an important core technology for eliminating transmission bit errors. Designing an efficient, low-complexity, and low-latency FEC encoding algorithm and implementation architecture has become a major technical challenge for next-generation Ethernet technologies.

[0004] In the related existing Ethernet communication architecture, The reason is , physical coding sublayer (P CS), Physical Medium Connection Sublayer (P MA) and physical media dependent (PThe PCS layer performs 64B / 66B encoding, 256B / 257B transcoding, alignment marker insertion, and Reed-Solomon (R The main data stream operations, such as RS encoding, are completed sequentially for the data streams. Then, the data streams obtained through RS encoding are distributed to physical coding sublayer lanes (PCS lanes), and multiplexing is performed in the multiplexer. (M The data stream obtained through the multiplexing process is then sent to the PMA layer through m output lanes. In the PMA layer, clock and data recovery is performed. (C In the PMD layer, operations such as data optical modulation and electrical-to-optical conversion are completed on the data stream output from the PMA layer, and an optical signal is output to the transmission medium to complete the overall data operation at the transmitting end.

[0005] However, in related existing Ethernet communication architectures, data streams are transmitted to the PMA layer of an optical module through m output lanes in the PCS layer, resulting in delay skew between physical lanes. To ensure data stream alignment, operations such as aligning, deskewing, and reordering multiple physical coding sublayer lanes must be completed, which results in significant complexity and delay costs. Furthermore, existing Ethernet communication architectures are only applicable to scenarios with throughputs of 400 Gbps or less. However, as Ethernet transmission rates increase, existing Ethernet communication architectures cannot meet the system error correction performance requirements required by next-generation Ethernet communication with throughputs greater than 400 Gbps. Summary of the Invention

[0006] Embodiments of this application disclose an encoding method, a decoding method, and related devices for separately performing inner code encoding processing on each of the z lanes of second data streams without performing operations such as deskewing and reordering on the z lanes of second data streams, which reduces operational complexity and delay.

[0007] According to a first aspect, an embodiment of this application provides an encoding method. The encoding method may be applied to an optical module or other encoding device. In the encoding method, m first data streams are obtained through m input lanes, where m is a positive integer. The m first data streams are processed to obtain z second data streams, where z is a positive integer. An encoding process is performed separately on each of the z second data streams to obtain z third data streams. A multiplexing process is performed on the z third data streams to obtain n fourth data streams, where n is a positive integer. It should be noted that each second data stream of a lane may include Y data blocks to be encoded, where the data blocks to be encoded may be understood as information bits to be encoded. For a data block to be encoded in the second data stream of a lane, a mapping relationship between the data block to be encoded and the RS codeword satisfies Y × length of data block to be encoded = X × (N × codeword length of RS codeword) / z, where Y and X are positive integers greater than or equal to 1. It should be noted that the length of each data block to be encoded is k, the parity bit length is p, and the total codeword length is n, where n, k, and p satisfy n=k+p, and n, k, and p are integers greater than 0. For example, if the length k of the data block to be encoded is 170 bits, the total codeword length of the data block to be encoded is 180 bits after 10 parity bits are added. Alternatively, if the length k of the data block to be encoded is 170 bits, the total codeword length of the data block to be encoded is 179 bits after 9 parity bits are added. Alternatively, if the length k of the data block to be encoded is 170 bits, the total codeword length of the data block to be encoded is 181 bits after 11 parity bits are added. Alternatively, if the length k of the data block to be encoded is 120 bits, the total codeword length of the data block to be encoded is 128 bits after 8 parity bits are added.These are merely used as illustrative examples here and are not particularly limiting in this application.

[0008] In the above scheme, in this embodiment of the present application, the inner code encoding process is performed separately for each of the second data streams of the z lanes, and the FEC codeword in each third data stream obtained through encoding includes a boundary identifier, which ensures that the inner code encoding is separated from the data obtained through encoding in the upper PCS layer and from the transmission in the lower PMD layer, thereby reducing delay skew and out-of-order processing delay, and thereby making the inner code encoding and decoding in this application applicable to scenarios that are sensitive to transmission delay.

[0009] In some possible implementations, each of the z lanes of the second data streams includes a data block to be encoded. In the encoding method, the encoding process may be performed on the z lanes of the second data stream in the following manner: performing an inner-code encoding process on the first data block to obtain one or more FEC codewords, where the first data block is at least C / z consecutive data blocks to be encoded in the corresponding second data stream, where C is a positive integer and C is an integer multiple of z. The encoding method may further include inserting a first identifier at a codeword boundary position of any one of the FEC codewords, where the first identifier identifies the codeword boundary of the FEC codeword, and the throughput or baud rate of the FEC codeword obtained through the insertion of the first identifier is an integer multiple of the reference clock. It should be noted that the position of the codeword boundary may be understood as a codeword start and / or a codeword end. This is not limited here. The codeword boundaries of the FEC codewords are identified by a first identifier, so that the boundary location of each FEC codeword can be determined by directly identifying the first identifier in the subsequent decoding process, avoiding cases where inner code decoding is invalid in the case of delay skew and unknown data start positions.

[0010] In some other possible implementations, each of the z lanes of the second data streams includes a data block to be encoded. In the encoding method, the encoding process may alternatively be performed on the z lanes of the second data stream in the following manner: inserting a first identifier into each data block to be encoded in a first data block to obtain a second data block, where the first data blocks are at least C / z consecutive data blocks to be encoded in the corresponding second data stream; and performing the encoding process on the second data block to obtain an FEC codeword, where the throughput or baud rate of the FEC codeword is an integer multiple of the reference clock. In the above manner, the codeword boundaries of the FEC codewords obtained through encoding are identified by the first identifier, so that the boundary positions of each FEC codeword can be determined by directly identifying the first identifier in a subsequent decoding process, thereby avoiding cases where inner code decoding is invalid due to delay skew and unknown data start positions.

[0011] In some other possible implementation manners, the first identifier is a preset identifier sequence. For example, the first identifier may be a sequence consisting of "1" and "0", or a sequence such as "101010" or "1010" may be selected as the first identifier, or the first identifier may be another known sequence. This is not limited here. In the above manners, the first identifier is set to be a preset identifier sequence, thereby enabling requirements in different scenarios to be met.

[0012] In some other possible implementations, the first identifier is obtained based on the value of a first bit in the first data block, where the first bit is any one of at least one bit in the first data block. Alternatively, the first identifier is obtained based on the bit values of at least L second bits in the first data block, where there is an s-bit interval between every two adjacent second bits among the L second bits, where L≧2 and s≧0, and L and s are integers. For example, the first bit may be the 0th bit in the first data block. If the value of the 0th bit is “0”, the first identifier, i.e., “1”, may be obtained by directly performing a negation operation on the value of the 0th bit. Alternatively, if the value of the 0th bit is “1”, the first identifier, i.e., “0”, may be obtained by directly performing a negation operation on the value of the 0th bit. This is not particularly limited here. In practical applications, the first bit may alternatively be the first bit, the second bit, etc. in the first data block. This is not limited here. For example, the codeword length of the first data block is 180 bits. The last bit may be selected for negation. That is, the value of the 179th bit may be selected to directly perform a negation operation to obtain the first identifier. The first identifier is obtained by performing a negation operation on the bits at the start or end of the codeword. This helps the receiving end quickly determine the codeword boundary. Alternatively, when L=4 and s=2, the four second bits selected from the first data block are the 0th bit, the 2nd bit, the 4th bit, and the 6th bit. In this way, the bit values corresponding to the 0th bit, the 2nd bit, the 4th bit, and the 6th bit may be processed through an exclusive OR operation, and the processing result may be used as the first identifier. It should be noted that in some examples, the four selected second bits may alternatively be the 1st bit, the 3rd bit, the 5th bit, the 7th bit, etc. This is not limited here.In practical applications, L may alternatively be 8 and s is 3, L is 6 and s is 4, etc. In this application, the value of L and the value of s are not limited. In the above scheme, the first identifier is determined based on the bits in the first data block, which can also be applicable to different scenarios.

[0013] In some other possible implementations, the first data streams of m lanes may be processed in the following manner to obtain the second data streams of z lanes: performing a demultiplexing process on the first data streams of m lanes based on a second ratio to obtain the second data streams of z lanes, where the second ratio is m to z. For example, if the first ratio is 16:4, the second ratio should be 4:16. Here, 4:16 is used merely as an example for explanation. In actual applications, the second ratio may be other values, which is not limited in this application. In the above manner, the demultiplexing process is directly performed on the first data streams of m lanes to obtain the second data streams of z lanes, providing several possible implementations.

[0014] In some other possible implementations, performing a demultiplexing process on the first data streams of m lanes based on the second ratio to obtain a second data stream of z lanes includes performing a demultiplexing process on the first data streams of m lanes based on the second ratio to obtain a fifth data stream of z lanes, and separately performing Q-stage processing on each of the third data streams of z lanes to obtain a second data stream of z lanes, wherein each stage of processing in the Q-stage processing performs round-robin distribution processing on the data stream obtained in the previous stage to obtain data sub-streams of at least two lanes. and performing a multiplexing process on the second data substream and the sixth data stream to obtain an output data stream obtained through the current-stage processing, wherein the first data substream is at least one of the data substreams of at least two lanes, the second data substream is a data substream of one lane within the data substreams of the at least two lanes and on which no delay processing is performed, Q is a positive integer, and the second data stream is a data stream obtained through the Q-stage processing. The above method provides several possible implementations of obtaining the second data streams of z lanes.

[0015] In some other possible implementations, the bit length of the sixth data stream is at least (N × codeword length of RS codeword) / (z × i) bits, where N is a positive integer and i is the number of data substreams.

[0016] In some other possible implementations, the encoding method further includes the steps of obtaining a seventh data stream of m lanes through m physical lanes, and performing a demultiplexing process on the seventh data stream of m lanes based on a second ratio to obtain an eighth data stream of z lanes, wherein processing the first data stream of m lanes to obtain a second data stream of z lanes includes performing a multiplexing process on the second data stream of z lanes and the eighth data stream of z lanes to obtain z second data streams obtained through the multiplexing process. In the above method, several possible implementations of obtaining the second data streams of z lanes are provided.

[0017] In some other possible implementations, the encoding method further includes identifying an alignment marker in the second data stream of each lane, where the alignment marker identifies a symbol boundary in the corresponding second data stream, and determining a symbol boundary in the corresponding second data stream based on the alignment marker. For example, a 120-bit known sequence AM alignment block is added to the first data stream of each lane, and a 48-bit common alignment marker is present within the 120-bit known sequence AM alignment block. In this case, lock and alignment may be achieved provided that the 48-bit common alignment marker is identified upon operation at the symbol boundary of the RS codeword.

[0018] In some other possible implementations, the first data streams of m lanes are obtained by performing a multiplexing process at a first ratio on the data streams of z lanes obtained through Reed-Solomon RS encoding. It should be noted that the first ratio may be understood as a ratio of z to m. For example, the first ratio may be 16:4, 32:4, 32:16, or 16:8. This is not limited here. Furthermore, the first data streams of m lanes may include a total of N RS codewords, and the first data stream of each lane may include (N × codeword length of RS codeword) / m bits.

[0019] According to a second aspect, an embodiment of the present application provides a decoding method. The decoding method may be applied to an optical module or other decoding device. In the decoding method, a fourth data stream of n lanes is obtained through n input lanes. A demultiplexing process is performed on the fourth data stream of n lanes to obtain a third data stream of z lanes. A decoding process is performed separately on each of the third data streams of z lanes to obtain a second data stream of z lanes. A multiplexing process is performed on the second data stream of z lanes based on a first ratio to obtain a first data stream of m lanes, where the first ratio and the second ratio are reciprocals of each other.

[0020] In some other possible implementations, the third data stream of the z lanes includes a first identifier, the first identifier identifying a codeword boundary of the FEC codeword. The decoding method further includes identifying a codeword boundary of the FEC codeword based on the first identifier and / or a decoding flag bit, the decoding flag bit indicating whether the inner code decoding process was successful.

[0021] In some other possible implementations, before identifying the codeword boundary of the FEC codeword based on the first identifier and / or the decoding flag bit, the decoding method further includes generating a first signal based on the first identifier and / or the decoding flag bit, where the first signal is for determining data and clock information. It should be noted that the first signal can be for determining the data and clock information, thereby accelerating the process of data and clock recovery by the CDR unit, allowing the data and clock information to be predetermined, reducing the time required for system lock, and facilitating the predetermined determination of the system transmission frequency. Furthermore, in designing a method for generating a sequence corresponding to the first identifier in this application, the autocorrelation characteristics of the sequence corresponding to the first identifier are taken into consideration, which helps the first identifier be detected more quickly, and the fixed 0-1 transition characteristics of the first identifier are taken into consideration, which helps the CDR unit to converge on the data and clock recovery. It should be noted that if the CDR unit first receives a signal fed back by the CDR unit and for successfully restoring the data and clock before receiving the first signal, the CDR unit may enter a locked state based on the signal for successfully restoring the data and clock and complete the data and clock recovery operation.

[0022] According to a third aspect, an embodiment of the present application provides another encoding method, in which a data stream to be transmitted is obtained, and an RS encoding process is performed on the data stream to be transmitted to obtain z-lane data streams, each of the z-lane data streams corresponding to one physical coding sublayer lane, and then a multiplexing process is performed on the z-lane data streams based on a first ratio to obtain m-lane first data streams, and the m-lane first data streams are transmitted through m output lanes.

[0023] In some other possible implementations, the encoding method may further include performing Q-stage processing on each of the z lanes' data streams to obtain z lanes' ninth data streams, where each stage of the Q-stage processing includes performing round-robin distribution processing on the ninth data stream obtained in the previous stage to obtain at least two lanes' data substreams, performing delay processing on the third data substream to obtain a tenth data stream, and performing multiplexing processing on the fourth data substream and the tenth data stream to obtain the ninth data stream obtained through the current stage's processing, where the third data substream is at least one of the at least two lanes' data substreams, and the fourth data substream is a lane's data substream that is included in the at least two lanes' data substreams and is not subjected to delay processing. Then, multiplexing processing is performed on the z lanes' ninth data streams based on the first ratio to obtain m lanes' first data streams.

[0024] According to a fourth aspect, an embodiment of the present application provides an encoding device. The encoding device includes a first acquisition unit and a first processing unit. The first acquisition unit is configured to acquire m lanes of first data streams through m input lanes, where m is a positive integer. The first processing unit is configured to process the m lanes of first data streams to acquire z lanes of second data streams, where z is a positive integer, separately perform an encoding process on each of the z lanes of second data streams to acquire z lanes of third data streams, and perform a multiplexing process on the z lanes of third data streams to acquire n lanes of fourth data streams, where n is a positive integer.

[0025] In some other possible implementations, each of the z second data streams includes a data block to be encoded, and the first processing unit is configured to perform an encoding process on the first data block to obtain one or more FEC codewords, where the first data block is at least C / z consecutive data blocks to be encoded in the corresponding second data stream, where C is a positive integer and C is an integer multiple of z, and is configured to insert a first identifier at a codeword boundary position of any one of the FEC codewords, where the first identifier identifies a codeword boundary of the FEC codeword, and the throughput or baud rate of the FEC codeword obtained through the insertion of the first identifier is an integer multiple of the reference clock. In the above scheme, the codeword boundary of the FEC codeword is identified by the first identifier, so that the boundary position of each FEC codeword can be determined by directly identifying the first identifier in a subsequent decoding process, and a case where inner code decoding is invalid in the case of delay skew and unknown data start position is avoided.

[0026] In some other possible implementations, each of the z second data streams includes a data block to be encoded, and the first processing unit is configured to insert a first identifier into each of the data blocks to be encoded in the first data block to obtain a second data block, where the first data block is C / z consecutive data blocks to be encoded, where C is a positive integer and C is an integer multiple of z, and is configured to perform an encoding process on the second data block to obtain an FEC code word, where the throughput or baud rate of the FEC code word is an integer multiple of the reference clock. In the above scheme, code word boundaries of the FEC code words are identified by the first identifier, so that the boundary positions of each FEC code word can be determined by directly identifying the first identifier in a subsequent decoding process, and a case where inner code decoding is invalid in the case of delay skew and unknown data start positions is avoided.

[0027] In some other possible implementations, the first identifier is a preset identifier sequence. In the above schemes, the first identifier is set to be a preset identifier sequence, so that requirements in different scenarios can be met.

[0028] In some other possible implementations, the first identifier is obtained based on a value of a first bit in the first data block, where the first bit is any one of at least one bit in the first data block, or the first identifier is obtained based on bit values of at least L second bits in the first data block, where there is an interval of s bits between every two adjacent second bits among the L second bits, where L≧2 and s≧0, and L and s are integers.

[0029] In some other possible implementations, the first processing unit is configured to perform a demultiplexing process on the first data streams of m lanes based on a second ratio to obtain second data streams of z lanes, where the second ratio is a ratio of m to z.

[0030] In some other possible implementations, the first processing unit is configured to perform demultiplexing processing on the first data streams of m lanes based on a second ratio to obtain a fifth data stream of z lanes, and separately perform Q-stage processing on each of the fifth data streams of the z lanes to obtain a second data stream of z lanes, wherein each stage of processing in the Q-stage processing includes: performing round-robin distribution processing on the data stream obtained in the previous stage to obtain data substreams of at least two lanes; performing delay processing on the first data substream to obtain a sixth data stream; and performing multiplexing processing on the second data substream and the sixth data stream to obtain an output data stream obtained through the current-stage processing, wherein the first data substream is at least one of the data substreams of the at least two lanes, and the second data substream is a data substream of one lane that is within the data substreams of the at least two lanes and for which delay processing is not performed, where Q is a positive integer, and the second data stream is a data stream obtained through the Q-stage processing.

[0031] In some other possible implementations, the bit length of the sixth data stream is at least (N × codeword length of RS codeword) / (z × i) bits, where N is a positive integer and i is the number of data substreams.

[0032] In some other possible implementations, the first processing unit is further configured to obtain a seventh data stream of m lanes through m input lanes, and the first processing unit is configured to perform a demultiplexing process on the seventh data stream of m lanes based on a second ratio to obtain an eighth data stream of z lanes, and to perform a multiplexing process on the second data stream of z lanes and the eighth data stream of z lanes to obtain z second data streams obtained through the multiplexing process.

[0033] In some other possible implementations, the first processing unit is further configured to identify an alignment marker in the second data stream of each lane, the alignment marker identifying a symbol boundary in the corresponding second data stream, and to determine the symbol boundary in the corresponding second data stream based on the alignment marker.

[0034] In some other possible implementations, the first data streams of m lanes are obtained by performing a multiplexing process at a first ratio on the data streams of z lanes obtained through Reed-Solomon RS encoding.

[0035] According to a fifth aspect, an embodiment of the present application provides a decoding device. The decoding device includes a second acquisition unit and a second processing unit. The second acquisition unit is configured to acquire a fourth data stream of n lanes through n input lanes. The second processing unit is configured to perform a demultiplexing process on the fourth data stream of n lanes to acquire a third data stream of z lanes, separately perform a decoding process on each of the third data streams of z lanes to acquire a second data stream of z lanes, and perform a multiplexing process on the second data stream of z lanes based on a first ratio to acquire a first data stream of m lanes, where the first ratio and the second ratio are reciprocals of each other.

[0036] In some other possible implementations, the third data stream of the z lanes includes a first identifier, the first identifier identifying a codeword boundary of the FEC codeword, and the second processing unit is further configured to identify the codeword boundary of the FEC codeword based on the first identifier and / or a decoding flag bit, and the decoding flag bit indicating whether the decoding process was successful or not.

[0037] In some other possible implementations, the second processing unit is further configured to generate a first signal based on the first identifier and / or the decoding flag bit before identifying the codeword boundary of the FEC codeword based on the first identifier and / or the decoding flag bit, where the first signal is for determining data and clock information. It should be noted that the first signal can be for determining the data and clock information, thereby accelerating the process of data and clock recovery by the CDR unit, allowing the data and clock information to be predetermined, reducing the time required for system lock, and facilitating the predetermined determination of the system transmission frequency. Furthermore, in designing a method for generating a sequence corresponding to the first identifier in this application, the autocorrelation characteristics of the sequence corresponding to the first identifier are taken into consideration, which helps the first identifier be detected more quickly, and the fixed 0-1 transition characteristics of the first identifier are taken into consideration, which helps the CDR unit to converge on the data and clock recovery. It should be noted that if the CDR unit first receives a signal fed back by the CDR unit and for successfully restoring the data and clock before receiving the first signal, the CDR unit may enter a locked state based on the signal for successfully restoring the data and clock and complete the data and clock recovery operation.

[0038] According to a sixth aspect, an embodiment of the present application provides an encoding device. The encoding device may include a memory configured to store computer-readable instructions. The encoding device may further include a processor coupled to the memory and configured to execute the computer-readable instructions in the memory to enable the encoding device to perform the encoding method according to the first aspect or any one of the possible implementation manners of the first aspect.

[0039] According to a seventh aspect, an embodiment of the present application provides a decoding device. The decoding device may include a memory configured to store computer-readable instructions. The decoding device may further include a processor coupled to the memory and configured to execute the computer-readable instructions in the memory to enable the decoding device to perform a method according to the second aspect or any one of possible implementation manners of the second aspect.

[0040] According to an eighth aspect, an embodiment of the present application provides a computer-readable storage medium comprising instructions which, when executed on a computer, enable the computer to perform a method according to the first aspect, the second aspect, or any one of the possible implementations of the first or second aspect.

[0041] According to a ninth aspect, an embodiment of the present application provides a computer program product comprising instructions, which when executed on a computer, enable the computer to perform a method according to the first aspect, the second aspect, or any one of the possible implementations of the first or second aspect.

[0042] A tenth aspect of the present application provides a chip system, which may include a processor configured to support an encoding device in implementing functions in an encoding method according to the first aspect or any one of possible implementations of the first aspect, or to support a decoding device in implementing functions in a decoding method according to the second aspect or any one of possible implementations of the second aspect.

[0043] Optionally, referring to the tenth aspect, in a first possible implementation manner, the chip system may further include a memory. The memory is configured to store program instructions and data required for the encoding device and the decoding device. The chip system may be composed of a chip, or may include a chip and other discrete devices. The chip system may include an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), other programmable logic devices, etc. Furthermore, the chip system may further include an interface circuit, etc.

[0044] It can be seen from the above technical solutions that the embodiments of this application have the following advantages:

[0045] In an embodiment of the present application, a first data stream of m lanes is obtained through m input lanes, where m is a positive integer, and the first data stream of m lanes is processed to obtain a second data stream of z lanes, where z is a positive integer. Then, an encoding process is performed separately on each of the second data streams of z lanes to obtain a third data stream of z lanes, and a multiplexing process is performed on the third data streams of z lanes to obtain a fourth data stream of n lanes, where n is a positive integer. In the above scheme, in this embodiment of the present application, an encoding process is performed separately on each of the second data streams of z lanes, and the FEC code word in each third data stream obtained through encoding includes a boundary identifier. This ensures that the inner code encoding is separated from the data obtained through encoding at the upper PCS layer, ensures that the inner code encoding is separated from the transmission at the lower PMD layer, and eliminates the need to perform operations such as deskewing and reordering, reducing the delay of handling delay skew and out-of-order, thereby making the inner code encoding and decoding in this application applicable to scenarios that are sensitive to transmission delay. [Brief explanation of the drawings]

[0046] In order to more clearly describe the technical solutions in the embodiments of this application, the following will briefly describe the accompanying drawings used in describing the embodiments. Obviously, the accompanying drawings in the following description only illustrate some embodiments of this application. [Figure 1A] 1 is a schematic diagram of an Ethernet communication architecture according to a related solution; [Figure 1B] FIG. 1 is a schematic diagram of skew and out-of-order data streams. [Figure 2] 1 is a schematic diagram of an application scenario according to an embodiment of the present application; [Figure 3] 1 is a schematic flowchart of an encoding method according to an embodiment of the present application; [Figure 4A]FIG. 2 is a schematic diagram of the transmission of data streams in an encoding process according to an embodiment of the present application; [Figure 4B] FIG. 2 is another schematic diagram of the transmission of data streams in the encoding process according to an embodiment of the present application; [Figure 4C] FIG. 2 is another schematic diagram of the transmission of data streams in the encoding process according to an embodiment of the present application; [Figure 4D] FIG. 2 is another schematic diagram of the transmission of data streams in the encoding process according to an embodiment of the present application; [Figure 4E] FIG. 2 is another schematic diagram of the transmission of data streams in the encoding process according to an embodiment of the present application; [Figure 4F] FIG. 2 is another schematic diagram of the transmission of data streams in the encoding process according to an embodiment of the present application; [Figure 5A] FIG. 2 is a schematic diagram of performing an inner code encoding processing operation according to an embodiment of the present application; [Figure 5B] FIG. 10 is another schematic diagram of performing an inner code encoding processing operation according to an embodiment of the present application. [Figure 6A] FIG. 1 is a schematic diagram of adding a first identifier according to an embodiment of the present application; [Figure 6B] FIG. 2 is a schematic diagram of a value assignment scheme for a first identifier according to an embodiment of the present application; [Figure 6C] FIG. 10 is a schematic diagram of another value assignment scheme for a first identifier according to an embodiment of the present application; [Figure 7] FIG. 2 is another schematic diagram of the transmission of data streams in the encoding process according to an embodiment of the present application; [Figure 8] 1 is a schematic diagram of the overall transmission of data streams in the PMA layer. [Figure 9] 1 is a schematic flowchart of a decoding method according to an embodiment of the present application; [Figure 10A] FIG. 2 is a schematic diagram of the transmission of data streams in a decoding process according to an embodiment of the present application; [Figure 10B]FIG. 10 is another schematic diagram of the transmission of data streams in the decoding process according to an embodiment of the present application; [Figure 11] 1 is a schematic diagram of a hardware structure of a communication device according to an embodiment of the present application; [Figure 12] 1 is a schematic diagram of the structure of an encoding device according to an embodiment of this application; [Figure 13] 1 is a schematic diagram of the structure of a decoding device according to an embodiment of the present application; DETAILED DESCRIPTION OF THE INVENTION

[0047] Embodiments of this application disclose an encoding method, a decoding method, and related apparatuses for separately performing encoding processing on each of the z lanes of second data streams without performing operations such as deskewing and reordering on the z lanes of second data streams, which reduces operational complexity and delay.

[0048] The following describes the technical solutions in the embodiments of this application with reference to the accompanying drawings in the embodiments of this application. Certainly It is clear that the embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative efforts shall fall within the protection scope of this application.

[0049] In the specification, claims, and accompanying drawings of this application, terms such as "first," "second," "third," and "fourth," when present, are intended to distinguish between similar objects, but do not necessarily indicate a particular order or sequence. It should be understood that such designated data are interchangeable under appropriate circumstances, thereby allowing the embodiments of this application described herein to be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprise" and "have," and any variations thereof, are intended to cover a non-exclusive inclusion. In this application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes an association relationship between related objects and indicates that three relationships may exist. For example, A and / or B may represent the following cases: only A is present; both A and B are present; and only B is present, and A and B may be singular or plural. The character " / " generally indicates an "or" relationship between related objects. "At least one of" or similar phrases refers to any combination of items and includes any combination of singular items or multiple items. For example, at least one of a, b, or c may represent a, b, c, a and b, a and c, b and c, or a, b, and c, where a, b, and c may be singular or plural. It should be noted that "at least one" may also be interpreted as "one or more."

[0050] In a related existing Ethernet communication architecture, the physical sublayer of the Ethernet communication architecture may be divided into a PCS layer, a PMA layer, and a PMD layer. FIG. 1A is a schematic diagram of an Ethernet communication architecture according to a related solution. As shown in FIG. 1A, a data stream is acquired from a MAC module, and a 64B / 66B encoding process, a 256B / 257B transcoding process, an alignment marker (AM) insertion process, and an RS encoding process are sequentially performed on the data stream in the PCS layer. Then, a multiplexing process is performed on the data stream acquired through the RS encoding process, and the multiplexed data stream is transmitted to the PMA layer through m output lanes. In the PMA layer, a CDR process and a bit multiplexing process are sequentially performed on the data stream received through m input lanes, and the processed data stream is transmitted from the PMA layer to the PMD layer. Then, a process such as optical modulation is completed on the data stream in the PMD layer, and an optical signal is output to a transmission medium to complete the entire data operation at the transmitting end. The data stream processing operation at the receiving end is the reverse operation. Specifically, the processing at the PMD layer and the processing at the PMA layer are completed sequentially at the receiving end. Then, the data stream is transmitted to the PCS layer through m output lanes.

[0051] However, in the related Ethernet communication architecture shown in FIG. 1A, when a data stream obtained through processing in the PCS layer is transmitted to the PMA layer through m output lanes, delay skew occurs among the m output lanes. As a result, the data streams obtained from the m output lanes are not synchronized in time, and the data streams received at the PMA layer cannot be aligned. For details, see the schematic diagram of data stream skew and out-of-order shown in FIG. 1B. Therefore, in the Ethernet communication architecture shown in FIG. 1A, encoding operations can be performed only after processing operations such as aligning, deskewing, and reordering of multiple physical coding sublayer lanes to align the data streams among the input lanes are completed. However, the delay required to complete operations such as data alignment, deskew, and reordering is 180 ns, which increases the complexity and delay of the operations. Furthermore, as Ethernet transmission rates increase, existing Ethernet communication architectures are only applicable to scenarios with throughputs of 400 Gbps or less and cannot meet the system error correction performance requirements required by next-generation Ethernet communication with throughputs greater than 400 Gbps.

[0052] Therefore, to solve the problems in FIGS. 1A and 1B, if a one-to-one correspondence can be formed between the inner code sublayer and the physical coding sublayer lanes in the PMA layer to separately perform inner code encoding for the data streams in each physical coding sublayer lane, processing operations such as deskewing and reordering shown in FIG. 1B may be omitted, which effectively reduces delay and complexity. Based on this, embodiments of this application provide encoding and decoding methods applicable to various optical communication scenarios, such as medium- and short-range interconnection communications, long-range interconnection communications, cloud storage, cloud computing, 5G base station backbone networks, optical transmission, optical access, and base station fronthaul in data centers. The encoding and decoding methods may also be applied to next-generation Ethernet communication architectures with throughputs greater than 400 Gbps (e.g., 800 Gbps or 1600 Gbps). Medium- and short-range interconnection communications include, but are not limited to, optical transmission scenarios where the distance is 40 km or less. FIG. 2 is a schematic diagram of an application scenario according to an embodiment of this application. As shown in FIG. 2, any two hosts realize data communication by using optical modules. For example, a data stream is transmitted from host A to host B. Optical module a is inserted into host A, optical module b is inserted into host B, and host A may sequentially transmit the data stream to host B via optical module a and optical module b. In order to omit processing operations such as deskewing and rearrangement, effectively reduce delay and complexity, and change the processing procedure of the host as little as possible, the data stream processing process of the optical module needs to be modified as follows: process the first data stream of m lanes obtained through m input lanes, restore the original second data stream of z lanes, and then separately perform inner code encoding processing on each of the second data streams of z lanes to obtain a third data stream of z lanes.The inner code encoding process is performed separately for the second data stream of each lane, without performing complex processes such as deskewing and reordering for the second data streams of the z lanes. When a breakout mode requirement exists in the system, it can be ensured that the second data stream of each lane can be transmitted separately, provided that each input lane and each output lane in the PMA layer can uniquely correspond to one transmission medium. The system is well suited for the breakout mode.

[0053] It should be noted that the above optical modules may be understood as optical modules used when a data stream is transmitted to a receiving end, or as optical modules used when a data stream is received from a receiving end, such as the above optical module a and optical module b. In practical applications, the data stream may alternatively be transmitted from host B to host B. This is not limited here. Furthermore, the host (e.g., host A or host B) may further include, but is not limited to, a switching chip or an interface chip used in a router, a switch, or an optical transport network (OTN) transmission device, or may be a mobile phone chip, a CPU chip, an interface chip requiring high-speed communication, etc. This is not limited here.

[0054] 3 is a schematic flowchart of an encoding method according to an embodiment of this application. As shown in FIG. 3, the encoding method may include the following steps:

[0055] 301: Obtain a first data stream of m lanes through m input lanes, where m is a positive integer.

[0056] In this example, after the data stream to be transmitted sent by the MAC module is obtained in the PCS layer, a 64B / 66B encoding process, a 256B / 257B transcoding process, and an RS encoding process are sequentially performed on the data stream to be transmitted to obtain z lane data streams. Furthermore, each of the z lane data streams corresponds to one physical coding sublayer lane (PCS lane) in the PCS layer, so that one lane data stream can be transmitted through one physical coding sublayer lane. Then, after the z lane data streams obtained through RS encoding are obtained, a multiplexing process is performed on the z lane data streams obtained through RS encoding based on a first ratio to obtain m lane first data streams (e.g., D1, D2, ... and D m ) may be obtained. For details, please refer to FIG. 1A for understanding. The details will not be described again here. The sign in It should be noted that may be understood as the first code in a concatenated code, i.e., the code included in the PCS layer.

[0057] In some other possible examples, before a multiplexing process is performed on the data streams of z lanes obtained through RS encoding based on the first ratio in the PCS layer to obtain the first data streams of m lanes, the following operation may be further performed first: perform Q-stage processing on each of the data streams of z lanes obtained through RS encoding to obtain a ninth data stream of z lanes, where each stage of processing in the Q-stage processing includes: performing round-robin distribution processing on the data stream obtained in the previous stage to obtain data substreams of at least two lanes, performing delay processing on the third data substream to obtain a tenth data stream, and performing multiplexing processing on the fourth data substream and the tenth data stream to obtain an output data stream obtained through the processing in the current stage, where the third data substream is at least one of the data substreams of the at least two lanes, the fourth data substream is a data substream of one lane that is within the data substreams of the at least two lanes and for which delay processing is not performed, Q is a positive integer, and the ninth data stream is the data stream obtained through the Q-stage processing. Then, a multiplexing process is performed on the ninth data stream of z lanes in the PCS layer based on the first ratio to obtain the first data stream of m lanes.

[0058] It should be noted that the specific process of performing the Q stage processing in the PCS layer can be understood with reference to the following contents of Figures 4B to 4D, and the details will not be described here.

[0059] The first ratio may be understood as the ratio of z to m, or the ratio of the number of physical coding sublayer lanes to the number of input lanes. For example, if the PCS layer intends to transmit 16-lane data streams to the PMA layer through four output lanes, a multiplexing process needs to be performed on the 16-lane data streams based on the first ratio of 16:4 to obtain four-lane first data streams. It should be noted that the example of the first ratio being 16:4 is used merely for the purpose of explanation here. In actual applications, the first ratio may alternatively be other values, such as 32:4, 32:16, or 16:8. This is not limited here.

[0060] Furthermore, the first data streams of the m lanes include a total of N RS codewords. For example, the value of N may be 2, 4, 6, etc. This is not limited here. The first data stream of each lane may include (N × codeword length of RS codeword) / m bits. For example, the data block length of the RS codeword is 514 symbols, the parity bit length is 62 symbols, the total codeword length is 576 symbols, the size of each symbol is 10 bits, and the error correction capability of the codeword is 31 correctable error symbols. Alternatively, the data block length of the RS codeword may be 514 symbols, the parity bit length is 30 symbols, the total codeword length is 544 symbols, the size of each symbol is 10 bits, and the error correction capability of the codeword is 15 correctable error symbols. It should be noted that the codeword length of the RS codeword is not limited in this application. In practical applications, other codeword lengths may also be included to achieve error correction of different error symbols.

[0061] In this way, after the m lanes of first data streams are acquired in the PCS layer, the m lanes of first data streams are transmitted from the PCS layer to the PMA layer. In this case, the PMA layer may acquire the m lanes of first data streams through m input lanes. It should be noted that the input lanes may be understood as physical medium connection sublayer lanes, physical lanes of the AUI interface, output lanes of the upper PMA layer, etc. This is not a limitation in this application.

[0062] 302: Process a first data stream of m lanes to obtain a second data stream of z lanes, where z is a positive integer.

[0063] In this example, the PMA layer has m input lanes (e.g., E1, E2, ... and E m ), the m-lane first data streams are transmitted by the PCS layer through the PCS layer. z ) may be processed to obtain z lane data streams. It should be noted that the number of lanes of the z second data streams is equal to the number of z lane data streams obtained by performing RS encoding on the data stream to be transmitted at the PCS layer in step 301. Furthermore, the z lane second data streams may also be referred to as PCS lane data streams in some possible examples.

[0064] The second data stream of each lane may include Y data blocks to be encoded, where a data block to be encoded may be understood as information bits to be encoded. Furthermore, for a data block to be encoded in the second data stream of a lane, the mapping relationship between the data block to be encoded and the RS codeword satisfies Y × length of block to be encoded = X × (N × codeword length of RS codeword) / z, where Y and X are positive integers.

[0065] Furthermore, the length of each data block to be encoded is k, the parity bit length is p, and the total codeword length is n, where n, k, and p satisfy n=k+p, and n, k, and p are integers greater than 0. For example, if the length k of the data block to be encoded is 170 bits, the total codeword length of the data block to be encoded is 180 bits after 10 parity bits are added. Alternatively, if the length k of the data block to be encoded is 170 bits, the total codeword length of the data block to be encoded is 179 bits after 9 parity bits are added. Alternatively, if the length k of the data block to be encoded is 170 bits, the total codeword length of the data block to be encoded is 181 bits after 11 parity bits are added. Alternatively, if the length k of the data block to be encoded is 120 bits, the total codeword length of the data block to be encoded is 128 bits after 8 parity bits are added. These are merely used as examples for the purpose of explanation herein and are not particularly limited in this application.

[0066] In some other possible examples, different processing operations may be performed on the first data streams of m lanes in the PMA layer to obtain the second data streams of z lanes. For example, the second data streams of z lanes may be obtained by directly performing a demultiplexing process on the first data streams of m lanes, or may be obtained by further performing a delay and multiplexing process on the data streams obtained through the demultiplexing process, or may be obtained by performing a multiplexing process on the data streams obtained through different RS encoding processes. Below, detailed descriptions are provided separately using different embodiments.

[0067] (1) Directly perform demultiplexing to obtain the second data stream of z lanes.

[0068] In some optional examples, the first data streams of m lanes may be processed to obtain the second data streams of z lanes in the following manner: performing a demultiplexing process on the first data streams of m lanes based on a second ratio to obtain the second data streams of z lanes, where the second ratio and the first ratio are reciprocals of each other.

[0069] In this example, the second ratio is a ratio of m to z, and the second ratio and the first ratio are reciprocals of each other. After the m-lane first data stream is obtained at the PMA layer through m input lanes, a data stream having the same number as the number of physical coding sublayer lanes, i.e., a z-lane second data stream, can be obtained by directly performing demultiplexing based on the second ratio. For example, if the first ratio is 16:4, the second ratio should be 4:16. After the four-lane first data stream is obtained through four input lanes, a 16-lane second data stream can be obtained through demultiplexing based on the second ratio 4:16. It should be noted that the bit length of each of the z-lane second data streams is (N × codeword length of the RS codeword) / z bits.

[0070] 4A is a schematic diagram of data stream transmission according to an embodiment of the present application. From FIG. 4A, it can be seen that in the PMA layer, after m-lane first data streams are obtained through m input lanes, a first demultiplexing process is performed on the m-lane first data streams based on a second ratio (e.g., m / z) to obtain z-lane second data streams. It should be noted that the first demultiplexing process may include, but is not limited to, DeMUX. Then, an inner-code encoding process is separately performed on each of the z-lane second data streams obtained through the demultiplexing process by using an inner-code (Inner-FEC) sublayer. For details, please refer to the content described in the following step 303. Details will not be described here. Then, a multiplexing process is performed on the z-lane third data streams to obtain n-lane fourth data streams. For details, please refer to the content described in the following step 304. Details will not be described here.

[0071] (2) Further performing delay and multiplexing processing on the data stream obtained through the demultiplexing processing to obtain a second data stream of z lanes.

[0072] In some optional examples, the demultiplexing process may alternatively be performed on the first data streams of m lanes in the PMA layer based on a second ratio to obtain second data streams of z lanes in the following manner: perform a demultiplexing process on the first data streams of m lanes based on a second ratio to obtain fifth data streams of z lanes; then perform Q-stage processing on each of the fifth data streams of z lanes to obtain second data streams of z lanes; and each stage of processing in the Q-stage processing performs round-robin distribution processing on the data stream obtained in the previous stage to obtain at least two obtain a data substream of a lane, perform a delay process on the first data substream to obtain a sixth data stream, and perform a multiplexing process on the second data substream and the sixth data stream to obtain an output data stream obtained through the current stage processing, wherein the first data substream is at least one of the data substreams of at least two lanes, and the second data substream is a data substream of one lane within the data substreams of the at least two lanes for which a delay process is not performed, Q is a positive integer, and the second data stream is a data stream obtained through the Q stage processing.

[0073] In this example, a demultiplexing process is performed on the first data streams of m lanes based on the second ratio to generate a fifth data stream (e.g., G1, G2, ... and G z ) is obtained. For understanding, refer to obtaining the second data stream of z lanes through demultiplexing in FIG. 4A. The details will not be described again here.

[0074] One of the fifth data streams of the lane (e.g., G1) is used as an example. In the PMA layer, a first-stage round-robin distribution process is performed on the previously acquired data stream to obtain at least two lane data sub-streams, and a delay process is performed on at least one of the lane data sub-streams to obtain the first-stage sixth data stream. Last time It should be noted that the acquired data stream is acquired by sequentially performing round-robin distribution processing, delay processing, and multiplexing processing on the fifth data stream of the previous stage. The data stream acquired previously and input for the first-stage round-robin distribution processing may be understood as the fifth data stream G1. The data stream acquired previously and input for the second-stage round-robin distribution processing may be understood as the output data stream acquired through the first multiplexing processing of the first stage. Then, multiplexing processing is performed on the data substream of one lane that is within the data substreams of at least two lanes and for which delay processing is not performed (i.e., the second data substream) and the sixth data stream of the first stage to acquire the output data stream acquired through the processing of the current stage. By analogy, the corresponding second data stream of one lane may be acquired through processing in the Q stage. That is, the second data stream is the data stream acquired through processing in the Q stage.

[0075] It should be noted that the above Q-phase processing may be understood as a Q-phase concatenation processing or a Q-phase iteration processing. The Q-phase concatenation processing may be understood with reference to the contents of the following Figures 4B to 4D. The Q-phase iteration processing may be understood with reference to the contents of the following Figure 4E. Below, different embodiments will be used to provide separate descriptions.

[0076] (1) Q-stage connection processing

[0077] 4B is another schematic diagram of data stream transmission according to an embodiment of this application. From FIG. 4B, it can be seen that, based on the structure shown in FIG. 4A, in the inner code sublayer, a first demultiplexing process is first performed on the first data streams of m lanes to obtain a fifth data stream of z lanes. Then, the fifth data streams of z lanes are processed together through Q-stage round-robin distribution processes, Q-stage first delay processes, and Q-stage first multiplexing processes to obtain a second data stream of z lanes. Specifically, after the fifth data streams of z lanes are obtained through demultiplexing, specifically the first demultiplexing process, the fifth data streams of z lanes may be transmitted to the first-stage round-robin distribution process through z physical medium connection sublayer lanes. It should be noted that the data stream previously obtained and input for the first-stage round-robin distribution process may also be understood as the fifth data stream. Furthermore, the bit length of each stage of the Q-stage concatenation process is (N×the codeword length of the RS codeword) / z bits.

[0078] One of the fifth data streams of the lane (for example, G1) is used as an example. The fifth data stream G1 is input for the first-stage round robin distribution process, and the round robin distribution process is performed on the fifth data stream G1 through the first-stage round robin distribution process to generate at least two first-stage data sub-streams of the lane (for example, G 11 1 , G 12 1 , G 13 1 and G 14 1 ) to get G 11 1 and G 12 1 is used as an example. One of the first stage data substreams of a lane (e.g., G 11 1) is input to the first delay process of the first stage, and the delay process delays the data substream G 11 1 The sixth data stream of the first stage of one lane (e.g., J1 1 ) is output. Then, the sixth data stream J1 of the first stage is output. 1 and the first stage data substream G of the other lane 12 1 is input to the first multiplexing process of the first stage, and the multiplexing process generates a sixth data stream J1 of the first stage through the first multiplexing process of the first stage. 1 and the data substream G of the other lane 12 1 , and the first stage output data stream of one lane (e.g., P1 1 ) to get G 11 1 may be understood as the first data sub-stream above, and G 12 1 It should be noted that may be understood as the second data sub-stream above.

[0079] Then, the first stage output data stream P1 1 is input to the second stage round robin distributed processing, and the round robin distributed processing distributes the first stage output data stream P1 through the second stage round robin distributed processing. 1 2. The second stage data substream (e.g., G 11 2 , G 12 2 , G 13 2 and G 14 2 ) to get G 11 2 and G 12 2 is used as an example. One of the data substreams of the lane (e.g., G 11 2) is input to the first delay process of the second stage, and the delay process delays the data substream G 11 2 The sixth data stream of the second stage of one lane (e.g., J1 2 In this case, the sixth data stream J1 of the second stage of the lane is obtained. 2 and the second stage data substream G of the other lane 12 2 is input to the second stage second multiplexing process, and through the multiplexing process, specifically, the second stage second output data stream of one lane (for example, P1 2 ) may be obtained.

[0080] The rest is the output data stream of the (Q-1)th stage (e.g., P1) in one lane of the Q-stage round-robin distributed processing. Q-1 ) to generate at least two lanes of Q-phase data substreams (e.g., G 11 Q , G 12 Q , G 13 Q and G 14 Q ) can be inferred by analogy until it is obtained. 11 Q and G 12 Q is used as an example. One of the data substreams of the Qth stage of the lane (e.g., G 11 Q ) is input to the first delay processing of the Q stage, and the data substream G 11 Q A delay process is performed on the sixth data stream of the Q stage of one lane (e.g., J1 Q ) is output. Then, the sixth data stream J1 of the Q stage is output. Q and the data substream G of the Qth stage of the other lane. 12 Qis input to the first multiplexing process of the Q stage, and is converted into the sixth data stream J1 of the Q stage through the first multiplexing process of the Q stage. Q and the data substream G of the Qth stage of the other lane. 12 Q A multiplexing process is performed on the data streams of one lane, ie, the second data stream (eg, F1), which is finally input for encoding process.

[0081] Similarly, the fifth data stream of the other lanes (e.g., G2, ... and G z ), the fifth data streams of the other lanes may also be processed through a first delay process in a Q stage and a first multiplexing process in a Q stage corresponding to each of the fifth data streams of the other lanes to obtain corresponding second data streams. The specific processing process can be understood by referring to the above processing process of the fifth data stream G1. The details will not be described again here.

[0082] Then, in the inner code sublayer, an inner code encoding process is separately performed on the obtained second data streams of z lanes to obtain corresponding third data streams of z lanes. For details, please refer to the content described in the subsequent step 303 for understanding. Details will not be described here. Then, a multiplexing process is performed on the third data streams of z lanes to obtain a fourth data stream of n lanes. For details, please refer to the content described in the subsequent step 304 for understanding. Details will not be described here.

[0083] It should be noted that in the process of performing any stage of the round robin distribution process, U bits may be used as the granularity, and the round robin distribution process is performed based on the granularity for the data stream input for the round robin distribution process stage. U = w × N × (the bit length of one symbol in the RS codeword), where w is a positive integer equal to or greater than 1. The above first stage round robin distribution process is used as an example for explanation. If the fifth data stream (e.g., G1) of one lane contains four RS codewords, there are a total of 136 symbols, and the bit length of each symbol is 10 bits, so when w = 2, the granularity U = 80 bits. The data substream G obtained through the round robin distribution process 11 1 and G 12 1 are each 680 bits in length.

[0084] It should be noted that each stage of the first multiplexing process in the above Q-stage first multiplexing process may include, but is not limited to, a symbol multiplexing (symbol MUX) unit, a bit multiplexing (bit MUX) unit, etc. Each stage of the first delay unit in the Q-stage first delay process may alternatively be understood as a buffer unit.

[0085] For example, FIG. 4C is another schematic diagram of data stream transmission according to an embodiment of the present application. As shown in FIG. 4C, Q=1 and z=16 are used as an example. After a first demultiplexing process is performed on the first data stream of four lanes, a fifth data stream of 16 lanes (e.g., G1, G2, ... and G 16 ) is acquired. The fifth data stream G 16 is used as an example. In the inner coding sublayer, the fifth data stream G 16 is input for the first stage round robin distributed processing, and the round robin distributed processing generates the fifth data stream G 16, and performs on at least two lanes of first-stage data substreams (e.g., G 161 1 , G 162 1 , G 163 1 and G 164 1 ) to get G 161 1 and G 162 1 is used as an example. One of the first stage data substreams of a lane (e.g., G 161 1 ) is input to the first delay process of the first stage, and the delay process delays the data substream G 161 1 , and the sixth data stream of the first stage of one lane (e.g., J 16 1 ) is then output as the sixth data stream J 16 1 and the first stage data substream G of the other lane 162 1 is input to the first multiplexing process of the first stage, and the multiplexing process generates a sixth data stream J of the first stage through the first multiplexing process of the first stage. 161 1 and the data substream G of the other lane 162 1 , and one lane of data stream, i.e., the second data stream F, is finally input for encoding and obtained through multiplexing. 16 Then, the second data stream F of the lane obtained through the multiplexing process is obtained. 16 For details, please refer to the content described in the following step 303 for understanding. The details will not be described here. 15 The processing of other fifth data streams such as 16 It should be noted that the above process can be understood with reference to the process of the previous section, and the details will not be described again here.

[0086] Alternatively, FIG. 4D is another schematic diagram of data stream transmission according to an embodiment of this application. As shown in FIG. 4D, Q=2 and z=16 are used as an example. After a first demultiplexing process is performed on the first data stream of four lanes, a fifth data stream of 16 lanes (e.g., G1, G2, ... and G 16 ) is acquired. The fifth data stream G 16 is used as an example. The fifth data stream G 16 is input for the first stage round robin distributed processing, and the round robin distributed processing generates the fifth data stream G 16 , and performs on at least two lanes of first-stage data substreams (e.g., G 161 1 , G 162 1 , G 163 1 and G 164 1 ) to get G 161 1 and G 162 1 is used as an example. One of the first stage data substreams of a lane (e.g., G 161 1 ) is input to the first delay process of the first stage, and the delay process delays the data substream G 161 1 , and the sixth data stream of the first stage of one lane (e.g., J 16 1 ) is then output as the sixth data stream J 16 1 and the first stage data substream G of the other lane 162 1 is input to the first multiplexing process of the first stage, and the multiplexing process generates a sixth data stream J of the first stage through the first multiplexing process of the first stage. 16 1 and the data substream G of the other lane162 1 , and the first stage output data stream of one lane (e.g., P 16 1 ) and obtain the output data stream P 16 1 is input to the second stage round robin distributed processing, and the round robin distributed processing distributes the first stage output data stream P 16 1 2. The second stage data substream (e.g., G 161 2 , G 162 2 , G 163 2 and G 164 2 ) to get G 161 2 and G 162 2 is used as an example. One of the data substreams of the lane (e.g., G 1612 ) is input to the first delay process of the first stage, and the delay process delays the data substream G 161 2 , and the sixth data stream of the second stage of one lane (e.g., J 16 2 ) in this case, the sixth data stream J of the second stage of the lane 16 2 and the second stage data substream G of the other lane 162 2 is input to the second multiplexing process of the second stage and finally to the encoding process, that is, the final one-lane data stream, i.e., the second data stream, e.g., F 16is output from the second multiplexing process of the second stage. It should be noted that an inner code encoding process is then performed on the second data stream of z lanes obtained through the multiplexing process. For details, please refer to the content described in the following step 303 for understanding. The details will not be described here.

[0087] For example, the number of bits of the sixth data stream is at least (N×the codeword length of the RS codeword) / (z×i) bits, where N is a positive integer and i is the number of data substreams. For example, the one-stage processing shown in FIG. 4C is used as an example. For example, when Q=1, if the number of data substreams obtained through the first-stage round-robin distribution processing is 4, the first-stage data substreams (e.g., G 161 1 , G 162 1 , G 163 1 and G 164 1 The bit length of the data substream of each lane in the first stage is (N × codeword length of RS codeword) / (z × 4). In this case, the sixth data stream J 16 1 The bit length of is at least (N×codeword length of RS codeword) / (z×4) bits.

[0088] It should be understood that in Figure 4C, a description is provided by using one-stage processing as an example, and in Figure 4D, a description is provided by using two-stage processing as an example. In practical applications, the value of Q only needs to be an integer equal to or greater than 1. The specific value may be determined based on requirements and is not limited here.

[0089] (2) Q-stage iterative processing

[0090] 4E is another schematic diagram of data stream transmission according to an embodiment of the present application. From FIG. 4E, it can be seen that based on the structure shown in FIG. 4A, in the inner code sublayer, a first demultiplexing process is first performed on the first data streams of m lanes to obtain a fifth data stream of z lanes. Then, Q stages of iterative processes are separately performed on the fifth data streams of z lanes to obtain a second data stream of z lanes.

[0091] Specifically, after the fifth data stream of z lanes is obtained through demultiplexing, specifically, the first demultiplexing process, the fifth data stream of z lanes may be transmitted to the first-stage round-robin distribution process through z physical medium connection sublayer lanes. It should be noted that the previously obtained data stream input for the first-stage round-robin distribution process may be understood as the fifth data stream. Furthermore, the bit length of each stage in the Q-stage iterative process is (N×codeword length of RS codeword) / z bits.

[0092] One of the fifth data streams of the lane (for example, G1) is used as an example. The fifth data stream G1 is input for the first-stage round robin distribution process, and the round robin distribution process is performed on the fifth data stream G1 through the first-stage round robin distribution process to generate at least two first-stage data sub-streams of the lane (for example, G 11 1 and G 12 1 ) to get G 11 1 and G 12 1 is used as an example. One of the first stage data substreams of a lane (e.g., G 11 1 ) is input to the first delay process of the first stage, and the delay process delays the data substream G 11 1The sixth data stream of the first stage of one lane (e.g., J1 1 ) is output. Then, the sixth data stream J1 of the first stage is output. 1 and the first stage data substream G of the other lane 12 1 is input to the first multiplexing process of the first stage, and the multiplexing process generates a sixth data stream J1 of the first stage through the first multiplexing process of the first stage. 1 and the data substream G of the other lane 12 1 , and the first stage output data stream of one lane (e.g., P1 1 ) to get G 11 1 may be understood as the first data sub-stream above, and G 12 1 It should be noted that may be understood as the second data sub-stream above.

[0093] Then, the first stage output data stream P1 1 continues to be input for the first stage round robin distributed processing, and the round robin distributed processing outputs the first stage output data stream P1 1 Continuing to perform on at least two lanes of second-stage data substreams (e.g., G 11 2 and G 12 2 ) to get G 11 2 and G 12 2 is used as an example. One of the data substreams of the lane (e.g., G 11 2 ) continues to be input for the first delay process of the first stage, and the delay process is performed to transfer the data substream G 11 2 The sixth data stream of the second stage of one lane (e.g., J1 2In this case, the sixth data stream J1 of the second stage of the lane is obtained. 2 and the second stage data substream G of the other lane 12 2 continues to be input for the second multiplexing process of the first stage, and through the multiplexing process, specifically, the second multiplexing process of the first stage, one lane of the second stage output data stream (for example, P1 2 ) may be obtained.

[0094] The rest is the output data stream of the (Q-1)th stage (e.g., P1) in one lane of the Q-stage round-robin distributed processing. Q-1 ) to generate at least two lanes of Q-phase data substreams (e.g., G 11 Q and G 12 Q ) can be inferred by analogy until it is obtained. 11 Q and G 12 Q is used as an example. One of the data substreams of the Qth stage of the lane (e.g., G 11 Q ) continues to be input for the first delay processing of the first stage, and the data substream G of the Q stage is 11 Q A delay process is performed on the sixth data stream of the Q stage of one lane (e.g., J1 Q ) is output. Then, the sixth data stream J1 of the Q stage is output. Q and the data substream G of the Qth stage of the other lane. 12 Q is input to the first multiplexing process of the first stage, and the sixth data stream J1 of the Q stage is generated through the first multiplexing process of the first stage. Q and the data substream G of the Qth stage of the other lane. 12 Q A multiplexing process is performed on the second data stream F1 of one lane.

[0095] Similarly, the fifth data stream of the other lanes (e.g., G2, ... and G z ), Q stages of iterative processing corresponding to each of the fifth data streams of the other lanes may also be performed to obtain the corresponding second data streams. The specific processing process can be understood with reference to the above processing process of the fifth data stream G1. The details will not be described again here.

[0096] Then, in the inner code sublayer, an inner code encoding process is separately performed on the obtained second data streams of z lanes to obtain corresponding third data streams of z lanes. For details, please refer to the content described in the subsequent step 303 for understanding. Details will not be described here. Then, a multiplexing process is performed on the third data streams of z lanes to obtain a fourth data stream of n lanes. For details, please refer to the content described in the subsequent step 304 for understanding. Details will not be described here.

[0097] It should be noted that the bit length of the sixth data stream obtained through the Q-stage iterative process can alternatively be understood by referring to the bit length of the sixth data stream obtained through the Q-stage concatenation process, and the details will not be described again here.

[0098] (3) Perform a multiplexing process on the data streams obtained through different RS encoding processes to obtain a second data stream of z lanes.

[0099] In some optional examples, the encoding method may further include obtaining a seventh data stream of m lanes through m first input lanes, and performing a demultiplexing process on the seventh data stream of m lanes based on the second ratio to obtain an eighth data stream of z lanes, and processing the first data stream of m lanes to obtain a second data stream of z lanes includes performing a multiplexing process on the second data stream of z lanes and the eighth data stream of z lanes to obtain the second data stream of z lanes obtained through the multiplexing process.

[0100] In this example, the seventh data stream of m lanes is obtained by performing a multiplexing process at a first ratio on the data stream of z lanes obtained through RS encoding. For details, refer to the first data stream of m lanes in step 301 for understanding. The details will not be described again here. In the PCS layer, the data stream obtained from the MAC module is divided into two data streams of the same number of parts. For each part, i.e., z data streams, in the PCS layer, processes such as 64B / 66B encoding, 256B / 257B transcoding, alignment marker AM insertion, and RS encoding are sequentially completed for the z data streams. Then, a multiplexing process is separately performed on the two parts based on a first ratio to obtain the first data stream of m lanes and the seventh data stream of m lanes, where each part is a data stream of z lanes obtained through RS encoding. Then, the PCS layer transmits the m-lane first data streams to the PMA layer through the m output lanes, and transmits the m-lane seventh data stream to the PMA layer through the m first output lanes. Thus, after receiving the m-lane first data streams transmitted by the PCS layer through the m input lanes, the PMA layer performs a demultiplexing process on the m-lane first data streams based on the second ratio to obtain z-lane second data streams. For details, please refer to FIG. 4A for understanding. The details will not be described again here. Furthermore, after receiving the m-lane seventh data streams through the m first input lanes, the PMA layer also performs a demultiplexing process on the m-lane seventh data stream based on the second ratio to obtain z-lane second data streams. zThe PMA layer may then perform a multiplexing process on the second data streams of the z lanes and the eighth data stream of the z lanes to obtain the second data streams of the z lanes obtained through the multiplexing process.

[0101] For example, Figure 4F is another schematic diagram of data stream transmission according to an embodiment of the present application. From Figure 4F, based on the structure shown in Figure 4A, it can be seen that in the PMA layer, a second demultiplexing process is first performed on the seventh data stream of m lanes based on a second ratio to obtain an eighth data stream of z lanes. Then, in the inner code sublayer of the PMA layer, a second multiplexing process is performed on the second data stream of z lanes and the eighth data stream of z lanes to obtain the second data stream of z lanes obtained through the multiplexing process. For example, z=16. The second data streams of the 16 lanes are denoted by F1, F2, ... and F 16 and the eighth data stream of 16 lanes is represented as W1, W2, ... and W 16 The second multiplexing process may be performed on the second data stream F1 and the eighth data stream W1 to obtain a second data stream of one lane obtained through the process. Similarly, the second multiplexing process may also be performed on the second data stream F2 and the eighth data stream W2 to obtain a second data stream of another lane obtained through the process. By analogy, a second data stream of 16 lanes may be obtained through the multiplexing process. Then, an inner code encoding process is performed on the second data streams of z lanes obtained through the multiplexing process. For details, please refer to the content described in the following step 303 for understanding. Details will not be described here.

[0102] In some possible examples, after performing a multiplexing process on the second data streams of z lanes and the eighth data stream of z lanes to obtain the second data streams of z lanes obtained through the multiplexing process, the encoding method includes separately performing Q-stage processing on each of the second data streams of z lanes obtained through the multiplexing process to obtain a twelfth data stream of z lanes, where each stage of processing in the Q-stage processing includes performing a round-robin distribution process on the data stream obtained in the previous stage to obtain data substreams of at least two lanes, performing a delay process on the fifth data substream to obtain a thirteenth data stream, and performing a sixth data substream to obtain a thirteenth data stream. performing a multiplexing process on the twelfth data stream and the thirteenth data stream to obtain an output data stream obtained through the current-stage processing, wherein the fifth data substream is at least one of the data substreams of at least two lanes, the sixth data substream is a data substream of one lane within the data substreams of the at least two lanes and on which a delay process is not performed, Q is a positive integer, and the second data stream obtained through the multiplexing process is a data stream obtained through the Q-stage processing; and separately performing an encoding process on each of the twelfth data streams of z lanes to obtain a third data stream of z lanes.

[0103] It should be noted that the Q-stage processing is performed separately for each of the z lanes of second data streams obtained through the multiplexing process. The specific process of the Q-stage processing can be understood by referring to the content described in (2). The details will not be described again here. Furthermore, the encoding process is performed separately for each of the z lanes of twelfth data streams. For details, please refer to the content described in the following step 303 for understanding. The details will not be described here.

[0104] The bit length of the thirteenth data stream is at least (N × codeword length of RS codeword) / (z × i) bits, where N is a positive integer and i is the number of data substreams. For details, please refer to the sixth data stream described in (2) for understanding. The details will not be described again here.

[0105] It should be noted that the acquired second data stream of z lanes may be understood as a data stream on which no processing such as data alignment, deskew, or rearrangement is performed. In this embodiment of the present application, in actual application, the first data stream of m lanes may be processed in other manners in addition to any of the manners in (1) to (3) above to acquire the second data stream of z lanes, which is not limited here.

[0106] 303: Separately perform an encoding process on each of the z lanes of the second data stream to obtain z lanes of the third data stream.

[0107] In this example, C inner code sublayers are instantiated in the PMA layer based on an integer multiple of the number of physical coding sublayer lanes, i.e., C is an integer multiple of B. In this way, after the second data streams of z lanes are obtained in the PMA layer, for the second data streams of each lane, a one-to-one correspondence may be formed between each of the C / z inner code sublayers and the second data stream of one lane, and an inner code encoding process is performed on the corresponding second data stream by separately using the C / z inner code sublayers to generate a corresponding data stream obtained through the inner code encoding process, i.e., a third data stream.

[0108] It should be understood that obtaining the third data streams of z lanes through the inner code encoding process may alternatively be understood as the data streams of each lane obtained through the encoding process including FEC code words. In some possible examples, the inner code sublayer in this application may also be referred to as an inner-forward error correction (Inner-FEC) coding sublayer. In actual applications, other names may alternatively be used. This is not particularly limited in this application. Furthermore, the inner code encoding process may be understood as a second code in a concatenated code, which is composed of the inner code encoding process described in step 301 and RS coding.

[0109] For example, a second data stream of 16 lanes obtained through processing, namely F1, F2, ... and F 16 If there are 16 inner code encoding operations, namely H1, H2, ... and H 16 are separately performed in the inner code sublayer of the PMA layer. Next, an inner code encoding process is performed on the data stream F1 through an inner code encoding process operation H1, an inner code encoding process is performed on the data stream F2 through an inner code encoding process operation H2, and so on. 16 Data stream through F 16 In some other examples, 32 inner code encoding operations, namely, H1, H2, H3, H4, ..., H 31 and H 32 Alternatively, the inner code encoding process may be performed separately in the inner code sublayer. Furthermore, the inner code encoding process is performed on the data stream F1 through two inner code encoding process operations H1 and H2, and the inner code encoding process is performed on the data stream F2 through two inner code encoding process operations H3 and H4, and by analogy, the two inner code encoding process operations H 31 and H 32 Data stream through F 16It should be noted that 16 inner code encoding processing operations and 32 inner code encoding processing operations are used merely as an example for the purpose of explanation here. In actual application, for 16 lanes of second data streams, 64 inner code encoding processing operations may alternatively be performed in the inner code sublayer, and the inner code encoding processing may be performed for each lane of the second data stream through four different inner code encoding processing operations. Alternatively, 128 inner code encoding processing operations, etc. may be performed, provided that C is an integer multiple of z. This is not limited here.

[0110] Alternatively, a second data stream of 32 lanes, namely F1, F2, ..., F, is obtained through processing. 16 , ..., F 31 and F 32 If there are 32 inner code encoding operations, namely H1, H2, ... and H 32 are separately performed in the inner code sublayer of the PMA layer. Next, an inner code encoding process is performed on the data stream F1 through an inner code encoding process operation H1, an inner code encoding process is performed on the data stream F2 through an inner code encoding process operation H2, and so on. 16 Data stream through F 16 The inner code encoding process is performed on..., and by analogy, the inner code encoding process operation H 32 Data stream through F 32 In some other examples, 64 inner code encoding operations, namely, H1, H2, H3, H4, ..., H 63 and H 64 Alternatively, the inner code sublayer may be implemented. Encoding process operation The data stream F1 is subjected to inner coding through H1 and H2, and the data stream F2 is subjected to inner coding through two inner coding operations H3 and H4. 63 and H64 Data stream through F 16 An inner code encoding process is performed on each lane of the second data stream. It should be noted that 32 inner code encoding process operations and 64 inner code encoding process operations performed in the inner code sublayer are used merely as an example for the purpose of explanation here. In actual applications, for the 32 lanes of the second data stream, 128 inner code encoding process operations may alternatively be performed, and the inner code encoding process is performed on each lane of the second data stream through four different inner code encoding process operations, etc. This is not limited here.

[0111] It should be noted that the above uses the 16-lane second data stream and the 32-lane second data stream as examples for illustration only. In practical applications, z may alternatively have other values, and the value of z depends on requirements, which is not limited here.

[0112] In some possible examples, the inner code encoding process may be actually understood as performing inner code encoding on the data block to be encoded in the second data stream, so that the inner code encoding may be performed in different ways in different scenarios, allowing the decoding sublayer to directly determine the boundary position of each codeword in the subsequent decoding process, in order to improve decoding accuracy. For example, the following two ways are referred to for understanding:

[0113] (1) An encoding process is performed on a first data block to obtain one or more FEC code words, the first data block being at least C / z consecutive data blocks to be encoded in a corresponding second data stream, where C is a positive integer and C is an integer multiple of z, a first identifier is inserted at a code word boundary position of any one of the FEC code words, the first identifier identifies a code word boundary of the FEC code word, and the throughput or baud rate of the FEC code word obtained through the insertion of the first identifier is an integer multiple of a reference clock.

[0114] In this example, a first data block may be understood as being at least C / z consecutive data blocks to be encoded in the corresponding second data stream, or as being composed of at least C / z consecutive data blocks to be encoded. Furthermore, the length of the first data block is the sum of the lengths of the at least C / z consecutive data blocks to be encoded. For example, the second data stream for each lane may be composed of I1, I2, ... and I Y The data blocks I1, I2, ... and I Y If the length of I is k, then when the first data block is I1, the length of the first data block is correspondingly k. Similarly, when the first data block is composed of I1 and I2, the length of the first data block is correspondingly 2k. The above is for the sake of illustration only, assuming I1, I2, ... and I Y It should be noted that the example uses the case where all of the lengths of k. In actual applications, the lengths of all data blocks to be encoded may alternatively be different, which is not limited here.

[0115] Furthermore, the number of FEC code words obtained is related to the number of data blocks to be encoded that the first data block constitutes.

[0116] For example, the second data stream of 16 lanes obtained through processing, namely F1, F2, ... and F16 If there is a second data stream F1 of the lane, then I1, I2, ... and I Y In this case, there are 16 inner code encoding process operations, namely, H1, H2, ... and H 16 are performed separately in the inner coding sublayer, the first data block is divided into Y data blocks to be coded I1, I2, ... and I Y , may be understood as one of the inner code encoding process operations. In this way, when each inner code encoding process operation is performed, the inner code encoding process may be performed on one of the first data blocks to obtain a corresponding FEC codeword. In this case, one FEC codeword is obtained through the inner code encoding process operation. For example, FIG. 5A is a schematic diagram of performing an inner code encoding process operation according to an embodiment of the present application. From FIG. 5A, it can be seen that by performing an inner code encoding process operation H1, an inner code encoding process may be performed on a data block I1 (e.g., k bits) to be encoded in the second data stream F1, and in this case, one FEC codeword (e.g., FEC codeword 1) may be obtained; by performing an inner code encoding process operation H2, an inner code encoding process may be performed on a data block I2 to be encoded in the second data stream F2, and in this case, one FEC codeword may be obtained; and by analogy, the inner code encoding process operations H 16 The second data stream F 16 Data block I to be coded 16It can be seen that an inner code encoding process may be performed on the data block I1 to be encoded by performing an inner code encoding process operation H1, and in this case, one FEC code word may be obtained. It should be noted that in this application, an example in which the inner code encoding process is performed on the data block I1 to be encoded by performing an inner code encoding process operation H1 is used for explanation purposes only. In actual application, the inner code encoding process may alternatively be performed on the data block I2 or I3 to be encoded by performing an inner code encoding process operation H1. This is not limited here. Furthermore, other inner code encoding process operations may also be understood with reference to the inner code encoding process operation H1. Details will not be described again here. Furthermore, other second data streams F2, ... and F 16 can also be understood with reference to the second data stream F1 in practice, and the details will not be explained again here.

[0117] Alternatively, there is still a 16-lane second data stream obtained through processing, but in this case, if 32 inner code encoding processing operations are performed in the inner code sublayer, the first data block is divided into Y data blocks to be encoded I1, I2, ... and I Y, may be understood as at least two consecutive data blocks to be coded in the second data stream F1. For example, the first data block may be composed of I1 and I2, or may be composed of I3 and I4. This is not limited here. For example, FIG. 5B is another schematic diagram of performing an inner code coding process according to an embodiment of the present application. From FIG. 5B, it can be seen that by performing inner code coding process operations H1 and H2, an inner code coding process may be performed on a first data block (e.g., k+k bits) composed of I1 and I2 in the second data stream F1, and in this case, two FEC codewords (e.g., FEC codeword 1 and FEC codeword 2) may be obtained; by performing inner code coding process operations H3 and H4, an inner code coding process may be performed on a first data block composed of I3 and I4 in the second data stream F2, and in this case, two FEC codewords may be obtained; and by analogy, the inner code coding process operations H 31 and H 32 The second data stream F 16 I in 31 and I 32 It can be seen that the inner code encoding process may be performed on the first data block consisting of I1 and I2, and in this case, two FEC code words may be obtained. It should be noted that in this application, an example in which the inner code encoding process is performed by performing inner code encoding process operations H1 and H2 on the first data block consisting of I1 and I2 is used for explanation purposes only. In actual application, the inner code encoding process may alternatively be performed on the first data block consisting of I3 and I4 in the second data stream F1, or on I5 in the second data stream F2. 31 and I 32 This may be performed by performing inner code encoding process operations H1 and H2 on the first data block consisting of the first data stream F1, ... and F2. This is not limited here. Furthermore, other inner code encoding processes may also be understood with reference to the inner code encoding process operations H1 and H2. Details will not be described again here. Furthermore, other second data streams F2, ... and F 16can also be understood with reference to the second data stream F1 in practice, and the details will not be explained again here.

[0118] Alternatively, if there is still a 16-lane second data stream obtained through processing, 64 inner code encoding processing operations may alternatively be performed in the inner code sublayer, in which case the first data block is divided into Y data blocks I1, I2, ... and I Y For example, the first data block may be composed of I1, I2, I3, and I4, or may be composed of I5, I6, I7, and I8. This is not limited here. In this case, by performing the inner code encoding process operations H1 to H4, an inner code encoding process may be performed on the first data block (e.g., k+k+k+k bits) composed of I1, I2, I3, and I4 in the second data stream F1, and in this case, four FEC codewords may be obtained. By performing the inner code encoding process operations H5 to H8, an inner code encoding process may be performed on the first data block composed of I5, I6, I7, and I8 in the second data stream F2, and in this case, four FEC codewords may be obtained. ...By analogy, the inner code encoding process operations H 61 ~H 64 The second data stream F 16 I in 61 , I 62 , I 63 and I 64In this case, four FEC code words may be obtained. It should be noted that in this application, an example in which the inner code encoding process is performed by performing inner code encoding process operations H1 to H4 on the first data block consisting of I1, I2, I3, and I4 in the second data stream F1 is used for explanation purposes only. In actual application, the inner code encoding process may alternatively be performed on the first data block consisting of I5, I6, I7, and I8 in the second data stream F1, or on I 61 , I 62 , I 63 and I 64 This may be performed by performing inner code encoding process operations H1 to H4 on the first data block consisting of the first data stream F1, ... and F2. This is not limited here. Furthermore, other inner code encoding process operations may also be understood with reference to the inner code encoding process operations H1 and H4. Details will not be described again here. Furthermore, other second data streams F2, ... and F3 may be performed by performing inner code encoding process operations H1 to H4 on the first data block consisting of the first data stream F3, ... and F4. 16 can also be understood with reference to the second data stream F1 in practice, and the details will not be explained again here.

[0119] z It should be noted that =16 is used merely as an example above. In actual applications, there may alternatively be a 32-lane second data stream, a 64-lane second data stream, etc. For details, please refer to the contents of the above 16 second data streams for understanding. The details will not be described again here.

[0120] In this way, after the FEC codewords are obtained, the first identifier may further be inserted at the codeword boundary of one of the FEC codewords. For example, as shown in FIG. 5A, the first identifier may be inserted at the codeword boundary of an FEC codeword (e.g., FEC codeword 1) obtained by performing inner code encoding process operation H1. Alternatively, as shown in FIG. 5B, the first identifier may be inserted at the codeword boundary of one of two FEC codewords (e.g., FEC codeword 1 and FEC codeword 2) obtained by performing inner code encoding process operations H1 and H2. For example, the first identifier may be inserted at the codeword boundary of FEC codeword 1, or the first identifier may be inserted at the codeword boundary of FEC codeword 2. This is not limited here. It should be noted that inserting a first identifier at the codeword boundary of one of the FEC codewords may alternatively be understood as inserting one first identifier at an interval of C / z FEC codewords.

[0121] It should be noted that the throughput or baud rate of the FEC codeword obtained through the insertion of the first identifier is an integer multiple of the reference clock. For example, when the data transmission rate is expressed in terms of throughput, assuming that the throughput of the data stream in the PCS layer is 850 Gbps, the throughput of the FEC codeword obtained through the insertion of the first identifier may be 910 Gbps. Alternatively, when the data transmission rate is expressed in terms of baud rate, the baud rate of each physical coding sublayer lane in the PCS layer is 26.5625 Gbaud. After the inner code encoding process is performed, the total length of the obtained FEC codeword is 180 bits. After the first identifier is inserted, the total length of the entire FEC codeword obtained through the insertion of the first identifier may change to 182 bits. In this case, the baud rate of the corresponding physical coding sublayer lane changes to 28.4375 Gbaud. As another example, assuming that the throughput of the data stream in the PCS layer is 850 Gbps, the throughput of the FEC codeword obtained through the insertion of the first identifier may be 900 Gbps. Alternatively, when the data transmission rate is expressed in baud rate, the baud rate of each physical coding sublayer lane in the PCS layer is 26.5625 Gbaud. After the inner code encoding process is performed, the total length of the obtained FEC codeword is 179 bits. After the first identifier is inserted, the total length of the entire FEC codeword obtained through the insertion of the first identifier may change to 180 bits. In this case, the baud rate of the corresponding physical coding sublayer lane changes to 28.125 Gbaud.

[0122] Here, the example of a throughput of 850 Gbps and the example of a baud rate of 26.5625 Gbaud are used for explanation purposes only. In practical applications, the transmission rate of the data stream in the PCS layer should be related to the load of the RS codeword. Furthermore, here, the examples of the throughput of the FEC codeword obtained through the insertion of the first identifier of 910 Gbps and 900 Gbps are used for explanation purposes only, and the baud rate of the physical coding sublayer lane is 28.4375 The examples of varying from 1 Gbaud to 28.125 Gbaud are used for explanation purposes only, which is not particularly limited in this application. The reference clock may be understood as 156.25 megahertz (MHz), or may be other values in actual applications, which is not limited here.

[0123] The reference clock mentioned above indicates the data stream transmission frequency, i.e., the number of transmissions that can be performed per second. Both the baud rate and the throughput may represent the data stream transmission rate. The throughput represents the number of bits transmitted per second, and the baud rate represents the number of symbols transmitted per second. For example, five symbols may be transmitted each time, or ten transmissions may be performed per second. In this case, a total of 50 symbols may be transmitted per second.

[0124] Furthermore, the location of the codeword boundary may be understood as a codeword start and / or a codeword end, which is not limited here. The codeword boundaries of the FEC codewords are identified by a first identifier, so that the boundary location of each FEC codeword can be determined by directly identifying the first identifier in the subsequent decoding process, avoiding the case where inner code decoding is invalid in the case of delay skew and unknown data start position.

[0125] It should be understood that the above first identifier may be a preset identifier sequence, or may be obtained based on the bit value of the first data block. The following examples are provided for separate explanation.

[0126] (1) The first identifier is a preset identifier sequence.

[0127] In this example, the first identifier may be a sequence of "1" and "0" or may be any other known sequence. This is not limited here. For example, FIG. 6A is a schematic diagram of inserting a first identifier according to an embodiment of this application. As shown in FIG. 6A, the first identifier, i.e., a sequence of "1" and "0", is added to the FEC codeword at the codeword start position, and the first identifier occupies 2 bits. Therefore, after the first identifier is added to the FEC codeword at the codeword boundary position, the total length of the codeword changes from n bits to n+2 bits. For example, if the length of the first data block is 170 bits, the total length of the FEC codeword is 180 bits after the inner code encoding process is performed. After the first identifier is inserted, the length of the entire FEC codeword obtained through the insertion of the first identifier changes to 182 bits.

[0128] It should be noted that when the first identifier is a preset identifier sequence, a sequence such as "101010" or "1010" may alternatively be selected as the first identifier, which is not limited here.

[0129] (2) A first identifier is obtained based on bit values of the first data block.

[0130] In this example, different first identifiers may be alternatively obtained for different bit values in the first data block. Specifically, the following two methods may be used for determination:

[0131] Scheme 1: The first identifier is obtained based on the value of a first bit in the first data block. Note that the first bit is any one of at least one bit in the first data block.

[0132] For example, FIG. 6B is a schematic diagram of a value assignment scheme for a first identifier according to an embodiment of this application. It can be seen from FIG. 6B that the first bit may be the 0th bit in the first data block. If the value of the 0th bit is "0", the first identifier, i.e., "1", may be obtained by directly performing a negation operation on the value of the 0th bit. Alternatively, if the value of the 0th bit is "1", the first identifier, i.e., "0", may be obtained by directly performing a negation operation on the value of the 0th bit. This is not particularly limited herein. Furthermore, in FIG. 6B, the example in which the 0th bit is the first bit is used merely for explanation. In actual application, the first bit may alternatively be the 1st bit, the 2nd bit, etc. in the first data block. This is not particularly limited herein. For example, the length of the first data block is 180 bits. The last bit may be selected for negation. That is, the value of the 179th bit is selected to directly perform a negation operation to obtain the first identifier. The first identifier is obtained by performing a negation operation on the bits at the beginning or end of the first data block, which helps the PMA layer at the receiving end to quickly determine the codeword boundary.

[0133] Scheme 2: The first identifier is obtained based on bit values of at least L second bits in the first data block, and there is an interval of s bits between every two adjacent second bits among the L second bits, where L≧2 and s≧0, and L and s are integers.

[0134] In this example, one second bit is selected at intervals of s bits in the first data block, for a total of L second bits, which may be processed through an exclusive OR operation, an OR operation, or an AND operation to obtain the first identifier.

[0135] For example, Figure 6C is a schematic diagram of another value assignment scheme for the first identifier according to an embodiment of the present application. From Figure 6C, it can be seen that when L = 4 and s = 2, the four second bits selected from the first data block are the 0th bit, the 2nd bit, the 4th bit, and the 6th bit. In this way, the bit values corresponding to the 0th bit, the 2nd bit, the 4th bit, and the 6th bit may be processed through an exclusive OR operation, and the processing result may be used as the first identifier. It should be noted that in some examples, the four selected second bits may alternatively be the 1st bit, the 3rd bit, the 5th bit, the 7th bit, etc. This is not limited here.

[0136] It should be noted that the example in which L is 4 and s is 2 is used merely for the purpose of explanation in Figure 6C. In actual applications, L may alternatively be 8 and s is 3, L is 6 and s is 4, etc. In this application, neither the value of L nor the value of s is limited.

[0137] Furthermore, in practical applications, the first identifier may be determined in other ways in addition to the above (1) and (2), which is not particularly limited in this application.

[0138] The above (1) mainly describes a solution in which the inner code encoding is first performed on the first data block, and then the first identifier is inserted. Below, we will explain a solution in which the first identifier also participates in the inner code encoding. The details are as follows:

[0139] (2) A first identifier is inserted into each encoding target data block in the first data block to obtain a second data block, where the first data block is C / z consecutive encoding target data blocks, where C is a positive integer and C is an integer multiple of z, and an inner code encoding process is performed on the second data block to obtain an FEC code word. It should be noted that the throughput or baud rate of the FEC code word is an integer multiple of the reference clock.

[0140] In this example, the second data block may be understood as being composed of the first data block and the first identifier, and the length of the second data block is the sum of the length of the first data block and the number of bits occupied by the first identifier. In this way, the first identifier is inserted into each data block to be encoded within the first data block. For example, when the first data block shown in FIG. 5B is composed of data blocks I1 and I2 to be encoded, the first identifier may be inserted at the position of the codeword boundary of the data block I1 to be encoded, and the first identifier may be inserted at the position of the codeword boundary of the data block I2 to be encoded. If the length of the first data block is k (i.e., the first data block occupies k bits) and the first identifier occupies 1 bit, the length of the second data block is k+2 bits.

[0141] An inner code encoding process may be performed on a second data block in the second data stream of each lane. For ease of understanding, refer to the process of performing the inner code encoding process on the first data block in (1). Details will not be described again here. Furthermore, the first data block may be understood by referring to the contents of (1). Details will not be described again here. Furthermore, the first identifier may alternatively be understood by referring to the contents described in (1) and (2). Details will not be described again here.

[0142] In some other possible examples, the encoding method may further include identifying an alignment marker in the second data stream of the lane, the alignment marker identifying a symbol boundary in the corresponding second data stream, and determining the symbol boundary in the corresponding second data stream based on the alignment marker.

[0143] In this example, at the PCS layer, a common alignment marker for the AM alignment block is added to each of the m first data streams of lanes. After the m first data streams of lanes are mapped to obtain z second data streams of lanes, the second data stream for each lane includes a corresponding alignment marker, and the symbol boundaries within the second data stream for each lane are identified by the alignment marker. Therefore, at the PMA layer, after the m first data streams of lanes are processed in any one of the possible manners shown in FIGS. 4A to 4F to obtain z second data streams of lanes, the alignment marker included in the second data stream for each lane may be further identified. After the corresponding alignment marker is identified, the alignment marker is locked, thereby enabling the symbol boundaries within the corresponding second data stream to be determined. For example, a 120-bit known sequence AM alignment block is added to the first data stream for each lane, and a 48-bit common alignment marker exists within the 120-bit known sequence AM alignment block. In this case, locking and alignment may be achieved provided that a 48-bit common alignment marker is identified for operation at the symbol boundaries of the RS codeword.

[0144] Then, the inner code encoding process is separately performed on the second data streams of the z lanes. For details, please refer to the content described in step 303 for understanding. The details will not be described again here.

[0145] For example, Fig. 7 is another schematic diagram of data stream transmission according to an embodiment of the present application. As shown in Fig. 7, based on the embodiment described in any one of Fig. 4A to Fig. 4F, in the inner code sublayer of the PMA layer, an alignment process may be performed separately on the second data streams of the z lanes, and then an inner code encoding process is performed separately.

[0146] 304: Perform a multiplexing process on the third data stream of z lanes to obtain a fourth data stream of n lanes, where n is a positive integer.

[0147] In this example, after the third data stream with z lanes is obtained in the PMA layer, if the PMA layer wants to send the third data stream with z lanes to the receiving end through n output lanes, the PMA layer still needs to perform multiplexing processing on the third data stream with z lanes to obtain a fourth data stream with n lanes, and then transmit the fourth data stream with n lanes to the PMA layer at the receiving end through n output lanes.

[0148] For example, the PMA layer multiplexes the third data streams of z lanes based on a third ratio (i.e., z / n) to obtain a fourth data stream of n lanes. Alternatively, the PMA layer may first multiplex the third data streams of z lanes based on a fourth ratio (i.e., z / m) to obtain a data stream of m lanes, and then perform a multiplexing process on the data streams of m lanes based on a fifth ratio (i.e., m / n) to obtain a fourth data stream of n lanes. The specific manner is not limited in this application. It should be noted that the value of n may be 4, 8, 16, etc., which is not limited here.

[0149] For example, Figure 8 is a schematic diagram of the overall transmission of data streams in the PMA layer. As shown in Figure 8, m-lane first data streams are obtained through m input lanes, and a first demultiplexing process is performed on the m-lane first data streams based on a ratio of m / z to obtain z-lane PCS lane data streams, i.e., z-lane second data streams. Then, C inner code encoding process operations are performed in the inner code sublayer to separately perform encoding processes on the z-lane PCS lane data streams to obtain z-lane third data streams, and the inner code encoding process of each lane's PCS lane data stream is realized through C / z inner code encoding process operations. Then, a multiplexing process is performed on the z-lane third data streams based on z / n to obtain n-lane fourth data streams, and the n-lane fourth data streams are transmitted through n output lanes.

[0150] 3 to 8 mainly describe the encoding method provided in the embodiment of this application. The decoding method provided in the embodiment of this application will be described below. FIG. 9 is a schematic flowchart of the decoding method according to the embodiment of this application. As shown in FIG. 9, the decoding method may include the following steps:

[0151] 901: Obtain a fourth data stream of n lanes through n input lanes.

[0152] In this example, after obtaining the n-lane fourth data stream, the PMA layer at the transmitting end may transmit the n-lane fourth data stream to the PMD layer. After the PMD layer performs processing such as optical-to-electrical conversion on the n-lane fourth data stream, the signal may be transmitted to the PMD layer at the receiving end by using a transmission medium, etc. Then, at the receiving end, the PMD layer may perform conversion processing on the signal received from the transmission medium to obtain the n-lane fourth data stream. Then, the PMD layer may transmit the n-lane fourth data stream to the PMA layer at the receiving end through n output lanes. In this way, the PMA layer may obtain the n-lane fourth data stream through n input lanes.

[0153] 902: Perform a demultiplexing process on the fourth data stream of n lanes to obtain a third data stream of z lanes.

[0154] After the n-lane fourth data streams are obtained in the PMA layer, a demultiplexing process may be performed on the n-lane fourth data streams based on the inverse of the third ratio to obtain z-lane third data streams. The third ratio can be understood with reference to step 304 in FIG. 3. The details will not be described again here.

[0155] 903: Separately perform a decoding process on each of the third data streams of the z lanes to obtain second data streams of the z lanes.

[0156] In this example, the decoding procedure is the reverse process of the encoding procedure in Fig. 3. C inner code decoding processing operations may also be performed in the inner code sublayer to separately perform inner code decoding processing for one lane of the third data stream by performing C / z different inner code decoding processing operations for the z lanes of the third data stream.

[0157] In some other possible examples, the decoding method may further include identifying a codeword boundary of the FEC codeword obtained through encoding based on the first identifier and / or a decoding flag bit, where the decoding flag bit indicates whether the inner code decoding process was successful or not.

[0158] The third data streams of the z lanes each include a corresponding first identifier. In a process of decoding the corresponding third data stream, the location of a codeword boundary of the FEC codeword in the third data stream of each lane may be known by identifying the first identifier and / or a decoding flag bit, thereby further improving decoding efficiency and decoding accuracy. For example, when identifying that each identifier value in the first identifier is correct, the PMA layer may further determine whether the inner code decoding process is successful by using the decoding flag bit. When the decoding flag bit indicates that the inner code decoding process is successful, the PMA layer identifies a codeword boundary of the FEC codeword based on the first identifier, and thereby performs a decoding process on the FEC codeword obtained through encoding.

[0159] It should be noted that identifying the codeword boundary of the FEC codeword obtained through encoding based on the first identifier and / or the decoding flag bit may be understood in three cases. Specifically, (1) the codeword boundary of the FEC codeword obtained through encoding may be identified based on the first identifier, (2) the codeword boundary of the FEC codeword obtained through encoding may be identified based on the decoding flag bit, or (3) the codeword boundary of the FEC codeword obtained through encoding may be identified based on the first identifier and the decoding flag bit. The specific manner is not limited in this application. Furthermore, the decoding flag bit may or may not be fed back in the decoding process, which is not limited here.

[0160] 904: Perform a multiplexing process on the second data streams of z lanes based on a first ratio to obtain first data streams of m lanes.

[0161] In this example, after obtaining the second data streams of z lanes, the PMA layer performs a multiplexing process on the second data streams of z lanes based on a first ratio to obtain the first data streams of m lanes. For example, when z=16, the first ratio may be 16:4, and the first data streams of four lanes are obtained through the multiplexing process.

[0162] 10A is a schematic diagram of the transmission of data streams in a decoding process according to an embodiment of this application. From FIG. 10A, it can be seen that first, a demultiplexing process is performed on the fourth data stream of n lanes to obtain a third data stream of z lanes. Then, in the inner code sublayer, an inner code decoding process is separately performed on the third data stream of z lanes to obtain a second data stream of z lanes. Finally, the second data stream of z lanes is processed.

[0163] In some other optional examples, the electrical signal is obtained through optical-to-electrical conversion in the PMD layer, and the data and clock recovery operations need to be first performed on the electrical signal by the CDR unit. The shorter the time required for the CDR unit to recover the clock and data, the better for the system. Based on this, the decoding method may further include generating a first signal based on the first identifier and / or the decoding flag bit before identifying the codeword boundary of the FEC codeword based on the first identifier and / or the decoding flag bit, where the first signal is for determining the data and clock information.

[0164] 10B is another schematic diagram of the transmission of data streams in the decoding process according to an embodiment of this application. From FIG. 10B, it can be seen that, based on FIG. 10A, a clock and data recovery process is first performed on the fourth data stream of n lanes before the third data stream of z lanes is obtained through a demultiplexing process. Then, a demultiplexing process is performed on the fourth data stream of n lanes obtained through the clock and data recovery process to obtain the third data stream of z lanes, and then an inner code decoding process is separately performed on the third data stream of z lanes. The CDR unit Reception It should be noted that each input lane uniquely corresponds to a data stream to be transmitted. Furthermore, there is a unique correspondence between each input lane and a physical coding sublayer lane, and each physical coding sublayer lane corresponds to C / z inner code decoding processing operations. Therefore, the decoding units connected to each CDR unit may also be fixed, and the decoding units and CDR units may be connected through connecting lines. For example, there are four input lanes in the PMD layer and 16 physical coding sublayer lanes in the PMA layer. If 32 inner code decoding processing operations may be performed in the inner code sublayer, each physical coding sublayer lane is connected to two corresponding decoding units. In the process of recovering the data and clock by the CDR unit, the inner code sublayer may first detect the first identifier and / or the decoding flag bit to generate a feedback signal, i.e., a first signal. In this case, when the CDR unit receives the first signal, the process of recovering the data and clock by the CDR unit may be accelerated, and the data and clock information is predetermined, thereby reducing the time required for system lock. Furthermore, in designing the generation method of the sequence corresponding to the first identifier in this application, the autocorrelation characteristics of the sequence corresponding to the first identifier are taken into consideration, which helps the first identifier to be detected more quickly, and the fixed 0-1 transition characteristics of the first identifier are taken into consideration, which helps the convergence speed of the data and clock recovery of the CDR unit.

[0165] Furthermore, if the CDR unit first receives a signal fed back by the CDR unit and for successfully restoring the data and clock before receiving the first signal, the CDR unit may enter a locked state based on the signal for successfully restoring the data and clock and complete the data and clock recovery operation.

[0166] In some other examples, after obtaining the m-lane first data streams, the PMA layer may alternatively transmit the m-lane first data streams to the PCS layer through m output lanes. Thus, after obtaining the m-lane first data streams through m input lanes, the PCS layer performs a demultiplexing process on the m-lane first data streams based on the second ratio to obtain an eleventh data stream with z lanes. It should be noted that the z-lane eleventh data streams correspond to the z-lane data streams obtained through the RS encoding process. The PCS layer may further sequentially perform an RS decoding process, a 256B / 257B transcoding process, and a 64B / 66B encoding process on the z-lane eleventh data stream. For details, please refer to FIG. 1A for understanding.

[0167] 1A and 1B, in this embodiment of the present application, an inner code encoding process is performed separately for each of the second data streams of z lanes in the PMA layer to obtain a third data stream of z lanes, and the FEC codeword in each third data stream obtained through encoding includes a boundary identifier. This ensures that the inner code encoding is separated from the data obtained through encoding in the upper PCS layer and from transmission in the lower PMD layer, reducing delay skew and out-of-order processing delay, thereby making the inner code encoding and decoding in this application applicable to scenarios sensitive to transmission delay. Furthermore, provided that the boundary identifier in the third data stream of a lane is identified, the codeword boundary of the third data stream of each lane can be determined, thereby allowing the inner code decoding process to be performed separately for each of the third data streams of z lanes without performing operations such as deskewing and reordering on the data streams, reducing operational complexity and delay.

[0168] The above mainly describes the solutions provided in the embodiments of this application from the perspective of methods. It can be understood that to realize the above functions, the PMA layer includes corresponding hardware structures and / or software modules for performing each function. Those skilled in the art should easily recognize that, in combination with the functions described in the embodiments disclosed in this specification, this application can be realized by hardware or a combination of hardware and computer software. Whether a function is performed by hardware or by hardware driven by computer software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to realize functions for each specific application, but the implementation method should not be considered to exceed the scope of this application.

[0169] In terms of physical devices, specifically, the PMA layer may be realized by one physical device, such as an optical module or other encoding or decoding device, or may be realized jointly by multiple physical devices, or may be a logical function unit within one physical device, which is not particularly limited in the embodiments of this application.

[0170] For example, the PMA layer may be implemented by a communication device in Fig. 11. Fig. 11 is a schematic diagram of a hardware structure of a communication device according to an embodiment of the present application. The communication device includes at least one processor 1101, a memory 1102, and a transceiver 1103.

[0171] The processor 1101 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit, or one or more integrated circuits configured to control program execution of the solutions in this application. The processor 1101 may perform operations, such as determinations, analyses, and actions, including, for example, processing a first data stream of m lanes to obtain a second data stream of z lanes, separately performing an inner code encoding process on each of the second data streams to obtain a third data stream of z lanes, etc.

[0172] The transceiver 1103 may be any device, such as a transceiver, configured to communicate with a communication network, such as an Ethernet, a radio access network (RAN), or a wireless local area network (WLAN), or other devices. The transceiver 1103 may be coupled to the processor 1101. The transceiver 1103 may obtain the first data stream of the m lanes, etc.

[0173] Memory 1102 may be read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, or random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or may be, but is not limited to, electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other compact disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disc storage media or other magnetic storage devices, or any other medium capable of carrying or storing possible program code in the form of instructions or data structures and accessible by a computer. Memory 1102 may exist independently or may be connected to processor 1101. Memory 1102 may alternatively be integrated with processor 1101.

[0174] The memory 1102 is configured to store computer-executable instructions for executing the solutions in this application, and the execution is controlled by the processor 1101. The processor 1101 is configured to execute the computer-executable instructions stored in the memory 1102 to realize the encoding and decoding methods provided in the above method embodiments of this application.

[0175] In a possible implementation manner, the computer executable instructions in this embodiment of this application may also be referred to as application program code, which is not particularly limited in this embodiment of this application.

[0176] In a specific implementation, in an embodiment, the processor 1101 may include one or more CPUs, such as CPU0 and CPU1 in FIG.

[0177] In terms of functional units, in this application, the PMA layer may be divided into functional units based on the above method embodiments. For example, each functional unit may be obtained through division based on its corresponding function, or two or more functions may be integrated into one functional unit. The integrated functional unit may be realized in the form of hardware or in the form of a software functional unit.

[0178] For example, when each functional unit is acquired through division in an integrated manner, Fig. 12 is a schematic diagram of the structure of an encoding device according to an embodiment of this application. As shown in Fig. 12, the embodiment of the encoding device in this application may include a first acquisition unit 1201 and a first processing unit 1202.

[0179] The first acquisition unit 1201 is configured to acquire m lanes of first data streams through m input lanes, where m is a positive integer. For details, please refer to the content of step 301 in Figure 3 for understanding. The details will not be described again here.

[0180] The first processing unit 1202 is configured to process the first data stream of m lanes to obtain the second data stream of z lanes, separately perform an encoding process on each of the second data streams of z lanes to obtain the third data stream of z lanes, and perform a multiplexing process on the third data stream of z lanes to obtain the fourth data stream of n lanes, where n and z are both positive integers. For details, please refer to the contents of steps 302 to 304 in Figure 3 for understanding. The details will not be described again here.

[0181] In some possible implementations, each of the z second data streams includes a data block to be encoded, and the first processing unit 1202 is configured to perform an encoding process on the first data block to obtain one or more FEC code words, where the first data block is at least C / z consecutive data blocks to be encoded in the corresponding second data stream, where C is a positive integer and C is an integer multiple of z, and to insert a first identifier at a code word boundary position of any one of the FEC code words, where the first identifier identifies the code word boundary of the FEC code word, and the throughput or baud rate of the FEC code word obtained through the insertion of the first identifier is an integer multiple of the reference clock. For details, please refer to step 303 in FIG. 3 for understanding. The details will not be described again here.

[0182] In some other possible implementations, each of the second data streams of the z lanes includes a data block to be encoded, and the first processing unit 1202 is configured to insert a first identifier into each data block to be encoded in the first data block to obtain a second data block, where the first data block is C / z consecutive data blocks to be encoded, where C is a positive integer and C is an integer multiple of z, and to perform an encoding process on the second data block to obtain an FEC code word, where the throughput or baud rate of the FEC code word is an integer multiple of the reference clock. For details, please refer to the content of step 303 in Figure 3 for understanding. The details will not be described again here.

[0183] In some possible implementations, the first identifier is a preset identifier sequence. For details, please refer to the content of step 303 in Figure 3 for understanding. The details will not be described again here.

[0184] In some possible implementations, the first identifier is obtained based on the value of a first bit in the first data block, where the first bit is any one of at least one bit in the first data block, or the first identifier is obtained based on the bit values of at least L second bits in the first data block, where there is an interval of s bits between every two adjacent second bits among the L second bits, where L≧2 and s≧0, and L and s are integers. For details, please refer to the content of step 303 in Figure 3 for understanding. The details will not be described again here.

[0185] In some possible implementations, the first processing unit 1202 is configured to perform demultiplexing processing on the first data stream of m lanes based on a second ratio to obtain a second data stream of z lanes, where the second ratio is a ratio of m to z.

[0186] In some possible implementations, the first processing unit 1202 is configured to perform a demultiplexing process on the first data streams of m lanes based on a second ratio to obtain a fifth data stream of z lanes, and separately perform Q-stage processing on each of the fifth data streams of the z lanes to obtain a second data stream of z lanes, where each stage of processing in the Q-stage processing includes: performing a round-robin distributed processing on the data stream obtained in the previous stage to obtain data substreams of at least two lanes; performing a delay processing on the first data substream to obtain a sixth data stream; and performing a multiplexing process on the second data substream and the sixth data stream to obtain an output data stream obtained through the current-stage processing, where the first data substream is at least one of the data substreams of the at least two lanes, and the second data substream is a data substream of one lane that is within the data substreams of the at least two lanes and for which no delay processing is performed, where Q is a positive integer, and the second data stream is a data stream obtained through the Q-stage processing.

[0187] In some possible implementations, the bit length of the sixth data stream is at least (N×codeword length of RS codeword) / (z×i) bits, where N is a positive integer and i is the number of data substreams.

[0188] In some possible implementations, the first processing unit 1201 is further configured to obtain a seventh data stream of m lanes through m input lanes, and the first processing unit 1202 is configured to perform a demultiplexing process on the seventh data stream of m lanes based on a second ratio to obtain an eighth data stream of z lanes, and to perform a multiplexing process on the second data stream of z lanes and the eighth data stream of z lanes to obtain z second data streams obtained through the multiplexing process.

[0189] In some possible implementations, the first processing unit 1202 is further configured to identify an alignment marker in the second data stream of each lane, the alignment marker identifying a symbol boundary in the corresponding second data stream, and to determine the symbol boundary in the corresponding second data stream based on the alignment marker.

[0190] In some possible implementations, the first data streams of m lanes are obtained by performing a multiplexing process at a first ratio on the data streams of z lanes obtained through Reed-Solomon RS encoding.

[0191] The encoding device provided in this embodiment of the present application is configured to perform the encoding method in the method embodiment corresponding to Fig. 3. Therefore, this embodiment of the present application can be understood with reference to the relevant parts in the method embodiment corresponding to Fig. 3.

[0192] The above mainly describes the encoding device provided in the embodiment of this application from the viewpoint of functional modules. The following describes the decoding device provided in the embodiment of this application from the viewpoint of functional modules. Figure 13 is a schematic diagram of the structure of the decoding device according to the embodiment of this application. As shown in Figure 13, the embodiment of the decoding device in this application may include a second obtaining unit 1301 and a second processing unit 1302.

[0193] The second acquisition unit 1301 is configured to acquire a fourth data stream of n lanes through n input lanes. For details, please refer to the content of step 901 in Figure 9 for understanding. The details will not be described again here.

[0194] The second processing unit 1302 is configured to perform a demultiplexing process on the n-lane fourth data stream to obtain z-lane third data streams, separately perform a decoding process on each of the z-lane third data streams to obtain z-lane second data streams, and perform a multiplexing process on the z-lane second data streams based on a first ratio to obtain m-lane first data streams, where the first ratio and the second ratio are reciprocals of each other. For details, please refer to steps 902 to 904 in FIG. 9 for understanding. The details will not be described again here.

[0195] In some possible implementations, the third data stream of the z lanes includes a first identifier, which identifies a codeword boundary of the FEC codeword, and the second processing unit 1302 is further configured to identify the codeword boundary of the FEC codeword based on the first identifier and / or a decoding flag bit, and the decoding flag bit indicates whether the decoding process is successful or not.

[0196] In some other possible implementations, the second processing unit 1302 is further configured to generate a first signal based on the first identifier and / or the decoding flag bit before identifying the codeword boundary of the FEC codeword based on the first identifier and / or the decoding flag bit, where the first signal is for determining data and clock information. It should be noted that the first signal can be for determining the data and clock information, thereby accelerating the process of data and clock recovery by the CDR unit, allowing the data and clock information to be predetermined, reducing the time required for system lock, and facilitating the predetermined determination of the system transmission frequency. Furthermore, in designing a method for generating a sequence corresponding to the first identifier in this application, the autocorrelation characteristics of the sequence corresponding to the first identifier are taken into consideration, which helps the first identifier be detected more quickly, and the fixed 0-1 transition characteristics of the first identifier are taken into consideration, which helps the CDR unit to converge on the data and clock recovery. It should be noted that if the CDR unit first receives a signal fed back by the CDR unit and for successfully restoring the data and clock before receiving the first signal, the CDR unit may enter a locked state based on the signal for successfully restoring the data and clock and complete the data and clock recovery operation.

[0197] The decoding device provided in this embodiment of the present application is configured to perform the decoding method in the method embodiment corresponding to Figure 9. Therefore, this embodiment of the present application can be understood with reference to the relevant parts in the method embodiment corresponding to Figure 9.

[0198] In an embodiment of this application, the encoding device and the decoding device are each presented in the form of a functional unit obtained through division in an integrated form. A "functional unit" here may be an application-specific integrated circuit (ASIC), a processor and memory executing one or more software or firmware programs, an integrated logic circuit, and / or other components capable of providing the above functionality. In a simple embodiment, those skilled in the art will understand that the encoding device and the decoding device may be in the form shown in FIG. 11.

[0199] For example, processor 1101 in Figure 11 may invoke computer-executable instructions stored in memory 1102 to cause the encoding device to perform the encoding method performed by the PMA layer in the method embodiment corresponding to Figure 3. Processor 1101 in Figure 11 may invoke computer-executable instructions stored in memory 1102 to cause the decoding device to perform the decoding method performed by the PMA layer in the method embodiment corresponding to Figure 9.

[0200] Specifically, the functions / implementation processes of the first processing unit 1202 in Fig. 12 and the second processing unit 1302 in Fig. 13 may be realized by the processor 1101 in Fig. 11 calling computer-executable instructions stored in the memory 1102. The functions / implementation processes of the first acquisition unit 1201 in Fig. 12 and the second acquisition unit 1301 in Fig. 13 may be realized by using the transceiver 1103 in Fig. 11.

[0201] In the device in FIG. 11 of this application, communication connections are realized between components. Specifically, the processing unit (or processor), the storage unit (or memory), and the transceiver unit (transceiver) communicate with each other through internal connection paths to transfer control signals and / or data signals. The above method embodiments of this application may be applied to a processor, or the steps in the above method embodiments may be implemented by a processor. The processor may be an integrated circuit chip having signal processing capabilities. In the implementation process, the steps in the above method embodiments may be completed by using hardware integrated logic circuits in the processor or by using instructions in the form of software. The processor may be a central processing unit (CPU), a network processor (NP), a combination of a CPU and an NP, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. The processor may implement or execute the methods, steps, and logic block diagrams disclosed in this application. A general-purpose processor may be a microprocessor, or the processor may be any conventional processor, etc. The steps of the methods disclosed in reference to this application may be directly performed and achieved by using a hardware decoding processor, or may be performed and achieved by using a combination of hardware and software modules in the decoding processor. The software modules may be located in storage media mature in the art, such as random access memory, flash, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers.The storage medium is located in a memory, and the processor reads information in the memory and completes the steps in the above method in combination with the processor hardware. Although only one processor is shown in the drawings, the device may include multiple processors, or the processor may include multiple processing units. Specifically, the processor may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor.

[0202] The memory is configured to store computer instructions executed by the processor. The memory may be a storage circuit or may be a memory. The memory may be volatile or nonvolatile memory, or may include volatile and nonvolatile memory. The nonvolatile memory may be read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, or flash. The volatile memory may be random access memory or may function as an external cache. The memory may be independent of the processor or may be a storage unit within the processor. This is not a limitation here. Although only one memory is shown in the drawings, the device may include multiple memories, or the memory may include multiple storage units.

[0203] The transceiver is configured to realize content exchange between the processor and other units or network elements. Specifically, the transceiver may be a communication interface of the device, a transceiver circuit, a communication unit, or a transceiver. Alternatively, the transceiver may be a communication interface or a transceiver circuit of the processor. Optionally, the transceiver may be a transceiver chip. Alternatively, the transceiver may include a transmitting unit and / or a receiving unit. In a possible implementation, the transceiver may include at least one communication interface. In another possible implementation, the transceiver may alternatively be a unit implemented in software. In an embodiment of this application, the processor may interact with other units or network elements by using the transceiver. For example, the processor obtains or receives content from other network elements by using the transceiver. If the processor and the transceiver are two physically separate components, the processor may exchange content with other units of the device without using the transceiver.

[0204] In a possible implementation, the processor, memory, and transceiver may be connected to each other through a bus, which may be a peripheral component interconnect (PCI) bus, an extended industry standard architecture (EISA) bus, etc. The bus may be categorized into an address bus, a data bus, a control bus, etc.

[0205] In the embodiments of this application, terms such as "example" or "for example" are intended to represent providing an example, illustration, or explanation. Any embodiment or design manner described as "example" or "for example" in the embodiments of this application should not be described as being preferred or having more advantages than other embodiments or design manners. Rather, the use of terms such as "example" or "for example" is intended to present a relative concept in a particular manner.

[0206] In the embodiments of this application, several examples are used for explanation to facilitate understanding, but these examples are merely examples and do not represent the best implementation methods for realizing this application.

[0207] All or part of the above embodiments may be realized by using software, hardware, firmware, or any combination thereof. When software is used for the implementation method, all or part of the embodiments may be realized in the form of a computer program product.

[0208] A computer program product includes one or more computer instructions. When the computer-executable instructions are loaded and executed on a computer, the procedures or functions according to the embodiments of this application are generated, in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from a computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, or digital subscriber line (DSL)) or wireless (e.g., infrared, radio, or microwave) method. The computer-readable storage medium may be any available medium accessible by a computer, or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, or a magnetic tape), an optical medium (e.g., a DVD), a semiconductor medium (e.g., a solid-state drive (SSD)), etc.

[0209] For the purpose of convenience and simple description, the detailed operation processes of the transmitting end optical module, the receiving end optical module, the unit and the module can be clearly understood by those skilled in the art, and the details will not be described again here.

[0210] The above embodiments are merely for illustrating the technical solutions in this application, and are not intended to limit this application. Although this application has been described in detail with reference to the above embodiments, it should be understood that those skilled in the art may still make modifications to the technical solutions described in the above embodiments, or may make equivalent substitutions for some technical features thereof. However, these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions in the embodiments of this application.

Claims

1. 1. An encoding method comprising: acquiring m lanes of a first data stream through m input lanes, where m is a positive integer; processing the m lanes of first data streams to obtain z lanes of second data streams, where z is a positive integer; separately performing an encoding process on each of the z lanes of the second data streams to obtain z lanes of the third data streams; performing a multiplexing process on the z lanes of third data streams to obtain n lanes of fourth data streams, where n is a positive integer; Including, Processing the m lanes of first data streams to obtain z lanes of second data streams includes: performing a demultiplexing process on the m lanes first data streams based on a second ratio to obtain z lanes fifth data streams; separately performing Q stages of processing on each of the z lanes of the fifth data stream to obtain the z lanes of the second data stream; Including, The processing of each stage in the Q-stage processing is as follows: performing round-robin distribution processing on the fifth data stream to obtain data sub-streams of at least two lanes; performing a delay process on the first data sub-stream to obtain a sixth data stream; performing a multiplexing process on the second data sub-stream and the sixth data stream to obtain an output data stream; Including, An encoding method, wherein the first data substream is at least one of the at least two lane data substreams, the second data substream is one lane on which delay processing is not performed, the second data stream is one lane of the at least two lane data substreams, the output data stream is the second data stream, and Q=1.

2. each of the z lanes of second data streams includes a data block to be encoded; Separately performing an encoding process on each of the z lanes of the second data stream includes: performing an encoding process on first data blocks to obtain one or more forward error correction (FEC) code words, the first data blocks being at least C / z consecutive data blocks to be encoded in a corresponding second data stream, where C is a positive integer and C is an integer multiple of z; Including, The encoding method comprises: inserting a first identifier at a codeword boundary of one of the FEC codewords; The encoding method of claim 1 further comprising:

3. each of the z lanes of second data streams includes a data block to be encoded; Separately performing an encoding process on each of the z lanes of the second data stream includes: Inserting a first identifier into each data block to be encoded in a first data block to obtain a second data block, wherein the first data block is C / z consecutive data blocks to be encoded, where C is a positive integer and C is an integer multiple of z; performing an encoding process on the second data block to obtain an FEC code word, wherein a throughput or baud rate of the FEC code word is an integer multiple of a reference clock; The encoding method of claim 1 , comprising:

4. The encoding method according to claim 2 , wherein the first identifier is a predetermined identifier sequence.

5. 3. The encoding method of claim 2, wherein the first identifier is obtained based on a value of a first bit in the first data block, the first bit being any one of at least one bit in the first data block, or the first identifier is obtained based on bit values of at least L second bits in the first data block, wherein there is an interval of s bits between every two adjacent second bits among the L second bits, L≧2 and s≧0, and L and s are integers.

6. 2. The encoding method of claim 1, wherein the sixth data stream has a bit length of at least (N×codeword length of RS codeword) / (z×i) bits, where N is a positive integer and i is the number of data substreams.

7. The encoding method comprises: identifying an alignment marker in the second data stream for each lane, the alignment marker identifying a symbol boundary in the corresponding second data stream; determining the symbol boundaries in the corresponding second data stream based on the alignment markers; The encoding method of claim 1 further comprising:

8. 2. The encoding method of claim 1, wherein the first data streams of the m lanes are obtained by performing a multiplexing process at a first ratio on the data streams of the z lanes obtained through Reed-Solomon (RS) encoding.

9. The encoding method of claim 1, wherein m=4, z=32, and n=4.

10. 1. A decoding method comprising: acquiring a fourth data stream of n lanes through n input lanes; performing a demultiplexing process on the n-lane fourth data stream to obtain z-lane third data stream; separately performing a decoding process on each of the z lanes of third data streams to obtain z lanes of second data streams; performing a multiplexing process on the z-lane second data streams based on a first ratio to obtain m-lane first data streams, wherein the first ratio is a ratio of z to m; Including, the third data stream of the z lanes includes a first identifier, the first identifier identifying a codeword boundary of an FEC codeword; The decoding method is identifying the codeword boundary of the FEC codeword based on the first identifier and / or a decoding flag bit, the decoding flag bit indicating whether the decoding process was successful or not; Further comprising: Before identifying the codeword boundary of the FEC codeword based on the first identifier and / or decoding flag bits, the decoding method comprises: generating a first signal based on the first identifier and / or the decoding flag bit, the first signal for determining data and clock information; The decoding method further comprises:

11. 1. A coding device comprising one or more processors, the one or more processors: configured to acquire m lanes of the first data stream through m input lanes, where m is a positive integer; performing a demultiplexing process on the m lanes' first data streams based on a second ratio to obtain z lanes' fifth data streams; configured to separately perform Q stages of processing on each of the z lanes of fifth data streams to obtain the z lanes of second data streams; In each stage of the Q-stage process, the one or more processors: performing round-robin distribution processing on the fifth data stream to obtain data substreams of at least two lanes; performing a delay process on the first data substream to obtain a sixth data stream; is configured to perform a multiplexing process on a second data substream and the sixth data stream to obtain an output data stream, wherein the first data substream is at least one of the at least two lane data substreams, the second data substream is one lane on which delay processing is not performed, the second data stream is one lane of the at least two lane data substreams, the output data stream is the second data stream, and Q=1; separately performing an encoding process on each of the z lanes of the second data stream to obtain z lanes of the third data stream; an encoding device configured to perform a multiplexing process on the z-lane third data streams to obtain n-lane fourth data streams, where n is a positive integer;

12. each of the z lanes of second data streams includes a data block to be encoded; the one or more processors: is configured to perform an encoding process on first data blocks to obtain one or more FEC code words, the first data blocks being at least C / z consecutive data blocks to be encoded in a corresponding second data stream, where C is a positive integer and C is an integer multiple of z; 12. The encoding device of claim 11, configured to insert a first identifier at a codeword boundary of one of the FEC codewords.

13. each of the z lanes of second data streams includes a data block to be encoded; the one or more processors: The encoding method is configured to insert a first identifier into each of the data blocks to be encoded in the first data block to obtain a second data block, wherein the first data block is C / z consecutive data blocks to be encoded, where C is a positive integer and C is an integer multiple of z; The encoding device according to claim 11 , configured to perform an encoding process on the second data block to obtain an FEC codeword, wherein a throughput or baud rate of the FEC codeword is an integer multiple of a reference clock.

14. The encoding device of claim 11, wherein m=4, z=32, and n=4.

15. 1. A decoding device comprising one or more processors, the one or more processors: obtaining a fourth data stream of n lanes through the n input lanes; performing a demultiplexing process on the n-lane fourth data stream to obtain z-lane third data stream; separately performing a decoding process on each of the z lanes of the third data stream to obtain z lanes of the second data stream; is configured to perform a multiplexing process on the z lanes' second data streams based on a first ratio to obtain m lanes' first data streams, wherein the first ratio is a ratio of z to m; the third data stream of the z lanes includes a first identifier, the first identifier identifying a codeword boundary of an FEC codeword; the one or more processors: further configured to identify the codeword boundary of the FEC codeword based on the first identifier and / or a decoding flag bit, the decoding flag bit indicating whether the decoding process was successful; the one or more processors are further configured to generate a first signal based on the first identifier and / or the decoding flag bits before identifying the codeword boundary of the FEC codeword based on the first identifier and / or the decoding flag bits, the first signal being for determining data and clock information.

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