A communication method, system, apparatus and computer readable storage medium

Abstract

The application discloses a communication method, system and device and a computer readable storage medium, and relates to the communication field. The application sets corresponding sending logic gate modules and receiving logic gate modules for N processors. After receiving data transmitted by an optical module through the receiving logic gate module, the processor judges whether the received data includes the identification information of the processor. If the received data includes the identification information of the processor, the corresponding sending logic gate module is enabled to work, and data transmission between the corresponding sending logic gate module and the optical module is performed. If the received data does not include the identification information of the processor, the corresponding sending logic gate module is controlled not to work, and data transmission between the corresponding sending logic gate module and the optical module is not performed. Only one processor in the N processors performs data transmission with the optical module at the same time. The application solves the connection problem between the sending logic gate with the hot plug function on the N processors and the optical module with the hot plug communication interface.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication, in particular to a communication method, system, device and computer readable storage medium. BACKGROUND

[0002] With the development of science and technology, the importance of data transmission field is increasing, especially through the processor and optical module for data transmission. In practical application, in order to ensure the stability of data transmission, mainly using N processor connection N optical module connection mode, wherein, N processor redundancy. Because the optical module contains communication interface, this communication interface is mainly used to realize the data transmission process of optical module and processor. Therefore, using this connection mode can ensure that the remaining processors can still transmit data with the optical module after one processor fails in the data transmission process of the processor and the optical module. However, how to realize the hot plug of the processor and the optical module under the premise of ensuring the stability of data transmission is a problem that people are concerned about.

[0003] In order to realize the hot plug of the processor and the optical module, the prior art increases the sending logic gate module and the receiving logic gate module with hot plug function on N processors, and uses N optical modules with hot plug communication interface. Although this connection mode can realize the hot plug of the processor and the optical module, it will cause the problem of line "and" because the output ends of N processors are connected to the hot plug communication interface of the optical module through the sending logic gate module. SUMMARY

[0004] The purpose of the present application is to provide a communication method, system, device and computer readable storage medium. After the processor receives the data transmitted by the optical module through the receiving logic gate module, it judges whether the received data includes its own identification information. If the data received by itself includes its own identification information, enable the corresponding sending logic gate module to work, and transmit data with the optical module through the corresponding sending logic gate module; if the data received by itself does not include its own identification information, control the corresponding sending logic gate module not to work, that is, do not transmit data with the optical module. So that only one processor in N processors transmits data with the optical module at the same time. Solve the problem of line "and" between N sending logic gates with hot plug function on N processors and N optical modules with hot plug communication interface.

[0005] To solve the above technical problems, the application provides a communication method, which is applied to any one of N processors of a communication device, wherein N is an integer greater than or equal to 2, and the communication device further comprises N optical modules provided with hot plug communication interfaces, and sending logic gate modules and receiving logic gate modules supporting hot plug which are connected with the processors one by one, each of the hot plug communication interfaces comprises a receiving interface, an AND gate and a sending interface, each of the sending logic gate modules is connected with the receiving interface, each of the receiving logic gate modules is connected with the sending interface, and the receiving interface in the hot plug communication interface is connected with the input end of the AND gate in the hot plug communication interface.

[0006] The method comprises:

[0007] judging whether the data received by itself includes the identification information of itself, wherein the data is sent by the optical module through the sending interface and the receiving logic gate module;

[0008] if the data received by itself includes the identification information of itself, enabling the sending logic gate module corresponding to itself to work, and communicating with the optical module sending the data through the working sending logic gate module;

[0009] if the data received by itself does not include the identification information of itself, controlling the sending logic gate module corresponding to itself to not work, so as to disconnect the communication between itself and each of the optical modules, and the sending logic gate module not working outputs a high resistance state.

[0010] Preferably, the optical module further comprises N receiving bus drivers supporting hot plug and N sending bus drivers supporting hot plug, the input end of each of the receiving bus drivers is connected with the receiving logic gate module one by one, the output end of each of the receiving bus drivers is connected with the receiving interface one by one, the input end of each of the sending bus drivers is connected with the sending interface one by one, and the output end of each of the sending bus drivers is connected with the sending logic gate module one by one.

[0011] Preferably, the sending logic gate module is N tri-state buffers supporting hot plug, and the receiving logic gate module is N bus drivers supporting hot plug, the enable end and the input end of each of the tri-state buffers are connected with the corresponding processor, the output end is connected with each of the receiving interfaces, the enable end and the output end of each of the bus drivers are connected with the corresponding processor, and the input end is connected with each of the sending interfaces.

[0012] enabling the sending logic gate module corresponding to itself to work comprises:

[0013] enabling the tri-state buffer corresponding to itself to work.

[0014] Preferably, when communicating with the optical module sending the data through the working sending logic gate module, it further comprises:

[0015] A square wave of a preset frequency is transmitted to the corresponding optical module through the sending logic gate module between the sending of the data to the optical module and the next data sent by the optical module being received by the processor.

[0016] To solve the above technical problems, the application further provides a communication system applied to any one of N processors of a communication device, wherein N is an integer not less than 2, and the communication device further comprises N optical modules provided with hot plug communication interfaces, and sending logic gate modules and receiving logic gate modules supporting hot plug connected with the processors one by one, each hot plug communication interface comprises a receiving interface, an AND gate and a sending interface, each sending logic gate module is connected with each receiving interface, each receiving logic gate module is connected with each sending interface, and the input end of the AND gate in the hot plug communication interface is connected with the receiving interface in the hot plug communication interface.

[0017] The system comprises:

[0018] A judging unit is configured to judge whether the data received by itself includes the identification information of itself, wherein the data is sent by the optical module through the sending interface and the receiving logic gate module;

[0019] An enabling unit is configured to enable the corresponding sending logic gate module of itself to work and communicate with the corresponding optical module through the working sending logic gate module if the data received by itself includes the identification information of itself.

[0020] A control unit is configured to control the corresponding sending logic gate module of itself not to work so as to disconnect the communication with the optical modules if the data received by itself does not include the identification information of itself.

[0021] To solve the above technical problems, the application further provides a communication device, which comprises:

[0022] N processors, wherein N is an integer not less than 2, N optical modules provided with hot plug communication interfaces, and sending logic gate modules and receiving logic gate modules supporting hot plug connected with the processors one by one, each hot plug communication interface comprises a receiving interface, an AND gate and a sending interface, each sending logic gate module is connected with each receiving interface, each receiving logic gate module is connected with each sending interface, and the input end of the AND gate in the hot plug communication interface is connected with the receiving interface in the hot plug communication interface.

[0023] Any one of the N processors is configured to execute the computer program to implement the steps of the communication method.

[0024] Preferably, the optical module further comprises N hot-plug supported receiving bus drivers and N hot-plug supported sending bus drivers, the input end of each receiving bus driver is connected to each receiving logic gate module one by one, the output end of each receiving bus driver is connected to each receiving interface one by one, the input end of each sending bus driver is connected to each sending interface one by one, and the output end of each sending bus driver is connected to each sending logic gate module one by one.

[0025] Preferably, the sending logic gate module is N hot-plug supported tri-state buffers, the receiving logic gate module is N hot-plug supported bus drivers, the enable end and the input end of each tri-state buffer are connected to the corresponding processor, the output end is connected to each receiving interface, the enable end and the output end of each bus driver are connected to the corresponding processor, and the input end is connected to each sending interface.

[0026] To solve the above technical problems, the application further provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the steps of the communication method.

[0027] The application aims to provide a communication method, system, device and computer readable storage medium, and each of the N processors is provided with a corresponding sending logic gate module and a receiving logic gate module. After receiving the data transmitted by the optical module through the receiving logic gate module, the processor judges whether the received data includes the identification information of the processor itself. If the received data includes the identification information of the processor itself, the corresponding sending logic gate module is enabled to work, and data transmission is performed between the processor and the optical module through the corresponding sending logic gate module; if the received data does not include the identification information of the processor itself, the corresponding sending logic gate module is controlled not to work, that is, the processor does not perform data transmission with the optical module. Therefore, only one of the N processors performs data transmission with the optical module at the same time. The problem of the connection between the N sending logic gates with the hot-plug function and the N optical modules provided with the hot-plug communication interface is solved. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed in the prior art and the embodiments. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort.

[0029] Figure 1 A process flow chart of a communication method provided by the present application;

[0030] Figure 2 A structural schematic diagram of a communication device provided by the present application;

[0031] Figure 3 A structural schematic diagram of another communication device provided by the present application;

[0032] Figure 4 A structural schematic diagram of a processor sending data to an optical module provided by the present application;

[0033] Figure 5 A structural schematic diagram of an optical module sending data to a processor provided by the present application;

[0034] Figure 6 A structural schematic diagram of a communication system provided by the present application. DETAILED DESCRIPTION

[0035] The core of the present application is to provide a communication method, system, device and computer readable storage medium. After receiving data transmitted by an optical module through a receiving logic gate module, a processor judges whether the received data includes its own identification information. If the received data includes its own identification information, the corresponding sending logic gate module is enabled to work, and data transmission is performed between the corresponding sending logic gate module and the optical module. If the received data does not include its own identification information, the corresponding sending logic gate module is controlled not to work, i.e. data transmission with the optical module is not performed. Thus, only one processor in N processors performs data transmission with the optical module at the same time. The problem of connection between N processors with hot plug sending logic gates and N optical modules provided with hot plug communication interfaces is solved.

[0036] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0037] Please refer to Figure 1 , Figure 1A process flow chart of a communication method provided by the application. The method is applied to any one of N processors of a communication device, N is an integer not less than 2, the communication device further comprises: N optical modules provided with hot plug communication interfaces and a sending logic gate module 1 and a receiving logic gate module 2 corresponding to each processor in a one-to-one manner, the hot plug communication interface comprises: a receiving interface 3, an AND gate 4 and a sending interface 5, each sending logic gate module 1 is connected with each receiving interface 3, each receiving logic gate module 2 is connected with each sending interface 5, and the receiving interface 3 in the hot plug communication interface is connected with the input end of the AND gate 4 in the hot plug communication interface;

[0038] The method comprises:

[0039] S10: judging whether the data received by the processor includes the identification information of the processor or not, the data being sent by the optical module through the sending interface 5 and the receiving logic gate module 2;

[0040] In the application, if the N processors communicate with the optical module sending data after receiving the data after the optical module sends data to the N processors, the line AND problem will be caused. Since the identification information is unique, the processor judges whether the data sent by the optical module includes the identification information of the processor or not to determine whether the processor needs to communicate with the optical module sending data, so that only one processor communicates with the optical module sending data, and the line AND problem is solved.

[0041] S11: if the data received by the processor includes the identification information of the processor, enabling the sending logic gate module 1 corresponding to the processor to work and communicating with the optical module sending data through the working sending logic gate module 1;

[0042] In the application, if the processor judges whether the data sent by the optical module includes the identification information of the processor or not after judging whether the data sent by the optical module includes the identification information of the processor or not, the processor enables the sending logic gate module 1 corresponding to the processor to work and communicates with the optical module sending data.

[0043] In actual application, the identification information can be id information, an IP address or other information.

[0044] S12: if the data received by the processor does not include the identification information of the processor, controlling the sending logic gate module 1 corresponding to the processor to not work, so as to disconnect the communication between the processor and the optical module, and the sending logic gate module 1 outputs a high resistance state when not working.

[0045] In the present application, the processor judges whether the data sent by the optical module includes the identification information of the processor itself. If the data sent by the optical module does not include the identification information of the processor itself, it is determined that the optical module sending the data does not need to communicate with the processor. The processor communicates with the optical module through the sending logic gate module 1, the receiving interface 3 and the AND gate 4. The AND gate 4 has N input ends and one output end. The output of the output end depends on the input of the input end. When the corresponding sending logic gate module 1 of the processor is not working, the high resistance state is output to the input end of the AND gate 4. At this time, the output of the output end of the AND gate 4 completely depends on the input of the working sending logic gate module 1, which ensures that only one processor communicates with the optical module sending the data, and solves the line "and" problem.

[0046] In actual application, when N is 2, the structure diagram of the communication device is as shown in Figure 2 It should be noted that in actual application, the specific direction of data transmission can be that the DP (Decentralized Peripherals) master (controller) sends data to the optical module through an optical fiber. The optical module sends data to the processor through the sending interface 5 and the receiving logic gate module 2. Because the data includes some address information and identification information, and because the communication protocol used in the present application is profibus DP (Process Field Bus Decentralized Peripherals) communication protocol. Therefore, when the processor receives the data, the processor judges whether the data is the message sent by the DP master (controller) to itself according to the profibus DP communication protocol by judging whether the data includes the identification information of the processor itself. When the data includes the identification information of the processor itself, it is proved that the data is the message sent by the DP master (controller) to itself according to the profibus DP communication protocol. At this time, the processor performs data response, enables the corresponding sending logic gate module 1 to work, and communicates with the optical module sending the data. When the data does not include the identification information of the processor itself, it is proved that the data is not the message sent by the DP master (controller) to itself according to the profibus DP communication protocol. At this time, the processor does not perform data response, controls the corresponding sending logic gate module 1 to not work, and does not communicate with the optical module sending the data. It is ensured that only one processor communicates with the optical module sending the data after the optical module sends data to the processor, and the line "and" problem in the prior art is solved.

[0047] It also needs to be explained that, for example, N is 2, at this time two processors and two optical modules for data transmission, at this time take one of the optical modules, for example, this optical module in the sending data to two processors after the completion of the processor in the control of their own corresponding sending logic gate module 1 does not work, it corresponds to the sending logic gate module 1 output high resistance state, another processor enables their own corresponding sending logic gate module 1 work. Because the optical module includes and gate 4 and receiving interface 3, so the actual connection is two processors through the corresponding sending logic gate module 1, receiving interface 3 and and gate 4 and optical module connection, because at this time a processor corresponding sending logic gate module 1 output high resistance state, at this time and gate 4 has two input terminals and an output terminal, so one of the input terminals of and gate 4 is high resistance state, so the output of its output depends on the input of the other input, so that the optical module in the premise of connecting multiple processors to read the data from the processor will not appear line "and" problem.

[0048] Finally, it needs to be explained that the optical module is a differential level signal (such as LVPECL, CML), or the user will be converted into a single-ended electrical signal (such as TTL level) difference level. But this level is point to point use, can not be directly connected together use.

[0049] In practical application, the processor control sending logic gate module 1 enable pin (OE#) to control the output state. Make sending logic gate module 1 enable pin enable so that can output data, make sending logic gate module 1 enable pin not enable so as not to send data. The processor receiving logic gate module 2 enable pin (OE) does not need to control, after power on enable, can not be interrupted to read the data sent by the optical module. A processor in reading multiple optical module data from the direct connection to the receiving logic gate module 2 two pin, there is no line "and" problem.

[0050] In practical application, sending logic gate module 1 can be N support hot plug tri-state buffer or other modules, receiving logic gate module 2 can be N support hot plug bus driver or other modules.

[0051] The embodiment provides a communication method, and each of the N processors is provided with a corresponding sending logic gate module 1 and a receiving logic gate module 2. After receiving data transmitted by the optical module through the receiving logic gate module 2, the processor judges whether the received data includes the identification information of the processor itself. If the received data includes the identification information of the processor itself, the corresponding sending logic gate module 1 is enabled to work, and data transmission between the corresponding sending logic gate module 1 and the optical module is performed; if the received data does not include the identification information of the processor itself, the corresponding sending logic gate module 1 is controlled not to work, that is, the data transmission between the corresponding sending logic gate module 1 and the optical module is not performed. Therefore, only one processor in the N processors performs data transmission with the optical module at the same time. The problem of the connection between the sending logic gate with the hot plug function on the N processors and the optical module with the hot plug communication interface is solved.

[0052] On the basis of the above embodiment,

[0053] Please refer to Figure 3 , Figure 3 The structure diagram of another communication device provided by the embodiment is shown.

[0054] As a preferred embodiment, the optical module further comprises N receiving bus drivers supporting hot plug and N sending bus drivers supporting hot plug, the input end of each receiving bus driver 6 is connected with each receiving logic gate module 2 in one-to-one correspondence, the output end of each receiving bus driver 6 is connected with each receiving interface 3 in one-to-one correspondence, the input end of each sending bus driver 7 is connected with each sending interface 5 in one-to-one correspondence, and the output end of each sending bus driver 7 is connected with each sending logic gate module 1 in one-to-one correspondence.

[0055] In the embodiment, the optical module further comprises N receiving bus drivers supporting hot plug and N sending bus drivers supporting hot plug. The N receiving bus drivers supporting hot plug and the N sending bus drivers supporting hot plug are always in an enabled state, so that the optical module can transmit and receive data in real time, and the communication efficiency is improved.

[0056] As a preferred embodiment, the sending logic gate module 1 is N tri-state buffers supporting hot plug, the receiving logic gate module 2 is N bus drivers supporting hot plug, the enable end and the input end of each tri-state buffer are connected with the corresponding processor, the output end is connected with each receiving interface 3, the enable end and the output end of each bus driver are connected with the corresponding processor, and the input end is connected with each sending interface 5.

[0057] Enabling the corresponding sending logic gate module 1 to work includes:

[0058] Enabling the corresponding tri-state buffer to work.

[0059] In the present application, the sending logic gate module 1 is N hot-plug supported tri-state buffers, when the processor receives the data from the optical module, the processor enables the corresponding tri-state buffer to work after judging that the data includes the identification information of the processor, and communicates with the optical module sending the data; the receiving logic gate module 2 is N hot-plug supported bus drivers, mainly used for sending the data from the optical module to the corresponding processor, the advantages of using the hot-plug supported tri-state buffer and the hot-plug supported bus driver are mainly fast transmission speed and high stability.

[0060] It should be noted that when N is 2, the structure of the processor sending data to the optical module is as shown in Figure 4 The sending logic gate module 1 in the figure is a two-input two-output tri-state buffer; the structure of the optical module sending data to the processor is as shown in Figure 5 The receiving logic gate module 2 in the figure is a two-input two-output bus driver.

[0061] As a preferred embodiment, when communicating with the optical module sending the data through the working sending logic gate module, it further includes:

[0062] Between sending the data to the optical module sending the data and the processor receiving the next data sent by the optical module, a square wave with a preset frequency is transmitted to the corresponding optical module through the sending logic gate module 1.

[0063] It should be noted that in actual application, the optical module generally uses AC coupling capacitor to communicate with the processor during data transmission. Because the capacitor is direct current isolation and alternating current, it needs to satisfy DC balance, that is, 1 and 0 in the bit stream appear alternately, which can be considered as an alternating current signal, so that it can pass through the capacitor smoothly; when DC is unbalanced, multiple continuous 1 or 0 in the bit stream can be considered as a direct current signal in the time period, which will cause encoding error after transmission due to the voltage level relationship. If the communication method appears 0 or 1, communication error is easy to occur. Because the optical module is a high-speed signal, it generally requires that the data satisfies DC balance. If a high-speed optical module is used to realize long-distance transmission in low-speed communication application, long 0 or long 1 cannot appear in the data, and generally a higher frequency signal is used to replace the low-speed 0 or 1 to realize DC balance of the data.

[0064] In the application, after the processor enables the corresponding sending logic gate module 1 to work, the processor communicates with the optical module sending data through the working sending logic gate module 1, that is, in the time between the processor sending data to the optical module sending data and receiving the next data sent by the optical module sending data, the processor is in an idle state. Since the idle state is high level (that is, long 1), it will cause the optical module data transceiver error. In order to solve this problem, the processor transmits a square wave of a preset frequency to the corresponding optical module through the sending logic gate module 1 in the idle state, which meets the DC balance and solves the problem of optical module data transceiver error caused by the idle state, thereby improving the reliability of communication.

[0065] In actual application, the unit of the preset frequency can be MHz, and the specific frequency is determined according to the system clock and debugging.

[0066] Please refer to Figure 6 , Figure 6 A structure schematic diagram of a communication system provided by the application is provided. Any one of N processors applied to a communication device, N is an integer not less than 2, the communication device further comprises: N optical modules provided with hot plug communication interfaces and sending logic gate modules 1 and receiving logic gate modules 2 supporting hot plug connected with the processors one by one, each hot plug communication interface comprises: a receiving interface 3, an AND gate 4 and a sending interface 5, each sending logic gate module 1 is connected with each receiving interface 3, each receiving logic gate module 2 is connected with each sending interface 5, the receiving interface 3 in the hot plug communication interface is connected with the input end of the AND gate 4 in the hot plug communication interface;

[0067] The system comprises:

[0068] A judging unit 1 is used for judging whether the data received by itself includes the identification information of itself or not, and the data is sent by the optical module through the sending interface 5 and the receiving logic gate module 2;

[0069] An enabling unit 2 is used for enabling the corresponding sending logic gate module 1 to work if the data received by itself includes the identification information of itself, and communicating with the corresponding optical module through the working sending logic gate module 1;

[0070] A control unit 3 is used for controlling the corresponding sending logic gate module 1 not to work if the data received by itself does not include the identification information of itself, so as to disconnect the communication between the processor and the optical module.

[0071] The communication system provided by the embodiment corresponds to the above method, so it has the same beneficial effects as the above method. Therefore, the embodiment of the communication system part is described in the embodiment of the method part, which is not described here.

[0072] The application further provides a corresponding embodiment of a communication device, comprising:

[0073] N processors, N being an integer not less than 2, N optical modules provided with hot plug communication interfaces, and N sending logic gate modules 1 and receiving logic gate modules 2 corresponding to the processors respectively, each hot plug communication interface comprising a receiving interface 3, an AND gate 4 and a sending interface 5, each sending logic gate module 1 being connected with each receiving interface 3, each receiving logic gate module 2 being connected with each sending interface 5, and each receiving interface 3 in the hot plug communication interface being connected with an input end of each AND gate 4 in the hot plug communication interface;

[0074] Any one of the N processors is used to execute a computer program to realize the steps of the above communication method.

[0075] As a preferred embodiment, the optical module further comprises N hot plug supporting receiving bus drivers 6 and N hot plug supporting sending bus drivers 7, the input ends of each receiving bus driver 6 are connected with each receiving logic gate module 2 respectively and one-to-one, the output ends of each receiving bus driver 6 are connected with each receiving interface 3 respectively and one-to-one, the input ends of each sending bus driver 7 are connected with each sending interface 5 respectively and one-to-one, and the output ends of each sending bus driver 7 are connected with each sending logic gate module 1 respectively and one-to-one.

[0076] As a preferred embodiment, the sending logic gate module 1 is an N hot plug supporting tri-state buffer, the receiving logic gate module 2 is an N hot plug supporting bus driver, the enable ends and the input ends of each tri-state buffer are connected with the corresponding processor, the output ends of each tri-state buffer are connected with each receiving interface 3, the enable ends and the output ends of each bus driver are connected with the corresponding processor, and the input ends of each bus driver are connected with each sending interface 5.

[0077] The communication device provided by the embodiment corresponds to the above method, and has the same beneficial effects as the above method, so the embodiments of the communication device part are described in the embodiments of the method part, which will not be described here.

[0078] The application further provides a corresponding embodiment of a computer readable storage medium, the computer readable storage medium storing a computer program, and the computer program is executed by a processor to realize the steps of the above communication method.

[0079] It can be understood that if the method in the above embodiment is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and performs all or part of the steps of the method of the embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0080] The computer readable storage medium provided by the embodiment has the same beneficial effects as the above method, so the embodiments of the computer readable storage medium part are described with reference to the description of the embodiments of the method part, and will not be described here.

[0081] It should be noted that in the specification, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0082] The above description of the disclosed embodiments enables a person skilled in the art to implement or use the present application. Various modifications to the embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A communication method, characterized by, Any one of N processors applied to a communication device, N is an integer not less than 2, the communication device further comprises: N optical modules provided with hot plug communication interfaces and support hot plug sending logic gate modules and receiving logic gate modules connected with each of the processors one by one, each of the hot plug communication interfaces comprises: a receiving interface, an AND gate and a sending interface, each of the sending logic gate modules is connected with each of the receiving interfaces, each of the receiving logic gate modules is connected with each of the sending interfaces, the receiving interface in the hot plug communication interface is connected with the input end of the AND gate in the hot plug communication interface; The method comprises: Judging whether the data received by itself includes the identification information of itself, the data being sent by the optical module through the sending interface and the receiving logic gate module; If the data received by itself includes the identification information of itself, enabling the corresponding sending logic gate module of itself to work, and communicating with the optical module sending the data through the working sending logic gate module; If the data received by itself does not include the identification information of itself, controlling the corresponding sending logic gate module of itself not to work, so as to disconnect the communication between itself and each of the optical modules, and the sending logic gate module not working outputs a high resistance state.

2. The communication method of claim 1, wherein, The optical module further comprises: N receiving bus drivers supporting hot plug and N sending bus drivers supporting hot plug, the input end of each of the receiving bus drivers is connected with each of the receiving logic gate modules one by one, the output end of each of the receiving bus drivers is connected with each of the receiving interfaces one by one, the input end of each of the sending bus drivers is connected with each of the sending interfaces one by one, and the output end of each of the sending bus drivers is connected with each of the sending logic gate modules one by one.

3. The communication method of claim 1, wherein, The sending logic gate module is N tri-state buffers supporting hot plug, and the receiving logic gate module is N bus drivers supporting hot plug, the enable end and the input end of each of the tri-state buffers are connected with the corresponding processor, the output end is connected with each of the receiving interfaces, the enable end and the output end of each of the bus drivers are connected with the corresponding processor, and the input end is connected with each of the sending interfaces; Enabling the corresponding sending logic gate module of itself to work comprises: Enabling the corresponding tri-state buffer of itself to work.

4. The communication method according to any one of claims 1 to 3, characterized by, When communicating with the optical module sending the data through the working sending logic gate module, it further comprises: Between sending data to the optical module and the processor receiving the next data sent by the optical module, a square wave of a preset frequency is transmitted to the corresponding optical module through the sending logic gate module.

5. A communication system, characterized by Any one of N processors applied to a communication device, N being an integer not less than 2, the communication device further comprising: N optical modules provided with hot plug communication interfaces and N sending logic gate modules and receiving logic gate modules supporting hot plug connected with the processors one by one, each of the hot plug communication interfaces comprising: a receiving interface, an AND gate and a sending interface, each of the sending logic gate modules being connected with each of the receiving interfaces, each of the receiving logic gate modules being connected with each of the sending interfaces, the receiving interface in the hot plug communication interface being connected with the input end of the AND gate in the hot plug communication interface; The system comprises: A judging unit configured to judge whether the data received by itself includes the identification information of itself, the data being sent by the optical modules through the sending interfaces and the receiving logic gate modules; An enabling unit configured to enable the corresponding sending logic gate module of itself to work and communicate with the corresponding optical module through the working sending logic gate module if the data received by itself includes the identification information of itself; A control unit configured to control the corresponding sending logic gate module of itself not to work so as to disconnect the communication with the optical modules if the data received by itself does not include the identification information of itself.

6. A communication device, comprising: Comprise: N processors, N being an integer not less than 2, N optical modules provided with hot plug communication interfaces and N sending logic gate modules and receiving logic gate modules supporting hot plug connected with the processors one by one, each of the hot plug communication interfaces comprising: a receiving interface, an AND gate and a sending interface, each of the sending logic gate modules being connected with each of the receiving interfaces, each of the receiving logic gate modules being connected with each of the sending interfaces, the receiving interface in the hot plug communication interface being connected with the input end of the AND gate in the hot plug communication interface; Any one of the N processors is configured to execute a computer program to implement the steps of the communication method according to any one of claims 1 to 4.

7. The communication device of claim 6, wherein the means for receiving the first signal comprises means for receiving the first signal in a first frequency band and means for receiving the second signal in a second frequency band. The optical module further comprises: N receiving bus drivers supporting hot plug and N sending bus drivers supporting hot plug, the input ends of the receiving bus drivers are connected with the receiving logic gate modules one by one respectively, the output ends of the receiving bus drivers are connected with the receiving interfaces one by one respectively, the input ends of the sending bus drivers are connected with the sending interfaces one by one respectively, and the output ends of the sending bus drivers are connected with the sending logic gate modules one by one respectively.

8. The communication apparatus of claim 6, wherein The sending logic gate modules are N tri-state buffers supporting hot plug, the receiving logic gate modules are N bus drivers supporting hot plug, the enable ends and the input ends of the tri-state buffers are connected with the processors, the output ends of the tri-state buffers are connected with the receiving interfaces, the enable ends and the output ends of the bus drivers are connected with the processors, and the input ends of the bus drivers are connected with the sending interfaces.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the steps of the communication method according to any one of claims 1 to 4.

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