Memory device, memory circuit, and method of manufacturing a memory circuit

Abstract

A memory device, a memory circuit, and a method of manufacturing the memory circuit are disclosed. The memory device includes a substrate, an oxide insulating layer, a first metal oxide layer, a first gate dielectric layer, a second metal oxide layer, a second gate dielectric layer, a first gate electrode, a source electrode, and a drain electrode. The oxide insulating layer is on the substrate. The first metal oxide layer is on the oxide insulating layer. The first gate dielectric layer is on the first metal oxide layer. The second metal oxide layer is on the first gate dielectric layer. The second gate dielectric layer is on the second metal oxide layer. The first gate electrode is on the second gate dielectric layer. The second metal oxide layer is between the first gate electrode and the first metal oxide layer. The source electrode and the drain electrode are electrically connected to the first metal oxide layer.

Description

Technical Field

[0001] This invention relates to a memory device, a memory circuit, and a method for manufacturing the memory circuit. Background Technology

[0002] Electronically erasable programmable read-only memory (EEPROM) is a memory device that can store data without a power supply. It has the advantages of fast access speed, large capacity and small size. Therefore, EEPROM is now widely used in various electronic products.

[0003] In a typical EEPROM, different control gate voltages (Vg) are applied to the gate to control whether electrons tunnel into the floating gate. When an electron enters the floating gate, the EEPROM's memory cell stores a "1". Conversely, when an electron escapes from the floating gate, the EEPROM's memory cell stores a "0". Summary of the Invention

[0004] The present invention provides a memory device, a memory circuit, and a method for manufacturing the memory circuit, wherein the memory device has the advantage of fast access speed.

[0005] At least one embodiment of the present invention provides a memory device. The memory device includes a substrate, an oxide insulating layer, a first metal oxide layer, a first gate dielectric layer, a second metal oxide layer, a second gate dielectric layer, a first gate, a source, and a drain. The oxide insulating layer is located on the substrate. The first metal oxide layer is located on the oxide insulating layer. The first gate dielectric layer is located on the first metal oxide layer. The second metal oxide layer is located on the first gate dielectric layer. The second gate dielectric layer is located on the second metal oxide layer. The first gate is located on the second gate dielectric layer. The second metal oxide layer is located between the first gate and the first metal oxide layer. The source and drain are electrically connected to the first metal oxide layer.

[0006] At least one embodiment of the present invention provides a memory circuit. The memory circuit includes a substrate, an oxide insulating layer, a first gate dielectric layer, a second gate dielectric layer, a memory device, and a thin-film transistor. The oxide insulating layer is located on the substrate and includes a first oxygen-containing structure and a second oxygen-containing structure. The first gate dielectric layer is located on the oxide insulating layer and includes a first dielectric structure and a second dielectric structure. The second oxygen-containing structure and the second dielectric structure are stacked to form a bump structure. The second gate dielectric layer is located on the first gate dielectric layer. The memory device includes a first metal oxide layer, a second metal oxide layer, a first gate, a first source, and a first drain. The first metal oxide layer is located on the first oxygen-containing structure. The first dielectric structure is located between the first metal oxide layer and the second metal oxide layer. The second gate dielectric layer is located between the second metal oxide layer and the first gate. The second metal oxide layer is located between the first gate and the first metal oxide layer. The first source and the first drain are electrically connected to the first metal oxide layer. The thin-film transistor includes a third metal oxide layer, a second gate, a second source, and a second drain. The third metal oxide layer covers the top surface and the side surface of the bump structure. The second gate electrode overlaps the third metal oxide layer. A second gate dielectric layer is located between the second gate electrode and the third metal oxide layer. The second source electrode and the second drain electrode are electrically connected to the third metal oxide layer.

[0007] At least one embodiment of the present invention provides a method for manufacturing a memory circuit, comprising: forming an oxide insulating layer on a substrate; forming a first metal oxide layer on the oxide insulating layer; forming a first gate dielectric layer on the first metal oxide layer; forming a second metal oxide layer on the first gate dielectric layer; forming a second gate dielectric layer on the second metal oxide layer; forming a first gate on the second gate dielectric layer, wherein the second metal oxide layer is located between the first gate and the first metal oxide layer; and forming a source and a drain electrically connected to the first metal oxide layer. Attached Figure Description

[0008] Figure 1 This is a cross-sectional schematic diagram of a memory circuit according to an embodiment of the present invention;

[0009] Figure 2A yes Figure 1 The circuit diagram of the memory circuit;

[0010] Figure 2B yes Figure 2A Signal diagram of the memory circuit;

[0011] Figures 3A to 3F yes Figure 1 A cross-sectional schematic diagram of the manufacturing method of the memory circuit;

[0012] Figure 4This is a cross-sectional schematic diagram of a memory circuit according to an embodiment of the present invention;

[0013] Figure 5 This is a cross-sectional schematic diagram of a memory circuit according to an embodiment of the present invention.

[0014] Symbol Explanation

[0015] 10, 20, 30: Memory circuits

[0016] 100:Substrate

[0017] 110: Buffer layer

[0018] 120: Oxide insulating layer

[0019] 122: First oxygen-containing structure

[0020] 124: Second oxygen-containing structure

[0021] 130: First gate dielectric layer

[0022] 132: First dielectric structure

[0023] 134: Second dielectric structure

[0024] 140: Second gate dielectric layer

[0025] 150: Interlayer dielectric layer

[0026] BG: Bottom Gate

[0027] BL: Bitline

[0028] ch1: First Channel Area

[0029] ch2: Second Channel Area

[0030] DL: Data cable

[0031] dr1: First drain region

[0032] dr2: Second drain region

[0033] D1: First drain electrode

[0034] D2: Second drain electrode

[0035] DP: Doping fabrication process

[0036] G1: First gate

[0037] G2: Second gate

[0038] g1a, g1b, g2a, g2b: Resistance gradient region

[0039] L1, L2: Length

[0040] ND: Normal direction

[0041] OS1, OS1': First metal oxide layer

[0042] OS2: Second metal oxide layer

[0043] OS3, OS3': Third metal oxide layer

[0044] P: Protruding structure

[0045] ROM: Memory device

[0046] SL: Source Line

[0047] S1: First Source

[0048] S2: Second source pole

[0049] sr1: First source region

[0050] sr2: Second source pole region

[0051] TFT: Thin Film Transistor

[0052] V1: First contact hole

[0053] V2: Second contact hole

[0054] V3: Third contact hole

[0055] V4: Fourth contact hole

[0056] WL: Word Line Detailed Implementation

[0057] Figure 1 This is a cross-sectional schematic diagram of a memory circuit according to an embodiment of the present invention.

[0058] Please refer to Figure 1 The memory circuit 10 includes a substrate 100, an oxide insulating layer 120, a first gate dielectric layer 130, a second gate dielectric layer 140, a memory device ROM, and a thin-film transistor TFT. In this embodiment, the memory circuit 10 further includes a buffer layer 110 and an interlayer dielectric layer 150.

[0059] The substrate 100 may be made of glass, quartz, organic polymer, or opaque / reflective materials (e.g., conductive materials, metals, wafers, ceramics, or other suitable materials) or other suitable materials. If conductive materials or metals are used, an insulating layer (not shown) is applied to the substrate 100 to prevent short circuits. In some embodiments, the substrate 100 is a flexible substrate, and the material of the substrate 100 may be, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethyl methacrylate (PMMA), polycarbonate (PC), polyimide (PI), or metal foil or other flexible materials.

[0060] In some embodiments, the buffer layer 110 is located on the substrate 100 and contains hydrogen. For example, the material of the buffer layer 110 includes hydrogen-containing silicon nitride (or hydrogenated silicon nitride) or other suitable materials. In some embodiments, the buffer layer 110 is blanketed onto the substrate 100. In some embodiments, the thickness of the buffer layer 110 is from 100 angstroms to 6000 angstroms.

[0061] An oxide insulating layer 120 is located on the substrate 100. In this embodiment, the oxide insulating layer 120 is located on the buffer layer 110. In some embodiments, the oxide insulating layer 120 is patterned and does not cover a portion of the buffer layer 110. In other words, the oxide insulating layer 120 covers a portion of the top surface of the buffer layer 110 but does not cover another portion of the top surface of the buffer layer 110. In some embodiments, the oxide insulating layer 120 includes a first oxygen-containing structure 122 and a second oxygen-containing structure 124. In some embodiments, the first oxygen-containing structure 122 and the second oxygen-containing structure 124 are separated from each other. In some embodiments, the material of the oxide insulating layer 120 includes silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, or other suitable materials. In some embodiments, the thickness of the oxide insulating layer 120 is 300 angstroms to 5000 angstroms.

[0062] The memory device ROM and the thin-film transistor TFT are located on the substrate 100. In some embodiments, the memory device ROM and the thin-film transistor TFT are located on the oxide insulating layer 120. The memory device ROM includes a first metal oxide layer OS1, a second metal oxide layer OS2, a first gate G1, a first source S1, and a first drain D1. The thin-film transistor TFT includes a third metal oxide layer OS3, a second gate G2, a second source S2, and a second drain D2.

[0063] The first metal oxide layer OS1 is located on the first oxygen-containing structure 122 of the oxide insulating layer 120, and the first metal oxide layer OS1 contacts the top surface of the first oxygen-containing structure 122. The first oxygen-containing structure 122 is located between the first metal oxide layer OS1 and the buffer layer 110. The buffer layer 110 and the first oxygen-containing structure 122 are located between the first metal oxide layer OS1 and the substrate 100.

[0064] The first metal oxide layer OS1 includes a first source region sr1, a first drain region dr1, and a first channel region ch1 located between the first source region sr1 and the first drain region dr1, wherein the resistivity of the first source region sr1 and the first drain region dr1 is lower than the resistivity of the first channel region ch1. In some embodiments, the distance between the first channel region ch1 and the substrate 100 is substantially equal to the distance between the first source region sr1 and the substrate 100 and the distance between the first drain region dr1 and the substrate 100.

[0065] In some embodiments, the first oxygen-containing structure 122 beneath the first metal oxide layer OS1 replenishes oxygen in the first metal oxide layer OS1, thereby increasing the resistivity of the first metal oxide layer OS1. In this embodiment, the first oxygen-containing structure 122 beneath the first source region sr1, the first drain region dr1, and the first channel region ch1 has a substantially uniform thickness.

[0066] The first gate dielectric layer 130 is located above the oxide insulating layer 120 and includes a first dielectric structure 132 and a second dielectric structure 134. The first dielectric structure 132 of the first gate dielectric layer 130 is located on and covers the first metal oxide layer OS1. In some embodiments, the first source region sr1, the first drain region dr1, and the first channel region ch1 are all located between the first oxygen-containing structure 122 of the oxide insulating layer 120 and the first dielectric structure 132 of the first gate dielectric layer 130.

[0067] The second dielectric structure 134 is located above the second oxygen-containing structure 124, and the second oxygen-containing structure 124 is located between the second dielectric structure 134 and the buffer layer 110. The second oxygen-containing structure 124 and the second dielectric structure 134 are stacked on top of each other to form a protrusion structure P. In some embodiments, the material of the first gate dielectric layer 130 includes silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, or other suitable materials. In some embodiments, the thickness of the first gate dielectric layer 130 is 100 angstroms to 1000 angstroms.

[0068] The second metal oxide layer OS2 is located above the first dielectric structure 132 of the first gate dielectric layer 130 and overlaps the first channel region ch1 of the first metal oxide layer OS1. The first dielectric structure 132 is located between the first metal oxide layer OS1 and the second metal oxide layer OS2.

[0069] The third metal oxide layer OS3 is located on the protrusion P, covering the top and side surfaces of the protrusion P, and extends to the top surface of the buffer layer 110. The third metal oxide layer OS3 contacts the top surface of the second dielectric structure 134, the side surface of the second dielectric structure 134, the side surface of the second oxygen-containing structure 124, and the top surface of the buffer layer 110.

[0070] The third metal oxide layer OS3 includes a second drain region dr2, a second source region sr2, a second channel region ch2, a resistive gradient region g2a connecting the second drain region dr2 and the second channel region ch2, and a resistive gradient region g2b connecting the second source region sr2 and the second channel region ch2. The second channel region ch2 covers the top surface of the second dielectric structure 134, and the protrusion structure P is located between the buffer layer 110 and the second channel region ch2. The resistive gradient regions g2a and g2b contact the sides of the protrusion structure P (including the sides of the second dielectric structure 134 and the sides of the second oxygen-containing structure 124). The second drain region dr2 and the second source region sr2 extend from the sides of the protrusion structure P in a direction away from the protrusion structure P, and the second drain region dr2 and the second source region sr2 contact the top surface of the buffer layer 110. The distance between the second channel region ch2 and the substrate 100 is greater than the distance between the second drain region dr2 and the substrate 100 and the distance between the second source region sr2 and the substrate 100.

[0071] In some embodiments, the protrusion P beneath the third metal oxide layer OS3 replenishes oxygen in the third metal oxide layer OS3, increasing its resistivity and thereby preventing the thin-film transistor (TFT) from short-circuiting due to the low resistivity of the second channel region ch2. Furthermore, in some embodiments, the first dielectric structure 132 beneath the second metal oxide layer OS2 also replenishes oxygen in the second metal oxide layer OS2, thereby adjusting its resistivity.

[0072] The overall thickness of the protrusion P affects its ability to replenish oxygen in the third metal oxide layer OS3, thus affecting the resistivity of the third metal oxide layer OS3 in different regions. Specifically, below the second channel region ch2, the overall thickness of the protrusion P is larger, therefore the resistivity of the second channel region ch2 is larger; below the resistance gradient regions g2a and g2b, the overall thickness of the protrusion P gradually decreases, therefore the resistivity of the resistance gradient regions g2a and g2b also gradually decreases. In other words, the resistivity of the resistance gradient regions g2a and g2b decreases as they move away from the second channel region ch2; there is no protrusion P below the second drain region dr2 and the second source region sr2, and the second drain region dr2 and the second source region sr2 have lower resistivity than the second channel region ch2, the resistance gradient regions g2a and g2b. In some embodiments, the oxygen concentration in the second channel region ch2 is greater than the oxygen concentration in the resistance gradient regions g2a and g2b, and the oxygen concentration in the resistance gradient regions g2a and g2b is greater than the oxygen concentration in the second drain region dr2 and the second source region sr2.

[0073] In some embodiments, the materials of the first metal oxide layer OS1, the second metal oxide layer OS2, and the third metal oxide layer OS3 include indium gallium tin zinc oxide (IGTZO) or indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), indium tungsten zinc oxide (IWZO), or oxides containing any three of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W), or lanthanide rare earth doped metal oxides (e.g., Ln-IZO). In some embodiments, the first metal oxide layer OS1, the second metal oxide layer OS2, and the third metal oxide layer OS3 comprise the same material. In other embodiments, the material of the first metal oxide layer OS1 is different from the materials of the second metal oxide layer OS2 and the third metal oxide layer OS3. In some embodiments, the second metal oxide layer OS2 and the third metal oxide layer OS3 belong to the same patterned layer. In some embodiments, the carrier mobility of the second metal oxide layer OS2 and the carrier mobility of the second channel region ch2 of the third metal oxide layer OS3 are greater than the carrier mobility of the first channel region ch1 of the first metal oxide layer OS1, thereby improving the switching speed of the thin-film transistor TFT.

[0074] The second gate dielectric layer 140 is located above the buffer layer 110, the first dielectric structure 132 of the first gate dielectric layer 130, the second metal oxide layer OS2, and the third metal oxide layer OS3. The second metal oxide layer OS2 is located between the first dielectric structure 132 of the first gate dielectric layer 130 and the second gate dielectric layer 140. The third metal oxide layer OS3 is located between the second dielectric structure 134 of the first gate dielectric layer 130 and the second gate dielectric layer 140, and between the buffer layer 110 and the second gate dielectric layer 140. In some embodiments, the material of the second gate dielectric layer 140 includes silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, or other suitable materials. In some embodiments, the thickness of the second gate dielectric layer 140 is 500 angstroms to 2000 angstroms. In some embodiments, the thickness of the first gate dielectric layer 140 is less than the thickness of the second gate dielectric layer 130, thereby making it easier for electrons to tunnel from the first channel region ch1 to the second metal oxide layer OS2, thereby improving the switching speed of the memory device ROM.

[0075] The first gate G1 and the second gate G2 are located on the second gate dielectric layer 140 and overlap the first channel region ch1 of the first metal oxide layer OS1 and the second channel region ch2 of the third metal oxide layer OS3, respectively. The second gate dielectric layer 140 is located between the first gate G1 and the second metal oxide layer OS2, and between the second gate G2 and the third metal oxide layer OS3. The second metal oxide layer OS2 is located between the first gate G1 and the first channel region ch1 of the first metal oxide layer OS1.

[0076] In some embodiments, the materials of the first gate G1 and the second gate G2 may include metals, such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), tin (Sn), lead (Pb), hafnium (Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn), or alloys of any combination of the above metals, or stacks of the above metals and / or alloys, but the present invention is not limited thereto. The first gate G1 and the second gate G2 may also use other conductive materials, such as metal nitrides, metal oxides, metal oxynitrides, stacks of metals and other conductive materials, or other materials with conductive properties.

[0077] An interlayer dielectric layer 150 is located on the second gate dielectric layer 140 and covers the first gate G1 and the second gate G2. In some embodiments, the material of the interlayer dielectric layer 150 includes silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, or other insulating materials.

[0078] The first contact hole V1 and the second contact hole V2 pass through the interlayer dielectric layer 150, the second gate dielectric layer 140, and the first dielectric structure 132. The first drain D1 and the first source S1 are located on the interlayer dielectric layer 150 and are respectively filled into the first contact hole V1 and the second contact hole V2 to electrically connect to the first metal oxide layer OS1. The first drain D1 and the first source S1 are respectively connected to the first drain region dr1 and the first source region sr1 of the first metal oxide layer OS1.

[0079] The third contact hole V3 and the fourth contact hole V4 pass through the interlayer dielectric layer 150 and the second gate dielectric layer 140. The second drain D2 and the second source S2 are located on the interlayer dielectric layer 150 and are respectively filled into the third contact hole V3 and the fourth contact hole V4 to electrically connect to the third metal oxide layer OS3. The second drain D2 and the second source S2 are respectively connected to the second drain region dr2 and the second source region sr2 of the third metal oxide layer OS3.

[0080] The materials of the first drain D1, the first source S1, the second drain D2, and the second source S2 may include metals, such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc (or any combination of the above metals or a stack of the above metals and / or alloys, but the present invention is not limited thereto). The first drain D1, the first source S1, the second drain D2, and the second source S2 may also use other conductive materials, such as metal nitrides, metal oxides, metal oxynitrides, stacks of metals and other conductive materials, or other materials with conductive properties.

[0081] Figure 2A yes Figure 1 The circuit diagram of the memory circuit. Figure 2B yes Figure 2A The signal diagram of the memory circuit. In Figure 2B In the diagram, the vertical axis represents voltage, and the horizontal axis represents time.

[0082] Please also refer to Figure 1 and Figure 2A The memory circuit 10 also includes a word line WL, a bit line BL, a data line DL, and a source line SL. The word line WL is electrically connected to the second gate G2 of the thin-film transistor (TFT). The bit line BL is electrically connected to the second drain D2 of the TFT. The second source S2 of the TFT is electrically connected to the first gate G1 of the memory device ROM. The data line DL is electrically connected to the first drain D1 of the memory device ROM. The source line SL is electrically connected to the first source S1 of the memory device ROM.

[0083] Please refer to Figure 1 , Figure 2A and Figure 2BWhen executing a write instruction for the memory device ROM, a voltage is applied to the second gate G2 of the thin-film transistor TFT via the word line WL to turn on the TFT, and simultaneously a first voltage (e.g., 15V to 30V) is applied to the second drain D2 of the TFT via the bit line BL. The signal on the bit line BL is transmitted to the first gate G1 of the memory device ROM, and an electric field causes electrons to tunnel from the first metal oxide layer OS1 through the first dielectric structure 132 of the first gate dielectric layer 130 to the second metal oxide layer OS2. Since electrons are stored in the second metal oxide layer OS2, the threshold voltage (Vth) of the memory device ROM is changed.

[0084] When executing a read instruction for the memory device ROM, a voltage is applied to the second gate G2 of the thin-film transistor (TFT) via the word line WL to turn on the TFT, and simultaneously a second voltage (e.g., 5V to 15V) is applied to the second drain D2 of the TFT via the bit line BL. The signal on the bit line BL is transmitted to the first gate G1 of the memory device ROM to turn on the ROM, and simultaneously a voltage is applied to the first drain D1 of the memory device ROM via the data line DL, creating a voltage difference between the first drain D1 and the first source S1 of the memory device ROM, allowing the signal to pass through the memory device ROM. By reading the signal passing through the memory device ROM, it can be determined whether the memory device ROM is currently in state "1" or state "0". The second voltage used when executing the read instruction is lower than the first voltage used when executing the write instruction; therefore, the threshold voltage of the memory device ROM is less likely to change due to electron tunneling when executing the write instruction.

[0085] When executing the erase command of the memory device ROM, a voltage is applied to the second gate G2 of the thin-film transistor TFT via the word line WL to turn on the thin-film transistor TFT, and simultaneously a third voltage (e.g., -15V to -30V) is applied to the second drain D2 of the thin-film transistor TFT via the bit line BL. The signal on the bit line BL is transmitted to the first gate G1 of the memory device ROM, and an electric field causes electrons to tunnel from the second metal oxide layer OS2 through the first dielectric structure 132 of the first gate dielectric layer 130 into the first metal oxide layer OS1, thereby allowing the threshold voltage of the memory device ROM to return to its original value.

[0086] Based on the above, the memory device ROM has the advantage of fast access speed.

[0087] Figures 3A to 3F yes Figure 1 A cross-sectional schematic diagram of the manufacturing method of the memory circuit.

[0088] Please refer to Figure 3AA buffer layer 110 and an oxide insulating layer 120 are formed on the substrate 100. In some embodiments, the buffer layer 110 is blanketed on the substrate 100, and the oxide insulating layer 120 is blanketed on the buffer layer 110.

[0089] Next, a first metal oxide layer OS1' is formed on the oxide insulating layer 120. In some embodiments, the method of forming the first metal oxide layer OS1' includes: forming a first semiconductor material layer (not shown) on the oxide insulating layer 120; forming a patterned photoresist (not shown) on the aforementioned first semiconductor material layer; etching the first semiconductor material layer using the patterned photoresist as a mask to form the first metal oxide layer OS1'; and finally, removing the patterned photoresist.

[0090] Please refer to Figure 3B A first gate dielectric layer 130 is formed on the first metal oxide layer OS1' and the oxide insulating layer 120. In some embodiments, the first gate dielectric layer 130 is blanketed on the first metal oxide layer OS1' and the oxide insulating layer 120.

[0091] Please refer to Figure 3C A patterning process is performed on the oxide insulating layer 120 and the first gate dielectric layer 130, such that the oxide insulating layer 120 includes a first oxygen-containing structure 122 and a second oxygen-containing structure 124, and the first gate dielectric layer 130 includes a first dielectric structure 132 and a second dielectric structure 134. A first metal oxide layer OS1' is located between the first oxygen-containing structure 122 and the first dielectric structure 132. The second oxygen-containing structure 124 and the second dielectric structure 134 are stacked to form a protrusion structure P. In some embodiments, the aforementioned patterning process includes wet etching or dry etching, and the etching in the aforementioned patterning process stops at the buffer layer 110.

[0092] In some embodiments, the oxide insulating layer 120 and the first gate dielectric layer 130 are patterned using the same photomask, so that the sidewalls of the first oxygen-containing structure 122 are aligned with the first dielectric structure 132, and the sidewalls of the second oxygen-containing structure 124 are aligned with the second dielectric structure 134.

[0093] Please refer to the following: Figure 3DA second metal oxide layer OS2 and a third metal oxide layer OS3' are formed on the first gate dielectric layer 130. In this embodiment, the second metal oxide layer OS2 is formed on the first dielectric structure 132 of the first gate dielectric layer 130, and the third metal oxide layer OS3' is formed on the top surface of the protrusion structure P, the side surface of the protrusion structure P, and the buffer layer 110. In some embodiments, the method of forming the second metal oxide layer OS2 and the third metal oxide layer OS3' includes: forming a second semiconductor material layer (not shown) on the buffer layer 110, the oxide insulating layer 120, and the first gate dielectric layer 130; forming a patterned photoresist (not shown) on the aforementioned second semiconductor material layer; etching the second semiconductor material layer using the patterned photoresist as a mask to form the second metal oxide layer OS2 and the third metal oxide layer OS3'; and finally, removing the patterned photoresist. In this embodiment, since the first metal oxide layer OS1' is covered by the first oxygen-containing structure 122 and the first dielectric structure 132, the aforementioned etching process will not damage the first metal oxide layer OS1'.

[0094] Please refer to Figure 3E A second gate dielectric layer 140 is formed on the second metal oxide layer OS2 and the third metal oxide layer OS3'. In this embodiment, the second gate dielectric layer 140 is located on the second metal oxide layer OS2, the first dielectric structure 132, the buffer layer 110, and the third metal oxide layer OS3'.

[0095] A first gate G1 and a second gate G2 are formed on the second gate dielectric layer 140. A second metal oxide layer OS2 is located between the first gate G1 and the first metal oxide layer OS1', and the second gate G2 overlaps the third metal oxide layer OS3'.

[0096] In some embodiments, prior to the formation of the first gate G1 and the second gate G2, a thermal processing step is performed to diffuse oxygen from the protrusion structure P into the third metal oxide layer OS3', thereby increasing the resistivity of the third metal oxide layer OS3' located on the protrusion structure P. In some embodiments, the thermal processing step also diffuses oxygen from the first dielectric structure 132 into the second metal oxide layer OS2, thereby increasing the resistivity of the second metal oxide layer OS2. In some embodiments, the aforementioned thermal processing step is, for example, a heating process during the deposition of the second gate dielectric layer 140, but the present invention is not limited thereto.

[0097] Next, using the first gate G1 and the second gate G2 as masks, a doping fabrication process DP is performed on the first metal oxide layer OS1' and the third metal oxide layer OS3'. This forms the first metal oxide layer OS1, which includes a first source region sr1, a first drain region dr1, and a first channel region ch1, and the third metal oxide layer OS3, which includes a second source region sr2, a second drain region dr2, a resistance gradient region g2a, a resistance gradient region g2b, and a second channel region ch2. In some embodiments, the doping fabrication process DP is, for example, a hydrogen plasma fabrication process or other suitable fabrication process. In some embodiments, the first gate G1 completely masks the second metal oxide layer OS2 in the normal direction ND of the top surface of the substrate 100. Therefore, the first source region sr1 and the first drain region dr1 are not masked by the second metal oxide layer OS2 during the doping fabrication process DP.

[0098] In some embodiments, the buffer layer 110 provides hydrogen to the third metal oxide layer OS3 during the fabrication process, thereby reducing the resistivity of the second source region sr2 and the second drain region dr2.

[0099] In this embodiment, the first gate G1 and the second gate G2 belong to the same patterning layer, and the first metal oxide layer OS1 and the second metal oxide layer OS2 can be doped by the same doping process DP, thus saving the manufacturing cost of memory devices and thin film transistors.

[0100] Please refer to Figure 3F An interlayer dielectric layer 150 is formed on the second gate dielectric layer 140. Next, an etching process is performed to form the first contact hole V1, the second contact hole V2, the third contact hole V3, and the fourth contact hole V4.

[0101] Finally, please return to Figure 1 A first drain D1, a first source S1, a second drain D2, and a second source S2 are formed on the interlayer dielectric layer 150 and respectively filled into the first contact hole V1, the second contact hole V2, the third contact hole V3, and the fourth contact hole V4. At this point, the memory circuit 10 is substantially complete. In some embodiments, the method for forming the first source S1, the first drain D1, the second source S2, and the second drain D2 includes: forming a conductive material layer (not shown) on the interlayer dielectric layer 150; forming a patterned photoresist (not shown) on the aforementioned conductive material layer; and applying the patterned photoresist...

[0102] Using photoresist as a mask, a conductive material layer is etched to form a first source S1, a first drain D1, a second source S2, and a second drain D2; finally, the patterned photoresist is removed. In other words, the first...

[0103] The source S1, the first drain D1, the second source S2, and the second drain D2 belong to the same patterned layer.

[0104] Figure 4 This is a cross-sectional schematic diagram of a memory circuit according to an embodiment of the present invention. It must be noted that... Figure 4 The embodiments follow Figure 1 The component reference numerals and partial contents of the embodiments, wherein

[0105] The same or similar reference numerals are used to represent the same or similar elements, and the description of the same technical content 0 is omitted. For the explanation of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0106] Figure 4 The memory circuit 20 and Figure 1 The main difference in memory circuit 10 is that the thin-film transistor (TFT) of memory circuit 20 also includes a bottom gate (BG).

[0107] Please refer to Figure 4 The bottom gate BG is located on the substrate 100. The buffer layer 110 is located on the bottom gate BG.

[0108] Above. The third metal oxide layer OS3 is located between the bottom gate BG and the second gate G2, and the protrusion structure P is located between the bottom gate BG and the third metal oxide layer OS3. In some embodiments, the bottom gate...

[0109] The length L2 of the gate BG is greater than the length L1 of the second gate G2.

[0110] Figure 5 This is a cross-sectional schematic diagram of a memory circuit according to an embodiment of the present invention. It must be noted that... Figure 5 The embodiments follow Figure 1 The component reference numerals and partial contents of the embodiments, wherein

[0111] The same or similar reference numerals are used to represent the same or similar elements, and the description of the same technical content 0 is omitted. For the explanation of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0112] Figure 5 The memory circuit 30 and Figure 1 The main difference between the memory circuit 10 and the memory circuit 30 is that the first metal oxide layer OS1 of the memory device ROM of the memory circuit 30 includes a resistive gradient region g1a and a resistive gradient region g1b. The resistive gradient region g1a is connected to the first drain region dr1 and the first channel region.

[0113] Between ch1, the resistance-gradient region g1b is connected between the first source region sr1 and the first channel region ch1. (See reference 5) Figure 5 The first channel region ch1 of the first metal oxide layer OS1 is located in the first oxygen-containing junction.

[0114] The first oxygen-containing structure 122 is located on the structure 122, and the first oxygen-containing structure 122 is located between the first channel region ch1 and the buffer layer 110. The resistance gradient region g1a and the second resistance gradient region g1b of the first metal oxide layer OS1 contact the side of the first oxygen-containing structure 122. The first drain region dr1 and the first source region sr1 are located on the first oxygen-containing structure 122.

[0115] The side extends away from the first oxygen-containing structure 122, and the first drain region dr1 and the first source region sr1 contact the top surface of the buffer layer 110. The distance between the first channel region ch1 and the substrate 100 is greater than...

[0116] The distance between the first drain region dr1 and the substrate 100 and the distance between the first source region sr1 and the substrate 100.

[0117] In some embodiments, the first oxygen-containing structure 122 beneath the first metal oxide layer OS1 replenishes oxygen to the first metal oxide layer OS1, thereby increasing the resistivity of the first metal oxide layer OS1 and preventing the memory device ROM from short-circuiting due to the low resistivity of the first channel region ch1.

[0118] The thickness of the first oxygen-containing structure 122 affects its ability to replenish oxygen in the first metal oxide layer OS1, thus affecting the resistivity of the first metal oxide layer OS1 in different regions. Specifically, below the first channel region ch1, the thickness of the first oxygen-containing structure 122 is larger, therefore the resistivity of the first channel region ch1 is larger; below the resistance gradient regions g1a and g1b, the thickness of the first oxygen-containing structure 122 gradually decreases, therefore the resistivity of the resistance gradient regions g1a and g1b also gradually decreases. In other words, the resistivity of the resistance gradient regions g1a and g1b decreases as they move away from the first channel region ch1. The first drain region dr1 and the first source region sr1 do not have the first oxygen-containing structure 122 below them, and the first drain region dr1 and the first source region sr1 have lower resistivity than the first channel region ch1, the resistance gradient regions g1a and g1b. In some embodiments, the oxygen concentration in the first channel region ch1 is greater than the oxygen concentration in the resistance gradient regions g1a and g1b, and the oxygen concentration in the resistance gradient regions g1a and g1b is greater than the oxygen concentration in the first drain region dr1 and the first source region sr1.

[0119] In some embodiments, the buffer layer 110 provides hydrogen to the first metal oxide layer OS1 during the fabrication process, thereby reducing the resistivity of the first source region sr1 and the first drain region dr1.

[0120] In summary, the second metal oxide layer OS2 of the memory device ROM of the present invention is located between the first gate G1 and the first metal oxide layer OS1. By applying a voltage to the first gate G1, electrons can tunnel between the first metal oxide layer OS1 and the second metal oxide layer OS2, thereby enabling the memory device ROM to switch quickly.

Claims

1. A memory circuit, comprising: substrate; An oxide insulating layer is located on the substrate and includes a first oxygen-containing structure and a second oxygen-containing structure. A first gate dielectric layer is located on the oxide insulating layer and includes a first dielectric structure and a second dielectric structure, wherein the second oxygen-containing structure and the second dielectric structure are stacked on each other to form a protrusion structure. The second gate dielectric layer is located above the first gate dielectric layer; Memory device, comprising: A first metal oxide layer is located on the first oxygen-containing structure; A second metal oxide layer, wherein the first dielectric structure is located between the first metal oxide layer and the second metal oxide layer; A first gate, wherein the second gate dielectric layer is located between the second metal oxide layer and the first gate, and the second metal oxide layer is located between the first gate and the first metal oxide layer; and The first source and the first drain are electrically connected to the first metal oxide layer; and Thin-film transistors, including: A third metal oxide layer covers the top and sides of the protruding structure; A second gate electrode is superimposed on the third metal oxide layer, and a second gate dielectric layer is located between the second gate electrode and the third metal oxide layer; and The second source and the second drain are electrically connected to the third metal oxide layer.

2. The memory circuit of claim 1, wherein the third metal oxide layer comprises: The channel area covers the top surface of the raised structure; The first and second resistance gradient regions contact the side of the protruding structure, wherein the resistivity of the first and second resistance gradient regions decreases as they move away from the channel region. as well as The source region and the drain region extend from the side of the protrusion structure away from the protrusion structure, wherein the first resistance gradient region is connected between the channel region and the source region, and the second resistance gradient region is connected between the channel region and the drain region.

3. The memory circuit as described in claim 2, further comprising: A buffer layer is located on the substrate and contains hydrogen. The protrusion structure is located between the channel region and the buffer layer, and the source region and the drain region are in contact with the buffer layer.

4. The memory circuit as described in claim 1, further comprising: The word line is electrically connected to the second gate. The bit line is electrically connected to the second drain, and the second source is electrically connected to the first gate; The data cable is electrically connected to the first drain electrode; The source wire is electrically connected to the first source.

5. The memory circuit of claim 1, wherein the thin-film transistor further comprises: The bottom gate, wherein the third metal oxide layer is located between the bottom gate and the second gate, and the protrusion structure is located between the bottom gate and the third metal oxide layer.

6. The memory circuit of claim 5, wherein the length of the bottom gate is greater than the length of the second gate.

7. The memory circuit of claim 1, wherein the second metal oxide layer and the third metal oxide layer belong to the same patterned layer.

8. A method for manufacturing a memory circuit, comprising: An oxide insulating layer is formed on the substrate; A first metal oxide layer is formed on the oxide insulating layer; A first gate dielectric layer is formed on the first metal oxide layer; A second metal oxide layer is formed on the first gate dielectric layer; A second gate dielectric layer is formed on the second metal oxide layer; A first gate is formed on the second gate dielectric layer, wherein the second metal oxide layer is located between the first gate and the first metal oxide layer; a source and a drain are formed that are electrically connected to the first metal oxide layer; A patterning process is performed on the oxide insulating layer and the first gate dielectric layer to make the oxide insulating layer include a first oxygen-containing structure and a second oxygen-containing structure, and to make the first gate dielectric layer include a first dielectric structure and a second dielectric structure, wherein the second oxygen-containing structure and the second dielectric structure are stacked on each other to form a protruding structure. The second metal oxide layer is formed on the first dielectric structure of the first gate dielectric layer, and the third metal oxide layer is formed on the top surface and side surface of the protrusion structure; The second gate dielectric layer is formed on the second metal oxide layer and the third metal oxide layer; The first gate and the second gate are formed on the second gate dielectric layer, wherein the second gate overlaps the third metal oxide layer; A second source and a second drain are formed that are electrically connected to the third metal oxide layer.

9. The method for manufacturing a memory circuit as described in claim 8, further comprising: Using the first gate and the second gate as masks, a doping process is performed on the first metal oxide layer and the third metal oxide layer.

10. The method for manufacturing a memory circuit as described in claim 8, further comprising: Before forming the first gate and the second gate, a heat treatment fabrication process is performed to allow oxygen in the protrusion structure to diffuse into the third metal oxide layer.

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