3D storage devices and their manufacturing methods

Abstract

Disclosed are a 3D memory device and a manufacturing method thereof. The 3D memory device comprises: a substrate; a gate stack structure located above the substrate, the gate stack structure comprising a plurality of interlayer insulation layers and a plurality of gate conductors stacked alternately; and a plurality of channel columns penetrating through the gate stack structure, the channel column comprising a functional layer located at a sidewall of the channel column, an oxide layer located at a bottom of the channel column, and a channel layer located on the functional layer and the oxide layer; the channel layer is located above an epitaxial layer and in contact with the epitaxial layer; wherein the functional layer comprises a gate oxide layer, a charge storage layer located on the gate oxide layer, and a tunneling oxide layer located on the charge storage layer; the charge storage layer is isolated from the channel layer at a corner of the functional layer. In the embodiment of the present application, the charge storage layer is isolated from the channel layer at the corner of the functional layer, so as to avoid the charge on the charge storage layer from leaking into the channel layer, thereby improving the stability of the threshold voltage of the bottom select gate of the 3D memory.

Description

[0001] This application is a divisional application of Chinese patent application filed on December 31, 2019, with application number 201911421883.2 and entitled "3D storage device and manufacturing method thereof". Technical Field

[0002] This invention relates to the field of memory technology, and in particular to 3D memory devices and their manufacturing methods. Background Technology

[0003] The increase in storage density of memory devices is closely related to advancements in semiconductor manufacturing processes. As the aperture of semiconductor manufacturing processes becomes smaller, the storage density of memory devices increases. To further improve storage density, three-dimensional memory devices (i.e., 3D memory devices) have been developed. 3D memory devices consist of multiple memory cells stacked along a vertical direction, which can multiply the integration density on a unit area of ​​wafer and reduce costs.

[0004] The formation process of existing 3D NAND memory generally includes: forming a stacked layer of alternating silicon nitride and silicon oxide layers on a substrate; etching the stacked layer to form a channel hole in the stacked layer; after forming the channel hole, etching the substrate at the bottom of the channel hole to form a groove in the substrate; forming an epitaxial silicon layer, usually called SEG, in the groove at the bottom of the channel hole by selective epitaxial growth; forming a functional layer and a channel layer in the sidewalls and bottom of the channel hole, the channel layer being connected to the epitaxial silicon layer (SEG); removing the silicon nitride layer, and forming a gate metal at the location where the silicon nitride layer was removed.

[0005] The functional layer includes a gate oxide layer, a charge storage layer on the gate oxide layer, and a tunneling oxide layer on the charge storage layer. The selected material can be a single-layer or multi-layer combination structure of oxide-nitride-oxide (ONO). The axial cross-section of the functional layer (ONO layer) can be two opposing L-shapes. The charge storage layer and the channel layer are in direct contact at the corner of the functional layer (L-foot position), which will generate high electrical resistivity at the corner. Due to the poor charge binding ability of the bottom select gate (BSG), the charge on the charge storage layer can easily leak into the channel layer, causing the threshold voltage Vt of the bottom select gate BSG to shift, affecting the performance of the 3D memory device, especially during erase or read / write processes. After repeated erase or read / write operations, a large amount of charge will accumulate at the corner, further shifting the threshold voltage Vt of the bottom select gate BSG. Summary of the Invention

[0006] In view of the above problems, the purpose of the present invention is to provide a 3D memory device and a method for manufacturing the same, wherein the charge storage layer and the channel layer are isolated at the corner of the functional layer, thereby improving the stability of the threshold voltage of the bottom select gate of the 3D memory.

[0007] According to one aspect of the present invention, a method for manufacturing a 3D memory device is provided, comprising: forming an insulating stack structure over a substrate, the insulating stack structure including a plurality of alternately stacked interlayer insulating layers and a plurality of sacrificial layers; forming a plurality of channel pillars penetrating the insulating stack structure, the step of forming the channel pillars comprising: forming a plurality of channel holes penetrating the insulating stack structure and a portion of the substrate; forming an epitaxial layer at the bottom of the channel holes, the epitaxial layer being in contact with the semiconductor substrate; and forming a functional layer on the sidewalls and bottom of the channel holes, wherein the functional layer includes a gate oxide layer, a charge storage layer located on the gate oxide layer, and a tunneling oxide layer located on the charge storage layer; removing the charge storage layer at the bottom of the channel holes; forming a channel layer on the functional layer, the channel layer being located above and in contact with the epitaxial layer; wherein the charge storage layer is isolated from the channel layer at the corners of the functional layer.

[0008] Preferably, the steps of forming a functional layer on the sidewall of the channel hole and removing the charge storage layer at the bottom of the channel hole include: forming the functional layer on the sidewall and bottom of the channel hole; etching the functional layer on the bottom of the channel hole to form a first opening exposing the epitaxial layer; removing the charge storage layer at the bottom of the channel hole to form a void; and forming an oxide layer on the surface of the functional layer, in the void, and on the sidewall and bottom surfaces of the first opening.

[0009] Preferably, the step of forming the void includes: when removing the charge storage layer at the bottom of the channel hole, the charge storage layer has a high etch selectivity relative to the gate oxide layer and the tunnel oxide layer.

[0010] Preferably, the etching rate ratio of the charge storage layer to the gate oxide layer and the tunneling oxide layer is at least greater than 30:1.

[0011] Preferably, forming a channel layer on the functional layer includes: forming a first channel layer on the functional layer and the oxide layer; etching the first channel layer and the oxide layer at the bottom of the first channel hole to form a second opening that exposes the epitaxial layer; and forming a second channel layer on the surface of the first channel layer and the bottom and sidewall surfaces of the second opening.

[0012] Preferably, the method for manufacturing the 3D storage device further includes: forming a filling layer on the channel layer; removing the filling layer at the top of the channel hole to form a groove, and forming a plug structure in the groove.

[0013] Preferably, the method for manufacturing the 3D memory device further includes: replacing the plurality of sacrificial layers with a plurality of gate conductors to form a gate stack structure.

[0014] According to another aspect of the present invention, a 3D memory device is provided, comprising: a substrate; a gate stack structure located above the substrate, the gate stack structure including a plurality of alternately stacked interlayer insulating layers and a plurality of gate conductors; and a plurality of channel pillars penetrating the gate stack structure, each channel pillar including a functional layer located on a sidewall of the channel pillar, an oxide layer located at a bottom of the channel pillar, and a channel layer located on the functional layer and the oxide layer; the channel layers are located above and in contact with the epitaxial layer; wherein the functional layer includes a gate oxide layer, a charge storage layer located on the gate oxide layer, and a tunneling oxide layer located on the charge storage layer; the charge storage layer is isolated from the channel layer at a corner of the functional layer.

[0015] Preferably, the charge storage layer has a high etch selectivity relative to the gate oxide layer and the tunneling oxide layer.

[0016] Preferably, the etching rate ratio of the charge storage layer to the gate oxide layer and the tunneling oxide layer is at least greater than 30:1.

[0017] Preferably, the 3D storage device further includes: a filling layer located in the channel post, the filling layer being in contact with the channel layer; and a plug structure located on the filling layer.

[0018] The present invention provides a 3D memory device and a method for manufacturing the same, wherein a functional layer is formed on the sidewall and bottom of the channel hole, wherein the functional layer includes a gate oxide layer, a charge storage layer located on the gate oxide layer, and a tunneling oxide layer located on the charge storage layer; the charge storage layer at the bottom of the channel hole is removed; a channel layer is formed on the functional layer; and the charge storage layer is isolated from the channel layer at the corner of the functional layer to prevent charge leakage from the charge storage layer into the channel layer, thereby improving the stability of the threshold voltage of the bottom select gate of the 3D memory. Attached Figure Description

[0019] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0020] Figure 1a and Figure 1b The circuit diagram and structural schematic diagram of the storage cell string of the 3D storage device are shown respectively;

[0021] Figure 2 A perspective view of a 3D storage device is shown;

[0022] Figures 3a to 3jCross-sectional views are shown of various stages of a 3D storage device manufacturing method according to an embodiment of the present invention. Detailed Implementation

[0023] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0024] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0025] In this invention, "above" refers to a location above the substrate plane, which can refer to direct contact between materials or spaced apart.

[0026] In this application, the term "semiconductor structure" refers to the collective term for the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. Many specific details of the invention, such as the structure, materials, dimensions, processing techniques, and methods of the device, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without adhering to these specific details.

[0027] This invention can be presented in various forms, some of which will be described below.

[0028] Figure 1a and 1b The circuit diagram and structural schematic diagram of the storage cell string of the 3D storage device are shown respectively. In this embodiment, the storage cell string shown includes four storage cells. It is understood that the invention is not limited thereto, and the number of storage cells in the storage cell string can be any number, for example, 32 or 64.

[0029] like Figure 1a As shown, the first end of the memory cell string 100 is connected to the bit line BL, and the second end is connected to the source line SL. The memory cell string 100 includes a plurality of transistors connected in series between the first and second ends, including: a first selection transistor Q1, memory cells M1 to M4, and a second selection transistor Q2. The gate of the first selection transistor Q1 is connected to the string selection line SSL, and the gate of the second selection transistor Q2 is connected to the ground selection line GSL. The gates of memory cells M1 to M4 are respectively connected to the corresponding word lines WL1 to WL4.

[0030] like Figure 1bAs shown, the selection transistors Q1 and Q2 of the memory cell string 100 each include a second conductor layer 122 and a third conductor layer 123, and the memory cells M1 to M4 each include a first conductor layer 121. The first conductor layer 121, the second conductor layer 122, and the third conductor layer 123 are arranged in the same order as the transistors in the memory cell string 100, and adjacent conductor layers are separated from each other by an insulating layer, thereby forming a gate stack structure.

[0031] Furthermore, the memory cell string 100 includes a memory string 110. The memory string 110 is adjacent to or penetrates the gate stack structure. In the middle portion of the memory string 110, a tunneling oxide layer 112, a charge storage layer 113, and a gate oxide layer 114 are sandwiched between the first conductor layer 121 and the channel layer 111, thereby forming memory cells M1 to M4. At both ends of the memory string 110, a gate oxide layer 114 is sandwiched between the second conductor layers 122 and 123 and the channel layer 111, thereby forming a first selection transistor Q1 and a second selection transistor Q2.

[0032] The channel layer 111 is composed, for example, of doped polysilicon; the tunneling oxide layer 112 and the gate oxide layer 114 are each composed of oxides, such as silicon oxide; the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals, such as silicon nitride containing metal or semiconductor particles; and the first conductor layer 121, the second conductor layer 122, and the third conductor layer 123 are composed of metals, such as tungsten. The channel layer 111 provides the channel region for the selection transistor and the control transistor, and the doping type of the channel layer 111 is the same as the type of the selection transistor and the control transistor. For example, for an N-type selection transistor and a control transistor, the channel layer 111 can be N-type doped polysilicon.

[0033] In this embodiment, the core of the memory string 110 is a channel layer 111, and a tunneling oxide layer 112, a charge storage layer 113, and a gate oxide layer 114 form a stacked structure surrounding the sidewalls of the core. In an alternative embodiment, the core of the memory string 110 is an additional insulating layer, and the channel layer 111, the tunneling oxide layer 112, the charge storage layer 113, and the gate oxide layer 114 form a stacked structure surrounding a semiconductor layer.

[0034] In this embodiment, the first selection transistor Q1 and the second selection transistor Q2, and the memory cells M1 to M4 use a common channel layer 111 and gate oxide layer 114. In the memory string 110, the channel layer 111 provides the source and drain regions of the plurality of transistors and the channel layer. In an alternative embodiment, the semiconductor layers and gate oxide layers of the first selection transistor Q1 and the second selection transistor Q2, as well as the semiconductor layers and gate oxide layers of the memory cells M1 to M4, can be formed in separate steps. In the memory string 110, the semiconductor layers of the first selection transistor Q1 and the second selection transistor Q2 are electrically connected to the semiconductor layers of the memory cells M1 to M4.

[0035] During the write operation, the memory cell string 100 utilizes FN tunneling efficiency to write data to selected memory cells M1 to M4. Taking memory cell M2 as an example, while the source line SL is grounded, the ground select line GSL is biased to approximately zero volts, causing the second select transistor Q2 corresponding to the ground select line GSL to turn off, and the string select line SSL is biased to a high voltage VDD, causing the select transistor Q1 corresponding to the string select line SSL to turn on. Further, the bit line BIT2 is grounded, the word line WL2 is biased to the programming voltage VPG, for example, around 20V, and the remaining word lines are biased to a low voltage VPS1. Since only the word line voltage of the selected memory cell M2 is higher than the tunneling voltage, electrons in the channel region of this memory cell M2 reach the charge storage layer 113 through the tunneling oxide layer 112, thereby converting the data into charge and storing it in the charge storage layer 113 of memory cell M2.

[0036] During the read operation, the storage cell string 100 determines the amount of charge in the functional layer based on the conduction state of selected storage cells M1 to M4, thereby obtaining the data represented by that charge amount. Taking storage cell M2 as an example, word line WL2 is biased at the read voltage VRD, while the other word lines are biased at a high voltage VPS2. The conduction state of storage cell M2 is related to its threshold voltage, i.e., related to the amount of charge in the functional layer, thus the data value can be determined based on the conduction state of storage cell M2. Storage cells M1, M3, and M4 are always in the conduction state; therefore, the conduction state of storage cell string 100 depends on the conduction state of storage cell M2. The control circuit determines the conduction state of storage cell M2 based on the electrical signals detected on bit line BL and source line SL, thereby obtaining the data stored in storage cell M2.

[0037] Figure 2 Perspective views of the 3D storage device are shown separately. For clarity, in Figure 2 The individual insulating layers in the 3D storage device are not shown.

[0038] The 3D storage device 200 shown in this embodiment includes 16 4x4 storage cell strings 100, each storage cell string 100 including 4 storage cells, thereby forming a 4x4x4 storage cell array with a total of 64 storage cells. It is understood that the present invention is not limited thereto; the 3D storage device may include any number of storage cell strings, for example, 1024, and the number of storage cells in each storage cell string may be any number, for example, 32 or 64.

[0039] In the 3D memory device 200, each memory cell string 100 includes its own channel pillar 110, and common first conductor layer 121, second conductor layer 122, and third conductor layer 123. The first conductor layer 121, second conductor layer 122, and third conductor layer 123 are arranged in the same order as the transistors in the memory cell string 100, and adjacent conductor layers are separated from each other by an insulating layer, thereby forming a gate stack structure 120. The insulating layer is not shown in the figure.

[0040] The internal structure of storage string 110 is as follows Figure 1b As shown, further details will not be provided here. In the middle portion of the memory string 110, the first conductor layer 121, together with the channel layer 111, tunnel oxide layer 112, charge storage layer 113, and gate oxide layer 114 inside the memory string 110, forms memory cells M1 to M4. At both ends of the memory string 110, the second conductor layer 122 and the third conductor layer 123, together with the channel layer 111 and gate oxide layer 114 inside the memory string 110, form the first selection transistor Q1 and the second selection transistor Q2.

[0041] The channel pillars 110 penetrate the gate stack structure 120 and are arranged in an array. The first ends of multiple memory strings 110 in the same column are connected to the same bit line (i.e., one of BL1-BL4), and the second ends are connected to the substrate 101. The second ends form a common source connection through the substrate 100.

[0042] The gate conductor 122 of the first selection transistor Q1 is divided into different gate lines by a gate line slit 102. The gate lines of multiple channel pillars 110 in the same row are connected to the same series select line (i.e., one of the series select lines SSL1 to SSL4).

[0043] The gate conductors 121 of the storage transistors M1 and M4 are connected together on different layers. If the gate conductors 121 of the storage transistors M1 and M4 are divided into different gate lines by gate line gaps 161, the gate lines on the same layer reach the interconnect layer 132 through their respective conductive channels 131, thereby interconnecting with each other, and then connected to the same word line (i.e., one of word lines WL1 to WL4) through conductive channels 133.

[0044] The gate conductors of the ground select transistor Q2 are connected as one. If the gate conductor 123 of the ground select transistor Q2 is divided into different gate lines by the gate line gap 161, the gate lines reach the interconnect layer 132 through their respective conductive channels 131, thereby interconnecting with each other, and then connected to the same ground select line GSL through the conductive channel 133.

[0045] Figures 3a to 3j Cross-sectional views are shown of various stages of a 3D storage device manufacturing method according to an embodiment of the present invention.

[0046] This method begins with a semiconductor structure that has already formed a channel via 102 and an epitaxial layer 103, such as Figure 3a As shown.

[0047] In this step, a deposition process, such as atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD), is used to form an insulating stack structure 150 on substrate 101, consisting of alternating stacked interlayer insulating layers 151 and sacrificial layers 152. A channel hole is formed through the insulating stack structure 150, and an epitaxial layer 103 is formed at the bottom of the channel hole. In this embodiment, substrate 101 is, for example, a single-crystal silicon substrate, interlayer insulating layer 151 is, for example, composed of silicon oxide, and sacrificial layer 152 is, for example, composed of silicon nitride. The sacrificial layer 152 will be replaced with a conductor layer in a subsequent gate formation process. Epitaxial layer 103 can be, for example, selective epitaxial growth (SEG).

[0048] In this embodiment, the insulating stack structure shown includes five sacrificial layers 152. In the manufacturing process of a specific 3D memory device, the number of sacrificial layers 152 may be set to other numbers according to the different requirements of different 3D memory devices for the number of memory cells.

[0049] Furthermore, a functional layer is formed on the sidewall of the channel hole 102, the functional layer including a gate oxide layer 114, a charge storage layer 113 located on the gate oxide layer, and a tunneling oxide layer 112 located on the charge storage layer, such as... Figure 3b As shown.

[0050] In this step, a gate oxide layer 114, a charge storage layer 113, and a tunneling oxide layer 112 (initial tunneling oxide layer) are formed within the channel via along its sidewalls and bottom. The selected materials can be single-layer and / or multi-layer combinations of oxide-nitride-oxide (ONO), but are not limited to the materials and combinations mentioned herein. In this embodiment, the gate oxide layer 114 and the tunneling oxide layer 112 are, for example, silicon oxide, and the charge storage layer 113 is, for example, silicon nitride. The gate oxide layer 114, the charge storage layer 113, and the tunneling oxide layer 112 are formed using a chemical vapor deposition process.

[0051] Further, the functional layer on the bottom of the channel hole 102 is etched to form a first opening 104 that exposes or extends into the epitaxial layer 103, such as... Figure 3c As shown.

[0052] In this step, the functional layer at the bottom of the channel hole is etched using an anisotropic dry etching process. In one embodiment, the anisotropic dry etching process is a plasma etching process, and the gas used in the plasma etching process includes a carbon-fluorine flammable gas.

[0053] Furthermore, the charge storage layer 113 on the bottom of the channel hole 102 is removed to form a void 105, such as Figure 3d As shown.

[0054] In this step, the charge storage layer 113 at the bottom of the channel hole is removed using dry etching. In one embodiment, the dry etching is anisotropic plasma etching. When removing the charge storage layer 113 at the bottom of the channel hole, the charge storage layer 113 has a high etching selectivity relative to the gate oxide layer 114 and the tunnel oxide layer 112, and the etching rate ratio of the charge storage layer 113 to the gate oxide layer 114 and the tunnel oxide layer 112 is at least greater than 30:1. Since the charge storage layer 113 is a nitride layer and the gate oxide layer 114 and the tunnel oxide layer 112 are oxide layers, that is, the charge storage layer 113 at the bottom of the channel hole is removed using an etching process with high etching selectivity for nitride layers (e.g., silicon nitride SiN) and oxide layers (e.g., silicon oxide), the amount of gate oxide layer 114 and tunnel oxide layer 112 on both sides of the first opening 104 is very small.

[0055] Furthermore, an oxide layer is formed on the surface of the functional layer, within the void 105, and on the sidewalls and bottom surface of the first opening 104, such as... Figure 3e As shown.

[0056] In this step, a tunneling oxide layer 112 is formed within the channel hole along the surface of the functional layer, within the void, and on the sidewalls and bottom surface of the first opening, such that the oxide layer at the bottom of the channel hole includes the gate oxide layer 114 and the tunneling oxide layer 112 located on the gate oxide layer. In some embodiments, there is no obvious interface between the gate oxide layer 114 and the tunneling oxide layer 112.

[0057] Furthermore, a first channel layer 111a is formed on the functional layer and the oxide layer, such as... Figure 3f As shown.

[0058] In this embodiment, the material of the first channel layer 111a is polysilicon. Further, the first channel layer 111a and the oxide layer on the bottom of the channel 102 are etched to form a second opening 106 that exposes or extends into the epitaxial layer. The oxide layer includes a gate oxide layer 114 and a tunneling oxide layer 112 located on the gate oxide layer, such as... Figure 3g As shown.

[0059] In this step, the first channel layer 111a and oxide layer on the bottom of the channel hole are etched using anisotropic dry etching. In one embodiment, the anisotropic dry etching process is a plasma etching process, and the gas used in the plasma etching process includes a carbon-fluorine containing gas.

[0060] Furthermore, a second channel layer 111b is formed on the surface of the first channel layer 111a and on the bottom and sidewall surfaces of the second opening 106, such as... Figure 3h As shown.

[0061] In this embodiment, the second channel layer 111b is made of polycrystalline silicon and formed by chemical vapor deposition. The second channel layer 111b and the first channel layer 111a together constitute the channel layer 111 of the NAND memory. At this time, the charge storage layer 113 is isolated from the channel layer 111.

[0062] Furthermore, a filling layer 115 is formed on the channel layer 111, and the filling layer 115 at the top of the channel hole 102 is removed to form a groove, in which a plug structure is formed, such as... Figure 3i As shown.

[0063] In this embodiment, the filler layer 115 is made of silicon oxide or other suitable material. Polycrystalline silicon is deposited within the groove to form a plug structure, which contacts the channel layer.

[0064] Furthermore, multiple gate conductors are used to replace the multiple sacrificial layers 152, thereby forming a gate stack structure 120, such as... Figure 3j .

[0065] In this step, the sacrificial layer 152 is replaced with gate conductors 121, 122, and 123, thereby forming a gate stack structure 120. The gate conductors 121, 122, and 123 can be made of metal or other conductive materials (such as polysilicon). In this embodiment, the conductive material is a metal, specifically one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni. The epitaxial layer 103 and the gate conductor 121 form a first selection transistor; the channel layer 111 and the gate conductor 122 form a plurality of storage transistors; and the channel layer 111 and the gate conductor 123 form a second selection transistor.

[0066] The present invention provides a 3D storage device and a method for manufacturing the same.

[0067] A functional layer is formed on the sidewall and bottom of the channel hole, wherein the functional layer includes a gate oxide layer, a charge storage layer on the gate oxide layer, and a tunneling oxide layer on the charge storage layer; the charge storage layer at the bottom of the channel hole is removed; a channel layer is formed on the functional layer; the charge storage layer is isolated from the channel layer at the corner of the functional layer to prevent charge leakage from the charge storage layer into the channel layer, thereby improving the stability of the threshold voltage of the bottom select gate of the 3D memory.

[0068] Other details of 3D storage devices, such as the structure of the storage array and peripheral interconnects, are not the focus of this invention and will not be described further here.

[0069] In the context of this invention, a three-dimensional storage device may be a 3D flash memory, such as a 3D NAND flash memory.

[0070] Flowcharts are used herein to illustrate the operations performed by the method according to embodiments of this application. It should be understood that the preceding operations are not necessarily performed in exact order. Instead, the steps can be processed in reverse order or simultaneously. Furthermore, other operations may be added to these processes, or one or more steps may be removed from them. For example, some steps are not essential and can therefore be omitted or replaced with other steps.

[0071] The semiconductor structure formed in the above embodiments can be used to obtain a three-dimensional memory device through subsequent conventional steps.

[0072] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A 3D memory device, characterized by, Comprising: a gate stack structure, the gate stack structure comprising a plurality of interlayer dielectric layers and a plurality of gate conductors stacked alternately; and a plurality of channel pillars penetrating through the gate stack structure; the channel pillars comprising, in a radial direction of the channel pillars, a channel layer, a tunneling oxide layer, a charge storage layer, and a gate oxide layer; wherein the gate oxide layer and the tunneling oxide layer are connected at least at a bottom of the charge storage layer, and a portion of the gate oxide layer and a portion of the tunneling oxide layer are stacked below the charge storage layer. 2.The 3D memory device of claim 1, wherein, The bottom of the charge storage layer is surrounded by the gate oxide layer and the tunneling oxide layer, and the charge storage layer is isolated from the channel layer. 3.The 3D memory device of claim 1, wherein, A height difference between a lowest surface of the bottom of the gate oxide layer and a bottom of the charge storage layer is greater than a thickness of the gate oxide layer in a radial direction of the channel pillars. 4.The 3D memory device of claim 1, wherein, An axial cross-section of the gate oxide layer comprises an L shape, and an axial cross-section of the tunneling oxide layer above the gate oxide layer comprises an L shape. 5.The 3D memory device of claim 4, wherein, The L-shaped axial cross-section of the gate oxide layer and the L-shaped axial cross-section of the tunneling oxide layer above the gate oxide layer are oppositely arranged on a same side of the channel pillars. 6.The 3D memory device of claim 1, wherein, The channel layer comprises a first channel layer surrounding a second channel layer. 7.The 3D memory device of claim 1, wherein, The 3D memory device further comprises: an epitaxial layer below the channel pillars, the epitaxial layer being in contact with the channel layer. 8.The 3D memory device of claim 1, wherein, The charge storage layer has a high etching selectivity ratio with respect to the gate oxide layer and the tunneling oxide layer. 9.The 3D memory device of claim 8, wherein, The etching rate ratio of the charge storage layer with respect to the gate oxide layer and the tunneling oxide layer is at least greater than 30:

1. 10.The 3D memory device of claim 1, wherein, The 3D memory device further comprises: a filling layer in the channel pillars, the filling layer being in contact with the channel layer; a plug structure on the filling layer.

11. A method for manufacturing a 3D memory device, comprising: Comprising: forming an insulating stack structure, the insulating stack structure comprising a plurality of interlayer dielectric layers and a plurality of sacrificial layers stacked alternately; forming a plurality of channel pillars penetrating through the insulating stack structure, the step of forming the channel pillars comprising: forming a plurality of channel holes penetrating through the insulating stack structure; forming, on a sidewall and a bottom of the channel hole, a gate oxide layer, a charge storage layer, a tunneling oxide layer, and a channel layer in a radial direction of the channel hole; wherein the gate oxide layer and the tunneling oxide layer are connected at least at a bottom of the charge storage layer, and a portion of the gate oxide layer and a portion of the tunneling oxide layer are stacked below the charge storage layer.

12. The manufacturing method according to claim 11, wherein The bottom of the charge storage layer is surrounded by the gate oxide layer and the tunneling oxide layer, and the charge storage layer is isolated from the channel layer.

13. The manufacturing method according to claim 11, wherein A height difference between a lowest surface of the bottom of the gate oxide layer and a bottom of the charge storage layer is greater than a thickness of the gate oxide layer in a radial direction of the channel pillars.

14. The manufacturing method according to claim 11, wherein The manufacturing method further comprises: forming an epitaxial layer on the bottom of the channel hole before forming the gate oxide layer; the gate oxide layer is formed above the epitaxial layer; and the channel layer is formed in contact with the epitaxial layer.

15. The manufacturing method according to claim 14, wherein The forming, on a sidewall and a bottom of the channel hole, a gate oxide layer, a charge storage layer, a tunneling oxide layer, and a channel layer in a radial direction of the channel hole comprises: A gate oxide layer, a charge storage layer, and an initial tunneling oxide layer are sequentially formed along a radial direction of the trench hole on a sidewall and a bottom of the trench hole; The initial tunneling oxide layer, the charge storage layer, and the gate oxide layer on the bottom of the trench hole are etched to form a first opening exposing the epitaxial layer; The charge storage layer on the bottom of the trench hole is removed to form a void; An oxide layer is formed on a surface of the initial tunneling oxide layer, in the void, and on a sidewall and a bottom surface of the first opening; wherein the remaining initial tunneling oxide layer and the oxide layer in the void are used to form the tunneling oxide layer; A channel layer is formed on the tunneling oxide layer, the channel layer being above and in contact with the epitaxial layer.

16. The manufacturing method according to claim 15, wherein The step of forming the void includes: The charge storage layer has a high etching selectivity ratio relative to the gate oxide layer and the tunneling oxide layer when the charge storage layer on the bottom of the trench hole is removed.

17. The manufacturing method according to claim 16, wherein The etching rate ratio of the charge storage layer relative to the gate oxide layer and the tunneling oxide layer is at least greater than 30:

1.

18. The manufacturing method of claim 15, wherein, The step of forming the channel layer includes: A first channel layer is formed on the tunneling oxide layer and the oxide layer; The first channel layer and the oxide layer on the bottom of the trench hole are etched to form a second opening exposing the epitaxial layer; A second channel layer is formed on a surface of the first channel layer and on a bottom and a sidewall surface of the second opening.

19. The manufacturing method of claim 11, wherein, The manufacturing method further includes: A filling layer is formed on the channel layer; The filling layer on the top of the trench hole is removed to form a recess, and a plug structure is formed in the recess.

20. The manufacturing method of claim 11, wherein, The manufacturing method further includes: A plurality of gate conductors are used to replace the plurality of sacrificial layers to form a gate stack structure.

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