Display driving circuit and method, LED display panel and display device

Abstract

A display driving circuit (10) and method, as well as an LED display panel (400) and a display device (900). The display driving circuit (10) comprises: an interface circuit (11) for acquiring a plurality of grayscale data and a plurality of current gain data; a command processing circuit (12) coupled to the interface circuit (11); a buffer circuit (13) coupled to the interface circuit (11) for buffering a plurality of grayscale data and a plurality of current gain data; a current source circuit (15) coupled to the command processing circuit (12) and comprising a plurality of channel current sources (151); a channel grayscale control circuit (17) coupled to the command processing circuit (12), the buffer circuit (13) and the current source circuit (15) for controlling the opening time of the plurality of channel current sources (151) according to the plurality of grayscale data; and a channel current control circuit (19) coupled to the buffer circuit (13) and the current source circuit (15) for controlling the output current of the plurality of channel current sources (151) according to the plurality of current gain data. Therefore, dynamic adjustment of channel current can be achieved to improve display bit depth.

Description

Technical Field

[0001] The present application relates to the field of display control technology, and in particular to a display driving circuit, an LED display panel, a display device and a display driving method. Background Art

[0002] At present, LED (Light Emitting Diode) display devices are applied to various fields due to their advantages such as low cost, low power consumption, high visibility, and freedom of assembly. At the same time, with the popularization of LED display devices, people's requirements for their display quality are getting higher and higher, so how to improve the display quality of LED display devices has become a research hotspot in this field.

[0003] As the application scenarios of LED increase, the brightness adjustability and universality of LED are receiving more and more attention. LED can be applied to outdoor high-brightness screens or indoor low-brightness conference screens; more and more customers require LED display devices to be able to adjust the brightness according to their own needs. An existing sixteen-output channel PWM (Pulse Width Modulation) type LED display driver chip based on a grayscale clock signal GCLK, whose channel control circuit typically includes a plurality of comparators corresponding to the sixteen output channels, a plurality of current sources corresponding to the sixteen output channels, an output buffer electrically coupled between the plurality of comparators and the plurality of current sources, and a global current gain regulator electrically coupled to the plurality of current sources. Due to the use of PWM drive control mode, and the brightness of the LED display device used is between 1000-20000nit, only 10-14bit of the 16-bit grayscale data can be displayed, so it is difficult to effectively improve the display bit depth by relying solely on the PWM drive control mode. Furthermore, with the gradual popularization of small-pitch LED display devices, the brightness of indoor small-pitch display devices is generally controlled between 100-1000nit. In some scenarios where the LED brightness needs to be dimmed, the existing PWM-type LED display driver chip has a built-in grayscale dispersion algorithm in which low-gray data often only appears once for a short display time, which often leads to problems such as uneven grayscale transition under low brightness and low gray or low low-gray refresh rate. Summary of the invention

[0004] Therefore, in order to overcome at least some of the defects and shortcomings in the prior art, the embodiments of the present application provide a display driving circuit, an LED display panel, a display device and a display driving method.

[0005] Specifically, a display driving circuit provided in an embodiment of the present application includes: an interface circuit for acquiring multiple grayscale data and multiple current gain data; a command processing circuit electrically coupled to the interface circuit; a cache circuit electrically coupled to the interface circuit for caching the multiple grayscale data and the multiple current gain data; a current source circuit electrically coupled to the command processing circuit and including multiple channel current sources; a channel grayscale control circuit electrically coupled to the command processing circuit, the cache circuit and the current source circuit, for controlling the opening time of the multiple channel current sources respectively according to the multiple grayscale data; and a channel current control circuit electrically coupled to the cache circuit and the current source circuit, for controlling the output current size of the multiple channel current sources respectively according to the multiple current gain data.

[0006] The embodiment of the present application designs the display driving circuit, which can obtain grayscale data and current gain data, and can control the opening time of each channel current source based on the grayscale data, and control the output current size of each channel current source based on the current gain data, so as to realize dynamic adjustment of channel current; in this way, the grayscale data can be improved by reducing the output current size (corresponding to the driving current of the display point), that is, the display bit depth can be improved. Furthermore, since the display effect of the LED display device is related to the refresh rate and the driving current of each grayscale, the grayscale refresh rate under low brightness and low gray can be effectively improved by reducing the driving current of the display point such as the LED lamp point at low grayscale and increasing the grayscale data. In addition, by reducing the output current size and increasing the grayscale data, the desired brightness value can be accurately obtained, thereby improving the display accuracy of the entire LED display device under low gray, so as to solve the problem of uneven grayscale transition under low brightness and low gray.

[0007] In one embodiment of the present application, the interface circuit includes a shift register circuit and is used to access a data clock signal, a latch signal and serial data; the shift register circuit is used to receive the serial data to obtain the multiple grayscale data and the multiple current gain data and accept the control of the data clock signal and the latch signal; the command processing circuit is electrically coupled to the shift register circuit and accepts the control of the data clock signal and the latch signal; the cache circuit is electrically coupled to the shift register circuit to obtain the multiple grayscale data and the multiple current gain data; and the channel grayscale control circuit accepts the control of the data clock signal. The interface circuit of this embodiment can realize the serial input and output of grayscale data and current gain data, which is beneficial to the cascade between multiple display driving circuits; and the channel grayscale control circuit accepts the control of the data clock signal, which is beneficial to reducing the number of input ports of the interface circuit.

[0008] In one embodiment of the present application, the channel grayscale control circuit includes: a counter, electrically coupled to the command processing circuit, for receiving a grayscale clock signal and generating a grayscale clock count value under the control of the grayscale clock signal; a grayscale scattering processing circuit, electrically coupled to the command processing circuit and the counter, for receiving the control of the command processing circuit to control the counting operation of the counter and generate a grayscale grouping control signal; an output buffer, electrically coupled to the multiple channel current sources of the current source circuit; and multiple comparators, electrically coupled to the cache circuit, the counter, the grayscale scattering processing circuit and the output buffer, for respectively obtaining the multiple grayscale data from the cache circuit, and generating multiple grayscale display control signals under the control of the grayscale clock count value and the grayscale grouping control signal, and transmitting them to the multiple channel current sources via the output buffer. The use of the grayscale scattering processing circuit in this embodiment is conducive to evenly scattering the high grayscale part and the low grayscale part, so that in some scenes where the grayscale is not fully realized, most of the grayscale can be realized as much as possible.

[0009] In one embodiment of the present application, the channel grayscale control circuit further includes: a frequency multiplication circuit electrically coupled to the counter, for generating the grayscale clock signal and transmitting it to the counter. The use of the frequency multiplication circuit in this embodiment is conducive to increasing the flexibility of grayscale clock signal generation.

[0010] In one embodiment of the present application, the current source circuit further includes a plurality of color component global current gain regulators, and each of the color component global current gain regulators is electrically coupled to a plurality of channel current sources for carrying the same color sub-pixels among the plurality of channel current sources; the channel current control circuit includes a plurality of channel current gain regulators, and the plurality of channel current gain regulators are respectively electrically coupled to the plurality of channel current sources and are respectively controlled by the plurality of current gain data. In this embodiment, the setting of the color component global current gain regulators is conducive to the global regulation of the channel current sources of the same color sub-pixels.

[0011] In one embodiment of the present application, the interface circuit includes a shift register circuit and is used to access a data clock signal, a latch signal, serial data, and a second clock signal different from the data clock signal; the shift register circuit is used to receive the serial data to obtain the plurality of grayscale data and the plurality of current gain data and accept the control of the data clock signal and the latch signal; the command processing circuit is electrically coupled to the shift register circuit and accepts the control of the data clock signal and the latch signal; the buffer circuit is electrically coupled to the shift register circuit to obtain the plurality of grayscale data and the plurality of current gain data; and the channel grayscale control circuit accepts the control of the second clock signal. The interface circuit of this embodiment can realize the serial input and output of grayscale data and current gain data, which is conducive to the cascade between multiple display driving circuits; and the channel grayscale control circuit accepts the control of the second clock signal different from the data clock signal, which can make the generation of the grayscale clock signal no longer limited to the data clock signal, thereby improving the flexibility of the generation of the grayscale clock signal.

[0012] In one embodiment of the present application, the display driving circuit further includes: a scanning control circuit electrically coupled to the channel grayscale control circuit, for sequentially generating a plurality of row scanning signals. In this embodiment, by integrating the scanning control circuit, it is possible to effectively improve the integration of the display driving circuit, and reduce the complexity of PCB (Printed Circuit Board) design when designing an LED display panel.

[0013] In one embodiment of the present application, the cache circuit includes a grayscale data storage area and a current gain data storage area, the grayscale data storage area is used to cache the plurality of grayscale data, and the current gain data storage area is used to cache the plurality of current gain data. This embodiment stores the grayscale data and the current gain data separately, which is conducive to simplifying data reading and writing operations.

[0014] In one embodiment of the present application, the grayscale data storage area includes two storage sub-areas for caching grayscale data frame by frame in a ping-pong storage manner, and the current gain data storage area includes two storage sub-areas for caching current gain data frame by frame in a ping-pong storage manner. The grayscale data and current gain data of this embodiment are both stored in a ping-pong storage manner, which is conducive to improving the processing speed and performance of the display drive circuit.

[0015] In one embodiment of the present application, the interface circuit, the command processing circuit, the cache circuit, the current source circuit, the channel grayscale control circuit, and the channel current control circuit are integrated into the same chip. This embodiment integrates various circuits into the same chip, that is, the display driver circuit is chip-based, which is conducive to improving the integration of the display driver circuit.

[0016] In one embodiment of the present application, the multiple current gain data are point-by-point current gain data, so that the same channel current source in the multiple channel current sources uses the current gain data corresponding to the different display points when driving different display points. The point-by-point current gain data of this embodiment is conducive to improving the precision of current dynamic regulation.

[0017] In one embodiment of the present application, the multiple current gain data are channel-by-channel current gain data, so that the current gain data used by the same channel current source in the multiple channel current sources in different display frames are different. The use of channel-by-channel circuit gain data in this embodiment can at least realize dynamic current adjustment frame by frame.

[0018] Furthermore, an LED display panel provided in an embodiment of the present application includes: a pixel array, including a plurality of pixel points and each of the pixel points includes a plurality of LEDs of different colors; and at least one display driving circuit as described in any of the aforementioned embodiments, wherein the plurality of channel current sources of the display driving circuit are electrically coupled to the pixel array.

[0019] The LED display panel of this embodiment can realize dynamic adjustment of channel current, which is beneficial to improving display bit depth, increasing grayscale refresh rate under low brightness and low gray, and improving the display accuracy of the entire LED display device under low gray to solve the problem of uneven grayscale transition under low brightness and low gray.

[0020] In addition, a display device provided in an embodiment of the present application includes: a front-end display control card for outputting multiple grayscale data and multiple current gain data; and an LED display panel as described above, wherein the display driving circuit of the LED display panel is electrically coupled to the front-end display control card to receive the multiple grayscale data and the multiple current gain data.

[0021] The display device of this embodiment can realize dynamic adjustment of channel current, which is beneficial to improving display bit depth, increasing grayscale refresh rate under low brightness and low gray, and improving the display accuracy of the entire LED display device under low gray to solve the problem of uneven grayscale transition under low brightness and low gray.

[0022] In addition, a display driving method provided in an embodiment of the present application includes: acquiring multiple grayscale data and multiple current gain data; cache the multiple grayscale data and the multiple current gain data; control the opening time of multiple channel current sources respectively according to the multiple grayscale data; and control the output current size of the multiple channel current sources respectively according to the multiple current gain data.

[0023] The display driving method of this embodiment can realize dynamic adjustment of channel current, which is beneficial to improving display bit depth, increasing grayscale refresh rate under low brightness and low gray, and improving the display accuracy of the entire LED display device under low gray to solve the problem of uneven grayscale transition under low brightness and low gray.

[0024] In one embodiment of the present application, the control of the opening duration of multiple channel current sources according to the multiple grayscale data includes: receiving a grayscale clock signal and generating a grayscale clock count value under the control of the grayscale clock signal; controlling the counting operation of the counter and generating a grayscale grouping control signal based on a grayscale scattering algorithm; respectively obtaining the multiple grayscale data, and generating multiple grayscale display control signals under the control of the grayscale clock count value and the grayscale grouping control signal and transmitting them to the multiple channel current sources respectively to control the opening duration of the multiple channel current sources. This embodiment can evenly scatter the high grayscale part and the low grayscale part based on the grayscale scattering algorithm, so that in some scenarios where the grayscale realization is incomplete, it can also ensure that most of the grayscale can be realized as much as possible.

[0025] In one embodiment of the present application, the controlling the opening duration of the plurality of channel current sources respectively according to the plurality of grayscale data further comprises: performing frequency doubling processing on the input clock signal to generate the grayscale clock signal. The frequency doubling processing of this embodiment is conducive to increasing the flexibility of grayscale clock signal generation.

[0026] In one embodiment of the present application, the output current magnitudes of the multiple channel current sources are controlled respectively according to the multiple current gain data, including: the output current magnitudes of the multiple channel current sources are controlled respectively according to multiple point-by-point current gain data. The use of point-by-point current gain data in this embodiment can enable the same channel current source to use the current gain data corresponding to the different display points when driving different display points (such as LED light points), thereby facilitating the improvement of the accuracy of dynamic current regulation.

[0027] In one embodiment of the present application, the caching of the plurality of grayscale data and the plurality of current gain data includes: caching the grayscale data frame by frame in a ping-pong storage manner; and caching the current gain data frame by frame in a ping-pong storage manner. The grayscale data and the current gain data of this embodiment are both stored in a ping-pong storage manner, which is conducive to improving processing speed and performance.

[0028] In one embodiment of the present application, the output current magnitudes of the multiple channel current sources are controlled respectively according to the multiple current gain data, including: controlling the output current magnitudes of the multiple channel current sources respectively according to the multiple channel-by-channel current gain data. The use of channel-by-channel current gain data in this embodiment can make the current gain data used by the same channel current source different in different display frames, which can at least realize dynamic current adjustment frame by frame.

[0029] The above technical solution may have the following advantages or beneficial effects: by designing the display driving circuit, it can obtain grayscale data and current gain data, and can control the opening time of each channel current source based on the grayscale data, and control the output current of each channel current source based on the current gain data, so as to realize dynamic adjustment of the channel current; in this way, the grayscale data can be improved by reducing the output current (corresponding to the driving current of the display point), that is, the display bit depth can be improved. Furthermore, since the display effect of the LED display device is related to the refresh rate and the driving current of each grayscale, by reducing the driving current of the display point such as the LED lamp point at low grayscale and increasing the grayscale data, the grayscale refresh rate under low brightness and low gray can be effectively improved. In addition, by reducing the output current and increasing the grayscale data, the desired brightness value can be accurately obtained, thereby improving the display accuracy of the entire LED display device under low gray, so as to solve the problem of uneven grayscale transition under low brightness and low gray. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1A A schematic diagram of the structure of a display driving circuit according to an embodiment of the present application.

[0032] Figure 1B for Figure 1A A specific structural schematic diagram of a display driving circuit is shown.

[0033] Figure 1C For related Figure 1A A specific structural schematic diagram of a current source circuit, a channel grayscale control circuit and a channel current control circuit in a display driving circuit is shown.

[0034] Figure 2 A schematic diagram of the specific structure of another display driving circuit provided in an embodiment of the present application.

[0035] Figure 3A schematic diagram of a specific structure of another display driving circuit provided in an embodiment of the present application.

[0036] Figure 4 This is a schematic diagram of a specific structure of another display driving circuit according to an embodiment of the present application.

[0037] Figure 5 This is a partial structural schematic diagram of an LED display panel according to an embodiment of the present application.

[0038] Figure 6 This is a partial structural schematic diagram of another LED display panel according to an embodiment of the present application.

[0039] Figure 7 This is a partial structural schematic diagram of another LED display panel according to an embodiment of the present application.

[0040] Figure 8 This is a partial structural schematic diagram of another LED display panel according to an embodiment of the present application.

[0041] Fig. 9 A schematic diagram of the structure of a display device according to an embodiment of the present application.

[0042] Fig.10 The figure is a flow chart of a display driving method according to an embodiment of the present application. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0044] [First embodiment]

[0045] Figure 1A FIG. 1 is a schematic diagram of a structure of a display driving circuit 10 provided in an embodiment of the present application. Figure 1A As shown, the display driving circuit 10 includes: an interface circuit 11, a command processing circuit 12, a cache circuit 13, a current source circuit 15, a channel grayscale control circuit 17 and a channel current control circuit 19.

[0046] The interface circuit 11 is used to obtain a plurality of grayscale data and a plurality of current gain data.

[0047] The command processing circuit 12 is electrically coupled to the interface circuit 11 , and includes, for example, a configuration register and circuit logic for responding to commands.

[0048] The buffer circuit 13 is electrically coupled to the interface circuit 11 and is used for buffering the plurality of grayscale data and the plurality of current gain data.

[0049] The current source circuit 15 is electrically coupled to the command processing circuit 12 and includes a plurality of channel current sources.

[0050] The channel grayscale control circuit 17 is electrically coupled to the command processing circuit 12 , the buffer circuit 13 and the current source circuit 15 , and is used to control the opening durations of the multiple channel current sources respectively according to the multiple grayscale data.

[0051] The channel current control circuit 19 is electrically coupled to the buffer circuit 13 and the current source circuit 15 , and is used to control the output current magnitudes of the multiple channel current sources respectively according to the multiple current gain data.

[0052] This embodiment designs the display driving circuit 10, which can obtain grayscale data and current gain data, and can control the opening time of each channel current source based on the grayscale data, and control the output current of each channel current source based on the current gain data, so as to realize dynamic adjustment of the channel current; in this way, the grayscale data can be improved by reducing the output current, that is, the display bit depth can be improved. Furthermore, since the display effect of the LED display device is related to the refresh rate and the driving current of each grayscale, the grayscale refresh rate under low brightness and low gray can be effectively improved by reducing the driving current of the display point such as the LED lamp point at low grayscale and increasing the grayscale data. In addition, by reducing the output current and increasing the grayscale data, the desired brightness value can be accurately obtained, thereby improving the display accuracy of the entire LED display device under low gray, so as to solve the problem of uneven grayscale transition under low brightness and low gray. In addition, in this embodiment, the interface circuit 11, the command processing circuit 12, the cache circuit 13, the current source circuit 15, the channel grayscale control circuit 17 and the channel current control circuit 19 can be integrated into the same chip to improve the integration of the entire display driving circuit 10, but the present application is not limited to this.

[0053] More specifically, see Figure 1B and Figure 1C, the interface circuit 11, for example, includes a shift register circuit 111 and is used to access the data clock signal DCLK, the latch signal LE and the serial data DIN[2:0]. The shift register circuit 111 is used to receive the serial data to obtain the multiple grayscale data and the multiple current gain data and accept the control of the data clock signal DCLK and the latch signal LE. For example, the shift register circuit 111 of this embodiment includes a shift register (Shift Register) and circuit logic for command response and data transmission (such as DMA transmission). DMA here is the abbreviation of Direct Memory Access, and its Chinese name is direct memory access.

[0054] The command processing circuit 12 is electrically coupled to the shift register circuit 111 and is controlled by the data clock signal DCLK and the latch signal LE.

[0055] The cache circuit 13 is electrically coupled to the shift register circuit 111 to obtain the plurality of grayscale data and the plurality of current gain data. For example, the cache circuit 13 of the present embodiment includes an SRAM (Static Random Access Memory) buffer memory and a RAM controller. Preferably, the cache circuit 13 is configured with two independent storage areas, a grayscale data storage area 131 and a current gain data storage area 133, for storing the plurality of grayscale data and the plurality of current gain data, respectively. Here, the grayscale data and the current gain data are stored separately, which is conducive to simplifying data reading and writing operations. Furthermore, each of the grayscale data storage area 131 and the current gain data storage area 133 is further divided into two storage sub-areas, which are used to cache grayscale data or current gain data frame by frame in a ping-pong storage manner; this grayscale data and current gain data are both stored in a ping-pong manner, which is beneficial to improving the processing speed and performance of the display driving circuit 10. Of course, those skilled in the art can understand that grayscale data and current gain data can also be accessed in other storage methods, and ping-pong storage is not used as a limitation here.

[0056] The channel grayscale control circuit 17 is controlled by the data clock signal DCLK, and includes, for example, a frequency multiplication circuit 171 , a counter 172 , a grayscale scattering processing circuit 173 , an output buffer 174 and a plurality of comparators 175 .

[0057] The frequency multiplication circuit 171 is used to perform frequency multiplication processing on the data clock signal DCLK to obtain the grayscale clock signal GCLK. For example, the frequency multiplication circuit 171 of the present embodiment includes a PLL (Phase Locked Loop) circuit or a PLL-like circuit, which can generate a 160MHZ grayscale clock signal GCLK through frequency multiplication processing, but the present embodiment is not limited thereto. The frequency multiplication circuit 171 of the present embodiment uses the data clock signal DCLK as an input clock signal for generating the grayscale clock signal GCLK, which can reduce the number of input ports of the display driving circuit 10.

[0058] The counter 172 is electrically coupled to the command processing circuit 12 and the frequency multiplication circuit 171, and is used to receive the gray clock signal GCLK and generate a gray clock count value under the control of the gray clock signal GCLK. The counter 172 of this embodiment is mainly used to count the pulses of the gray clock signal GCLK, and can be a 16-bit counter (16-bit Counter), but this embodiment is not limited to this. Furthermore, the counter 172 is configured by the command processing circuit 12. For example, when the gray clock count reset value is 1024, the gray clock count value of the counter 172 reaches 1024 and is reset to zero and restarts counting, or when the gray clock count reset value is 256, the gray clock count value of the counter 172 reaches 256 and is reset to zero and restarts counting. Of course, the gray clock count reset value of this embodiment is not limited to the above-listed values.

[0059] The grayscale scattering processing circuit 173 is electrically coupled to the command processing circuit 12 and the counter 172, and is used to accept the control of the command processing circuit 12, thereby controlling the counting operation of the counter 172 and generating a grayscale grouping control signal. In this embodiment, the grayscale scattering processing circuit 173 is, for example, a processing circuit capable of running a grayscale scattering algorithm, typically including a memory storing a grayscale scattering algorithm code and a processor electrically coupled to the memory and used to execute the grayscale scattering algorithm code; the grayscale scattering processing circuit 173 can generate a grayscale grouping display control signal according to the grayscale data scattering mode configured by the command processing circuit 12 and the grayscale depth to be achieved; as for the grayscale scattering algorithm, an existing mature algorithm can be used, which will not be described in detail here. Furthermore, taking the display driving circuit 10 applied to drive and control red, green and blue (RGB) full-color LED pixels as an example, the display control data of a single LED pixel includes red (R) component display control data, green (G) component display control data and blue (B) component display control data, and the single color component display control data includes, for example, 16-bit grayscale data and 8-bit current gain data; for the 16-bit grayscale data, it can be divided into 64 grayscale groups according to the grayscale scattering algorithm, and the grayscale level of each grayscale group is 1024, so that 1024*64=65536=2 can be achieved through 64 grayscale groups. 16 gray levels; or, if the gray level of a single gray group is set to 256, the display of 16-bit gray data needs to be divided into 256 gray groups; of course, the number of gray groups and the gray level of a single gray group in this embodiment are not limited to the above listed values.

[0060] The output buffer 174 is electrically coupled to the multiple channel current sources 151 of the current source circuit 15 .

[0061] The plurality of comparators 175 are electrically coupled to the buffer circuit 13, the counter 172, the grayscale scattering processing circuit 173 and the output buffer 174, and are used to obtain the plurality of grayscale data from the buffer circuit 13 respectively, and generate a plurality of grayscale display control signals under the control of the grayscale clock count value and the grayscale grouping control signal, and transmit them to the plurality of channel current sources 151 respectively via the output buffer 174, so as to control the opening time of each channel current source 151. Taking the display driving circuit 10 as an LED display driving chip as an example, it has 96 output channels DOUT[95:0], so that it can carry / drive 96 columns of LED light points (display points); taking RGB three LED light points as an example to form an LED pixel, it can carry 32 columns of RGB full-color LED pixels, that is, the 96 output channels DOUT[95:0] are divided into 32 red (R) component output channels, 32 green (G) component output channels and 32 blue (B) component output channels.

[0062] Furthermore, if Figure 1C As shown, the current source circuit 15, in addition to the multiple channel current sources 151, also includes, for example, an R component global current gain regulator 15R, a G component global current gain regulator 15G, and a B component global current gain regulator 15B. The R component global current gain regulator 15R is electrically coupled to the multiple channel current sources 151 for carrying red (R component) sub-pixels (or display points such as LED light points), the G component global current gain regulator 15G is electrically coupled to the multiple channel current sources 151 for carrying green (G component) sub-pixels, and the B component global current gain regulator 15B is electrically coupled to the multiple channel current sources 151 for carrying blue (B component) sub-pixels.

[0063] The channel current control circuit 19 includes a plurality of channel current gain regulators 191 , and the plurality of channel current gain regulators 191 are respectively electrically coupled to the plurality of channel current sources 151 and are respectively controlled by the plurality of current gain data.

[0064] by Figure 1CTaking the display driving circuit 10 configured with 96 output channels DOUT[95:0] as an example, the R component global current gain regulator 15R is electrically coupled to 32 red output channels such as DOUT2, ..., DOUT95 among the 96 output channels DOUT[95:0], the G component global current gain regulator 15G is electrically coupled to 32 green output channels such as DOUT1, ..., DOUT94 among the 96 output channels DOUT[95:0], and the B component global current gain regulator 15G is electrically coupled to 32 blue output channels such as DOUT0, ..., DOUT93 among the 96 output channels DOUT[95:0]. The three color component global current gain regulators, namely the R component global current gain regulator 15R, the G component global current gain regulator 15G and the B component global current gain regulator 15B, can be externally connected to resistors respectively. The multiple channel current gain regulators 191 are 96 channel current gain regulators, which are controlled by corresponding current gain data to be responsible for the single-channel current gain regulation of 96 output channels DOUT[95:0], and for example, each includes a resistor network controlled by the current gain data and electrically coupled to the corresponding channel current source 151. Of course, it can be understood that in practical applications, it is also possible to consider integrating the three component global current gain regulators, such as the R component global current gain regulator 15R, the G component global current gain regulator 15G, and the B component global current gain regulator 15B, into one global current gain regulator, so that a single global current gain regulator is responsible for the global current gain regulation of the 96 output channels DOUT[95:0], that is, the global current gain regulation does not distinguish between the R, G, and B components. Even in some design methods, the current source circuit 15 can also omit these global current gain regulators 15R, 15G, and 15B.

[0065] To facilitate a clearer understanding of the display driving circuit 10 of this embodiment, the following will be combined with Figures 1A-1C An example is given to illustrate its working principle.

[0066] When the display driving circuit 10 starts to power on normally, the data clock signal DCLK at the data clock input end sends the R, G, B component display control data in the serial data DIN[2:0] input from the serial data input end to the shift register circuit 111. The display driving circuit 10 collects 3-bit display control data at each rising edge of the data clock signal DCLK, 1 bit for each R, G, B component. When 72-bit display control data (24 bits for each R, G, B component, 16 bits for grayscale data and 8 bits for current gain data, that is, the number of bits of grayscale data is greater than the number of bits of current gain data) is collected, the data clock signal DCLK and the latch signal LE transmit the 3*16-bit grayscale data+3*8-bit current gain data contained in the 72-bit display control data in the shift register circuit 111 to the grayscale data storage area 131 and the current gain data storage area 133 in the cache circuit 13 through a combined command (generally, the latch signal includes a rising edge of the data clock signal DCLK).

[0067] The sizes of the grayscale data storage area 131 and the current gain data storage area 133 are associated with the number of output channels and the number of scanning lines supported by the display driving circuit 10. For example, for a display driving circuit supporting 96 output channels (32 output channels for R, G, and B, respectively) and 64 scanning lines, the size of the grayscale data storage area 131 is 96*16bit*64=96Kb, and the size of the current gain data storage area 133 is 96*8bit*64=48Kb. At the same time, since the cache circuit 13 of the display driving circuit 10 adopts the form of ping-pong operation, that is, the grayscale data of the previous frame is used when the grayscale data is displayed, and the data is buffered in the current frame, the sizes of the grayscale data storage area 131 and the current gain data storage area 133 are 192Kb and 96Kb, respectively, for storing two frames of complete grayscale data and current gain data.

[0068] In order to display synchronously with the display data of the front-end video source, the display driving circuit 10 also has corresponding synchronous display processing. When the command processing circuit 12 receives the Vsync command (which is also a combination command of the latch signal LE including the number of rising edges of the data clock signal DCLK, generally 2 to 3), the display driving circuit 10 will switch the ping-pong data in the cache circuit 13, switch the display control data (including grayscale data and current gain data) cached in the previous frame to read and output, and switch the storage sub-area of ​​the displayed display control data to the coupled shift register circuit 111 for receiving new display control data. At the same time, the Vsync command will clear the grayscale clock count value of the counter 172 that counts the pulses of the grayscale clock signal GCLK generated by the frequency multiplication circuit 171.

[0069] Before actually starting the grayscale display, the display driving circuit 10 needs to configure some working states such as the working mode and the global current gain according to the register data received by the command processing circuit 12 (for example, written into the configuration register via the shift register circuit 111); at this time, the content that needs to be configured includes the grayscale data dispersion mode, the grayscale depth to be achieved, the global current gain, etc., and the register configuration is also distinguished by different data clock signal DCLK and latch signal LE combination commands.

[0070] After the configuration is completed, the display driver circuit 10 starts to realize the grayscale. To light up an LED lamp, the periphery already has a coordinated row drive current. The display driver circuit 10 needs to control the on / off of the output channel DOUT[95:0] according to the display control data of different rows to complete the lighting of the LED lamp. However, to realize the distinction of grayscale data, there are two related parts, one is the output current size of the output channel, and the other is the opening time of the output channel. For example, to realize the red component grayscale data of 1000 grayscale values ​​and 2000 grayscale values, at this time, if the current size of the two is the same, such as 10mA, the grayscale data of 1000 grayscale values ​​needs 1000 grayscale clock signal cycles to be realized using PWM. The grayscale clock signal here is Figure 1BIn the GCLK, similarly, 2000 grayscale clock signal cycles are required to realize grayscale data with a grayscale value of 2000. In this way, different grayscale data are converted into lighting times showing different time lengths. In this embodiment, the switching state of the output channel DOUT[95:0] of the display driving circuit 10 is controlled by the grayscale data and the grayscale clock count value through the common control method of the current gain data and the grayscale data, and the actual maximum brightness of the LED lamp point is controlled by the current gain data. The control of each channel current source 151 of the display driving circuit 10 is jointly controlled by the external resistor and the internal configuration resistor. The external resistor is fixed after the LED display board is determined. Therefore, the lighting brightness of the LED lamp point can be controlled by the global current gain and the current gain data. For example, to realize the grayscale data with a grayscale value of 1000, By selecting a current of 10mA to light up 1000 grayscale clock signal cycles, the current gain data collaborative control method proposed in this embodiment provides a new lighting method. The same benchmark is to achieve a grayscale data display effect of 1000 grayscale values. The same effect as the original 10mA and 1000 grayscale clock signal cycles can be achieved by reducing the current and increasing the grayscale data. For example, the current can be reduced to 5mA and the number of grayscale clock signal cycles can be increased to 2000 grayscale clock signal cycles. This effect is close to that of the previous implementation. Similarly, the current data can be reduced to 8mA and the number of grayscale clock signal cycles for lighting can be increased to 1200. The effects can also be consistent. Specifically, the precise implementation method conversion can be achieved by collecting the implementation relationship between the current gain data lighting effect and the grayscale data.

[0071] Furthermore, when using PWM to implement grayscale, a grayscale scattering algorithm is used to group and display grayscale data, which can improve the refresh rate when implementing grayscale. At the same time, it can also prevent problems such as the inability to achieve low grayscale when the refresh rate is not an integer multiple of the grayscale clock signal period.

[0072] In summary, the display driving circuit 10 of the embodiment of the present application is designed to receive display control data including grayscale data and current gain data, and can control the opening time of each channel current source 151 based on the grayscale data, and control the output current of each channel current source 151 based on the current gain data, so as to realize dynamic adjustment of channel current; in this way, the grayscale data can be improved by reducing the output current (corresponding to the driving current of the display point), that is, the display bit depth can be improved. In addition, since the display effect of the LED display device is related to the refresh rate and the driving current of each grayscale, the grayscale refresh rate under low brightness and low gray can be effectively improved by reducing the driving current of the display point such as the LED lamp point at low grayscale and increasing the grayscale data. Furthermore, by reducing the output current and increasing the grayscale data, the desired brightness value can be accurately obtained, thereby improving the display accuracy of the entire LED display device under low gray, so as to solve the problem of uneven grayscale transition under low brightness and low gray.

[0073] [Second embodiment]

[0074] Figure 2 FIG. 2 is a schematic diagram of a specific structure of another display driving circuit 30 provided in an embodiment of the present application. Figure 2 As shown, the circuit structure of the display driving circuit 30 is similar to Figure 1A and 1B The circuit structure of the display driving circuit 10 shown is basically the same, and also includes: an interface circuit 11, a command processing circuit 12, a buffer circuit 13, a current source circuit 15, a channel grayscale control circuit 17 and a channel current control circuit 19; and the channel grayscale control circuit 17 includes a frequency multiplication circuit 171, a counter 172, a grayscale scattering processing circuit 173, an output buffer 174 and a plurality of comparators 175. As for the connection relationship between these circuits and their respective structures and functions, reference can be made to the relevant description in the aforementioned first embodiment, and no further description is given here.

[0075] The difference is that the interface circuit 11 in the display driving circuit 30 of this embodiment includes a shift register circuit 111 and is used to access the data clock signal DCLK, the latch signal LE, the serial data DIN[2:0] and the second clock signal CLK different from the data clock signal DCLK; the shift register circuit 111 is used to receive the serial data DIN[2:0] to obtain the multiple grayscale data and the multiple current gain data and accept the control of the data clock signal DCLK and the latch signal LE; the command processing circuit 12 is electrically coupled to the shift register circuit 111 and accepts the control of the data clock signal DCLK and the latch signal LE; the cache circuit 13 is electrically coupled to the shift register circuit 111 to obtain the multiple grayscale data and the multiple current gain data; and the channel grayscale control circuit 17 is controlled by the second clock signal CLK. The frequency multiplication circuit 171 of this embodiment uses another clock signal CLK not used for the data clock signal DCLK as an input clock signal for generating the grayscale clock signal GCLK, which makes the generation of the grayscale clock signal GCLK no longer limited by the data clock signal DCLK, thereby improving the flexibility of the generation of the grayscale clock signal GCLK. In addition, it is worth mentioning that the clock CLK can be generated by an external crystal oscillator circuit.

[0076] [Third embodiment]

[0077] Figure 3 FIG. 5 is a schematic diagram of a specific structure of another display driving circuit 50 provided in an embodiment of the present application. Figure 3 As shown, the internal circuit structure of the display driving circuit 50 is similar to Figure 1A and 1B The circuit structure of the display driving circuit 10 shown is basically the same, and also includes: an interface circuit 11, a command processing circuit 12, a cache circuit 13, a current source circuit 15, a channel grayscale control circuit 17 and a channel current control circuit 19; as for the connection relationship between these circuits and their respective structures and functions, reference may be made to the relevant description in the aforementioned first embodiment, which will not be repeated here.

[0078] The difference is that the channel grayscale control circuit 17 in the display driving circuit 50 of this embodiment includes a counter 172, a grayscale scattering processing circuit 173, an output buffer 174 and a plurality of comparators 175, that is, the frequency multiplication circuit 171 is omitted. Furthermore, the interface circuit 11 in the display driving circuit 50 of the present embodiment includes a shift register circuit 111 and is used to access the data clock signal DCLK, the latch signal LE, the serial data DIN[2:0] and the grayscale clock signal GCLK different from the data clock signal DCLK; the shift register circuit 111 is used to receive the serial data DIN[2:0] to obtain the plurality of grayscale data and the plurality of current gain data and to accept the control of the data clock signal DCLK and the latch signal LE; the command processing circuit 12 is electrically coupled to the shift register circuit 111 and is controlled by the data clock signal DCLK and the latch signal LE; the buffer circuit 13 is electrically coupled to the shift register circuit 111 to obtain the plurality of grayscale data and the plurality of current gain data; and the channel grayscale control circuit 17 is controlled by the grayscale clock signal GCLK. The channel grayscale control circuit 17 of the present embodiment adopts the external grayscale clock signal GCLK, so the frequency multiplication circuit 171 can be omitted.

[0079] [Fourth embodiment]

[0080] Figure 4 FIG. 7 is a schematic diagram of a specific structure of another display driving circuit 70 provided in an embodiment of the present application. Figure 4 As shown, the circuit structure of the display driving circuit 70 is similar to Figure 1A and 1B The circuit structure of the display driving circuit 10 shown is basically the same, and also includes: an interface circuit 11, a command processing circuit 12, a buffer circuit 13, a current source circuit 15, a channel grayscale control circuit 17 and a channel current control circuit 19; and the channel grayscale control circuit 17 includes a frequency multiplication circuit 171, a counter 172, a grayscale scattering processing circuit 173, an output buffer 174 and a plurality of comparators 175. As for the connection relationship between these circuits and their respective structures and functions, reference can be made to the relevant description in the aforementioned first embodiment, and no further description is given here.

[0081] The difference is that the display driving circuit 70 of this embodiment further includes: a scanning control circuit 59, which is electrically coupled to the grayscale scattering processing circuit 173 in the channel grayscale control circuit 17, and is used to sequentially generate a plurality of row scanning signals, for example, it has 64 output channels LINE[63:0] to sequentially output 64 row scanning signals. This embodiment integrates the scanning control circuit 59 into the display driving circuit 70, which can effectively improve the integration of the display driving circuit 70 and reduce the complexity of PCB design when designing an LED display panel. As for the working principle of the scanning control circuit 59, for example, since the grayscale implementation of the display driving circuit 70 is coordinated and controlled by the grayscale scattering processing circuit 173 and the counter 172, for example, after the grayscale scattering algorithm is turned on, each time a set number, such as 256 grayscale clock signal cycles, is achieved, a line break must be started. At this time, it is necessary to notify the scanning control circuit 59 to perform a line break operation. Of course, since the grayscale data inside the display driving circuit 70 is stored in sequence, it is also implemented in a scanning sequence. At this time, the scanning control circuit 59 (for example, from the grayscale scattering processing circuit 173) receives a simple logic to perform accumulation operations and zeroing operations to complete the output of the scanning signal.

[0082] [Fifth embodiment]

[0083] Figure 5 This is a partial structural diagram of an LED display panel provided in an embodiment of the present application. Figure 5 As shown, the LED display panel 400 includes: a pixel array PA, a display driving circuit 10 and a scanning control chip 420 .

[0084] The pixel array PA includes 32 columns of pixels P, and each pixel P includes a plurality of LEDs of different colors, such as R, G, and B three-primary color LED lamps, so that the pixel array PA has 96 columns of LED lamps. These 96 columns of LED lamps are electrically coupled to the 96 output channels DOUT0 to DOUT95 of the display driving circuit 10, and the pixels P in each column are electrically coupled to three adjacent output channels of the display driving circuit 10. Furthermore, the pixel array PA includes 64 rows of pixels P, and these 64 rows of pixels P are electrically coupled to the 64 output channels LINE0 to LINE63 of the scan control chip 420.

[0085] The scan control chip 420 of the present embodiment includes, for example, a row decoding chip, which can cooperate with the display driving circuit 10 to sequentially generate 64 row scanning signals (or scan driving signals) in each round of 64 scanning. It should be noted that the output channels of the scan control chip 420 of the present embodiment are not limited to 64, and can also be other numbers such as 32, etc. The specific number can be determined according to actual application requirements.

[0086] In addition, the display driving circuit 10 of the present embodiment receives inputs of a data clock signal DCLK, serial data DIN[2:0], and a latch signal LE.

[0087] [Sixth embodiment]

[0088] Figure 6 This is a partial structural diagram of another LED display panel provided in an embodiment of the present application. Figure 6 As shown, the LED display panel 600 includes: a pixel array PA, a display driving circuit 30 and a scanning control chip 420 .

[0089] The pixel array PA includes 32 columns of pixels P, and each pixel P includes a plurality of LEDs of different colors, such as R, G, and B three-primary color LED lamps, so that the pixel array PA has 96 columns of LED lamps. These 96 columns of LED lamps are electrically coupled to the 96 output channels DOUT0 to DOUT95 of the display driving circuit 30, and the pixels P in each column are electrically coupled to three adjacent output channels of the display driving circuit 30. Furthermore, the pixel array PA includes 64 rows of pixels P, and these 64 rows of pixels P are electrically coupled to the 64 output channels LINE0 to LINE63 of the scan control chip 420.

[0090] The scan control chip 420 of the present embodiment includes, for example, a row decoding chip, which can cooperate with the display driving circuit 30 to sequentially generate 64 row scanning signals (or scan driving signals) in each round of 64 scanning. It should be noted that the output channels of the scan control chip 420 of the present embodiment are not limited to 64, and can also be other numbers such as 32, etc. The specific number can be determined according to actual application requirements.

[0091] In addition, the display driving circuit 30 of the present embodiment receives inputs of a data clock signal DCLK, serial data DIN[2:0], a latch signal LE, and a second clock signal CLK for generating a gray clock signal GCLK.

[0092] [Seventh embodiment]

[0093] Figure 7 This is a partial structural diagram of another LED display panel provided in the embodiment of the present application. Figure 7 As shown, the LED display panel 800 includes: a pixel array PA, a display driving circuit 50 and a scanning control chip 420 .

[0094] The pixel array PA includes 32 columns of pixels P, and each pixel P includes a plurality of LEDs of different colors, such as R, G, and B three-primary color LED lamps, so that the pixel array PA has 96 columns of LED lamps. These 96 columns of LED lamps are electrically coupled to the 96 output channels DOUT0 to DOUT95 of the display driving circuit 50, and the pixels P in each column are electrically coupled to three adjacent output channels of the display driving circuit 50. Furthermore, the pixel array PA includes 64 rows of pixels P, and these 64 rows of pixels P are electrically coupled to the 64 output channels LINE0 to LINE63 of the scan control chip 420.

[0095] The scan control chip 420 of the present embodiment includes, for example, a row decoding chip, which can cooperate with the display driving circuit 50 to sequentially generate 64 row scanning signals (or scan driving signals) in each round of 64 scanning. It should be noted that the output channels of the scan control chip 420 of the present embodiment are not limited to 64, and can also be other numbers such as 32, etc. The specific number can be determined according to actual application requirements.

[0096] In addition, the display driving circuit 50 of the present embodiment receives inputs of a data clock signal DCLK, serial data DIN[2:0], a latch signal LE, and a grayscale clock signal GCLK.

[0097] [Eighth embodiment]

[0098] Figure 8 This is a partial structural diagram of another LED display panel provided in the embodiment of the present application. Figure 8 As shown, the LED display panel 1000 includes: a pixel array PA and a display driving circuit 70.

[0099] The pixel array PA includes 32 columns of pixel points P, and each pixel point P includes a plurality of LEDs of different colors, such as R, G, and B three-primary color LED light points, so that the pixel array PA has 96 columns of LED light points. These 96 columns of LED light points are electrically coupled to the 96 output channels DOUT0 to DOUT95 of the display driving circuit 70, and the pixel points P in each column are electrically coupled to three adjacent output channels of the display driving circuit 70. Furthermore, the pixel array PA includes 64 rows of pixels P, and these 64 rows of pixels P are electrically coupled to the 64 output channels LINE0 to LINE63 of the display driving circuit 70.

[0100] The display driving circuit 70 of this embodiment is integrated with the scanning control circuit 59 (such as Figure 4As shown in FIG. 1 , it can sequentially generate 64 row scanning signals (or scanning drive signals) in each round of 64 scanning. It should be noted that the output channels of the row scanning signals of the display drive circuit 70 of this embodiment are not limited to 64, but can also be other numbers such as 32, etc. The specific number can be determined according to actual application requirements.

[0101] [Ninth embodiment]

[0102] Fig. 9 This is a schematic diagram of the structure of a display device provided in an embodiment of the present application. Fig. 9 As shown, the display device 900 includes: a front-end display control card 901 and an LED display board 903 .

[0103] Among them, the front-end display control card 901 is used to output display control data including grayscale data and current gain data. It adopts, for example, a hardware structure similar to a mature receiving card, scanning card or module controller in the field of LED display control technology, that is, a programmable logic device such as an FPGA (Field Programmable Gate Array) device is used as an image processor; however, the image processor of this embodiment can directly output the display control data including grayscale data and current gain data, or an FPGA device or an ASIC (Application Specific Integrated Circuit) device is added to the back end of the image processor to convert the grayscale data output by the image processor into the display control data including grayscale data and current gain data.

[0104] The LED display board 903 may adopt the LED display board 400, 600, 800 or 1000 described in the fifth embodiment, the sixth embodiment, the seventh embodiment or the eighth embodiment, and the display driving circuit included therein is electrically coupled to the front-end display control card 901 to receive the display control data to realize image display.

[0105] It is worth noting that the display device 900 of this embodiment may be an LED display box including a front-end display control card 901 and one or more LED display panels 903 , but this is only an example and is not intended to limit the embodiments of the present application.

[0106] The display device 900 of this embodiment can realize dynamic adjustment of channel current, which is beneficial to improving display bit depth, increasing grayscale refresh rate under low brightness and low gray, and improving the display accuracy of the entire LED display device under low gray to solve the problem of uneven grayscale transition under low brightness and low gray.

[0107] [Tenth embodiment]

[0108] Fig.10 A flow chart of a display driving method provided in an embodiment of the present application is shown in FIG. Fig.10 As shown, the display driving method of this embodiment includes the following steps:

[0109] S110: Acquire a plurality of grayscale data and a plurality of current gain data;

[0110] S130: Buffering the plurality of grayscale data and the plurality of current gain data;

[0111] S150: Controlling the opening time of multiple channel current sources respectively according to the multiple grayscale data;

[0112] S170: Controlling the output current magnitudes of the multiple channel current sources respectively according to the multiple current gain data.

[0113] As for the specific details of the aforementioned steps S110 to S170, reference may be made to the relevant description of the display driving circuit 10 of the aforementioned first embodiment, which will not be repeated here. Furthermore, the display driving method of this embodiment can realize dynamic adjustment of the channel current, which is beneficial to improving the display bit depth, improving the grayscale refresh rate under low brightness and low gray, and improving the display accuracy of the entire LED display device under low gray to solve the problem of uneven grayscale transition under low brightness and low gray.

[0114] As an embodiment of the present application, step S150 includes: (i) receiving a grayscale clock signal and generating a grayscale clock count value under the control of the grayscale clock signal; (ii) controlling the counting operation of the counter and generating a grayscale grouping control signal based on a grayscale scattering algorithm; and (iii) respectively acquiring the plurality of grayscale data and generating a plurality of grayscale display control signals under the control of the grayscale clock count value and the grayscale grouping control signal and transmitting them to the plurality of channel current sources respectively to control the opening time of the plurality of channel current sources. This embodiment can evenly scatter the high grayscale part and the low grayscale part based on the grayscale scattering algorithm, so that in some scenarios where the grayscale realization is incomplete, it can also ensure that most of the grayscale can be realized as much as possible.

[0115] As an implementation of the present application, the step S150 further includes: performing frequency doubling processing on the input clock signal to generate the grayscale clock signal. The frequency doubling processing of this implementation is conducive to increasing the flexibility of generating the grayscale clock signal.

[0116] As an embodiment of the present application, the step S170 includes: controlling the output current magnitudes of the multiple channel current sources respectively according to multiple point-by-point current gain data. The use of point-by-point current gain data in this embodiment can enable the same channel current source to use the current gain data corresponding to the different display points when driving different display points (such as LED light points), thereby facilitating the improvement of the accuracy of the dynamic current regulation.

[0117] As an implementation of the present application, step S130 includes: caching grayscale data frame by frame in a ping-pong storage manner; and caching current gain data frame by frame in a ping-pong storage manner. In this implementation, both grayscale data and current gain data are stored in a ping-pong storage manner, which is conducive to improving processing speed and performance.

[0118] As an embodiment of the present application, the step S170 includes: controlling the output current magnitudes of the multiple channel current sources respectively according to the multiple channel-by-channel current gain data. The use of the channel-by-channel current gain data in this embodiment can make the current gain data used by the same channel current source different in different display frames, which can at least realize the dynamic adjustment of the current frame by frame.

[0119] In addition, it can be understood that the aforementioned embodiments are only exemplary descriptions of the present application. Under the premise that the technical features do not conflict, the structures do not contradict, and the invention purpose of the present application is not violated, the technical solutions of the various embodiments can be arbitrarily combined and used in combination.

[0120] Furthermore, it is worth noting that the aforementioned embodiments of the present application are described by taking a single display driving circuit as an example to complete the grayscale implementation of multiple color components, but the embodiments of the present application are not limited to this. A single display driving circuit can also be designed to only complete the grayscale implementation of a single color component. In this way, the grayscale data of the three color components R, G, and B can be implemented using three display driving circuits respectively.

[0121] In addition, it is worth noting that in the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0122] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0123] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0124] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform some steps of the methods of each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store program codes.

[0125] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

[0126] [Industrial Applicability]

[0127] The embodiment of the present application designs the display driving circuit, which can obtain grayscale data and current gain data, and can control the opening time of each channel current source based on the grayscale data, and control the output current size of each channel current source based on the current gain data, so as to realize dynamic adjustment of channel current; in this way, the grayscale data can be improved by reducing the output current size (corresponding to the driving current of the display point), that is, the display bit depth can be improved. Furthermore, since the display effect of the LED display device is related to the refresh rate and the driving current of each grayscale, the grayscale refresh rate under low brightness and low gray can be effectively improved by reducing the driving current of the display point such as the LED lamp point at low grayscale and increasing the grayscale data. In addition, by reducing the output current size and increasing the grayscale data, the desired brightness value can be accurately obtained, thereby improving the display accuracy of the entire LED display device under low gray, so as to solve the problem of uneven grayscale transition under low brightness and low gray.

Claims

1. A display driving circuit, characterized in that: include: An interface circuit, used for acquiring a plurality of grayscale data and a plurality of current gain data; A command processing circuit electrically coupled to the interface circuit; A buffer circuit, electrically coupled to the interface circuit, for buffering the plurality of grayscale data and the plurality of current gain data; a current source circuit electrically coupled to the command processing circuit and comprising a plurality of channel current sources; a channel grayscale control circuit, electrically coupled to the command processing circuit, the buffer circuit and the current source circuit, and configured to control the opening durations of the multiple channel current sources respectively according to the multiple grayscale data; A channel current control circuit electrically coupled to the buffer circuit and the current source circuit, and configured to control the output current magnitudes of the multiple channel current sources respectively according to the multiple current gain data; wherein the channel current control circuit comprises multiple channel current gain regulators, and the multiple channel current gain regulators are electrically coupled to the multiple channel current sources respectively, and are controlled by the multiple current gain data respectively; The current source circuit also includes multiple color component global current gain regulators or one global current gain regulator, and when the current source circuit includes multiple color component global current gain regulators, each of the color component global current gain regulators is electrically coupled to multiple channel current sources among the multiple channel current sources for carrying the same color sub-pixels; when the current source circuit includes one global current gain regulator, the global current gain regulator is electrically connected to multiple channel current sources, and the multiple channel current sources are used to carry all the color sub-pixels therein.

2. The display driving circuit according to claim 1, characterized in that: The interface circuit includes a shift register circuit and is used to access a data clock signal, a latch signal and serial data; the shift register circuit is used to receive the serial data to obtain the plurality of grayscale data and the plurality of current gain data and to accept the control of the data clock signal and the latch signal; The command processing circuit is electrically coupled to the shift register circuit and is controlled by the data clock signal and the latch signal; The buffer circuit is electrically coupled to the shift register circuit to obtain the plurality of grayscale data and the plurality of current gain data; and the channel grayscale control circuit is controlled by the data clock signal.

3. The display driving circuit according to claim 1, wherein: The channel grayscale control circuit comprises: a counter, electrically coupled to the command processing circuit, for receiving a grayscale clock signal and generating a grayscale clock count value under the control of the grayscale clock signal; A grayscale scattering processing circuit, electrically coupled to the command processing circuit and the counter, and configured to be controlled by the command processing circuit to control the counting operation of the counter and generate a grayscale grouping control signal; an output buffer electrically coupled to the plurality of channel current sources of the current source circuit; A plurality of comparators are electrically coupled to the cache circuit, the counter, the grayscale scattering processing circuit and the output buffer, and are used to respectively obtain the plurality of grayscale data from the cache circuit, and generate a plurality of grayscale display control signals under the control of the grayscale clock count value and the grayscale grouping control signal, which are respectively transmitted to the plurality of channel current sources via the output buffer.

4. The display driving circuit according to claim 3, characterized in that: The channel grayscale control circuit further includes: a frequency multiplication circuit electrically coupled to the counter and used for generating the grayscale clock signal and transmitting the signal to the counter.

5. The display driving circuit according to claim 1, wherein: The interface circuit includes a shift register circuit and is used to access a data clock signal, a latch signal, serial data, and a second clock signal different from the data clock signal; the shift register circuit is used to receive the serial data to obtain the plurality of grayscale data and the plurality of current gain data and is controlled by the data clock signal and the latch signal; The command processing circuit is electrically coupled to the shift register circuit and is controlled by the data clock signal and the latch signal; The buffer circuit is electrically coupled to the shift register circuit to obtain the plurality of grayscale data and the plurality of current gain data; and the channel grayscale control circuit is controlled by the second clock signal.

6. The display driving circuit according to claim 1, wherein: The display driving circuit further includes: a scanning control circuit electrically coupled to the channel grayscale control circuit for sequentially generating a plurality of row scanning signals.

7. The display driving circuit according to claim 1, wherein: The buffer circuit comprises a grayscale data storage area and a current gain data storage area. The grayscale data storage area is used to cache the plurality of grayscale data, and the current gain data storage area is used to cache the plurality of current gain data.

8. The display driving circuit according to claim 7, characterized in that: The grayscale data storage area includes two storage sub-areas for caching grayscale data frame by frame in a ping-pong storage manner, and the current gain data storage area includes two storage sub-areas for caching current gain data frame by frame in a ping-pong storage manner.

9. The display driving circuit according to claim 1, wherein: The interface circuit, the command processing circuit, the cache circuit, the current source circuit, the channel grayscale control circuit and the channel current control circuit are integrated into the same chip.

10. The display driving circuit according to claim 1, wherein: The multiple current gain data are point-by-point current gain data, so that the same channel current source among the multiple channel current sources uses the current gain data corresponding to the different display points when driving different display points.

11. The display driving circuit according to claim 1, characterized in that: The multiple current gain data are channel-by-channel current gain data, so that the current gain data used by the same channel current source in the multiple channel current sources in different display frames are different.

12. An LED display panel, characterized in that: include: A pixel array, comprising a plurality of pixel points, each of which comprises a plurality of LEDs of different colors; as well as At least one display driving circuit as claimed in any one of claims 1 to 11, wherein the plurality of channel current sources of the display driving circuit are electrically coupled to the pixel array.

13. A display device, characterized in that: include: A front-end display control card is used to output multiple grayscale data and multiple current gain data; as well as The LED display panel as claimed in claim 12, wherein the display driving circuit of the LED display panel is electrically coupled to the front-end display control card to receive the plurality of grayscale data and the plurality of current gain data.

14. A display driving method, characterized in that: include: Acquire multiple grayscale data and multiple current gain data through the interface circuit; Buffering the plurality of grayscale data and the plurality of current gain data through a buffer circuit electrically coupled to the interface circuit; By means of a channel grayscale control circuit electrically coupling the command processing circuit, the buffer circuit and the current source circuit, the opening duration of the multiple channel current sources is controlled respectively according to the multiple grayscale data; as well as The output current magnitudes of the plurality of channel current sources are respectively controlled according to the plurality of current gain data by means of a channel current control circuit electrically coupled to the buffer circuit and the current source circuit; wherein the channel current control circuit comprises a plurality of channel current gain regulators, and the plurality of channel current gain regulators are respectively electrically coupled to the plurality of channel current sources and are respectively controlled by the plurality of current gain data; The current source circuit also includes multiple color component global current gain regulators or one global current gain regulator, and when the current source circuit includes multiple color component global current gain regulators, each of the color component global current gain regulators is electrically coupled to multiple channel current sources among the multiple channel current sources for carrying the same color sub-pixels; when the current source circuit includes one global current gain regulator, the global current gain regulator is electrically connected to multiple channel current sources, and the multiple channel current sources are used to carry all the color sub-pixels therein.

15. The display driving method according to claim 14, wherein: The step of controlling the opening time of multiple channel current sources respectively according to the multiple grayscale data comprises: receiving a grayscale clock signal and generating a grayscale clock count value under the control of the grayscale clock signal; Controlling the counting operation of the counter based on the grayscale scattering algorithm and generating a grayscale grouping control signal; The plurality of grayscale data are acquired respectively, and a plurality of grayscale display control signals are generated under the control of the grayscale clock count value and the grayscale grouping control signal and transmitted to the plurality of channel current sources respectively to control the opening time of the plurality of channel current sources.

16. The display driving method according to claim 15, characterized in that: The method of controlling the opening time of the plurality of channel current sources respectively according to the plurality of grayscale data further includes: The input clock signal is frequency-multiplied to generate the gray-scale clock signal.

17. The display driving method according to claim 14, wherein: The step of respectively controlling the output current magnitudes of the plurality of channel current sources according to the plurality of current gain data comprises: The output current magnitudes of the plurality of channel current sources are respectively controlled according to the plurality of point-by-point current gain data.

18. The display driving method according to claim 17, wherein: The buffering of the plurality of grayscale data and the plurality of current gain data comprises: Ping-pong storage is used to cache grayscale data frame by frame and point by point; Ping-pong storage is used to cache the current gain data frame by frame and point by point.

19. The display driving method according to claim 14, wherein: The step of respectively controlling the output current magnitudes of the plurality of channel current sources according to the plurality of current gain data comprises: The output current magnitudes of the plurality of channel current sources are respectively controlled according to the plurality of channel-by-channel current gain data.

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