A network-on-chip conversion interface for a DDR3 controller
By designing an on-chip network conversion interface for the DDR3 controller, the problem of exchange rate between the on-chip network and the DDR3 controller was solved, achieving high-speed communication and improved cost-effectiveness.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 58TH RES INST OF CETC
- Filing Date
- 2023-01-31
- Publication Date
- 2026-06-23
AI Technical Summary
In existing technologies, there are issues with the exchange rate between the on-chip network and the DDR3 controller, resulting in low communication efficiency.
An on-chip network conversion interface for DDR3 controllers is designed, including an input asynchronous bridge, an output asynchronous bridge, and a protocol conversion processing module. Data buffering and cross-clock domain processing are implemented through asynchronous FIFO and valid-ready handshake logic, and data packets are converted to AXI bus signals. Protocol conversion of request and response packets is supported.
It enables high-speed communication between the on-chip network and the DDR3 controller, shortening the development cycle and reducing development costs.
Smart Images
Figure CN115982071B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit communication technology, and in particular to an on-chip network conversion interface for DDR3 controllers. Background Technology
[0002] Integrated circuit technology has been developing rapidly in accordance with Moore's Law. However, as the size of integrated circuits has continued to shrink in recent years, Moore's Law is approaching its physical limits, and the cost and cycle time for developing application-specific integrated circuits (ASICs) are gradually increasing. Market demand for semiconductor performance continues to grow; therefore, combining circuit functions at the chip level will play a significant role in continuously improving chip performance. Summary of the Invention
[0003] The purpose of this invention is to provide an on-chip network conversion interface for DDR3 controllers to solve the problem of the current exchange rate between on-chip networks and DDR3 controllers, and to realize high-speed communication between on-chip networks and storage devices.
[0004] To address the aforementioned technical problems, this invention provides an on-chip network conversion interface for a DDR3 controller, used to connect the on-chip network and the DDR3 controller, receive data packets of various request types, execute corresponding configuration procedures for the DDR3 controller to control the DDR3 SDRAM to complete read and write operations, and return data packets of various response types to the on-chip network;
[0005] The on-chip network conversion interface for the DDR3 controller includes an input asynchronous bridge, an output asynchronous bridge, and a protocol conversion processing module; wherein the input asynchronous bridge and the output asynchronous bridge are both implemented by asynchronous FIFO and valid-ready handshake logic;
[0006] The input asynchronous bridge receives request packets from the on-chip network input port, performs data buffering and cross-clock domain processing based on asynchronous FIFO, and outputs the request packets to the protocol conversion processing module.
[0007] The output asynchronous bridge receives the response packet and acknowledgment packet output by the protocol conversion processing module, performs data buffering and cross-clock domain processing based on asynchronous FIFO, and finally outputs to the on-chip network through the output port;
[0008] The protocol conversion processing module as a whole realizes the conversion between data packets and AXI bus signals. On the one hand, it receives request packets from the input asynchronous bridge, and the request packet processing module in the protocol conversion processing module realizes the protocol conversion from request packets to AXI read and write control. On the other hand, it receives AXI responses, and the response packet processing module in the protocol conversion processing module realizes the protocol conversion from AXI responses to response packets.
[0009] In one embodiment, the protocol conversion processing module includes a request packet processing module, a response packet processing module, a request queue, and an output control module. The request queue is written by the request packet processing module and read by the response packet processing module, and is used by the request packet processing module to transmit pending response channel information to the response packet processing module. The output control module handles possible output conflicts between two data streams, and is responsible for arbitration and multiplexing. One input data stream is a response packet from the response packet processing module, and the other input data stream is a read confirmation packet from the request packet processing module. The output is connected to an output asynchronous bridge.
[0010] In one embodiment, the request packet processing module includes unpacking logic, verification logic, an end-to-end read confirmation packet module, a request packet processing protocol conversion control state machine, a response information register, an ID lock, and a write data concatenation module.
[0011] The unpacking logic unpacks the input request packet and outputs the unpacking information to the request packet processing protocol conversion control state machine; the verification logic verifies the input request packet fragments and outputs the verification result to the request packet processing protocol conversion control state machine.
[0012] The end-to-end read confirmation packet module packages the read confirmation packet according to the input information and outputs it to the output control module; the response information register receives the response information, stores it, and outputs it to the response packet processing module.
[0013] The ID lock receives an unlock request from the response packet processing module to unlock the corresponding TID, receives a lock request from the request packet processing protocol conversion control state machine to lock the corresponding TID, and receives a check signal from the request packet processing protocol conversion control state machine to output the current ID lock state of the corresponding TID; the write data splicing module receives write data and control information from the request packet processing protocol conversion control state machine and completes data splicing.
[0014] In one implementation, the request packet processing protocol conversion control state machine is the core of the request packet processing module. The request packet processing protocol conversion control state machine receives unpacking information and verification results, controls the protocol conversion process of the request packet to the AXIAW channel and the AXIAR channel, drives the write data splicing module to complete the splicing and alignment of data, and thus completes the protocol conversion process of writing data to the AXIW channel.
[0015] The request packet processing protocol conversion control state machine also controls the workflow of other modules or outputs necessary information to other modules. Specifically, it outputs read confirmation packet information and control signals to the end-to-end read confirmation packet module, controls the response channel type to be written to the request queue, outputs write data verification error vector to the response packet processing module, controls the response information and register enable to be written to the response information register, and queries whether the corresponding TID of the currently processed data packet is locked.
[0016] In one embodiment, the end-to-end read confirmation packet module includes an end-to-end read confirmation packet information register, a read confirmation packet control state machine, and read confirmation packet packing logic. The end-to-end read confirmation packet module controls the generation and output process of each microchip in the read confirmation packet through the read confirmation packet control state machine, and updates the end-to-end read confirmation packet information by handshaking with the request packet processing protocol conversion control state machine through the read request verification completion signal and the final read confirmation completion signal. In the read confirmation packet packing logic, the on-chip network routing module is instantiated to obtain the on-chip network routing information required in the header microchip, and various types of microchips are generated according to the data packet format, while adding a check bit to each microchip.
[0017] In one embodiment, the response packet processing module includes a response packet processing protocol conversion control state machine, a read data splicing module, and packaging logic. The response packet processing protocol conversion control state machine is the core of the response packet processing module. The response packet processing module receives the pending response channel type information from the request queue and the write data verification error vector and response information from the request packet processing module. It completes the transmission processing of the AXI B channel and the AXI R channel, outputs the read data to the read data splicing module to complete data splicing and alignment, controls the packaging logic to complete the packaging of the response packet, and is also responsible for initiating an unlock request to the ID lock in the request packet processing module. The read data splicing module receives read data and control signals from the response packet processing protocol conversion control state machine and outputs the spliced data to the packaging logic. The packaging logic is controlled by the response packet processing protocol conversion control state machine, receives the response information and the spliced read data to complete the packaging of the response packet, and outputs it to the output control module.
[0018] In one implementation, the output control module resolves output conflicts by using a 2-to-1 multiplexer and fixed-priority arbitration to perform multiplexing on two data packets from the end-to-end read acknowledgment module and the response packet processing module. The output control module arbitrates and multiplexes on a data packet-by-data packet basis. Arbitration is performed when both data packet headers are received simultaneously. The packet that gains permission occupies the response path until the entire data packet is output, while the other data packet waits for the next arbitration. The arbitration method is fixed-priority arbitration, where the read acknowledgment packet from the end-to-end read acknowledgment module is currently set to have a higher priority. The output control module also uses valid and ready signals to handshake with other modules to ensure that no data is lost during transmission.
[0019] In one implementation, the output control module is a single-bit queue that can be used as a synchronous FIFO with a bit width of 1. The request packet processing module controls the writing, and the response packet processing module controls the reading. The single-bit data in the queue indicates the type of AXI response channel that the response packet processing module needs to process next. When it is 0, it represents an AXI R channel, and when it is 1, it represents an AXI B channel. After reading the data from the request queue, the response packet processing module will execute a read response process or a write response process accordingly.
[0020] In one implementation, data transmission in the on-chip network is defined as being performed in units of data packets, and the data transmitted on a data link in the on-chip network within one clock cycle is defined as a micro-slice. Each data packet consists of several micro-slices. All data packets contain a header micro-slice, several body micro-slices, and a tail micro-slice. The header micro-slice stores all valid information of the current data packet to mark the start position of the data packet, the body micro-slices are used to load the valid data payload, and the tail micro-slice is used to mark the end position of the data packet.
[0021] Define the various event types in data transmission: general events, shared write events, DMA events, erase events, and interrupt events; among them, general events include write data events, write response events, read request events, and read response events; DMA events include DMA write data events, DMA write response events, and DMA read request events.
[0022] This invention provides an on-chip network conversion interface for DDR3 controllers, including an input asynchronous bridge, an output asynchronous bridge, and a protocol conversion processing module. Both the input and output asynchronous bridges are implemented using asynchronous FIFO and valid-ready handshake logic. The input asynchronous bridge receives request packets from the on-chip network input port, performs data buffering and cross-clock domain processing based on the asynchronous FIFO, and outputs the request packets to the protocol conversion processing module. The output asynchronous bridge receives response and acknowledgment packets output by the protocol conversion processing module, also performs data buffering and cross-clock domain processing based on the asynchronous FIFO, and finally outputs the packets to the on-chip network through the output port. The protocol conversion processing module as a whole implements the conversion between data packets and AXI bus signals. This invention will play a crucial role in the rapid integration and expansion of DDR3 and other storage devices, significantly shortening the development cycle and reducing development costs. Attached Figure Description
[0023] Figure 1 This is a schematic diagram of the structure of an on-chip network conversion interface for a DDR3 controller provided by the present invention;
[0024] Figure 2 This invention provides a conversion interface for the protocol conversion of basic events.
[0025] Figure 3 This is a block diagram of the request packet processing module;
[0026] Figure 4 This is an overall block diagram of the end-to-end read confirmation packet module;
[0027] Figure 5 This is an overall block diagram of the response packet processing module. Detailed Implementation
[0028] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the on-chip network conversion interface for DDR3 controllers proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.
[0029] This invention primarily implements the design of an on-chip network conversion interface for a DDR3 controller. It mainly consists of an input asynchronous bridge, an output asynchronous bridge, and a protocol conversion processing module. The protocol conversion processing module comprises a request packet processing module, a response packet processing module, a request queue, and an output control module. The input asynchronous bridge receives request packets from the on-chip network input port, performs data buffering and cross-clock domain processing based on an asynchronous FIFO, and outputs the request packet to the protocol conversion processing module. The output asynchronous bridge receives response packets and acknowledgment packets output by the output control module in the protocol conversion processing module, also performs data buffering and cross-clock domain processing based on an asynchronous FIFO, and finally outputs them to the on-chip network through the output port. The protocol conversion processing module as a whole implements the conversion between data packets and AXI bus signals. On one hand, it receives request packets from the input asynchronous bridge, and the request packet processing module performs protocol conversion from request packets to AXI read / write control; on the other hand, it receives AXI responses, and the response packet processing module performs protocol conversion from AXI responses to response packets. The request queue within the protocol conversion processing module is written by the request packet processing module and read by the response packet processing module. It is used by the request packet processing module to transmit pending response channel information (i.e., AXI B or AXI R) to the response packet processing module. The output control module within the protocol conversion processing module handles potential output conflicts between the two data streams, handling arbitration and multiplexing. One input stream is a response packet from the response packet processing module, and the other is a read acknowledgment packet from the request packet processing module. The output is connected to an asynchronous bridge at the output end. Specific design details are as follows:
[0030] This invention provides an on-chip network conversion interface (i.e., a DDR3 conversion interface) for a DDR3 controller, the structure of which is as follows: Figure 1 As shown; the protocol conversion processing module mainly consists of a request packet processing module, a response packet processing module, a request queue, and an output control module.
[0031] The asynchronous bridge in this invention is implemented using an asynchronous FIFO and valid-ready handshake logic. The input asynchronous bridge receives request packets from the on-chip network input port, performs data buffering and cross-clock domain processing based on the asynchronous FIFO, and outputs the request packets to the protocol conversion processing module. The output asynchronous bridge receives response packets and acknowledgment packets output by the output control module in the protocol conversion processing module, also performs data buffering and cross-clock domain processing based on the asynchronous FIFO, and finally outputs them to the on-chip network through the output port.
[0032] The DDR3 conversion interface of this invention is used to connect the on-chip network and the DDR3 controller, such as... Figure 2As shown, the interface can receive data packets of various request types and execute corresponding configuration procedures for the DDR3 controller to control the DDR3 SDRAM to complete read and write operations, and return data packets of various response types to the on-chip network. The DDR3 conversion interface only supports read and write operations with word-aligned addresses, meaning the address of the read and write operation must be a multiple of 4. Data transmission in the on-chip network is specified to be performed in units of data packets, and the data transmitted on a data link in the network within one clock cycle is defined as a micro-pie, with each data packet consisting of several micro-pies. All data packets contain a header micro-pie, several body micro-pies, and a tail micro-pie; the header micro-pie stores all valid information of the current data packet to mark the start position of the data packet, the body micro-pie is used to load the valid data payload, and the tail micro-pie is used to mark the end position of the data packet. Various event types in data transmission are specified: general events, shared write events, DMA events, erase events, and interrupt events. General events include write data events, write response events, read request events, and read response events; DMA events include DMA write data events, DMA write response events, and DMA read request events.
[0033] The block diagram of the request packet processing module is as follows: Figure 3 As shown, the system includes unpacking logic, verification logic, an end-to-end read confirmation packet module, a request packet processing protocol conversion control state machine, a response information register, an ID lock, and a write data concatenation module. The unpacking logic unpacks the input request packet and outputs unpacking information to the request packet processing protocol conversion control state machine. The verification logic verifies the input request packet fragments and outputs the verification result to the request packet processing protocol conversion control state machine. The end-to-end read confirmation packet module packages the read confirmation packet according to the input information and outputs it to the output control module. The response information register receives response information, stores it, and outputs it to the response packet processing module. The ID lock receives unlock requests from the response packet processing module to unlock the corresponding TID, receives lock requests from the request packet processing protocol conversion control state machine to lock the corresponding TID, and receives check signals from the request packet processing protocol conversion control state machine to output the current ID lock state of the corresponding TID. The write data concatenation module receives write data and control information from the request packet processing protocol conversion control state machine and completes data concatenation.
[0034] The request packet processing protocol conversion control state machine is the core of the request packet processing module. This state machine receives unpacking information and verification results, controls the protocol conversion process of request packets to the AXI AW channel and AXI AR channel, drives the write data splicing module to complete data splicing and alignment, and thus completes the protocol conversion process of write data to the AXI W channel. Furthermore, the request packet processing protocol conversion control state machine also controls the workflow of other modules or outputs necessary information to other modules. Specifically, this includes outputting read confirmation packet information and control signals to the end-to-end read confirmation packet module, controlling the response channel type to be written to the request queue, outputting write data verification error vectors to the response packet processing module, controlling the response information and register enable to be written to the response information register, and checking whether the corresponding TID of the currently processed data packet is locked, etc.
[0035] The overall block diagram of the end-to-end read confirmation packet module is as follows: Figure 4 As shown, the module includes an end-to-end read confirmation packet information register, a read confirmation packet control state machine, and read confirmation packet packing logic. The end-to-end read confirmation packet module primarily controls the generation and output process of each micro-piece within the read confirmation packet through the read confirmation packet control state machine. It updates the end-to-end read confirmation packet information by handshaking with the request packet processing protocol transition control state machine using the rdreq_checkdone signal (i.e., the read request verification completion signal) and the last_rdack_done signal (i.e., the final read confirmation completion signal). The read confirmation packet packing logic instantiates a NoP (Network on Chip) routing module to obtain the required NoP routing information from the header micro-pieces, generates various types of micro-pieces according to the data packet format, and adds check bits to each micro-piece.
[0036] The overall block diagram of the response packet processing module is as follows: Figure 5 As shown, the overall system includes a response packet processing protocol conversion control state machine, a data reading and splicing module, and packetization logic. Figure 5 As shown, the response packet processing protocol conversion control state machine is the core of the response packet processing module. This module receives the pending response channel type information from the request queue, the write data verification error vector, and the response information from the request packet processing module. It completes the transmission processing of the AXI B and AXI R channels, outputs the read data to the read data splicing module for data splicing and alignment, controls the packaging logic to package the response packet, and is also responsible for initiating an unlock request to the ID lock within the request packet processing module. The read data splicing module receives read data and control signals from the response packet processing protocol conversion control state machine and outputs the spliced data to the packaging logic. The packaging logic, controlled by the response packet processing protocol conversion control state machine, receives the response information and the spliced read data to package the response packet and outputs it to the output control module.
[0037] The output control module in this invention resolves output conflicts by using a 2-to-1 multiplexer and fixed-priority arbitration to perform multiplexing on two data packets: one from the end-to-end read acknowledgment module and the other from the response packet processing module. The output control module arbitrates and multiplexes on a data packet-by-data packet basis. Specifically, arbitration is performed when both data packet header fragments are received simultaneously. The packet that gains permission occupies the response path until the entire data packet is output (i.e., the tail fragment is output), while the other data packet waits for the next arbitration. The arbitration method is fixed-priority arbitration, with the read acknowledgment packet from the end-to-end read acknowledgment module currently having a higher priority. The output control module also uses valid and ready signals to handshake with other modules, ensuring no data loss occurs during transmission.
[0038] The output control module in this invention is a single-bit queue, which can be used as a synchronous FIFO with a bit width of 1. The request packet processing module controls the writing, and the response packet processing module controls the reading. The single-bit data in the queue indicates the type of AXI response channel that the response packet processing module needs to process next; 0 represents an AXI R channel, and 1 represents an AXI B channel. After reading the data from the request queue, the response packet processing module will execute either a read response process or a write response process accordingly.
[0039] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. An on-chip network conversion interface for a DDR3 controller, characterized in that, It is used to connect the on-chip network and the DDR3 controller, receive data packets of various request types, execute corresponding configuration procedures for the DDR3 controller to control the DDR3 SDRAM to complete read and write operations, and return data packets of various response types to the on-chip network. The on-chip network conversion interface for the DDR3 controller includes an input asynchronous bridge, an output asynchronous bridge, and a protocol conversion processing module; wherein the input asynchronous bridge and the output asynchronous bridge are both implemented by asynchronous FIFO and valid-ready handshake logic; The input asynchronous bridge receives request packets from the on-chip network input port, performs data buffering and cross-clock domain processing based on asynchronous FIFO, and outputs the request packets to the protocol conversion processing module. The output asynchronous bridge receives the response packet and acknowledgment packet output by the protocol conversion processing module, performs data buffering and cross-clock domain processing based on asynchronous FIFO, and finally outputs to the on-chip network through the output port; The protocol conversion processing module as a whole realizes the conversion between data packets and AXI bus signals. On the one hand, it receives request packets from the input asynchronous bridge, and the request packet processing module in the protocol conversion processing module realizes the protocol conversion from request packets to AXI read and write control. On the other hand, it receives AXI responses, and the response packet processing module in the protocol conversion processing module realizes the protocol conversion from AXI responses to response packets.
2. The on-chip network conversion interface for a DDR3 controller as described in claim 1, characterized in that, The protocol conversion processing module includes a request packet processing module, a response packet processing module, a request queue, and an output control module. The request queue is written by the request packet processing module and read by the response packet processing module, and is used by the request packet processing module to transmit the response channel information to be processed to the response packet processing module. The output control module handles possible output conflicts between two data streams, and is responsible for arbitration and multiplexing. One input data stream is a response packet from the response packet processing module, and the other input data stream is a read confirmation packet from the request packet processing module. The output is connected to the output asynchronous bridge.
3. The on-chip network conversion interface for a DDR3 controller as described in claim 2, characterized in that, The request packet processing module includes unpacking logic, verification logic, end-to-end read confirmation packet module, request packet processing protocol conversion control state machine, response information register, ID lock and write data splicing module; The unpacking logic unpacks the input request packet and outputs the unpacking information to the request packet processing protocol conversion control state machine; the verification logic verifies the input request packet fragments and outputs the verification result to the request packet processing protocol conversion control state machine. The end-to-end read confirmation packet module packages the read confirmation packet according to the input information and outputs it to the output control module; The response information register receives response information, stores it, and outputs it to the response packet processing module. The ID lock receives an unlock request from the response packet processing module to unlock the corresponding TID, receives a lock request from the request packet processing protocol conversion control state machine to lock the corresponding TID, and receives a check signal from the request packet processing protocol conversion control state machine to output the current ID lock state of the corresponding TID; the write data splicing module receives write data and control information from the request packet processing protocol conversion control state machine and completes data splicing.
4. The on-chip network conversion interface for a DDR3 controller as described in claim 3, characterized in that, The request packet processing protocol conversion control state machine is the core of the request packet processing module. The request packet processing protocol conversion control state machine receives unpacking information and verification results, controls the protocol conversion process of the request packet to the AXI AW channel and the AXI AR channel, drives the write data splicing module to complete the splicing and alignment of data, and then completes the protocol conversion process of writing data to the AXI W channel. The request packet processing protocol conversion control state machine also controls the workflow of other modules or outputs necessary information to other modules. Specifically, it outputs read confirmation packet information and control signals to the end-to-end read confirmation packet module, controls the response channel type to be written to the request queue, outputs write data verification error vector to the response packet processing module, controls the response information and register enable to be written to the response information register, and queries whether the corresponding TID of the currently processed data packet is locked.
5. The on-chip network conversion interface for a DDR3 controller as described in claim 4, characterized in that, The end-to-end read confirmation packet module includes an end-to-end read confirmation packet information register, a read confirmation packet control state machine, and read confirmation packet packaging logic. The end-to-end read confirmation packet module controls the generation and output process of each micro-chip in the read confirmation packet through the read confirmation packet control state machine, and updates the end-to-end read confirmation packet information by handshaking with the read request verification completion signal and the final read confirmation completion signal and the request packet processing protocol conversion control state machine. In the read confirmation packet packaging logic, the on-chip network routing module is instantiated to obtain the on-chip network routing information required in the header micro-chip, and various types of micro-chips are generated according to the data packet format, while adding check bits to each micro-chip.
6. The on-chip network conversion interface for a DDR3 controller as described in claim 5, characterized in that, The response packet processing module includes a response packet processing protocol conversion control state machine, a read data splicing module, and packaging logic. The response packet processing protocol conversion control state machine is the core of the response packet processing module. This module receives the pending response channel type information from the request queue, the write data verification error vector, and the response information from the request packet processing module. It completes the transmission processing of the AXI B and AXI R channels, outputs the read data to the read data splicing module for data splicing and alignment, controls the packaging logic to package the response packet, and is also responsible for initiating an unlock request to the ID lock within the request packet processing module. The read data splicing module receives read data and control signals from the response packet processing protocol conversion control state machine and outputs the spliced data to the packaging logic. The packaging logic, controlled by the response packet processing protocol conversion control state machine, receives the response information and the spliced read data to package the response packet and outputs it to the output control module.
7. The on-chip network conversion interface for a DDR3 controller as described in claim 6, characterized in that, The output control module resolves output conflicts by using a two-to-one multiplexer and fixed-priority arbitration to perform multiplexing on two data packets from the end-to-end read acknowledgment packet module and the response packet processing module. The output control module will arbitrate and multiplex data packets. Arbitration will be performed when two data packet header fragments are received simultaneously. The one that obtains permission will occupy the response path until the entire data packet is output, while the other data packet will wait for the next arbitration. The arbitration method is fixed priority arbitration. Currently, the read confirmation packet from the end-to-end read confirmation packet module is set to have a higher priority. The output control module also uses valid and ready signals to handshake with other modules to ensure that no data is lost during transmission.
8. The on-chip network conversion interface for a DDR3 controller as described in claim 7, characterized in that, The output control module is a single-bit queue that can be used as a synchronous FIFO with a bit width of 1. It is controlled by the request packet processing module for writing and the response packet processing module for reading. The single-bit data in the queue indicates the type of AXI response channel that the response packet processing module needs to process next. When it is 0, it represents an AXI R channel, and when it is 1, it represents an AXI B channel. After reading the data from the request queue, the response packet processing module will execute a read response process or a write response process accordingly.
9. The on-chip network conversion interface for a DDR3 controller as described in claim 8, characterized in that, The data transmission in the on-chip network is specified to be carried out in units of data packets, and the data transmitted on a data link in the on-chip network within one clock cycle is defined as a micro-slice. Each data packet consists of several micro-slices. All data packets contain a header micro-slice, several body micro-slices, and a tail micro-slice. The header micro-slice stores all the valid information of the current data packet to mark the start position of the data packet, the body micro-slices are used to load the valid data payload, and the tail micro-slice is used to mark the end position of the data packet. Define the various event types in data transmission: general events, shared write events, DMA events, erase events, and interrupt events; among them, general events include write data events, write response events, read request events, and read response events; DMA events include DMA write data events, DMA write response events, and DMA read request events.