A method for establishing a transistor model based on an artificial neural network
By using an artificial neural network-based method, an initial transistor model is established and current signals are fitted, which solves the problem of low efficiency in transistor model establishment in existing technologies. This achieves high-precision and fast transistor modeling, applicable to transistors with various process technologies and physical principles.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUZHOU FUHU ELECTRONIC TECH CO LTD
- Filing Date
- 2023-01-03
- Publication Date
- 2026-06-30
AI Technical Summary
Existing methods for building transistor models have limitations, making it difficult to build transistor models quickly and efficiently, especially under small size effects and new processes. Traditional models lack automated processes and the simulation results are inaccurate.
By employing an artificial neural network-based approach, an initial model is established by acquiring the transistor's process type. DC and AC voltage signals are applied to its ports, and a pre-defined artificial neural network is used to fit the DC current output signal. The gate-drain, gate-source, and gate-body capacitance values are then calculated to establish a high-precision transistor model.
It significantly improves the simulation accuracy and versatility of transistor models while maintaining fast simulation speed, making it applicable to transistors with different process technologies and physical principles, and shortening the modeling time of module circuits.
Smart Images
Figure CN115983177B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of circuit layout technology, specifically a method for establishing transistor models based on artificial neural networks. Background Technology
[0002] Transistors are key components of analog integrated circuits, and their compact models play a crucial role in integrated circuit design. The accuracy of the compact model has a significant impact on the design of analog circuits. As a mainstream transistor model, several versions of the BSIM model have been developed over decades. Traditional compact transistor models, such as BSIM, PSP, and HiSim, are physical-driven models and are widely used in industry.
[0003] However, with the advancement of Moore's Law, the mainstream BSIM compact model faces challenges. As transistor dimensions continue to shrink, the impact of small-size effects (such as short-channel effects) increases, making the physical characteristics of transistor devices more complex and thus making the BSIM model more difficult to fit. Furthermore, with the continuous shrinking of manufacturing processes, new transistor technologies are being developed, requiring updates or even the complete redevelopment of corresponding transistor models. For example, the emergence of new transistor device structures (such as tunneling field-effect transistors and negative capacitance field-effect transistors) can no longer be modeled using traditional BSIM models. In addition, traditional physics-driven models, due to their increasingly complex formulas and lack of automated model extraction processes, mean that the accuracy of the extracted transistor models largely depends on the engineer's experience.
[0004] Compared to traditional compact transistor physical models, lookup tables (LUTs) have been proposed as an alternative to physical models. However, LUT models still have some problems. First, LUT models require large-scale circuit simulations to obtain a large amount of simulation data. Second, when simulating and verifying large-scale circuits, convergence problems in LUT models may affect the simulation results. Furthermore, since there are no input parameters, different sizes require corresponding simulation data, so a separate LUT model needs to be built for each device. These problems make the LUT method difficult to apply in practice.
[0005] Therefore, most existing methods for establishing transistor models have many limitations and cannot establish transistor models quickly and efficiently. Summary of the Invention
[0006] In view of this, the purpose of this invention is to provide a transistor model building method based on artificial neural networks, so as to solve the technical problem that most existing transistor model building methods have many limitations and cannot quickly and efficiently build transistor models.
[0007] To achieve the above objectives, the present invention adopts the following technical solution:
[0008] The present invention provides a method for establishing a transistor model based on an artificial neural network, comprising the following steps:
[0009] Obtain the transistor process type;
[0010] An initial transistor model is established based on the transistor process type, and the initial transistor model includes multiple ports;
[0011] A DC voltage input signal is applied to each port of the transistor initial model, and the DC current output signal of each port of the transistor initial model is extracted.
[0012] A transistor DC model is obtained by fitting the DC voltage input signal and the DC current output signal using a preset artificial neural network.
[0013] Furthermore, when the transistor model includes a gate terminal and a drain terminal, the transistor model establishment method further includes:
[0014] A DC voltage signal is applied to each port of the initial transistor model, and an AC voltage signal is applied to the drain terminal of the initial transistor model.
[0015] After applying a DC voltage signal to each port of the initial transistor model and an AC voltage signal to the drain terminal of the initial transistor model, a current signal is extracted from the gate terminal of the initial transistor model.
[0016] A current-frequency Bode plot is drawn based on the DC voltage signal and the current signal, where the horizontal axis of the current-frequency Bode plot is frequency and the vertical axis is current.
[0017] Extract the target point from the current-frequency Bode plot, and calculate the transistor gate-drain capacitance C based on the current and frequency of the target point. gd The gate-drain capacitance value C of the transistor gd The calculation formula is:
[0018] V ac = I ac × 1 / (2×π×f×C gd )
[0019] In the formula, V ac Iac is the AC voltage signal, Iac is the current signal at the target point, and f is the frequency of the target point;
[0020] Based on the transistor gate-drain capacitance value C gdA transistor gate-drain capacitance model is established, wherein the input signal of the transistor gate-drain capacitance model is a DC voltage signal, and the output signal of the transistor gate-drain capacitance model is the transistor gate-drain capacitance value C. gd。
[0021] Furthermore, when the transistor model includes a gate terminal and a source terminal, the transistor model establishment method further includes:
[0022] A DC voltage signal is applied to each port of the initial transistor model, and an AC voltage signal is applied to the source terminal of the initial transistor model.
[0023] A DC voltage signal is applied to each port of the transistor initial model, and an AC voltage signal is applied to the source terminal of the transistor initial model. Then, a current signal is extracted from the gate terminal of the transistor initial model.
[0024] A current-frequency Bode plot is drawn based on the DC voltage signal and the current signal, where the horizontal axis of the current-frequency Bode plot is frequency and the vertical axis is current.
[0025] Extract the target point from the current-frequency Bode plot, and calculate the transistor gate-source capacitance C based on the current and frequency of the target point. gs The gate-source capacitance value C of the transistor gs The calculation formula is:
[0026] V ac = I ac × 1 / (2×π×f×C gs )
[0027] In the formula, V ac Iac is the AC voltage signal, Iac is the current signal at the target point, and f is the frequency of the target point;
[0028] Based on the transistor gate-source capacitance value C gs A transistor gate-source capacitance model is established, wherein the input signal of the transistor gate-source capacitance model is a DC voltage signal, and the output signal of the transistor gate-source capacitance model is the transistor gate-source capacitance value C. gs。
[0029] Furthermore, when the transistor model includes a gate terminal and a body terminal, the transistor model establishment method further includes:
[0030] A DC voltage signal is applied to each port of the initial transistor model, and an AC voltage signal is applied to the body terminal of the initial transistor model.
[0031] After applying a DC voltage signal to each port of the initial transistor model and an AC voltage signal to the body terminal of the initial transistor model, a current signal is extracted from the gate terminal of the initial transistor model.
[0032] A current-frequency Bode plot is drawn based on the DC voltage signal and the current signal, where the horizontal axis of the current-frequency Bode plot is frequency and the vertical axis is current.
[0033] Extract the target point from the current-frequency Bode plot, and calculate the transistor gate capacitance C based on the current and frequency of the target point. gb The gate capacitance value C of the transistor gb The calculation formula is:
[0034] V ac = I ac × 1 / (2×π×f×C gb )
[0035] In the formula, V ac Iac is the AC voltage signal, Iac is the current signal at the target point, and f is the frequency of the target point;
[0036] Based on the transistor gate capacitance value C gb A transistor gate capacitance model is established, wherein the input signal of the transistor gate capacitance model is a DC voltage signal, and the output signal of the transistor gate capacitance model is the transistor gate capacitance value C. gb。
[0037] The beneficial effects of this invention are as follows: This invention provides a transistor model establishment method based on an artificial neural network. The method involves: acquiring the transistor process type; establishing an initial transistor model based on the transistor process type, the initial transistor model including multiple ports; applying a DC voltage input signal to each port of the initial transistor model and extracting the DC current output signal of each port; and fitting the DC voltage input signal and the DC current output signal to a preset artificial neural network to obtain a DC transistor model. This invention uses an artificial neural network to capture the relationship between the input and output (current and voltage) of the transistor model. The model simultaneously considers both DC and AC signals. It enables high-precision modeling of transistors and significantly improves the simulation accuracy of transistors while maintaining a fast simulation speed. Attached Figure Description
[0038] The present invention will be further described below with reference to the accompanying drawings and embodiments:
[0039] Figure 1 is a flowchart illustrating a method for establishing a transistor model based on an artificial neural network;
[0040] Figure 2 is a schematic diagram of the transistor model in this application;
[0041] Figure 3 is a current-frequency Bode plot in one embodiment of this application. Detailed Implementation
[0042] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.
[0043] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0044] Numerous details are explored in the following description to provide a more thorough explanation of embodiments of this application; however, it will be apparent to those skilled in the art that embodiments of this application may be practiced without these specific details.
[0045] like Figures 1-2 As shown, a method for establishing a transistor model based on an artificial neural network in this embodiment includes the following steps:
[0046] S110, obtain the transistor process type;
[0047] S120, Establish an initial transistor model based on the transistor process type, the initial transistor model including multiple ports;
[0048] S130, apply DC voltage input signals to each port of the transistor initial model, and extract DC current output signals from each port of the transistor initial model;
[0049] S140, the DC voltage input signal and the DC current output signal are fitted by a preset artificial neural network to obtain a transistor DC model.
[0050] In one embodiment of the present invention, when the transistor model includes a gate terminal and a drain terminal, the transistor model building method further includes the following steps:
[0051] S210, apply a DC voltage signal to each port of the transistor initial model and apply an AC voltage signal to the drain terminal of the transistor initial model;
[0052] S220, After applying a DC voltage signal to each port of the transistor initial model and applying an AC voltage signal to the drain terminal of the transistor initial model, a current signal is extracted from the gate terminal of the transistor initial model.
[0053] S230, Plot a current-frequency Bode plot based on the DC voltage signal and the current signal, wherein the horizontal axis of the current-frequency Bode plot is frequency and the vertical axis of the current-frequency Bode plot is current;
[0054] S240, extract the target point from the current-frequency Bode plot, and calculate the transistor gate-drain capacitance C based on the current and frequency of the target point. gd The gate-drain capacitance value C of the transistor gd The calculation formula is:
[0055] V ac = I ac × 1 / (2×π×f×C gd )
[0056] In the formula, V ac Iac is the AC voltage signal, Iac is the current signal at the target point, and f is the frequency of the target point;
[0057] S250, based on the transistor gate-drain capacitance value C gd A transistor gate-drain capacitance model is established, wherein the input signal of the transistor gate-drain capacitance model is a DC voltage signal, and the output signal of the transistor gate-drain capacitance model is the transistor gate-drain capacitance value C. gd。
[0058] In one embodiment of the present invention, when the transistor model includes a gate terminal and a source terminal, the transistor model establishment method further includes:
[0059] S310, apply a DC voltage signal to each port of the transistor initial model and apply an AC voltage signal to the source terminal of the transistor initial model;
[0060] S320, apply a DC voltage signal to each port of the transistor initial model, and after applying an AC voltage signal to the source terminal of the transistor initial model, extract a current signal from the gate terminal of the transistor initial model;
[0061] S330, Plot a current-frequency Bode plot based on the DC voltage signal and the current signal, wherein the horizontal axis of the current-frequency Bode plot is frequency and the vertical axis of the current-frequency Bode plot is current;
[0062] S340, extract the target point from the current-frequency Bode plot, and calculate the transistor gate-source capacitance C based on the current and frequency of the target point. gs The gate-source capacitance value C of the transistor gs The calculation formula is:
[0063] V ac = I ac × 1 / (2×π×f×C gs )
[0064] In the formula, V ac Iac is the AC voltage signal, Iac is the current signal at the target point, and f is the frequency of the target point;
[0065] S350, based on the transistor gate-source capacitance value C gs A transistor gate-source capacitance model is established, wherein the input signal of the transistor gate-source capacitance model is a DC voltage signal, and the output signal of the transistor gate-source capacitance model is the transistor gate-source capacitance value C. gs。
[0066] In one embodiment of the present invention, when the transistor model includes a gate terminal and a body terminal, the transistor model building method further includes:
[0067] S410, apply a DC voltage signal to each port of the transistor initial model and apply an AC voltage signal to the body terminal of the transistor initial model;
[0068] S420, after applying a DC voltage signal to each port of the transistor initial model and applying an AC voltage signal to the body terminal of the transistor initial model, extract a current signal from the gate terminal of the transistor initial model;
[0069] S430, Plot a current-frequency Bode plot based on the DC voltage signal and the current signal, wherein the horizontal axis of the current-frequency Bode plot is frequency and the vertical axis of the current-frequency Bode plot is current;
[0070] S440, extract the target point from the current-frequency Bode plot, and calculate the transistor gate capacitance C based on the current and frequency of the target point. gb The gate capacitance value C of the transistor gb The calculation formula is:
[0071] V ac = Iac × 1 / (2×π×f×C gs )
[0072] In the formula, V ac Iac is the AC voltage signal, Iac is the current signal at the target point, and f is the frequency of the target point;
[0073] S450, based on the transistor gate capacitance value C gb A transistor gate capacitance model is established, wherein the input signal of the transistor gate capacitance model is a DC voltage signal, and the output signal of the transistor gate capacitance model is the transistor gate capacitance value C. gb。
[0074] In another embodiment of this application, a method for establishing a transistor model based on an artificial neural network may include the following steps:
[0075] A1. Determine the transistor process structure type and the transistor modeling port;
[0076] A2. Extract the input DC voltage and output DC current data of each port of the transistor (DC voltage is used as the model input of ANN, and DC current is used as the model output of ANN).
[0077] A3. Use artificial neural networks (ANN) to perform curve fitting on the DC voltage and DC current at the transistor port to obtain the DC-ANN model of the circuit.
[0078] A4. Apply DC voltages to each port (D, G, S, B) of the transistor. Apply a small AC signal voltage to the drain terminal (D) of the transistor. Then extract the current at the gate terminal (G) of the transistor and plot the current-frequency Bode plot (e.g., ...). Figure 3 As shown in the figure, the corresponding gate-drain capacitance value Cgd of the transistor can be calculated from the diagonal line in the figure using the formula Vac = Iac × 1 / (2×π×f×C);
[0079] A5. Apply DC voltage to each port (D, G, S, B) of the transistor, and apply a small AC signal voltage to the source terminal (S) of the transistor. Then extract the current at the gate terminal (G) of the transistor and plot the current-frequency Bode plot (e.g., Figure 3 As shown in the figure, the corresponding gate-source capacitance value Cgs of the transistor can be calculated from the diagonal line in the figure using the formula Vac = Iac × 1 / (2×π×f×C);
[0080] A6. Apply DC voltages to each port (D, G, S, B) of the transistor, and apply a small AC signal voltage to the body terminal (B) of the transistor. Then extract the current at the gate terminal (G) of the transistor and plot the current-frequency Bode plot (e.g., Figure 3As shown in the figure, the corresponding gate capacitance value Cgb of the transistor can be calculated from the diagonal line in the figure using the formula Vac = Iac × 1 / (2×π×f×C);
[0081] A7. Construct an ANN model of Cgd using the transistor port DC voltage from A4 and the calculated transistor gate-drain capacitance value. The input variable of the ANN model is the transistor's DC port voltage, and the output value is the gate-drain capacitance value Cgd corresponding to the DC port voltage.
[0082] A8. Construct an ANN model of Cgs using the transistor port DC voltage from A5 and the calculated transistor gate-source capacitance value. The input variable of the ANN model is the transistor's DC port voltage, and the output value is the gate-source capacitance value Cgs corresponding to the DC port voltage.
[0083] A9. Construct an ANN model of Cgb using the transistor port DC voltage from A6 and the calculated transistor gate capacitance value. The input variable of the ANN model is the transistor's DC port voltage, and the output value is the gate capacitance value Cgb corresponding to the DC port voltage.
[0084] A10. Represent the artificial neural network transistor models for DC and AC obtained above using Verilog-A.
[0085] The beneficial effects of this application include:
[0086] It can model transistors of any type (different process technology, different physical principles), and there are no restrictions on the number and type of transistor ports;
[0087] Applying a DC voltage to each port of the transistor will generate a DC current in each port, which can be done in both normal and abnormal operating conditions.
[0088] The artificial neural network here can be any type of neural network structure, or a non-neural network structure (such as a multinomial function). It fits the model input voltage to obtain the model output current. Various preprocessing functions can be used to preprocess the input and output data to improve the fitting accuracy.
[0089] Because of the gate-drain capacitance Cgd, a small AC signal voltage applied to the port will cause a change in the output port current. Here, a small AC signal can be applied to the gate to extract current from the drain. Alternatively, a small AC signal can be applied to the drain to extract current from the gate. This requires covering all DC bias voltage conditions.
[0090] Because of the gate-source capacitance Cgs, a small AC signal voltage applied to the port will cause a change in the output port current. Here, a small AC signal can be applied to the gate to extract current from the source. Alternatively, a small AC signal can be applied to the source to extract current from the gate. This requires covering all DC bias voltage conditions.
[0091] Because of the capacitance Cgb at the gate, a small AC signal voltage applied to the port will cause a change in the output port current. Here, a small AC signal can be applied to the gate to extract current from the body. Alternatively, a small AC signal can be applied to the body to extract current from the gate. This requires covering all DC bias voltage conditions.
[0092] In the ANN model of the gate-drain capacitance of a transistor, the input is the different DC bias voltages at each port of the transistor, and the output is the gate-drain capacitance value under different DC bias voltages.
[0093] In the ANN model of the gate-source capacitance of a transistor, the input is the different DC bias voltages at each port of the transistor, and the output is the gate-source capacitance value under different DC bias voltages.
[0094] In the ANN model of the gate capacitance of a transistor, the input is the different DC bias voltages at each port of the transistor, and the output is the gate capacitance value under different DC bias voltages.
[0095] The resulting transistor model function expression can be expressed and used for circuit simulation in any form, such as netlists, Verilog-a, etc.
[0096] The differences between this application and current mainstream modeling methods:
[0097] Compared to the mainstream BSIM modeling method, our invented transistor modeling method can model transistors with different process technologies or different physical principles, thus achieving the universality of the method.
[0098] By using artificial neural network structures and an automated artificial neural network model parameter optimization process, we can greatly shorten the time for modular circuit modeling and improve modeling efficiency.
[0099] By using the Verilog-A behavioral description language, we can flexibly implement more functional descriptions.
[0100] In summary, the present invention provides a transistor model building method based on an artificial neural network. This method involves: acquiring the transistor process type; establishing an initial transistor model based on the process type, the initial model including multiple ports; applying DC voltage input signals to each port of the initial transistor model and extracting the DC current output signals from each port; and fitting the DC voltage input signals and DC current output signals to the transistor model using a pre-set artificial neural network to obtain a DC transistor model. This invention uses an artificial neural network to capture the relationship between the input and output (current and voltage) of the transistor model. The model simultaneously considers both DC and AC signals. It enables high-precision modeling of transistors and significantly improves the simulation accuracy while maintaining a fast simulation speed.
[0101] In the above embodiments, although the present application has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art based on the foregoing description. The embodiments of the present application are intended to cover all such substitutions, modifications, and variations falling within the broad scope of the appended claims.
[0102] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.
Claims
1. A method for establishing a transistor model based on an artificial neural network, characterized in that: Including the following steps: Obtain the transistor process type; An initial transistor model is established based on the transistor process type, and the initial transistor model includes multiple ports; A DC voltage input signal is applied to each port of the transistor initial model, and the DC current output signal of each port of the transistor initial model is extracted. A transistor DC model is obtained by fitting the DC voltage input signal and the DC current output signal using a preset artificial neural network. When the transistor model includes a gate terminal and a drain terminal, the transistor model establishment method further includes: A DC voltage signal is applied to each port of the initial transistor model, and an AC voltage signal is applied to the drain terminal of the initial transistor model. After applying a DC voltage signal to each port of the initial transistor model and an AC voltage signal to the drain terminal of the initial transistor model, a current signal is extracted from the gate terminal of the initial transistor model. A current-frequency Bode plot is drawn based on the DC voltage signal and the current signal, where the horizontal axis of the current-frequency Bode plot is frequency and the vertical axis is current. Extract the target point from the current-frequency Bode plot, and calculate the transistor gate-drain capacitance C based on the current and frequency of the target point. gd The gate-drain capacitance value C of the transistor gd The calculation formula is: V ac = I ac × 1 / (2×π×f×C gd ) In the formula, V ac Iac is the AC voltage signal, Iac is the current signal at the target point, and f is the frequency of the target point; Based on the transistor gate-drain capacitance value C gd A transistor gate-drain capacitance model is established, wherein the input signal of the transistor gate-drain capacitance model is a DC voltage signal, and the output signal of the transistor gate-drain capacitance model is the transistor gate-drain capacitance value C. gd .
2. The method for establishing a transistor model based on an artificial neural network according to claim 1, characterized in that: When the transistor model includes a gate terminal and a source terminal, the transistor model establishment method further includes: A DC voltage signal is applied to each port of the initial transistor model, and an AC voltage signal is applied to the source terminal of the initial transistor model. A DC voltage signal is applied to each port of the transistor initial model, and an AC voltage signal is applied to the source terminal of the transistor initial model. Then, a current signal is extracted from the gate terminal of the transistor initial model. A current-frequency Bode plot is drawn based on the DC voltage signal and the current signal, where the horizontal axis of the current-frequency Bode plot is frequency and the vertical axis is current. Extract the target point from the current-frequency Bode plot, and calculate the transistor gate-source capacitance C based on the current and frequency of the target point. gs The gate-source capacitance value C of the transistor gs The calculation formula is: V ac = I ac × 1 / (2×π×f×C gs ) In the formula, V ac Iac is the AC voltage signal, Iac is the current signal at the target point, and f is the frequency of the target point; Based on the transistor gate-source capacitance value C gs A transistor gate-source capacitance model is established, wherein the input signal of the transistor gate-source capacitance model is a DC voltage signal, and the output signal of the transistor gate-source capacitance model is the transistor gate-source capacitance value C. gs .
3. The method for establishing a transistor model based on an artificial neural network according to claim 1, characterized in that: When the transistor model includes a gate terminal and a body terminal, the transistor model establishment method further includes: A DC voltage signal is applied to each port of the initial transistor model, and an AC voltage signal is applied to the body terminal of the initial transistor model. After applying a DC voltage signal to each port of the initial transistor model and an AC voltage signal to the body terminal of the initial transistor model, a current signal is extracted from the gate terminal of the initial transistor model. A current-frequency Bode plot is drawn based on the DC voltage signal and the current signal, where the horizontal axis of the current-frequency Bode plot is frequency and the vertical axis is current. Extract the target point from the current-frequency Bode plot, and calculate the transistor gate capacitance C based on the current and frequency of the target point. gb The gate capacitance value C of the transistor gb The calculation formula is: V ac = I ac × 1 / (2×π×f×C gb ) In the formula, V ac Iac is the AC voltage signal, Iac is the current signal at the target point, and f is the frequency of the target point; Based on the transistor gate capacitance value C gd A transistor gate capacitance model is established, wherein the input signal of the transistor gate capacitance model is a DC voltage signal, and the output signal of the transistor gate capacitance model is the transistor gate capacitance value C. gd .