A chip verification package

Abstract

The application discloses a kind of chip verification packages, technical solutions include DBC substrate and side plate, the side plate is vertically arranged in the edge of DBC substrate, and then the DBC substrate and side plate form a square cavity;Including gasket one, gasket two, gasket three and gasket four, the gasket one, gasket two, gasket three and gasket four are welded on DBC substrate and electrically connected with DBC substrate, pin needle one, pin needle two, pin needle three and pin needle four are vertically arranged on the gasket one, gasket two, gasket three and gasket four respectively, the advantages of the present application provide the mounting space of integrated sensor chip, avoid pin needle and chip back heat dissipation cause signal interference, directly measure chip performance is convenient.

Description

Technical Field

[0001] This invention relates to the field of chip packaging, and more particularly to a chip verification package. Background Technology

[0002] Insulated Gate Bipolar Transistors (IGBTs) are widely used in industrial, information, new energy, medical, transportation, military, and aerospace fields due to their characteristics of low on-state voltage drop, large current capacity, high input impedance, fast response speed, and simple control. With the continuous advancement of IGBT module packaging technology and the increasing demands of applications, sensors are being integrated into the modules to fully realize their advantages while better protecting the internal chips.

[0003] Currently, Chinese patent CN108288616A, entitled "Chip Packaging," discloses a chip packaging solution comprising: a first semiconductor chip, a second semiconductor chip, a polymer layer disposed between the first semiconductor chip and the second semiconductor chip, a first metal layer located on the first semiconductor chip, the second semiconductor chip, and the polymer layer, wherein the first metal layer connects the first semiconductor chip and the second semiconductor chip, a first dielectric layer located on the first metal layer and above the first semiconductor chip, the second semiconductor chip, and the polymer layer, a second metal layer located above the first dielectric layer, the first semiconductor chip, the second semiconductor chip, and the polymer layer; a second dielectric layer located on the second metal layer and above the first dielectric layer, the first semiconductor chip, the second semiconductor chip, and the polymer layer; and a first metal bump located on the second metal layer.

[0004] However, we are currently encountering the following problems:

[0005] With the increasing use of larger IGBTs and FRDs (high voltage phasers) and the integration of sensors into the IGBT chips, existing package sizes are insufficient to accommodate these large IGBTs and FRDs. Furthermore, the heat dissipation from the pins and the back of the chip causes signal interference, resulting in sensor distortion of the IGBT chip and making it impossible to directly measure chip performance. Summary of the Invention

[0006] To address the shortcomings of the prior art, the present invention aims to provide a chip verification package, which has the advantages of providing mounting space for integrated sensor chips, avoiding signal interference caused by heat dissipation from pins and the back of the chip, and facilitating direct measurement of chip performance.

[0007] The above-mentioned technical objective of the present invention is achieved through the following technical solution:

[0008] A chip verification package, characterized in that:

[0009] It includes a DBC substrate and a side plate, the side plate being vertically disposed at the edge of the DBC substrate, thereby the DBC substrate and the side plate forming a rectangular cavity;

[0010] It includes a first sheet, a second sheet, a third sheet, and a fourth sheet. The first sheet, a second sheet, a third sheet, and a fourth sheet are soldered onto the DBC substrate and electrically connected to the DBC substrate. The first sheet, a second sheet, a third sheet, and a fourth sheet are respectively vertically provided with pins.

[0011] Furthermore, the end of the first liner is provided with a rectangular welding part, and the tail of the first pin is welded to the welding part.

[0012] Furthermore, the end of the second liner is provided with a rectangular welding part, the tail of the second pin is welded to the welding part, and the end of the second liner away from the welding part is bent at 90°.

[0013] Furthermore, the end of the liner three is provided with a rectangular welding part three, the tail of the pin three is welded to the welding part three, and the end of the liner three away from the welding part three is bent at 90°.

[0014] Furthermore, the end of the liner four is provided with a rectangular welding part four, the tail of the pin four is welded to the welding part four, and the end of the liner four away from the welding part four is bent at 90°.

[0015] Furthermore, the DBC substrate is welded with a panel one, and a horizontally arranged pin five is welded on the panel one, with the head of the pin five extending out of the side plate.

[0016] Furthermore, the DBC substrate is welded with a second panel, and a sixth pin arranged horizontally is welded on the second panel, with the head of the sixth pin extending out of the side plate.

[0017] Furthermore, the DBC substrate is welded with a panel three, and horizontally arranged pins seven are welded on the panel three, with the heads of the pins seven extending out of the side plate.

[0018] Furthermore, the first, second, third, and fourth linings are arranged in a zigzag shape, and the corners of the first, second, third, and fourth linings are rounded.

[0019] Furthermore, a step is provided at the top of the side panel.

[0020] In summary, the present invention has the following beneficial effects:

[0021] 1. The chip sensor is electrically connected to the DBC substrate via aluminum wire bonding. The pins are directly soldered to the substrate, allowing external devices to directly connect to the pins to measure the chip's performance. This also effectively avoids signal interference with the back heat sink.

[0022] 2. The DBC substrate and side plate form a rectangular cavity, providing sufficient mounting space for the chip. Furthermore, the substrates 1, 2, 3, and 4 are designed in a zigzag shape, allowing them to be arranged around the chip and making reasonable use of the space within the package. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the chip packaging structure.

[0024] In the diagram, 1. DBC substrate; 11. Backing sheet 1; 111. Soldering part 1; 112. Pin 1; 12. Backing sheet 2; 121. Soldering part 2; 122. Pin 2; 13. Backing sheet 3; 131. Soldering part 3; 132. Pin 3; 14. Backing sheet 4; 141. Soldering part 4; 142. Pin 4; 15. Panel 1; 151. Pin 5; 16. Panel 2; 161. Pin 6; 17. Panel 2; 171. Pin 7; 2. Side plate; 21. Step. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the device proposed by this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, only for the purpose of conveniently and clearly illustrating the embodiments of this invention. Please refer to the accompanying drawings to make the objectives, features, and advantages of this invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives achieved by this invention, should still fall within the scope of the technical content disclosed in this invention.

[0026] Example:

[0027] A chip verification package, such as Figure 1 As shown, it includes a DBC substrate and a side plate, which together form a rectangular cavity to provide space for mounting chips and to protect the chips mounted therein.

[0028] Specifically, such as Figure 1 As shown, a DBC substrate is soldered with a panel 1, on which horizontally arranged pins 5 are soldered, the heads of which protrude from the side. A second panel is soldered with the same number of horizontally arranged pins 6, the heads of which protrude from the side. A third panel is also soldered with the same number of horizontally arranged pins 7, the heads of which protrude from the side. Panel 2 is rectangularly positioned between panels 1 and 3. Panel 1 has a groove on its edge that engages with the lower left corner of panel 2, and panel 3 also has a groove on its edge that engages with the upper right corner of panel 2. Pins 5, 6, and 7 are parallel to each other.

[0029] Specifically, such as Figure 1 As shown, the top of the side panel is provided with a step so that a cover can be connected on the step to seal the package.

[0030] like Figure 1 As shown, a chip verification package further includes substrate 1, substrate 2, substrate 3, and substrate 4, which are soldered onto and electrically connected to the DBC substrate. Substrates 1, 2, 3, and 4 are zigzag-shaped, and the corners of substrates 1, 2, 3, and 4 are rounded to avoid stress concentration.

[0031] like Figure 1 As shown, the end of substrate 1 has a rectangular solder joint 1, on which a pin 1 is vertically mounted, and the tail of pin 1 is soldered to the top surface of solder joint 1; the end of substrate 2 has a rectangular solder joint 2, on which a pin 2 is vertically mounted, and the tail of pin 2 is soldered to the top surface of solder joint 2; the end of substrate 3 has a rectangular solder joint 3, on which a pin 3 is vertically mounted, and the tail of pin 3 is soldered to the top surface of solder joint 3; the end of substrate 4 has a rectangular solder joint 4, on which a pin 4 is vertically mounted, and the tail of pin 4 is soldered to the top surface of solder joint 4. With this soldering connection method, external devices can directly connect to the pins to directly measure the chip's performance, and signal interference with the back heat sink is effectively avoided.

[0032] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0033] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A chip verification package, characterized in that: It includes a DBC substrate and a side plate, the side plate being vertically disposed at the edge of the DBC substrate, thereby the DBC substrate and the side plate forming a rectangular cavity; It includes a first sheet, a second sheet, a third sheet, and a fourth sheet. The first sheet, a second sheet, a third sheet, and a fourth sheet are soldered onto the DBC substrate and electrically connected to the DBC substrate. The first sheet, a second sheet, a third sheet, and a fourth sheet are respectively vertically provided with pins. The DBC substrate is welded with a panel one, and a horizontally arranged pin five is welded on the panel one, with the head of the pin five extending out of the side plate. The DBC substrate is soldered with a panel two, and a horizontally arranged pin six is ​​soldered on the panel two, with the head of the pin six extending out of the side plate; The DBC substrate is soldered with a panel three, and a horizontally arranged pin seven is soldered on the panel three, with the head of the pin seven extending out of the side plate. External devices connect directly to the pins to directly measure the chip's performance.

2. The chip verification packaging according to claim 1, characterized in that: The end of the liner is provided with a rectangular welding part, and the tail of the pin is welded to the welding part.

3. The chip verification packaging according to claim 2, characterized in that: The end of the second liner is provided with a rectangular welding part, the tail of the second pin is welded to the welding part, and the end of the second liner away from the welding part is bent at 90°.

4. The chip verification packaging according to claim 3, characterized in that: The end of the liner three is provided with a rectangular welding part three, the tail of the pin three is welded to the welding part three, and the end of the liner three away from the welding part three is bent at 90°.

5. A chip verification package according to claim 4, characterized in that: The end of the liner four is provided with a rectangular welding part four, the tail of the pin four is welded to the welding part four, and the end of the liner four away from the welding part four is bent at 90°.

6. The chip verification packaging according to claim 1, characterized in that: The lining sheet 1, lining sheet 2, lining sheet 3 and lining sheet 4 are arranged in a zigzag shape, and the corners of the lining sheet 1, lining sheet 2, lining sheet 3 and lining sheet 4 are rounded.

7. The chip verification package according to claim 1, characterized in that: The top of the side panel is provided with a step.

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