Method and test system for determining interface properties
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2023-01-05
- Publication Date
- 2026-07-03
Smart Images
Figure CN115993515B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor device testing technology, and includes, but is not limited to, a method for determining interface characteristics and a testing system. Background Technology
[0002] The characteristics of the silicon-silicon dioxide (Si-SiO2) interface are closely related to semiconductor reliability. According to mechanistic models, both hot carrier injection (HCI) and negative bias temperature instability (NBTI) contribute to defects at the Si-SiO2 interface. Therefore, characterizing the Si-SiO2 interface is crucial for evaluating the HCI / NBTI of devices. However, current techniques cannot accurately characterize the Si-SiO2 interface features. Summary of the Invention
[0003] This disclosure provides a method and testing system for determining interface characteristics.
[0004] On one hand, embodiments of this disclosure provide a method for determining interface characteristics. The method includes: applying an excitation signal to the gate of a voltage-driven device and testing the substrate current of the device to obtain a first response current; applying a preset voltage to the gate of the device for a preset duration, and then applying the excitation signal to the gate to test the substrate current of the device to obtain a second response current; determining the phase difference between the excitation signal and the first response current and the second response current, respectively, and obtaining a first phase difference and a second phase difference accordingly; and determining the characteristics of the interface under test in the device based on the first phase difference and the second phase difference; wherein the difference between the frequency of the excitation signal and the characteristic frequency of the interface under test is within a first preset range.
[0005] In some embodiments, the method further includes: acquiring the characteristic frequency of the interface under test; determining a target characteristic frequency based on the characteristic frequency of the interface under test and the first preset range; determining a target amplitude of the excitation signal to be generated; adjusting the amplitude of a first clock signal having the target characteristic frequency to the target amplitude to obtain the excitation signal.
[0006] In some embodiments, obtaining the characteristic frequency of the interface under test includes: obtaining the transfer function of the system composed of the device; drawing the Nyquist plot or Bode plot of the system based on the transfer function; and obtaining the characteristic frequency of the interface under test based on the frequency corresponding to the imaginary extreme point in the Nyquist plot, or based on the frequency corresponding to the phase extreme point in the Bode plot.
[0007] In some embodiments, determining the target amplitude of the excitation signal to be generated includes: randomly selecting a value from a set of initial target amplitudes to obtain the target amplitude; the initial target amplitude is the amplitude corresponding to the real and imaginary parts of the impedance of the device satisfying the Kramer-Kroning relation.
[0008] In some embodiments, the method further includes: adjusting the amplitude of a first clock signal having a target characteristic frequency until the real and imaginary parts of the impedance of the tested device satisfy the Kramers-Kroning relationship to obtain the initial target amplitude.
[0009] In some embodiments, adjusting the amplitude of a first clock signal having a target characteristic frequency until the real and imaginary parts of the impedance of the tested device satisfy the Kramers-Kroning relationship to obtain the initial target amplitude includes: applying the preset voltage and the first clock signal to the gate of the device, adjusting the amplitude of the first clock signal, and testing the impedance of the device; and determining the amplitude corresponding to the real and imaginary parts of each impedance satisfying the Kramers-Kroning relationship as the initial target amplitude.
[0010] In some embodiments, randomly selecting a value from the set of initial target amplitudes to obtain the target amplitude includes: selecting the largest amplitude from the set of initial target amplitudes to obtain the target amplitude.
[0011] In some embodiments, determining the characteristics of the interface under test in the device based on the first phase difference and the second phase difference includes: determining the difference between the first phase difference and the second phase difference; and determining that the interface state of the interface under test remains unchanged when the difference is within a second preset range.
[0012] In some embodiments, determining the interface characteristics of the interface under test in the device based on the first phase difference and the second phase difference further includes: determining that the interface state of the interface under test has changed when the difference is not within the second preset range.
[0013] In some embodiments, the excitation signal includes a square wave signal or a sine wave signal.
[0014] In some embodiments, the expression for the sinusoidal signal is: ΔV = |ΔV| × sin(ωt); where |ΔV| is the target amplitude, and ω is related to the reciprocal of the target characteristic frequency.
[0015] In some embodiments, the target amplitude ranges from 15 millivolts to 25 millivolts.
[0016] In some embodiments, the device includes a MOS device, and the interface under test includes a Si-SiO2 interface.
[0017] On the other hand, embodiments of this disclosure also provide a testing system for interface characteristics. The testing system includes: an application component for: applying an excitation signal to the gate of a voltage-driven device; applying the excitation signal to the gate of the device after applying a preset voltage for a preset duration; a current testing component for: testing the substrate current of the device to obtain a first response current and a second response current; and a processing component for: determining the phase difference between the excitation signal and the first response current and the second response current, respectively, and obtaining a first phase difference and a second phase difference accordingly; and determining the characteristics of the interface under test in the device based on the first phase difference and the second phase difference; wherein the difference between the frequency of the excitation signal and the characteristic frequency of the interface under test is within a first preset range.
[0018] In some embodiments, the processing component is further configured to: determine the difference between the first phase difference and the second phase difference; if the difference is within a second preset range, determine that the interface state of the tested interface has not changed; if the difference is not within the second preset range, determine that the interface state of the tested interface has changed.
[0019] In this embodiment, firstly, an excitation signal is applied to the gate of a voltage-driven device, and the substrate current of the device is tested to obtain a first response current; secondly, after applying a preset voltage to the gate of the device for a preset duration, an excitation signal is applied to the gate, and the substrate current of the device is tested to obtain a second response current; thirdly, the phase difference between the excitation signal and the first and second response currents is determined, and a first phase difference and a second phase difference are obtained accordingly; finally, based on the first and second phase differences, the characteristics of the interface under test in the device are determined; wherein, the difference between the frequency of the excitation signal and the characteristic frequency of the interface under test is within a first preset range. The method for determining interface characteristics in this embodiment has the following advantages: on the one hand, since the excitation signal used is a small AC signal, it can reflect the behavior of the interface under test of the voltage-driven device under preset voltage conditions, and can characterize the interface state of the interface under test in situ, shortening the time for evaluating device damage caused by HCI or NBTI effects; on the other hand, since the frequency of the excitation signal can be adjusted according to the actual situation of the device, it can avoid the mixing of defect information from other layers (such as gate oxide layer) or other interfaces, improving the accuracy of determining the characteristics of the interface under test. Attached Figure Description
[0020] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.
[0021] Figure 1a This is a schematic diagram of the hot carrier injection effect in related technologies;
[0022] Figure 1b A schematic diagram of a reaction-diffusion model for the effect of temperature instability under negative bias;
[0023] Figure 1c A schematic diagram of the Si-H bond breaking reaction at the interface during the temperature instability effect of negative bias.
[0024] Figure 2a This is a diagram of a test apparatus for IV characteristic testing technology in related technologies;
[0025] Figure 2b This is a diagram of a test apparatus for charge pump testing technology in related technologies;
[0026] Figure 3 A schematic diagram illustrating the implementation process of a method for determining interface characteristics provided in this embodiment of the disclosure;
[0027] Figure 4 This is a schematic diagram of the structure of a MOS device;
[0028] Figure 5 Schematic diagram of interface state response under excitation signals of different frequencies;
[0029] Figure 6 Nyquist plot provided for embodiments of this disclosure;
[0030] Figure 7 Bode plots provided for embodiments of this disclosure;
[0031] Figure 8 A schematic diagram of the equivalent resistance circuit model of a device provided in an embodiment of this disclosure;
[0032] Figure 9 A schematic diagram illustrating the implementation process of a method for determining interface characteristics provided in this embodiment of the disclosure;
[0033] Figure 10 This is a schematic diagram of the composition structure of a test system for interface characteristics provided in an embodiment of this disclosure. Detailed Implementation
[0034] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0035] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.
[0036] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.
[0037] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.
[0038] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0039] Before introducing the embodiments of this disclosure, the HCI effect, NBTI effect, and commonly used evaluation methods for the HCI effect and NBTI effect will be introduced.
[0040] refer to Figure 1a This section introduces the hot carrier injection effect. As process dimensions continue to shrink, the supply voltage does not decrease proportionally with the reduction in dimensions such as channel length, junction depth, and gate oxide thickness of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), nor with the increase in substrate doping concentration. This leads to a significant increase in both the transverse and longitudinal electric fields of the channel. The high electric field accelerates carrier movement, transforming them into high-energy hot carriers (corresponding to...). Figure 1a (①The charge carriers in the process gain sufficient energy).
[0041] When the extra energy of the charge carriers in substrate 10 exceeds three times the band gap, the collisional ionization of the charge carriers with the lattice (corresponding to...) Figure 1a Collision ionization (②) becomes one of the main forms of energy consumption. When the energy of the charge carriers exceeds the barrier height of Si-SiO2 (3.5 eV), the charge carriers can be directly injected or enter the gate oxide layer 20 (corresponding to) through tunneling. Figure 1a (③ Hot carrier injection into the gate oxide layer) The injected hot carriers change the charge distribution in the gate oxide layer 20, generating defects in the gate oxide layer 20 (corresponding to...) Figure 1a (④ In the process of injecting carriers, defects are generated in the gate oxide layer, which causes the threshold voltage V of the MOS device to decrease.) th Parameters such as transconductance (gm) in the linear region may drift or degrade, thus affecting the reliability of the device (corresponding to...). Figure 1a (⑤ Defects in the gate oxide layer cause device instability, which ultimately leads to circuit failure.)
[0042] The NBTI effect refers to the degradation of a series of electrical parameters caused by applying a negative gate voltage to a MOS device at high temperatures (typically under a constant temperature of 125 degrees Celsius with the gate oxide field, source, drain, and substrate grounded). A commonly used explanatory model for NBTI is as follows: Figure 1b The reaction-diffusion model is shown. Also refer to... Figure 1b and Figure 1c When the source, drain, and substrate 10 of the device are grounded, the gate 40 is under negative bias V. g1 In the device, after hydrogen passivation at the Si-SiO2 interface 30, a large number of Si-H bonds are formed. Under the action of a vertical electric field, the generated holes 50 tunnel and react with the Si-H bonds, causing the Si-H bonds to break. This leaves interface defects and hydrogen atoms in the channel. The hydrogen atoms form hydrogen gas and then escape from the gate 40 through the gate oxide layer 20. The silicon dangling bonds after the reaction attract a charge, becoming a positively charged interface trap charge. The unstable state formed in this way is called the interface state, which is a reversible electrochemical reaction.
[0043] Currently, commonly used methods for evaluating the HCI and NBTI effects include IV characteristic testing techniques and charge pump testing techniques. For the IV characteristic testing technique, the testing equipment can be found at [reference needed]. Figure 2a For a MOS device with a channel width of ΔL, a DC stress V can be applied to the gate 40. g2 (For example, 3 / 2.5 / 1.9 / 1.5 / 1 / 0.5 volts), a source voltage V is applied to the source 102 (S) and the drain 103 (D) respectively. s (e.g., 0V) and drain voltage V d (For example, 3.1V), when the DC stress applied to the gate 40 is large, the longitudinal electric field in the space charge region of the substrate 10 is also high. The thermally excited electrons in the space charge region can also be "pulled" into the gate oxide layer 20 by the longitudinal electric field, while the holes generated are swept into the substrate 10, forming the substrate current I. sub During implementation, the substrate current I can be tested. sub , with I sub As a criterion for judging the lifetime of HCI effect experiments.
[0044] The test setup for charge pump testing technology can be found in the following reference. Figure 2b A periodic pulse is applied to the gate 40, and the same reverse bias voltage V is applied to the source 102 and drain 103 respectively. rSubstrate 10 is grounded. Under the influence of periodic pulsed voltages, the channel of the MOS device repeatedly transitions between accumulation and inversion states. In inversion, the interface states are filled with carriers from the source and drain regions. In channel accumulation, majority carriers from the substrate recombine with minority carriers trapped in the interface states to generate a substrate current, also known as the charge pump current. This current contains information about the interface states located in the upper or lower half of the bandgap; the fixed trap charge can be deduced from the changes in the pump current edge.
[0045] Currently, charge pump testing techniques mainly include: Figure 2b The three pulse modes are: Mode A, which keeps the pulse reference in the accumulation region and changes the pulse amplitude to gradually invert the surface; Mode B, which changes the pulse reference to move the surface from the accumulation region to the inversion region while keeping the pulse amplitude constant; and Mode C, which keeps the pulse reference in the inversion region and changes the pulse amplitude to gradually accumulate on the surface.
[0046] Since the NBTI and HCI effects have essentially the same impact on device performance parameters, the HCI effect testing method is often used for the NBTI effect. Charge pump testing technology has the following drawbacks: 1) The pump current generated by the transition from accumulation to inversion actually includes information on interface charge and gate oxide trap charge, making it difficult to isolate the interface charge information in practice; 2) Because the channel repeatedly transitions between accumulation and inversion, charge pump testing technology is an unsteady-state test; it often involves applying pressure for a period of time and then characterizing the interface state with charge pump, repeating this process multiple times, which is time-consuming and labor-intensive, and cannot characterize the interface state information under fixed gate voltage conditions in situ; 3) Charge pump testing technology requires the source and drain to be shorted, making it impossible to characterize the interface state information under the actual operating state of the device in situ. To accurately measure device damage caused by the HCI or NBTI effects in situ, it is necessary to establish an in-situ Si-SiO2 interface parameter extraction method, i.e., a method for determining Si-SiO2 interface characteristics. Interface characteristics, including interface state density and charge trapping defects, play a crucial role in evaluating device performance. For example, the presence of high-density interface states or near-interface traps can have an adverse effect on field-effect mobility and threshold voltage.
[0047] This disclosure provides a method for determining interface characteristics, referring to... Figure 3 The method includes steps S301 to S304, wherein:
[0048] Step S301: Apply an excitation signal to the gate of the voltage-driven device and test the substrate current of the device to obtain the first response current;
[0049] Here, a voltage-driven device refers to a device that can be controlled to turn on or off by applying a certain voltage signal between the control terminal and the common terminal of the device. Voltage-driven devices include MOS devices and insulated gate bipolar transistors (IGBTs), etc. The embodiments of this disclosure mainly use MOS devices as an example for illustration.
[0050] refer to Figure 4 The MOS device includes a substrate 10, a gate oxide layer 20, a Si-SiO2 interface 30, an ohmic contact layer (not shown), and a gate metal layer (i.e., the gate) 40. The substrate 10 includes a depletion layer 101, a source 102, a channel 104, and a drain 103. When an excitation signal ΔV (also known as a perturbation signal, a small signal) is applied to the gate 40 of the MOS device, the ohmic contact layer does not respond to the excitation signal ΔV; the gate oxide layer 20, due to its fixed charge, responds to the excitation signal ΔV at a low frequency; the interface state response of the Si-SiO2 interface 30 is similar to an adsorption process, and the response is at a mid-frequency; the excitation signal ΔV causes the source 102, drain 103, and channel 104 to respond, but the response signal is not related to the substrate current ΔI. sub This causes the interface state response of the Si-SiO2 interface 30 to actually occur at high frequencies rather than mid frequencies; due to the presence of the source 102, the depletion layer 101 does not respond to the excitation signal ΔV.
[0051] refer to Figure 5 In Figure (a), when the frequency of the excitation signal ΔV is higher than the characteristic frequency of the interface state, the interface state parameters have not yet responded before the disturbance signal begins to excite in the reverse direction. In this case, the AC component of the interface state is frozen. (See reference...) Figure 5 In Figure (b), when the frequency of the excitation signal ΔV is much lower than the characteristic frequency of the interface state, the interface state response is at the same frequency as the excitation signal ΔV. (Reference) Figure 5 In Figure (c), when the frequency of the excitation signal ΔV is close to the characteristic frequency of the interface state, the interface state response lags the excitation signal ΔV by π / 4, meaning there is a phase difference of π / 4 between them. To reflect the interface state's response to the excitation signal ΔV, in this embodiment of the disclosure, the difference between the frequency of the excitation signal ΔV and the characteristic frequency of the interface under test is within a first preset range; for example, the frequency of the excitation signal ΔV is equal to the characteristic frequency of the interface under test.
[0052] In some embodiments, the excitation signal can be an arbitrary periodic signal, such as a clock signal, like a square wave or a sine wave. In practice, the excitation signal can be obtained simply by adjusting the frequency and amplitude of the clock signal.
[0053] First response current ΔI sub1 It is the substrate current I subThe AC part, which is the response current to the AC excitation signal ΔV, is also an AC signal with the same frequency as the excitation signal, but with a phase difference.
[0054] Step S302: After applying a preset voltage to the gate of the device for a preset duration, an excitation signal is applied to the gate to test the substrate current of the device in order to obtain the second response current.
[0055] Applying a preset voltage to the gate of the device is to apply a bias voltage to the device. After a preset time, all variables remain unchanged over time. Then, a small AC disturbance signal is applied, allowing the electrical parameters of the device to be tested under the preset voltage. Here, the second response current ΔI... sub2 Also the substrate current I sub The AC section is the response current of the device's measured interface to the excitation signal after the device performance degrades due to the application of a preset voltage. It has the same frequency as the excitation signal but a phase difference.
[0056] Step S303: Determine the phase difference between the excitation signal and the first response current and the second response current, respectively, and obtain the first phase difference and the second phase difference accordingly;
[0057] Here, the phase difference between the excitation signal and the response current is different before and after a preset voltage is applied to the gate of the device; the phase difference between the excitation signal and the first response current is the first phase difference, which is the initial phase difference, and can be denoted as... The phase difference between the excitation signal and the second response current is called the second phase difference, which is the phase difference after device performance degradation, and can be denoted as:
[0058] Step S304: Based on the first phase difference and the second phase difference, determine the characteristics of the interface under test in the device.
[0059] Here, by monitoring the first and second response currents, the external device can obtain the phase relationship between the response current and the excitation signal. Changes in the phase relationship reflect the interface state information of the measured interface. By comparing the first phase difference and the second phase difference—that is, comparing the initial phase difference and the phase difference after device performance degradation—it can be determined whether the measured interface has undergone significant changes due to the preset voltage. In other words, by monitoring the response current ΔI... sub The phase difference with the excitation signal ΔV can be used to evaluate the characteristics of the interface under test in situ.
[0060] In practice, the interface under test may include a Si-SiO2 interface, a channel, a gate oxide layer, and a depletion layer, etc. This disclosure does not limit this, and this disclosure mainly uses the Si-SiO2 interface as an example for illustration.
[0061] In this embodiment, firstly, an excitation signal is applied to the gate of a voltage-driven device, and the substrate current of the device is tested to obtain a first response current; secondly, after applying a preset voltage to the gate of the device for a preset duration, an excitation signal is applied to the gate, and the substrate current of the device is tested to obtain a second response current; thirdly, the phase difference between the excitation signal and the first and second response currents is determined, and a first phase difference and a second phase difference are obtained accordingly; finally, based on the first and second phase differences, the characteristics of the interface under test in the device are determined; wherein, the difference between the frequency of the excitation signal and the characteristic frequency of the interface under test is within a first preset range. The method for determining interface characteristics in this embodiment has the following advantages: on the one hand, since the excitation signal used is a small AC signal, it can reflect the behavior of the interface under test of the voltage-driven device under preset voltage conditions, and can characterize the interface state of the interface under test in situ, shortening the time for evaluating device damage caused by HCI or NBTI effects; on the other hand, since the frequency of the excitation signal can be adjusted according to the actual situation of the device, it can avoid the mixing of defect information from other layers (such as gate oxide layer) or other interfaces, improving the accuracy of determining the characteristics of the interface under test.
[0062] In some embodiments, step S304, "determining the characteristics of the interface under test in the device based on the first phase difference and the second phase difference," may include steps S3041 and S3042a, wherein:
[0063] Step S3041: Determine the difference between the first phase difference and the second phase difference;
[0064] Step S3042a: If the difference is within the second preset range, determine that the interface state of the tested interface remains unchanged.
[0065] Here, the second preset range can be a range determined based on experience. When the difference between the first phase difference and the second phase difference is within the specified range, it indicates that the measured interface has not changed significantly due to the preset voltage, that is, the voltage-driven device has not degraded significantly.
[0066] In some embodiments, step S304 may further include step S3042b, determining that the interface state of the tested interface has changed if the difference is not within the second preset range.
[0067] Here, if the difference between the first phase difference and the second phase difference is not within the second preset range, it indicates that there is a defect in the measured interface and the parameters of the measured interface have degraded or drifted. In other words, the performance of the voltage-type drive device degrades due to the preset voltage, and the voltage-type drive device becomes unstable.
[0068] In some embodiments, the method for determining interface characteristics further includes steps S305 to S308, wherein:
[0069] Step S305: Obtain the feature frequencies of the interface under test;
[0070] In practice, the characteristic frequencies of the measured interface can be obtained from the Nyquist plot or the Bode plot. The Nyquist plot is a frequency response diagram for a linear control system. For a continuous-time linear time-invariant system, it plots the gain and phase of its frequency response in polar coordinates. The Nyquist plot is commonly used in control systems or signal processing to determine the stability of a feedback system. Each point on the curve in the Nyquist plot represents the magnitude (distance from the origin) and phase (geometric angle), and the many different points forming the curve reflect the system's response to many different inputs. The Bode plot is a graphical method for representing the system's frequency response. It consists of an magnitude plot and a phase plot, both plotted logarithmically according to the frequency; therefore, the Bode plot is also called a logarithmic coordinate plot.
[0071] In some embodiments, step S305 includes steps S3051 to S3053, wherein:
[0072] Step S3051: Obtain the transfer function of the system composed of devices;
[0073] A system is considered a linear time-invariant system if it meets the following three conditions: 1) Stability, meaning the system returns to its original state after the excitation signal is removed; 2) Linearity, meaning the response has the same frequency as the excitation signal and there are no harmonic signals; 3) Causality, meaning the system responds to the excitation signal without noise. Under the action of an excitation signal, the system composed of devices is a linear time-invariant system. The steady-state response of this system is a signal with the same frequency as the excitation signal but different amplitude and phase. The ratio of the output amplitude to the input amplitude, A(ω), represents the amplitude-frequency characteristic, and the phase difference between the output signal and the input signal represents the frequency response. This refers to the phase frequency characteristic. The relationship between the frequency characteristic and the transfer function can be found in formula (1):
[0074] G(jω)=G(s)s=jω Formula (1);
[0075] Where G(jω) is the frequency response and G(s) is the transfer function.
[0076] Step S3052a: Draw the Nyquist plot of the system based on the transfer function;
[0077] Step S3053a: Based on the frequencies corresponding to the imaginary extreme points in the Nyquist plot, the characteristic frequencies of the interface under test are obtained.
[0078] refer to Figure 6The Nyquist plot of the system is drawn based on the transfer function G(s) (where Z' represents the real part of the frequency response, Z'' represents the imaginary part of the frequency response, and R...). (Si-SiO2) (This represents the Si-SiO2 interface resistance). Then, find the extreme point C of the imaginary part Z'' in the Nyquist diagram, and thus obtain the angular frequency ω' corresponding to the extreme point C. In this way, the characteristic frequency f1 of the measured interface can be obtained.
[0079] In some implementations, step S3052a can be replaced by step S3052b, which draws the Bode plot of the system based on the transfer function; correspondingly, step S3053a can be replaced by step S3053b, which obtains the characteristic frequency of the interface under test based on the frequency corresponding to the phase angle extremum point in the Bode plot.
[0080] refer to Figure 7 Based on the transfer function G(s), the Bode plot of the system is drawn. Then, the phase angle extremum point D in the Bode plot is found, thereby obtaining the angular frequency corresponding to the phase angle extremum point D. Figure 7 It can be seen that the angular frequency corresponding to the phase angle extreme point D is 3.69 radians / second (rad / sec), so the characteristic frequency f1 of the measured interface can be obtained.
[0081] Step S306: Determine the target feature frequency based on the feature frequency of the interface under test and the first preset range;
[0082] Here, the first preset range can be an allowable error range, for example, the first preset range is (-ξ, +ξ), where ξ can be determined based on the accuracy determined by the interface characteristics. Where permissible, the target characteristic frequency can be equal to the characteristic frequency f1 of the interface being measured.
[0083] Step S307: Determine the target amplitude of the excitation signal to be generated;
[0084] When the amplitude of the excitation signal is the target amplitude, the system formed by the device is a linear time-invariant system, that is, the system satisfies the conditions of causality, stability and linearity.
[0085] Step S308: Adjust the amplitude of the first clock signal with the target characteristic frequency to the target amplitude to obtain the excitation signal.
[0086] In this embodiment of the present disclosure, firstly, a Nyquist plot or Bode plot is obtained based on the transfer function of the system in which the device is located, and the characteristic frequency f1 of the interface under test is determined based on the Nyquist plot or Bode plot. Secondly, a target characteristic frequency is determined based on the characteristic frequency of the interface under test and a first preset range. After that, the target amplitude of the excitation signal to be generated is obtained, and the amplitude of the first clock signal with the target characteristic frequency is adjusted to the target amplitude, thereby obtaining the excitation signal.
[0087] In some embodiments, the implementation of step S307, "determining the target amplitude of the excitation signal to be generated", may include randomly selecting a value from the set of initial target amplitudes to obtain the target amplitude; the initial target amplitude is the amplitude corresponding to the real part and imaginary part of the impedance of the device satisfying the Kramers-Kroning relationship.
[0088] Here, the Kramers-Kroning relation is a mathematical formula connecting the real and imaginary parts of a complex half-analyzable function. This relation is often used for linear response functions of physical systems. Physically, causality (the system response must occur after an application of force) implies that the response function must satisfy the half-analyzability of the complex surface; conversely, the analytical nature of the response function implies the causality of the corresponding physical system.
[0089] The initial target amplitude is the amplitude corresponding to the real and imaginary parts of the device impedance satisfying the Kramers-Kroning relationship. This means that when a first clock signal with the target characteristic frequency and the initial target amplitude is applied to the gate of the device, the real and imaginary parts of the device impedance obtained by the test satisfy the Kramers-Kroning relationship. In other words, the validity of the data can be verified by the Kramers-Kroning relationship.
[0090] In some embodiments, the method for determining interface characteristics further includes step S309, adjusting the amplitude of a first clock signal having a target characteristic frequency until the real and imaginary parts of the impedance of the tested device satisfy the Kramers-Kroning relationship to obtain an initial target amplitude.
[0091] In practice, step S309 can be achieved through steps S3091 and S3092, wherein:
[0092] Step S3091: Apply a preset voltage and a first clock signal to the gate of the device, adjust the amplitude of the first clock signal, and test the impedance of the device;
[0093] Step S3091 is a dynamic process in which the amplitude of the first clock signal needs to be continuously adjusted and the impedance of the device needs to be tested.
[0094] Step S3092: Determine the initial target amplitude as the amplitude corresponding to the real and imaginary parts of each impedance satisfying the Kramers-Kroning relationship.
[0095] In some embodiments, the equivalent resistance circuit model diagram of the device is as follows: Figure 8As shown, the equivalent resistance of the device is equal to the series resistance obtained by connecting the following three parallel components: the gate metal layer and gate oxide interface resistance R1 and the interface capacitance C1; the gate oxide layer resistance R2 and the capacitance C2; and the substrate and gate oxide layer interface resistance R3 and the interface capacitance C3. When the real and imaginary parts of the impedance of the tested device satisfy the Kramers-Kroning relationship, the corresponding amplitude is recorded, thus obtaining at least one initial target amplitude.
[0096] During implementation, the largest amplitude can be selected from the set of initial target amplitudes as the target amplitude. This can reduce noise interference and further improve the accuracy of interface characteristic determination.
[0097] This explanation uses a sinusoidal excitation signal as an example. (Reference) Figure 9 First, determine the characteristic frequency f1 of the interface under test based on the Nyquist plot or Bode plot;
[0098] Secondly, the frequency of the sinusoidal signal CLK (i.e., the first clock signal) of any period is adjusted to f1;
[0099] Next, the amplitude of the first clock signal with a characteristic frequency is adjusted according to the steady-state condition, that is, the validity of the data is verified by the Kramers-Kroning relationship, so as to obtain at least one initial target amplitude. In practice, the largest amplitude can be selected as the target amplitude from the set of initial target amplitudes, and the amplitude of the first clock signal with a characteristic frequency is adjusted to the target amplitude to obtain the excitation signal ΔV.
[0100] In some embodiments, the expression for the excitation signal (i.e., the sinusoidal signal) can be referred to formula (2):
[0101] ΔV=|ΔV|×sin(ωt) Formula (2);
[0102] Where |ΔV| is the target amplitude, and ω is related to the reciprocal of the target characteristic frequency.
[0103] Finally, an excitation signal ΔV is applied to the gate of the MOS device, and the substrate current I is tested. sub The first response current ΔI is obtained. sub1 A preset voltage V is applied to the gate of the device. GS After a preset time period, i.e., after device degradation, an excitation signal ΔV is applied to the gate of the MOS device, and the substrate current I is measured. sub The second response current ΔI is obtained. sub2 This allows us to obtain the first and second phase differences, which in turn enable us to determine the characteristics of the interface under test in the MOS device. In other words, by monitoring the response current ΔI... subThe phase difference with the excitation signal ΔV can be used to evaluate the characteristics of the interface under test in situ.
[0104] In some embodiments, the target amplitude ranges from 15 millivolts (mV) to 25 mV, for example, the target amplitude can be 20 mV.
[0105] This disclosure also provides a system for testing interface characteristics, with reference to... Figure 10 The testing system 1000 for this interface feature includes:
[0106] The application component 1001 is used to: apply an excitation signal to the gate of a voltage-driven device; and apply an excitation signal to the gate after applying a preset voltage to the gate of the device for a preset duration.
[0107] The current testing component 1002 is used to: test the substrate current of the device to obtain a first response current and a second response current;
[0108] The processing component 1003 is used to: determine the phase difference between the excitation signal and the first response current and the second response current, respectively, and obtain the first phase difference and the second phase difference accordingly; and determine the characteristics of the interface under test in the device based on the first phase difference and the second phase difference.
[0109] The difference between the frequency of the excitation signal and the characteristic frequency of the interface under test is within a first preset range.
[0110] Here, the current testing component can include any device capable of testing current, such as a multimeter or ammeter, and this disclosure is not limited thereto. The processing component can include any device capable of determining the phase difference between the excitation signal and the response current, such as a phase meter.
[0111] In some embodiments, the processing component 1003 is further configured to: determine the difference between the first phase difference and the second phase difference; if the difference is within a second preset range, determine that the interface state of the tested interface has not changed; if the difference is not within the second preset range, determine that the interface state of the tested interface has changed.
[0112] In some embodiments, the excitation signal includes a square wave signal or a sine wave signal. The expression for a sine wave signal can be found in formula (2):
[0113] ΔV=|ΔV|×sin(ωt) Formula (2);
[0114] Where |ΔV| is the target amplitude, and ω is related to the reciprocal of the target characteristic frequency. In practice, the target amplitude ranges from 15mV to 25mV, for example, 20mV.
[0115] In some embodiments, the device includes a MOS device, and the interface under test includes a Si-SiO2 interface.
[0116] In this embodiment of the disclosure, the interface characteristic testing system includes the aforementioned application component, current testing component, and processing component. Since the application component applies a small AC signal to the device, the testing system can accurately measure the behavior of the tested interface of the device under a preset voltage, thereby characterizing the interface state of the tested interface in situ and shortening the time for evaluating device damage caused by HCI or NBTI effects. In addition, since the frequency of the excitation signal can be adjusted according to the actual situation of the device, it can avoid the mixing of defect information from other layers (such as gate oxide layer) or other interfaces, thereby improving the testing accuracy of the testing system.
[0117] In the several embodiments provided in this disclosure, it should be understood that the disclosed systems and methods can be implemented in a non-target manner. The system embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.
[0118] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.
[0119] The features disclosed in the several method or system embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or system embodiments.
[0120] The above descriptions are merely some embodiments of this disclosure, but the protection scope of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this disclosure should be included within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the scope of the claims.
Claims
1. A method of determining interface properties, characterized by, The method includes: An excitation signal is applied to the gate of a voltage-driven device, and the substrate current of the device is tested to obtain a first response current. After applying a preset voltage to the gate of the device for a preset duration, the excitation signal is applied to the gate, and the substrate current of the device is tested to obtain a second response current. The phase difference between the excitation signal and the first response current and the second response current is determined, and the first phase difference and the second phase difference are obtained accordingly. Based on the first phase difference and the second phase difference, the characteristics of the interface under test in the device are determined; Wherein, the difference between the frequency of the excitation signal and the characteristic frequency of the interface under test is within a first preset range; the method further includes: Obtain the characteristic frequencies of the interface under test; The target feature frequency is determined based on the feature frequency of the interface under test and the first preset range; Determine the target amplitude of the excitation signal to be generated; The amplitude of a first clock signal having the target characteristic frequency is adjusted to the target amplitude to obtain the excitation signal; Determining the target amplitude of the excitation signal to be generated includes: Randomly select a value from the set of initial target amplitudes to obtain the target amplitude; the initial target amplitude is the amplitude corresponding to the real part and imaginary part of the impedance of the device satisfying the Kramers-Kroning relationship.
2. The method of claim 1, wherein, Obtaining the feature frequencies of the interface under test includes: Obtain the transfer function of the system composed of the aforementioned devices; Draw the Nyquist plot or Bode plot of the system based on the transfer function; The characteristic frequencies of the measured interface are obtained based on the frequencies corresponding to the imaginary extreme points in the Nyquist plot, or based on the frequencies corresponding to the phase extreme points in the Bode plot.
3. The method of claim 1, wherein, The method further includes: The amplitude of the first clock signal with the target characteristic frequency is adjusted until the real and imaginary parts of the impedance of the tested device satisfy the Kramers-Kroning relationship, thus obtaining the initial target amplitude.
4. The method according to claim 3, characterized in that, The adjustment of the amplitude of the first clock signal having the target characteristic frequency until the real and imaginary parts of the impedance of the tested device satisfy the Kramers-Kroning relationship, to obtain the initial target amplitude, includes: The preset voltage and the first clock signal are applied to the gate of the device, the amplitude of the first clock signal is adjusted, and the impedance of the device is tested. The amplitude corresponding to the real and imaginary parts of each impedance satisfying the Kramers-Kroning relationship is determined as the initial target amplitude.
5. The method according to claim 4, characterized in that, The step of randomly selecting a value from the set of initial target amplitudes to obtain the target amplitude includes: The target amplitude is obtained by selecting the largest amplitude from the set of initial target amplitudes.
6. The method according to any one of claims 1 to 5, characterized in that, Based on the first phase difference and the second phase difference, the characteristics of the interface under test in the device are determined, including: Determine the difference between the first phase difference and the second phase difference; If the difference is within a second preset range, it is determined that the interface state of the tested interface remains unchanged.
7. The method according to claim 6, characterized in that, Determining the interface characteristics of the measured interface in the device based on the first phase difference and the second phase difference further includes: If the difference is not within the second preset range, it is determined that the interface state of the tested interface has changed.
8. The method according to any one of claims 1 to 5, characterized in that, The excitation signal includes a square wave signal or a sine wave signal.
9. The method according to claim 8, characterized in that, The expression for the sinusoidal signal is: ΔV = |ΔV| × sin(ωt); where |ΔV| is the target amplitude, and ω is related to the reciprocal of the target characteristic frequency.
10. The method according to claim 9, characterized in that, The target amplitude ranges from 15 millivolts to 25 millivolts.
11. The method according to any one of claims 1 to 5, characterized in that, The device includes a MOS device, and the interface under test includes a Si-SiO2 interface.