Display device and display driving method

Abstract

Embodiments of the present disclosure relate to a display apparatus and a display driving method. Specifically, a display apparatus can be provided, including a display panel including a plurality of sub-pixels and a plurality of driving voltage lines providing driving voltages to the plurality of sub-pixels, a plurality of data driving circuits providing data voltages to the display panel, and a timing controller controlling the plurality of data driving circuits to supply compensated data voltages according to positions in the display panel, wherein in the compensated data voltages, a first compensation gain for at least some of the sub-pixels varies depending on positions of the plurality of data driving circuits corresponding to a first direction of the display panel, and a second compensation gain for at least some of the sub-pixels varies depending on distances from the plurality of data driving circuits in a second direction of the display panel.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0138625, filed on October 18, 2021, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] Embodiments of this disclosure relate to a display device, a data driving circuit, and a display driving method that can enhance the brightness uniformity of a display panel by compensating for the voltage drop of the driving voltage, which varies depending on the position of the sub-pixels. Background Technology

[0004] With the development of the information society, the demand for display devices for displaying images is increasing, and various types of display devices are being used, such as liquid crystal displays (LCDs) and organic light-emitting displays.

[0005] Among these display devices, organic light-emitting diode (OLED) displays use organic light-emitting diodes (OLEDs), which result in fast response times and various advantages in terms of contrast, luminous efficiency, brightness, and viewing angle.

[0006] Organic light-emitting diode (OLED) displays include organic light-emitting diodes arranged in sub-pixels on a display panel, and emit organic light-emitting diodes by controlling the current flowing to the organic light-emitting diodes, thereby controlling the brightness represented by each sub-pixel when displaying an image.

[0007] This display device includes a drive voltage power supply for supplying various drive voltages required to drive the display panel to the drive circuit and the display panel, and various components for transmitting the drive voltage.

[0008] However, since the voltage drop of the driving voltage transmitted through the driving voltage lines in the display panel varies depending on the position of the sub-pixel, the brightness will vary depending on the position in the display panel.

[0009] Therefore, variations in brightness may occur at specific locations on the display panel, a phenomenon known as uneven brightness, which can reduce image quality. Summary of the Invention

[0010] Therefore, methods for improving the brightness uniformity of display panels are being investigated. However, since each subpixel in a display panel emits light at different brightness depending on its horizontal or vertical two-dimensional (2D) position, a method is needed that can take into account the two-dimensional position of the subpixels to control the emitted light brightness in order to increase the brightness uniformity of the display panel.

[0011] The inventors of this specification have invented a display device and a display driving method that can improve brightness uniformity by compensating for the voltage drop of the driving voltage, which varies depending on the two-dimensional position of the sub-pixels in the display panel.

[0012] Embodiments of this disclosure can provide a display device and a display driving method that can mitigate brightness non-uniformity based on the two-dimensional position of sub-pixels by taking into account different voltage drop standards for the driving voltage in a first direction of the display panel and in a second direction perpendicular to the first direction.

[0013] Embodiments of this disclosure can provide a display device and a display driving method that can mitigate brightness non-uniformity based on the two-dimensional position of sub-pixels by taking into account the voltage drop of the driving voltage that varies depending on the position of the data driving circuit corresponding to a first direction of the display panel and the voltage drop of the driving voltage that varies depending on the resistance component of the driving voltage line in a second direction of the display panel.

[0014] Embodiments of this disclosure can provide a display device and a display driving method that can effectively mitigate brightness non-uniformity based on the two-dimensional position of sub-pixels, taking into account voltage drops in the driving voltage that vary depending on the pattern of the input image data.

[0015] According to embodiments of the present disclosure, a display device may be provided, comprising: a display panel including a plurality of sub-pixels and a plurality of driving voltage lines providing driving voltages to the plurality of sub-pixels; a plurality of data driving circuits configured to provide data voltages to the display panel; and a timing controller configured to control the plurality of data driving circuits for supplying compensation data voltages according to their positions in the display panel, wherein the compensation data voltages have a first compensation gain for a group of first sub-pixels and a second compensation gain for a group of second sub-pixels, the first compensation gain varying based on the positions of the plurality of data driving circuits corresponding to a first direction of the display panel, and the second compensation gain varying based on the distance from the plurality of data driving circuits in a second direction of the display panel.

[0016] According to embodiments of this disclosure, a display device and a display driving method can be provided that can improve brightness uniformity by compensating for the data voltage by taking into account the voltage drop of the driving voltage, which varies depending on the two-dimensional position of the sub-pixels in the display panel.

[0017] According to embodiments of the present disclosure, a display device and a display driving method can be provided, which can take into account different voltage drop standards for driving voltages in a first direction of the display panel and in a second direction perpendicular to the first direction to mitigate brightness non-uniformity based on the two-dimensional position of sub-pixels.

[0018] According to embodiments of the present disclosure, a display device and a display driving method can be provided that can mitigate brightness non-uniformity based on the two-dimensional position of sub-pixels by taking into account the voltage drop of the driving voltage that varies depending on the position of the data driving circuit corresponding to a first direction of the display panel and the driving voltage drop that varies depending on the resistance component of the driving voltage line in a second direction of the display panel.

[0019] According to embodiments of the present disclosure, a display device and a display driving method can be provided that can take into account the voltage drop of the driving voltage, which varies depending on the pattern of the input image data, and effectively reduce the brightness non-uniformity based on the two-dimensional position of the sub-pixels.

[0020] The first direction may be the direction in which the plurality of data driving circuits are arranged.

[0021] The first compensation gain may vary based on a first region overlapping with the plurality of data driving circuits and a second region between the plurality of data driving circuits.

[0022] The multiple driving voltage lines located in the first region can have a linear structure, and the multiple driving voltage lines located in the second region can have a curved structure.

[0023] The first compensation gain can be applied to a sub-pixel located in the first region using a first value, and the first compensation gain can be applied to a sub-pixel located in the second region using a second value, the second value being greater than the first value.

[0024] The second compensation gain can be set differently based on the position of the at least some second sub-pixels and based on the average gray level of the input image data.

[0025] The second compensation gain can be stored in a lookup table stored in memory.

[0026] The compensated data voltage can be determined based on the voltage drop associated with the sub-pixel furthest from the plurality of data driving circuits and the average gray level of the image data.

[0027] The compensated data voltage can be associated with a selected reference brightness.

[0028] The second compensation gain can be applied to sub-pixels located in non-black grayscale regions.

[0029] In one aspect, a display device is provided, which may include: a data driving circuit, and a display panel including: a first sub-pixel coupled to a data line of the data driving circuit; a second sub-pixel coupled to the data line, wherein the first sub-pixel is located between the data driving circuit and the second sub-pixel; and a driving voltage line coupled to the first sub-pixel and the second sub-pixel;

[0030] In an image frame, the data line, during operation, applies a first compensated data voltage to the first sub-pixel, the first compensated data voltage being generated based on a first value of a second compensation gain; and applies a second compensated data voltage to the second sub-pixel, the second compensated data voltage being generated based on a second value of the second compensation gain, the second value being greater than the first value.

[0031] The display device may further include: a memory for storing the first value and the second value;

[0032] A compensation circuit, in operation, generates compensated image data associated with the image frame based on the first value and the second value, and outputs the compensated image data to the data driving circuit; and a digital-to-analog converter, in operation, generates the first compensated data voltage and the second compensated data voltage based on the compensated image data.

[0033] In operation, the display device can determine the second compensation gain based on the voltage drop of the driving voltage supplied through the driving voltage line, the voltage drop being determined according to the position of the driving voltage line in a second direction.

[0034] The compensation circuit, in operation, can compensate for deviations in the drive voltage associated with the position, the compensation being based on the value of the second compensation gain stored in the memory.

[0035] The display device may further include: a third sub-pixel coupled to a second data line adjacent to the data line and coupled to a second driving voltage line adjacent to the driving voltage line; wherein the first sub-pixel and the second sub-pixel are in a first region overlapping with the data driving circuit, and the third sub-pixel is in a second region between the data driving circuit and a second data driving circuit adjacent to the data driving circuit; wherein the data line, in operation: supplies a third compensated data voltage to the third sub-pixel, the third compensated data voltage being generated based on a first compensation gain, the first compensation gain in the second region being greater than the first compensation gain in the first region.

[0036] The first and second values ​​can be generated as fractions of grayscale associated with the white.

[0037] The score may decrease with increasing proximity to the data driving circuit.

[0038] On the other hand, a method may be provided that includes:

[0039] A first compensated data voltage is applied to a first sub-pixel, the first compensated data voltage being generated based on a first value of a second compensated gain and applied via a first data line, the first value being associated with a first distance from the data driving circuit, the first sub-pixel being in an image frame; and

[0040] A second compensated data voltage is applied to a second sub-pixel in the same image frame. The second compensated data voltage is generated based on a second value of the second compensation gain and is applied via the first data line. The second value is associated with a second distance from the data driving circuit and is greater than the first value.

[0041] The method may further include: generating image data associated with the image frame based on the first value and the second value; outputting the compensated image data to the data driving circuit; and generating the first compensated data voltage and the second compensated data voltage based on the compensated image data.

[0042] The method may further include: applying a third compensated data voltage to a third sub-pixel in the image frame via a second data line adjacent to the first data line, the third compensated data voltage being generated based on a value of a first compensation gain associated with a second region where the third sub-pixel is located, the second region being between the data driving circuit and a second data driving circuit adjacent to the data driving circuit, the first sub-pixel being in a first region overlapping with the data driving circuit, the value being greater than another value associated with the first region. Attached Figure Description

[0043] The above and other objects, features and advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0044] Figure 1 This is a view that schematically illustrates the configuration of a display device according to various embodiments of the present disclosure;

[0045] Figure 2 This is a diagram illustrating an example of a system of a display device according to an embodiment of the present disclosure;

[0046] Figure 3This is a diagram illustrating an example of a circuit constituting a sub-pixel in a display device according to an embodiment of the present disclosure;

[0047] Figure 4 This is a diagram illustrating an example of the transmission path of the driving voltage in a display device according to an embodiment of the present disclosure;

[0048] Figure 5 This is a diagram illustrating an example of image non-uniformity in a display panel caused by a drop in the driving voltage.

[0049] Figure 6 This is a view illustrating an example of the concept of differential compensation for voltage drop relative to a first direction in a display device, according to an embodiment of the present disclosure.

[0050] Figure 7 This is a view illustrating the concept of voltage drop in a second direction along which the driving voltage line extends in a display device according to an embodiment of the present disclosure;

[0051] Figure 8 This is a view illustrating an example of a second compensation gain in a display device that varies depending on the pattern of the input image when setting the data voltage, according to an embodiment of the present disclosure;

[0052] Figure 9 This is a view schematically illustrating a process for compensating data voltage applied to a display panel in a display device according to an embodiment of the present disclosure;

[0053] Figure 10 and Figure 11 This illustrates an embodiment of the present disclosure in which, taking into account the input image pattern, the display device changes the data voltage with respect to the position in the second direction, resulting in a second compensation gain.

[0054] Figure 12 This is a view illustrating an example of enhancing brightness uniformity by compensating for data voltage, taking into account the voltage drop in the driving voltage that varies depending on the two-dimensional position of the sub-pixels in the display panel of the display device according to an embodiment of the present disclosure; and

[0055] Figure 13 This is a flowchart illustrating a display driving method according to an embodiment of the present disclosure. Detailed Implementation

[0056] In the following description, some embodiments of this disclosure will be described in detail with reference to the exemplary accompanying drawings. In the following description of examples or embodiments of this disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are illustrated by way of illustration, and wherein the same reference numerals and symbols may be used to denote the same or similar components, even if they are shown in different drawings. Furthermore, in the following description of examples or embodiments of this disclosure, detailed descriptions of well-known functions and components contained herein will be omitted when it is determined that the description may make the subject matter of some embodiments of this disclosure unclear. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed by” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “as long as.” As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0057] Terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used herein to describe elements of this disclosure. Each of these terms is not used to define an element, order, sequence, or quantity, but only to distinguish the corresponding element from other elements.

[0058] When referring to the first element being "connected or coupled" or "in contact or overlapping" with the second element, it should be understood that not only can the first element be "directly connected or coupled" or "directly in contact or overlapping" with the second element, but a third element can also be "inserted" between the first and second elements, or the first and second elements can be "connected or coupled," "in contact or overlapping," etc., with a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or coupled," "in contact or overlapping," etc., with each other.

[0059] When using time-related terms such as “after,” “follow,” “next,” or “before” to describe a process or operation of an element or configuration, or a flow or step in the operation, processing, or manufacture, these terms may be used to describe a non-continuous or non-sequential process or operation, unless the terms “direct” or “immediate” are used together.

[0060] Furthermore, when referring to any size, relative size, etc., the numerical value or corresponding information of the element or feature (e.g., grade, range, etc.) should be taken into account, including the possible tolerances or error ranges. Even if no relevant description is specified, it will be affected by various factors (e.g., process factors, internal or external influences, noise, etc.). Moreover, the word "can" fully encompasses all the meanings of the word "able to".

[0061] In the following, various embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0062] Figure 1 This is a view that schematically illustrates the configuration of a display device according to various embodiments of the present disclosure.

[0063] Reference Figure 1 The display device 100 according to the present disclosure may include: a display panel 110, wherein a plurality of gate lines GL and data lines DL are connected, and a plurality of sub-pixels SP are arranged in a matrix; a gate driving circuit 120, which drives the plurality of gate lines GL; a data driving circuit 130, which provides data voltage through the plurality of data lines DL; a timing controller 140, which controls the gate driving circuit 120 and the data driving circuit 130; and a power management circuit 150.

[0064] The display panel 110 displays images based on scan signals transmitted from the gate drive circuit 120 via multiple gate lines GL and data voltages transmitted from the data drive circuit 130 via multiple data lines DL.

[0065] In the case of an organic light-emitting display, the display panel 110 can be implemented using a top-emitting scheme, a bottom-emitting scheme, or a dual-emitting scheme.

[0066] In the display panel 110, multiple pixels can be arranged in a matrix, and each pixel can include sub-pixels SP with different colors, such as white sub-pixels, red sub-pixels, green sub-pixels and blue sub-pixels, and each sub-pixel SP can be defined by multiple data lines DL and multiple gate lines GL (e.g., located in the area where multiple data lines DL and multiple gate lines GL overlap).

[0067] A sub-pixel SP may include, for example, a thin-film transistor (TFT) formed in an overlapping area between a data line DL and a gate line GL, a light-emitting element such as an organic light-emitting diode charged with a data voltage, and a storage capacitor electrically connected to the light-emitting element to maintain the voltage.

[0068] For example, when a display device 100 with a resolution of 2160×3840 includes four sub-pixels SP of white (W), red (R), green (G), and blue (B), 3840 data lines DL can be connected to 2160 gate lines GL and the four sub-pixels WRGB, thus providing 3840×4=15360 data lines DL. Each sub-pixel SP is located in the overlapping area between the gate lines GL and the data lines DL.

[0069] The gate drive circuit 120 can be controlled by the controller 140 to sequentially output scan signals to multiple gate lines GL disposed in the display panel 110, thereby controlling the driving timing of multiple sub-pixels SP.

[0070] In a display device 100 with a resolution of 2160×3840, sequentially outputting scan signals from the first gate line to the 2160th gate line to 2160 gate lines GL can be referred to as 2160-phase driving. Sequentially outputting scan signals to each group of four gate lines GL, for example, after sequentially outputting scan signals to the first to fourth gate lines, sequentially outputting scan signals to the fifth to eighth gate lines, is called four-phase driving. In other words, sequentially outputting scan signals to every N gate lines GL can be referred to as N-phase driving.

[0071] The gate driving circuit 120 may include one or more gate driving integrated circuits (GDICs). Depending on the driving scheme, the gate driving circuit 120 may be located only on one side of the display panel 110 or on each of two opposite sides. The gate driving circuit 120 may be implemented as a gate in-panel (GIP) embedded in the bezel area of ​​the display panel 110.

[0072] The data driving circuit 130 receives image data DATA from the timing controller 140 and converts the received image data DATA into an analog data voltage. Then, as the data voltage is output to each data line DL according to the timing of the scan signal applied through the gate line GL, each sub-pixel SP connected to the data line DL displays a light-emitting signal with a brightness corresponding to the data voltage.

[0073] Similarly, the data driver circuit 130 may include one or more source driver integrated circuits (SDICs), and the source driver integrated circuits (SDICs) may be connected to the bonding pads of the display panel 110 in the form of tape auto-bonding (TAB) or chip-on-glass (COG) type, or may be directly disposed on the display panel 110.

[0074] In some cases, each source driver integrated circuit (SDIC) can be integrated and disposed on the display panel 110. Furthermore, each source driver integrated circuit (SDIC) can be implemented as a chip-on-film (COF) type, and in this case, each source driver integrated circuit (SDIC) can be mounted on a circuit film and electrically connected to the data line DL of the display panel 110 via the circuit film.

[0075] The timing controller 140 provides various control signals to the gate drive circuit 120 and the data drive circuit 130, and controls the operation of the gate drive circuit 120 and the data drive circuit 130. In other words, the timing controller 140 can control the gate drive circuit 120 to output a scan signal according to the timing implemented in each frame, and on the other hand, transmit the image data DATA received from the outside to the data drive circuit 130.

[0076] In this case, the timing controller 140 receives several timing signals along with image data DATA from the external host system 200, including, for example, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, and the master clock MCLK.

[0077] The host system 200 can be any of a television (TV) system, set-top box, navigation system, personal computer (PC), home theater system, mobile device, and wearable device.

[0078] Therefore, the timing controller 140 can generate control signals based on various timing signals received from the host system 200, and transmit the control signals to the gate drive circuit 120 and the data drive circuit 130.

[0079] For example, timing controller 140 outputs several gate control signals, including, for example, a gate start pulse GSP, a gate clock GCLK, and a gate output enable signal GOE, to control gate drive circuit 120. The gate start pulse GSP controls the timing of the start of operation of one or more gate driver integrated circuits (GDICs) constituting gate drive circuit 120. The gate clock GCLK is a clock signal commonly input to one or more gate driver integrated circuits (GDICs) and controls the shift timing of the scan signal. The gate output enable signal GOE specifies timing information regarding one or more gate driver integrated circuits (GDICs).

[0080] The timing controller 140 outputs various data control signals, including, for example, a source start pulse (SSP), a source sampling clock (SCLK), and a source output enable signal (SOE), to control the data drive circuit 130. The source start pulse (SSP) controls the timing of data sampling initiated by one or more source driver integrated circuits (SDICs) constituting the data drive circuit 130. The source sampling clock (SCLK) is the clock signal that controls the data sampling timing in the source driver integrated circuit (SDIC). The source output enable signal (SOE) controls the output timing of the data drive circuit 130.

[0081] The display device 100 may also include a power management circuit 150 that provides various voltages or currents to, for example, the display panel 110, the gate driving circuit 120, and the data driving circuit 130, or controls the various voltages or currents to be provided.

[0082] The power management circuit 150 adjusts the DC input voltage Vin provided from the host system 200 to generate the power required to drive the display panel 100, the gate drive circuit 120, and the data drive circuit 130.

[0083] Subpixels SP are located in the overlapping area between gate line GL and data line DL, and light-emitting elements can be disposed in each subpixel SP. For example, an organic light-emitting diode display may include light-emitting elements such as organic light-emitting diodes in each subpixel SP, and images can be displayed by controlling the current flowing to the light-emitting elements according to the data voltage.

[0084] The display device 100 can be one of various types of devices, such as a liquid crystal display, an organic light-emitting diode display, or a plasma display panel.

[0085] Figure 2 This is a diagram illustrating an example of a system of a display device according to an embodiment of the present disclosure.

[0086] Reference Figure 2 In the display device 100 according to an embodiment of the present disclosure, the source driver integrated circuit SDIC included in the data driver circuit 130 and the gate driver integrated circuit GDIC included in the gate driver circuit 120 are implemented as chip-on-film (COF) types of various types (e.g., TAB, COG or COF).

[0087] One or more gate driver integrated circuits (GDICs) included in the gate driver circuit 120 may each be mounted on a gate film GF, and one side of the gate film GF may be electrically connected to the display panel 110. Lines for electrically connecting the gate driver integrated circuits (GDICs) and the display panel 110 may be provided on the gate film GF.

[0088] Depending on the driving method, the gate driving circuit 120 may be located on only one side or on each of the two opposite sides of the display panel 110. The gate driving circuit 120 may be implemented as an in-panel gate (GIP) embedded in the bezel area of ​​the display panel 110.

[0089] Similarly, one or more source driver integrated circuits (SDICs) included in the data driver circuit 130 can each be mounted on the source film SF, and one side of the source film SF can be electrically connected to the display panel 110. Lines for electrically connecting the source driver integrated circuits (SDICs) and the display panel 110 can be provided on the source film SF.

[0090] The display device 100 may include at least one source printed circuit board (SPCB) for circuit connections between multiple source driver integrated circuits (SDICs) and other devices; and a control printed circuit board (CPCB) for mounting control components and various electronic devices.

[0091] The other side of the source film SF, on which the active driver integrated circuit SDIC is mounted, can be connected to at least one source printed circuit board SPCB. In other words, the side of the source film SF on which the active driver integrated circuit SDIC is mounted can be electrically connected to the display panel 110, while the other side can be electrically connected to the source printed circuit board SPCB.

[0092] The timing controller 140 and the power management circuit (power management IC) 150 can be mounted on the control printed circuit board (CPCB). The timing controller 140 can control the operation of the data drive circuit 130 and the gate drive circuit 120. The power management circuit 150 can provide drive voltage or current to the display panel 110, the data drive circuit 130, and the gate drive circuit 120, and control the provided voltage or current.

[0093] At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) can be circuitally connected via at least one connecting member. The connecting member may include, for example, a flexible printed circuit (FPC) or a flexible flat cable (FFC). In this case, the connecting member connecting the at least one source printed circuit board (SPCB) and the control printed circuit board (CPCB) can vary depending on the size and type of the display device 100. At least one source printed circuit board (SPCB) and the control printed circuit board (CPCB) can be integrated into a single printed circuit board.

[0094] In the display device 100 configured in this way, the power management circuit 150 transmits the drive voltage required for display driving or characteristic value sensing to the source printed circuit board SPCB via a flexible printed circuit FPC or a flexible flat cable FFC. The drive voltage transmitted to the source printed circuit board SPCB is provided by the source driver integrated circuit SDIC to emit light or sense specific sub-pixels SP in the display panel 110.

[0095] Each sub-pixel SP in the display panel 110 arranged in the display device 100 may include an organic light-emitting diode as a light-emitting element and circuit elements for driving the light-emitting diode, such as a driving transistor.

[0096] The type and number of circuit elements that make up each sub-pixel SP can vary depending on the functionality and design scheme to be provided.

[0097] Figure 3 This is a diagram illustrating an example of a circuit constituting a sub-pixel in a display device according to an embodiment of the present disclosure.

[0098] Reference Figure 3 In the display device 100 according to an embodiment of the present disclosure, the sub-pixel SP may include one or more transistors and capacitors, as well as an organic light-emitting diode (OLED) as a light-emitting element ED.

[0099] For example, a subpixel SP may include a driving transistor DRT, a switching transistor SWT, a sensing transistor SENT, a storage capacitor Cst, and a light-emitting element ED.

[0100] The driving transistor DRT includes a first node N1, a second node N2, and a third node N3. The first node N1 of the driving transistor DRT can be the gate node where a data voltage Vdata is applied from the data driving circuit 130 via the data line DL when the switching transistor SWT is turned on. The second node N2 of the driving transistor DRT can be electrically connected to the anode of the light-emitting element ED and can be either a source node or a drain node. The third node N3 of the driving transistor DRT can be electrically connected to the driving voltage line DVL to which the driving voltage EVDD is applied and can be either a drain node or a source node.

[0101] In this configuration, during the display drive cycle, the drive voltage EVDD required to display the image can be supplied to the drive voltage line DVL. For example, the drive voltage EVDD required to display the image could be 27V.

[0102] The switching transistor SWT is electrically connected between the first node N1 of the driving transistor DRT and the data line DL, and the gate line GL is connected to the gate node. Therefore, the switching transistor SWT operates according to the scan signal SCAN provided through the gate line GL. When turned on, the switching transistor SWT transmits the data voltage Vdata provided through the data line DL to the gate node of the driving transistor DRT, thereby controlling the operation of the driving transistor DRT.

[0103] The sensing transistor SENT is electrically connected between the second node N2 of the driving transistor DRT and the reference voltage line RVL, and the gate line GL is connected to the gate node. The sensing transistor SENT operates according to the sensing signal SENSE provided through the gate line GL. When the sensing transistor SENT is turned on, the reference voltage Vref provided through the reference voltage line RVL is transmitted to the second node N2 of the driving transistor DRT.

[0104] In other words, as the switching transistor SWT and the sensing transistor SENT are controlled, the voltage of the first node N1 and the second node N2 of the driving transistor DRT are controlled, so that current can be provided to drive the light-emitting element ED.

[0105] The gate nodes of the switching transistor SWT and the sensing transistor SENT can be connected to a common gate line GL, or they can be connected to different gate lines GL. An example is shown where the switching transistor SWT and the sensing transistor SENT are connected to different gate lines GL. In this case, the switching transistor SWT and the sensing transistor SENT can be independently controlled by the scan signal SCAN and the sensing signal SENSE transmitted through different gate lines GL.

[0106] Conversely, if the switching transistor SWT and the sensing transistor SENT are connected to a gate line GL, the switching transistor SWT and the sensing transistor SENT can be controlled simultaneously by the scan signal SCAN or the sensing signal SENSE transmitted through a gate line GL, and the aperture ratio of the sub-pixel SP can be increased.

[0107] The transistor set in the sub-pixel SP can be an n-type transistor or a p-type transistor, and in the example shown, the transistor is an n-type transistor.

[0108] The storage capacitor Cst is electrically connected between the first node N1 and the second node N2 of the driving transistor DRT, and holds the data voltage Vdata during one frame.

[0109] Depending on the type of driving transistor DRT, the storage capacitor Cst can also be connected between the first node N1 and the third node N3 of the driving transistor DRT. The anode of the light-emitting element ED can be electrically connected to the second node N2 of the driving transistor DRT, and the base voltage EVSS can be applied to the cathode of the light-emitting element ED.

[0110] The base voltage EVSS can be ground voltage or a voltage higher or lower than ground voltage. The base voltage EVSS can vary depending on the driving state. For example, the base voltage EVSS during display driving and the base voltage EVSS during sensing driving can be set to be different from each other.

[0111] The sub-pixel SP structure described above as an example is a 3T (transistor) 1C (capacitor) structure. This is merely an example and may further include one or more transistors, or in some cases, one or more capacitors. Multiple sub-pixel SPs may have the same structure, or some sub-pixels in multiple sub-pixel SPs may have different structures.

[0112] In order to effectively sense characteristic values ​​of the driving transistor DRT, such as threshold voltage or mobility, the display device 100 according to embodiments of the present disclosure may use a method for measuring the current flowing from the voltage charged into the storage capacitor Cst during characteristic value sensing of the driving transistor DRT, referred to as current sensing.

[0113] In other words, the characteristic value or change in characteristic value of the driving transistor DRT in the sub-pixel SP can be calculated by measuring the current flowing from the voltage charged into the storage capacitor Cst during characteristic value sensing of the driving transistor DRT.

[0114] In this case, the reference voltage line RVL is used not only to transmit the reference voltage Vref, but also as a sensing line for sensing the characteristic values ​​of the driving transistor DRT in the sub-pixel SP. Therefore, the reference voltage line RVL can also be called a sensing line.

[0115] In this scenario, the period for sensing the driving characteristic values ​​(threshold voltage and mobility) of the driving transistor DRT can be performed after the power-on signal is generated and before the display driving begins. For example, if a power-on signal is applied to the display device 100, the timing controller 140 loads the parameters required to drive the display panel 110 and then drives the display. In this case, the parameters required to drive the display panel 110 may include information related to the sensing and compensation driving characteristic values ​​previously performed on the display panel 110. During the parameter loading process, the sensing of the driving characteristic values ​​(threshold voltage and mobility) of the driving transistor DRT can be performed. As described above, the process of sensing the driving characteristic values ​​during the parameter loading process after the power-on signal is generated is called the on-sensing process.

[0116] Alternatively, the period for sensing the driving characteristic value of the driving transistor DRT can continue after the power-off signal of the display device 100 is generated. For example, when a power-off signal is generated in the display device 100, the timing controller 140 can cut off the data voltage supplied to the display panel 110 and can sense the driving characteristic value of the driving transistor DRT for a predetermined or selected time. Thus, the process of sensing the driving characteristic value when the data voltage is cut off at the time of the power-off signal is called the off-sensing process.

[0117] Alternatively, the sensing cycle of the driving characteristic values ​​of the driving transistor DRT can be performed in real time while driving the display. This sensing process is called real-time (RT) sensing. In real-time sensing, the sensing process can be performed on one or more sub-pixel SPs in one or more sub-pixel SP rows during each blank period of the display driving cycle.

[0118] Figure 4 This is a view illustrating an example of the transmission path of the driving voltage in a display device according to an embodiment of the present disclosure. Here, Figure 2 Part A shown is enlarged and displayed.

[0119] Reference Figure 4In the display device 100 according to an embodiment of the present disclosure, a plurality of sub-pixels SP defined by a plurality of intersecting data lines DL and a plurality of gate lines GL (e.g., located in the region where the plurality of data lines DL and the plurality of gate lines GL overlap) are disposed on a display panel 110. In this case, each sub-pixel SP receives a driving voltage EVDD through a plurality of driving voltage lines DVL arranged in a direction parallel to the plurality of data lines DL.

[0120] Multiple drive voltage lines (DVL) can be formed between multiple data lines (DL) to be parallel to the multiple data lines (DL), or they can be formed to be shared by two sub-pixels that are adjacent to each other in the left-right direction.

[0121] Multiple drive voltage lines (DVLs) can be connected together to a common drive voltage line 135 formed in the upper non-display area of ​​the display panel 110.

[0122] The drive voltage EVDD transmitted from the power management circuit 150 is supplied to the common drive voltage line 135 through multiple data drive circuits 130.

[0123] In order to transmit the drive voltage EVDD to multiple drive voltage lines DVL, a first drive voltage supply line 131, a second drive voltage supply line 132, a third drive voltage supply line 133, and a fourth drive voltage supply line 134 can be set.

[0124] The first drive voltage supply line 131, the second drive voltage supply line 132, and the third drive voltage supply line 133 can be electrically connected to the source printed circuit board (SPCB).

[0125] The fourth drive voltage supply line 134 can branch to two opposite sides of the source driver integrated circuit SDIC in the data driver circuit 130, and the third drive voltage supply line 133 can be electrically connected to the common drive voltage line 135.

[0126] The third drive voltage supply line 133 can be located in the region adjacent to the source film SF and can be electrically connected to the fourth drive voltage supply line 134 formed in the data drive circuit 130.

[0127] Since the first drive voltage supply line 131 corresponds to the portion to which the drive voltage EVDD supplied from the power management circuit 150 is applied, the first drive voltage supply line 131 can be formed to have a relatively larger area than the third drive voltage supply line 133.

[0128] The second drive voltage supply line 132 can branch from the first drive voltage supply line 131 with a predetermined or selected interval and connect to the third drive voltage supply line 133.

[0129] In this case, since the second drive voltage supply line 132 is located in the region before the drive voltage EVDD branches through multiple drive voltage lines DVL, the second drive voltage supply line 132 has a relatively high current density compared to the fourth drive voltage supply line 134 and the drive voltage lines DVL.

[0130] Therefore, due to the high density current, the second drive voltage supply line 132 is more likely to experience temperature rise and defects.

[0131] Meanwhile, the data driver circuit 130 can group multiple source driver integrated circuits SDIC into a group to provide the drive voltage EVDD by group.

[0132] In this case, the drive voltage EVDD output from the power management circuit 150 experiences a voltage drop (e.g., IRdrop) due to the resistive component of the lines as it is transmitted through drive voltage supply lines 131, 132, 133 and 134 and drive voltage line DVL.

[0133] Figure 5 This is a diagram illustrating an example of image unevenness in a display panel caused by a voltage drop in the driving voltage.

[0134] Reference Figure 5 In the display device 100, the driving voltage EVDD transmitted through the driving voltage line DVL may experience a voltage drop due to the resistive component of the driving voltage line DVL, and if the drop in driving voltage EVDD varies depending on the position, non-uniformity will appear in the image displayed on the display panel 110.

[0135] In particular, if such image non-uniformity is a predetermined or selected reference value or more, the user's eye may perceive a quality defect.

[0136] In this case, image non-uniformity due to voltage drop of the driving voltage may occur at the locations of driving voltage supply lines 131, 132, 133 and 134 in the data driving circuit 130.

[0137] In other words, the drive voltage supply lines 131, 132, 133, and 134 are configured via each source film SF of the source driver integrated circuit SDIC mounted in the data drive circuit 130, and the line resistance varies depending on the path of the drive voltage line DVL extending from it. Therefore, image inhomogeneity may occur.

[0138] Correspondingly, although the driving voltage line DVL in the display panel forms a relatively short path in the area where it overlaps with the data driving circuit 130 in the extension direction of the driving voltage line DVL, the driving voltage line DVL in the area where it does not overlap with the data driving circuit 130 forms a relatively long path.

[0139] As a result, a voltage drop occurs between the driving voltage line DVL located in the region overlapping with the data driving circuit 130 and the driving voltage line DVL located in the region not overlapping with the data driving circuit 130, leading to image non-uniformity.

[0140] According to embodiments of the present disclosure, the display device 100 can compensate for the data voltage Vdata by the voltage drop depending on the location of the driving voltage EVDD in the first direction where the data driving circuit 130 is arranged, based on whether it overlaps with the data driving circuit 130, thereby improving the uniformity of the image displayed on the display panel 110.

[0141] Figure 6 This is a view illustrating an example of the concept of differential compensation of the driving voltage relative to a first direction in a display device according to an embodiment of the present disclosure.

[0142] Reference Figure 6 According to embodiments of the present disclosure, the display device 100 can compensate for the voltage drop of the driving voltage EVDD, which depends on the position in the first direction where the data driving circuit 130 is arranged, based on whether it overlaps with the data driving circuit 130, thereby improving image uniformity.

[0143] The first direction is the direction in which multiple data driving circuits 130 are arranged on the display panel 110, and if the multiple data driving circuits 130 are arranged in the horizontal direction, such as... Figure 6 As shown, the first direction corresponds to the horizontal direction.

[0144] Therefore, the sub-pixels SP arranged in the first direction, which is horizontal, are divided depending on whether they correspond to the overlapping area (or "first area") of the data driving circuit 130 or the non-overlapping area (or "second area") of the data driving circuit 130, and different compensation values ​​for the provided data voltage Vdata are applied to each area, thereby enhancing image uniformity.

[0145] In this case, the overlapping area Area1 corresponding to the data driving circuit 130 can be the area corresponding to the position where it overlaps with the data driving circuit 130 in the extension direction of the driving voltage line DVL, for example, in the second direction perpendicular to the first direction.

[0146] Therefore, since the overlapping area Area1 corresponding to the data driving circuit 130 corresponds to the position where it overlaps with the data driving circuit 130 in the second direction of the extension of the driving voltage line DVL, the first driving voltage line DVL1 provided in the overlapping area Area1 corresponding to the data driving circuit 130 can be formed as a linear structure from the data driving circuit 130.

[0147] The non-overlapping area Area 2, which does not correspond to the data driving circuit 130, can be a region that does not overlap with the data driving circuit 130 in the second direction along which the driving voltage line DVL extends. The non-overlapping area Area 2, which does not correspond to the data driving circuit 130, can correspond to a region corresponding to the space between adjacent data driving circuits 130 in the second direction. It should be understood that the overlapping area Area 1 and the non-overlapping area Area 2 can extend in the second direction (e.g., the Y-axis direction) and can be arranged in the first direction (e.g., the X-axis direction). The overlapping area Area 1 can be understood as a protrusion extending from the data driving circuit 130 (e.g., an extension in the second direction), and the second non-overlapping area Area 2 can be understood as a protrusion extending from the space between the data driving circuits 130 (e.g., an extension in the second direction).

[0148] Therefore, since the non-overlapping area Area2, which does not correspond to the data driving circuit 130, corresponds to a position where the driving voltage line DVL does not overlap with the data driving circuit 130 in the second direction along which it extends, the second driving voltage line DVL2 provided in the non-overlapping area Area2, which does not correspond to the data driving circuit 130, can be formed as a structure that bends from the data driving circuit 130.

[0149] Therefore, compared with the first driving voltage line DVL1 disposed in the overlapping area Area 1 corresponding to the data driving circuit 130, the second driving voltage line DVL2 disposed in the non-overlapping area Area 2 not corresponding to the data driving circuit 130 can have a relatively long line path.

[0150] As a result, the voltage drop generated by the second drive voltage line DVL2, which is located in the non-overlapping area Area 2 that does not correspond to the data drive circuit 130, is relatively greater than the voltage drop generated by the first drive voltage line DVL1, which is located in the overlapping area Area 1 corresponding to the data drive circuit 130. It should be understood that "bend" can mean that the drive voltage line includes a horizontal segment (e.g., in the X-axis direction) connected to a vertical segment (e.g., in the Y-axis direction). For example, the second drive voltage line DVL2 includes a horizontal segment that extends through the data drive circuit 130 and is attached to the vertical segment extending through the non-overlapping area Area 2. This horizontal segment may not be present in the first data voltage line DVL1, such that the second drive voltage line DVL2 has an additional voltage drop (or IR drop) due to the horizontal segment.

[0151] Therefore, for sub-pixels SP in the first direction, the display device 100 of this disclosure can enhance the uniformity of the image displayed in the first direction by reducing the first compensation gain of the data voltage Vdata for the sub-pixels SP located in the overlapping area Area 1 of the data driving circuit 130, while increasing or maintaining the first compensation gain of the data voltage Vdata for the sub-pixels SP located in the non-overlapping area Area 2 of the data driving circuit 130. For example, a first value of the first compensation gain can be associated with the sub-pixels SP located in the overlapping area Area 1, and a second value of the first compensation gain can be associated with the sub-pixels SP located in the non-overlapping area Area 2. The second value can be greater than the first value.

[0152] Furthermore, the display device 100 of this disclosure can enhance the uniformity of the image displayed on the display panel 110 by applying a second compensation gain differently along a second direction perpendicular to the first direction, depending on the magnitude by which the driving voltage EVDD drops according to the position along the driving voltage line DVL, to compensate the data voltage Vdata.

[0153] Figure 7 This is a view illustrating the concept of voltage drop in a second direction along which the driving voltage line extends in a display device according to an embodiment of the present disclosure.

[0154] Reference Figure 7 In the display device 100 according to an embodiment of the present disclosure, the drive current flowing through the drive voltage line DVL by the drive voltage EVDD is reduced by the line resistance of the drive voltage line DVL.

[0155] In this case, the resistance component of the drive voltage line DVL can be defined relative to its overlap with the gate line GL. Therefore, the resistance component between the node where the drive voltage EVDD is introduced and the first gate line GL1 can be called the introduction resistance R0, the resistance component between the first gate line GL1 and the second gate line GL2 can be called the first resistance R1, the resistance component between the second gate line GL2 and the third gate line GL3 can be called the second resistance R2, and the resistance component between the third gate line GL3 and the fourth gate line GL4 can be called the third resistance R3.

[0156] The introduction current It flowing through the introduction resistor R0 is branched into the first light-emitting current I1 flowing through the first gate line GL1 to the first light-emitting element ED1 and the driving current It-I1 flowing through the first resistor R1.

[0157] Therefore, the first drive voltage V1 corresponding to the first gate line GL1 can be calculated as EVDD-R0*It.

[0158] The driving current It-I1 flowing through the first resistor R1 is branched into the second light-emitting current I2 flowing through the second gate line GL2 to the second light-emitting element ED2 and the driving current It-I1-I2 flowing through the second resistor R2.

[0159] Therefore, the second driving voltage V2 corresponding to the second gate line GL2 can be calculated as V1-R1*(It-I1).

[0160] The driving current It-I1-I2 flowing through the second resistor R2 is branched into the third light-emitting current I3 flowing through the third gate line GL3 to the third light-emitting element ED3 and the driving current It-I1-I2-I3 flowing through the third resistor R3.

[0161] Therefore, the third driving voltage V3 corresponding to the third gate line GL3 can be calculated as V2-R2*(It-I1-I2).

[0162] In this way, the level of the drive voltage at the intersection of the drive voltage line DVL and each gate line GL can be calculated. Therefore, using the drive voltage level at the intersection with each gate line GL, the voltage drop based on the position of the drive voltage line DVL can be calculated, and the corresponding compensation value for the data voltage Vdata can be determined.

[0163] Furthermore, since the voltage drop of the driving voltage line DVL can vary depending on the pattern of the input image in the display device 100 of this disclosure, the image uniformity can be effectively enhanced according to the image pattern by setting different second compensation gains for the data voltage Vdata depending on the pattern of the input image.

[0164] Figure 8This is a view illustrating an example of a second compensation gain in a display device that varies depending on the pattern setting data voltage of the input image, according to an embodiment of the present disclosure.

[0165] Reference Figure 8 In the display device 100 according to an embodiment of the present disclosure, the magnitude of the voltage drop of the drive voltage line DVL can vary depending on the pattern of the input image.

[0166] For example, if the input image is black data with a grayscale of 0, the voltage drop between the first gate line GL1 and the nth gate line GLn may be small; if the input image is white data with a grayscale of 255, the voltage drop between the first gate line GL1 and the nth gate line GLn may be large.

[0167] The closer the grayscale is to white, the higher the brightness of the applied data voltage Vdata. Therefore, due to the operating characteristics of the circuit elements driving the display panel 110, the temperature of the display panel 110 will increase, or the voltage drop of the drive voltage line DVL will increase.

[0168] Therefore, to compensate for the increase in voltage drop across the drive voltage line DVL as the grayscale of the input image increases, the difference between the second compensation gain for the gate line near the data drive circuit 130 (e.g., the first gate line GL1) and the second compensation gain for the data voltage Vdata applied to the gate line away from the data drive circuit 130 (e.g., the nth gate line GLn) can be set to increase as the grayscale of the input image increases. For example, the second compensation gain may have a first value associated with the gate line near the data drive circuit 130 and a second value associated with the gate line away from the data drive circuit 130, the second value being greater than the first value.

[0169] Conversely, if the grayscale of the input image is low, the voltage drop across the drive voltage line DVL is relatively small. The difference between the second compensation gain for the gate line near the data drive circuit 130 (e.g., the first gate line GL1) and the second compensation gain for the data voltage Vdata applied to the gate line far from the data drive circuit 130 (e.g., the nth gate line GLn) can be set to be small.

[0170] For example, if black data with a grayscale of 0 is input, a relatively small voltage drop will occur between the first gate line GL1 and the nth gate line GLn. Therefore, the second compensation gain of the first gate line GL1 and the second compensation gain of the nth gate line GLn will only have a difference between 240 / 256 and 256 / 256 (16 / 256). However, if white data with a grayscale of 255 is input, the second compensation gain of the first gate line GL1 and the second compensation gain of the nth gate line GLn can have a difference between 208 / 256 and 256 / 256 (48 / 256).

[0171] Therefore, the compensation value of the data voltage Vdata for the second direction of the driving voltage line DVL extension can depend on the pattern of the input image (e.g., the grayscale of the input image) and different second compensation gain differences can be set for the sub-pixels SP corresponding to the gate line GL.

[0172] For each grayscale of the input image, a second compensation gain, applied to the data voltage Vdata of the sub-pixel SP corresponding to each gate line GL, is shown as an example.

[0173] For example, if the input image has a grayscale value of 0, a second compensation gain of 240 / 256 can be applied to the sub-pixel SP corresponding to the first gate line GL1, and a second compensation gain of 256 / 256 can be applied to the sub-pixel SP corresponding to the nth gate line GLn.

[0174] Conversely, if the input image has a grayscale value of 255, a second compensation gain of 208 / 256 can be applied to the sub-pixel SP corresponding to the first gate line GL1, and a second compensation gain of 256 / 256 can be applied to the sub-pixel SP corresponding to the nth gate line GLn.

[0175] The second compensation gain data (e.g., a first value and a second value) based on the data voltage Vdata of such an input image pattern can be stored in memory in the form of a lookup table. For example, the lookup table can associate each of the sub-pixels SP or each of the gate lines GL1-GLn of the display panel 110 with a second compensation gain value. The lookup table can associate each of the sub-pixels SP or each of the gate lines GL1-GLn with a different value of the second compensation gain for each grayscale value (e.g., different values ​​of 0G, 16G, 32G, ... 255G). One or more different values ​​can have the same magnitude, for example, when the difference between the second compensation gain of the first gate line GL1 and the second compensation gain of the nth gate line GLn is 16 / 256 (e.g., 256 / 256 - 240 / 256), and the number n is in the thousands. In one embodiment, the lookup table associates each of the sub-pixels SP or each of the gate lines GL1-GLn with a different value of the second compensation gain for each grayscale value (e.g., different values ​​of 0G, 1G, 2G, 3G, ... 255G).

[0176] Figure 9 This is a view schematically illustrating a process for compensating the data voltage applied to a display panel in a display device according to an embodiment of the present disclosure.

[0177] Reference Figure 9 The display device 100 according to an embodiment of the present disclosure may include a component for compensating for deviations in the drive voltage EVDD based on the position in the display panel 110.

[0178] For example, during a display drive cycle in which a drive voltage EVDD is applied, the display device 100 may determine a first compensation gain by taking into account the position of the data drive circuit 130 corresponding to the first direction in which the data drive circuit 130 is disposed on the display panel 110, and determine a second compensation gain of the data voltage Vdata by taking into account the voltage drop of the drive voltage EVDD determined based on the two-dimensional position of the drive voltage line DVL extending in the second direction.

[0179] The timing controller 140 of the display device 100 may include: a memory MEM for storing a first compensation gain and a second compensation gain determined according to the two-dimensional position of the display panel 110; and a compensation circuit COMP for compensating for deviations in the drive voltage EVDD according to the first compensation gain or the second compensation gain stored in the memory MEM and according to the two-dimensional position of the display panel 110.

[0180] Therefore, the compensation circuit COMP of the timing controller 140 can use the first compensation gain or the second compensation gain extracted from the memory MEM to compensate the image data DATA to be supplied to the data drive circuit 130 corresponding to each position of the display panel 110, and output the compensated image data DATA_comp to the data drive circuit 130.

[0181] Therefore, the data driving circuit 130 can convert the compensated image data DATA_comp into a compensated data voltage Vdata_comp of analog signal type via a digital-to-analog converter (DAC), and transmit the compensated data voltage Vdata_comp to the data line DL via the output buffer BUF. As a result, the deviation of the driving voltage EVDD for the sub-pixel SP can be compensated according to the two-dimensional position of the display panel 110.

[0182] The compensation circuit COMP can exist inside or outside the timing controller 140. The memory MEM can be located outside the timing controller 140 or can be implemented inside the timing controller 140 in the form of a register.

[0183] Figure 10 and Figure 11 This is a view illustrating an example of a display device according to an embodiment of the present disclosure that applies a second compensation gain to the data voltage by applying an input image pattern that varies depending on the position of the input image pattern in a second direction.

[0184] Reference Figure 10 According to the embodiments of the present disclosure, the display device 100 can receive white data of grayscale 255 (255G) as image data DATA.

[0185] Therefore, the data driving circuit 130 supplies the grayscale 255 (255G) data voltage Vdata to the display panel 110. However, the driving voltage EVDD transmitted through the driving voltage line DVL extending from the data driving circuit 130 to the display panel 110 experiences a voltage drop due to line resistance. As a result, the luminous brightness decreases as one moves away from the data driving circuit 130.

[0186] For example, a sub-pixel SP located near the data driving circuit 130 exhibits a brightness of 640 nits through a data voltage Vdata of grayscale 255 (255G), while a sub-pixel SP located far from the data driving circuit 130 exhibits a brightness of 580 nits due to the voltage drop of the driving voltage line DVL.

[0187] In order to compensate for the deviation of the driving voltage EVDD, taking into account the voltage drop of the driving voltage line DVL according to the image pattern of grayscale 255, the display device 100 can apply a compensated data voltage Vdata_comp according to the position of the display panel 110 in the second direction, thereby uniformly compensating the luminance of the display panel 110 to the reference luminance Lref.

[0188] As a second compensation gain used to generate the compensated data voltage Vdata_comp, it can be used in Figure 8 The values ​​specified in the table are for white data with a grayscale of 255 (255G).

[0189] In this case, the timing controller 140 can extract from the memory MEM the brightness value (e.g., grayscale 208 (208G)) of the light emitted at the location furthest from the data drive circuit 130 due to the voltage drop of the drive voltage EVDD, based on the image pattern, and determine it as the reference grayscale value of the compensated data voltage Vdata_comp.

[0190] In other words, if white data of grayscale 255 (255G) is applied, the sub-pixel SP furthest from the data driving circuit 130 will exhibit grayscale 208 (208G). Therefore, taking into account the voltage drop of the driving voltage EVDD, a second compensation gain can be applied so that the compensated data voltage Vdata_comp of grayscale 208 (208G) is uniformly applied to all sub-pixels SP of the display panel 110.

[0191] In other words, applying a second compensation gain of 208 / 256 causes the compensated data voltage Vdata_comp of grayscale 208 (208G) to be applied to the sub-pixel SP in the display panel 110 near the data driving circuit 130. A second compensation gain of 232 / 256 can be applied so that the compensated data voltage Vdata_comp of grayscale 232 (232G) is applied to the middle region, and a second compensation gain of 256 / 256 can be applied so that the compensated data voltage Vdata_comp of grayscale 255 (255G) is applied to the region away from the data driving circuit 130.

[0192] As a result, due to the voltage drop of the driving voltage EVDD, the compensated data voltage Vdata_comp of grayscale 208 (208G) reaches the sub-pixel SP located in the middle region and far away from the data driving circuit 130, just like the sub-pixel SP close to the data driving circuit 130, so that the entire display panel 110 emits light with the same reference brightness Lref (580 nit).

[0193] In this case, the reference brightness Lref, which is determined by inputting an image pattern or can be changed by settings, is presented by the display panel 110 via a compensated data voltage Vdata_comp. For example, the reference brightness Lref can be selected (e.g., by the manufacturer, user, etc.).

[0194] Furthermore, the display device 100 of this disclosure can determine the compensated data voltage Vdata_comp by taking into account the intermediate grayscale image data DATA (if input), as well as the white data of grayscale 255 (255G) and the black data of grayscale 0.

[0195] Reference Figure 11 In the display device 100 according to the present disclosure, image data DATA corresponding to an intermediate gray level between gray level 0 and gray level 255 can be input.

[0196] For example, a frame of image data DATA may include black regions with grayscale 0 and white regions with grayscale 255, and may have an average grayscale value equal to 32 (e.g., Figure 8 The value is "32G".

[0197] Therefore, the data driving circuit 130 can be operated such that a grayscale 255 (255G) data voltage Vdata is applied to the white area, and a grayscale 0 (0G) data voltage Vdata is applied to the black area. However, the driving voltage EVDD transmitted through the driving voltage line DVL extending from the data driving circuit 130 to the display panel 110 experiences a voltage drop due to line resistance. Therefore, the luminous brightness decreases as one moves away from the data driving circuit 130.

[0198] For example, a grayscale 255 (255G) data voltage Vdata can be applied to a white area formed near the data driving circuit 130, and in the white area, the sub-pixel SP closest to the data driving circuit 130 can present a brightness of 640 nits, and due to the voltage drop of the driving voltage EVDD, the sub-pixel SP farthest from the data driving circuit 130 in the white area can present a brightness of 630 nits.

[0199] Since the data voltage Vdata of grayscale 0 (0G) is applied to the black area formed at the position furthest from the data driving circuit 130, the black area can present a brightness of 0 nits.

[0200] Because of the white and black areas, the average gray level of a frame identified can be equal to 32.

[0201] In this case, since image non-uniformity occurs in the white area, the compensation data voltage Vdata_comp can be applied only to the white area to compensate for the voltage drop of the drive voltage EVDD, while the compensation data voltage Vdata_comp for grayscale 0 (0G) can be applied to the black area.

[0202] In other words, for an image pattern with intermediate grayscale, the display device 100 can apply a position-compensated data voltage Vdata_comp to the second direction of the white area of ​​the display panel 110, taking into account the voltage drop of the driving voltage line DVL, based on the image pattern with intermediate grayscale, thereby uniformly compensating the luminance of the display panel 110 to the reference luminance Lref.

[0203] Assuming the second compensation gain is used Figure 8 In the case of image data in the middle of the table (e.g., 32 (32G)), the timing controller 140 can extract the brightness value (e.g., grayscale 230 (230G)) of the light emitted at the position furthest from the data drive circuit 130 due to the voltage drop of the drive voltage EVDD from the memory MEM according to the image pattern, and determine it as the reference grayscale value of the compensated data voltage Vdata_comp.

[0204] In other words, when 32 (32G) of image data is applied, if the sub-pixel SP furthest from the data driving circuit 130 presents 230 (230G), control can be performed to apply a compensated data voltage Vdata_comp of grayscale 230 (230G) to all sub-pixels SP of the display panel 110, taking into account the voltage drop of the driving voltage EVDD.

[0205] In other words, a second compensation gain of 230 / 256 is applied, such that the compensated data voltage Vdata_comp of grayscale 230 (230G) is applied to the sub-pixel SP in the display panel 110 near the data driving circuit 130. A second compensation gain of 236 / 256 is applied, such that the compensated data voltage Vdata_comp of grayscale 236 (236G) is applied to the middle region where the white and black regions meet.

[0206] The compensation voltage Vdata_comp for grayscale 0 (0G) can be applied to the black area where black data with grayscale 0 has been applied.

[0207] As a result, the compensated data voltage Vdata_comp of grayscale 230 (230G) reaches the sub-pixel SP located in the white area, causing the white area in the display panel 110 to emit light with the same reference brightness Lref (580nit).

[0208] In this case, the reference brightness Lref, which is determined by inputting an image pattern or can be changed by settings, is provided by the display panel 110 via a compensated data voltage Vdata_comp. For example, the reference brightness Lref can be selected (e.g., by the manufacturer, user, etc.).

[0209] Thus, considering that the voltage drop of the driving voltage EVDD varies depending on the position of the data driving circuit 130 in the first direction in which the data driving circuit 130 is arranged, the display device 100 of this disclosure can determine the first compensation data voltage.

[0210] Then, the display device 100 can determine the second compensated data voltage by taking into account the voltage drop of the drive voltage EVDD, which varies depending on the resistive component of the drive voltage line DVL in the second direction in which the drive voltage line DVL extends in the display panel 110.

[0211] Therefore, voltage drops in the first direction and voltage drops in the second direction of the display panel 110 can be considered to mitigate brightness non-uniformity depending on the two-dimensional position of the sub-pixel SP.

[0212] Figure 12 This is a view illustrating an example of enhancing brightness uniformity by compensating for a data voltage drop through the application of a driving voltage that varies depending on the two-dimensional position of a sub-pixel in a display panel in a display device, according to an embodiment of the present disclosure.

[0213] Reference Figure 12 Considering that the voltage drop of the driving voltage EVDD varies depending on the position of the data driving circuit 130 corresponding to the first direction of the display panel 110, and that the voltage drop of the driving voltage EVDD varies depending on the resistance component of the driving voltage line DVL in the second direction of the display panel 110, the display device 100 according to the embodiments of the present disclosure can mitigate brightness non-uniformity depending on the two-dimensional position of the sub-pixel SP.

[0214] In particular, considering that the voltage drop of the driving voltage EVDD varies depending on the pattern of the input image data in the second direction of the display panel 110, the display device 100 according to the present disclosure can effectively reduce the brightness non-uniformity depending on the two-dimensional position of the sub-pixel SP.

[0215] Figure 13 This is a flowchart illustrating a display driving method according to an embodiment of the present disclosure.

[0216] Reference Figure 13The display driving method according to embodiments of the present disclosure may include: step S100: determining a first compensation data voltage by applying a first compensation gain according to a position corresponding to a data driving circuit 130 in a first direction of the display panel 110; step S200: storing a second compensation gain for each position as a lookup table according to an image pattern in a second direction of the display panel 110; step S300: extracting a second compensation gain corresponding to an image pattern in the image data DATA from the lookup table; step S400: determining a second compensation data voltage by applying the extracted second compensation gain to the first compensation data voltage; and step S500: providing the second compensation data voltage to the display panel 110.

[0217] Step S100, which determines the first compensated data voltage based on the position of the data driving circuit 130 in the first direction of the display panel 110, is a process in which the area overlapping with the data driving circuit 130 and the area not overlapping with the data driving circuit 130 are divided in the first direction in which the data driving circuit 130 is arranged, and the compensated data voltage Vdata_comp is determined taking into account that the driving voltage EVDD depends on the voltage drop at the position.

[0218] Step S200, which stores the second compensation gain of each position as a lookup table based on the image pattern in the second direction of the display panel 110, is performed as follows: the second compensation gain of the data voltage Vdata is stored in memory in the form of a lookup table based on the grayscale of the input image in the second direction along which the driving voltage line DVL of the display panel 110 extends. Step S200 can be performed during the manufacture of the display device 100 or during the driving of the display device 100.

[0219] The step S300 of extracting the second compensation gain corresponding to the image pattern of the image data DATA from the lookup table is as follows: determining the gray level of the image data DATA input to the display device 100, and extracting the second compensation gain for each position of the sub-pixel SP from the lookup table stored in the memory MEM based on the gray level of the image data DATA.

[0220] The step S400 of determining the second compensation data voltage by applying the extracted first compensation gain to the first compensation data voltage is as follows: the final compensation data voltage Vdata_comp is determined by considering the first compensation data voltage in the first direction where the data drive circuit 130 is arranged and the second compensation data voltage in the second direction where the drive voltage line DVL extends.

[0221] Step S500, which supplies the second compensation data voltage to the display panel 110, is a process in which the compensation data voltage Vdata_comp, determined by taking into account the two-dimensional position of the sub-pixel SP, is supplied to the display panel 110.

[0222] Therefore, considering that the voltage drop of the driving voltage EVDD varies depending on the position of the data driving circuit 130 corresponding to the first direction of the display panel 110 and the voltage drop of the driving voltage EVDD varies depending on the resistance component of the driving voltage line DVL in the second direction of the display panel 110, the display driving method according to the embodiments of the present disclosure can alleviate the brightness non-uniformity depending on the two-dimensional position of the sub-pixel SP.

[0223] The aforementioned implementation methods are briefly described below.

[0224] According to an embodiment of the present disclosure, a display device 100 includes: a display panel 110, the display panel 110 including a plurality of sub-pixels SP and a plurality of drive voltage lines DVL providing drive voltages to the plurality of sub-pixels SP; a plurality of data drive circuits 130 configured to provide data voltages to the display panel 110; and a timing controller 140 configured to control the plurality of data drive circuits 130 for supplying compensated data voltages according to the position of the display panel 110, wherein the compensated data voltages have a first compensation gain for at least some sub-pixels, the first compensation gain depending on the position of the plurality of data drive circuits 130 in a first direction corresponding to the display panel, and have a second compensation gain for at least some sub-pixels, the second compensation gain depending on the distance from the plurality of data drive circuits 130 in a second direction of the display panel 110.

[0225] The first direction can be the direction in which multiple data drive circuits are arranged.

[0226] The compensated data voltage can vary depending on the overlapping regions corresponding to the plurality of data driving circuits and the non-overlapping regions not corresponding to the plurality of data driving circuits.

[0227] The driving voltage line DVL located in the overlapping region Area1 can have a linear structure, while the driving voltage line DVL located in the non-overlapping region Area2 can have a curved structure.

[0228] A first compensation gain with a low value can be applied to sub-pixels SP located in the overlapping area Area1 among the multiple sub-pixels SP, and a second compensation gain with a high value can be applied to sub-pixels SP located in the non-overlapping area Area2 among the multiple sub-pixels SP.

[0229] The second compensation gain can be set to vary depending on the position of the sub-pixel SP relative to the average gray level of the input image data DATA.

[0230] The second compensation gain can be a lookup table stored in memory MEM.

[0231] The compensated data voltage can be determined by taking into account the maximum voltage drop (e.g., maximum voltage drop) that may be expected for the data line in the sub-pixel SP farthest from the plurality of data driving circuits 130 relative to the average gray level of the image data DATA.

[0232] The compensated data voltage can represent a predetermined or referenced brightness.

[0233] The second compensation gain can be applied to sub-pixels located in non-black grayscale regions among multiple sub-pixels.

[0234] A display driving method according to an embodiment of the present disclosure may include: determining a first compensation data voltage by applying a first compensation gain according to a position corresponding to a data driving circuit 130 in a first direction of the display panel 110; storing a second compensation gain for each position as a lookup table according to an image pattern in a second direction of the display panel 110; extracting a second compensation gain according to an image pattern based on input image data DATA from the lookup table; determining a second compensation data voltage by applying the extracted second compensation gain to the first compensation data voltage; and providing the second compensation data voltage to the display panel 110.

[0235] The first direction can be the direction in which multiple data drive circuits are arranged.

[0236] The second direction can be the direction in which the drive voltage line DVL extends to provide the drive voltage EVDD to the display panel 110.

[0237] The first compensation data voltage may vary depending on the overlapping regions corresponding to the plurality of data driving circuits and the non-overlapping regions not corresponding to the plurality of data driving circuits.

[0238] A first compensation gain with a low value can be applied to sub-pixels SP located in the overlapping area Area1 among the multiple sub-pixels SP, and a second compensation gain with a high value can be applied to sub-pixels SP located in the non-overlapping area Area2 among the multiple sub-pixels SP.

[0239] The second compensation gain can be set to vary depending on the position of the sub-pixel SP relative to the average gray level of the input image data DATA.

[0240] The second compensation data voltage can be determined by taking into account the maximum expected voltage drop (e.g., maximum voltage drop) of SP in the sub-pixel farthest from the plurality of data driving circuits 130 relative to the average gray level of the image data DATA.

[0241] The second compensation data voltage can represent a predetermined or selected reference brightness.

[0242] The second compensation gain can be applied to sub-pixels located in non-black grayscale regions among multiple sub-pixels.

[0243] The above description is intended to enable any person skilled in the art to make and use the technical ideas of this disclosure, and is provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this disclosure. The above description and drawings provide examples of the technical ideas of this disclosure and are for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical ideas of this disclosure. Therefore, the scope of this disclosure is not limited to the embodiments shown, but should be accorded the widest scope consistent with the claims. The scope of protection of this disclosure should be determined by the appended claims, and all technical ideas within their equivalent scope should be interpreted as being included within the scope of this disclosure.

Claims

1. A display device, comprising: The display panel includes multiple sub-pixels and multiple driving voltage lines that provide driving voltages to the multiple sub-pixels; Multiple data driving circuits are configured to provide data voltage to the display panel; as well as A timing controller is configured to control the plurality of data drive circuits for supplying compensation data voltage based on their position on the display panel. The compensated data voltage has a first compensation gain for a group of first sub-pixels and a second compensation gain for a group of second sub-pixels. The first compensation gain varies based on the position of the plurality of data driving circuits corresponding to a first direction of the display panel, and the second compensation gain varies based on the distance from the plurality of data driving circuits in a second direction of the display panel. The first compensation gain varies based on a first region overlapping with the plurality of data driving circuits and a second region between the plurality of data driving circuits.

2. The display device according to claim 1, wherein, The first direction is the direction in which the plurality of data driving circuits are arranged.

3. The display device according to claim 1, wherein, The multiple driving voltage lines located in the first region have a linear structure, and The multiple drive voltage lines located in the second region have a bent structure.

4. The display device according to claim 1, wherein, The first compensation gain is applied to the sub-pixels located in the first region using a first value, and the first compensation gain is applied to the sub-pixels located in the second region using a second value, the second value being greater than the first value.

5. The display device according to claim 1, wherein, The second compensation gain is set to vary based on the position of at least some of the second sub-pixels and the average gray level of the input image data.

6. The display device according to claim 5, wherein, The second compensation gain is stored in a lookup table stored in memory.

7. The display device according to claim 5, wherein, The compensated data voltage is determined based on the voltage drop associated with the sub-pixel furthest from the plurality of data driving circuits and the average gray level based on the image data.

8. The display device according to claim 1, wherein, The compensated data voltage is associated with the selected reference brightness.

9. The display device according to claim 1, wherein, The second compensation gain is applied to sub-pixels located in non-black grayscale regions.

10. A display device, comprising: Data drive circuit, and The display panel includes: The first sub-pixel is coupled to the data line of the data driving circuit; The second sub-pixel is coupled to the data line, and the first sub-pixel is located between the data driving circuit and the second sub-pixel; The driving voltage line is coupled to the first sub-pixel and the second sub-pixel; and The third sub-pixel is coupled to a second data line adjacent to the data line, and is also coupled to a second driving voltage line adjacent to the driving voltage line; In the image frame, the data line, during operation: A first compensated data voltage is applied to the first sub-pixel, the first compensated data voltage being generated based on a first value of the second compensated gain; and A second compensated data voltage is applied to the second sub-pixel. This second compensated data voltage is generated based on a second value of the second compensation gain, which is greater than the first value. Wherein the first sub-pixel and the second sub-pixel are in a first region overlapping with the data driving circuit, and the third sub-pixel is in a second region between the data driving circuit and a second data driving circuit adjacent to the data driving circuit; and The data cable, during operation: A third compensated data voltage is supplied to the third sub-pixel. The third compensated data voltage is generated based on a first compensated gain, and the first compensated gain in the second region is greater than the first compensated gain in the first region.

11. The display device according to claim 10, further comprising: A memory that stores the first value and the second value; A compensation circuit, in operation, generates compensated image data associated with the image frame based on the first value and the second value, and outputs the compensated image data to the data driving circuit; as well as A digital-to-analog converter, in operation, generates a first compensated data voltage and a second compensated data voltage based on the compensated image data.

12. The display device of claim 11, wherein, in operation, the second compensation gain is determined based on a voltage drop of a driving voltage supplied through the driving voltage line, the voltage drop being determined according to the position of the driving voltage line in a second direction in which it extends.

13. The display device of claim 12, wherein the compensation circuit, in operation, compensates for a deviation of the drive voltage associated with the position, the compensation being based on a value of the second compensation gain stored in the memory.

14. The display device of claim 10, wherein the first value and the second value are generated as a fraction of grayscale associated with white.

15. The display device of claim 14, wherein the fraction decreases with increasing proximity to the data driving circuit.

16. A display driving method, comprising: A first compensated data voltage is applied to a first sub-pixel, the first compensated data voltage being generated based on a first value of a second compensated gain and being applied via a first data line, the first value being associated with a first distance from the data driving circuit, the first sub-pixel being in an image frame; as well as A second compensated data voltage is applied to a second sub-pixel in the same image frame. This second compensated data voltage is generated based on a second value of the second compensation gain and is applied via the first data line. The second value is associated with a second distance from the data driving circuit and is greater than the first value. A third compensated data voltage is applied to a third sub-pixel in the image frame via a second data line adjacent to the first data line. The third compensated data voltage is generated based on the value of a first compensated gain, which is associated with a second region where the third sub-pixel is located. The second region is between the data driving circuit and a second data driving circuit adjacent to the data driving circuit. The first sub-pixel is located in a first region overlapping with the data driving circuit. The value is greater than another value associated with the first region.

17. The display driving method according to claim 16, further comprising: Image data associated with the image frame is generated based on the first value and the second value; The compensated image data is output to the data driving circuit; as well as The first compensated data voltage and the second compensated data voltage are generated based on the compensated image data.

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