System and method for centralized address capture circuitry

Abstract

The present disclosure relates to systems and methods for centralized address capture circuitry. A memory device includes a command interface configured to receive a command from a host device via a plurality of command address bits. The memory device also includes a centralized command decoder configured to receive the command and determine whether the command matches a bit pattern corresponding to a plurality of command types, such as a write command and a read command. The centralized command decoder is also configured to assert a latch signal in response to the command matching the bit pattern. The memory device also includes a latch configured to capture the plurality of command address bits based at least in part on the assertion of the latch signal.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the field of semiconductor devices. More specifically, embodiments of the present disclosure relate to a centralized command decoder for read and write commands of a memory device. Background Art

[0002] Semiconductor devices (e.g., memory devices) utilize shifting of timing and data signals, data strobes, commands, and / or other signals to perform operations. Command address bits are used to decode and capture commands. Some memory devices utilize two-cycle commands, such as write (WR), write auto-precharge (WRA), read (RD), and read auto-precharge (RDA) commands, which use common address bits to be captured in the first cycle and / or the second cycle based on the decoded command. Some memory devices utilize a separate decoder for each command, which may utilize excessive circuitry, have excessive cost, and / or have excessive size for the memory device.

[0003] Embodiments of the present disclosure may be directed to one or more of the problems set forth above. Summary of the invention

[0004] In one aspect, the present disclosure provides a memory device comprising: a command interface configured to receive a command from a host device via a plurality of command address bits; and a centralized command decoder configured to: receive the command; determine whether the command matches a bit pattern corresponding to a plurality of command types, wherein the plurality of command types include a write command and a read command; and in response to the command matching the bit pattern: assert a latch signal; and transmit at least one bit of the command that is not in the bit pattern; and a combinational circuit system configured to output a command signal based on the latch signal and the at least one bit of the command.

[0005] In another aspect, the present disclosure provides a memory device comprising: a command interface configured to receive a command from a host device via a plurality of command address bits; and a centralized command decoder configured to: receive the command; determine whether the command matches a bit pattern corresponding to a first command type and a second command type; and in response to the command matching the bit pattern, assert a latch signal; and a combinational circuit system configured to combine the latch signal and bits of the command that are not in the bit pattern and configured to output a command signal corresponding to the command.

[0006] In yet another aspect, the present disclosure provides a method for capturing bits in a memory device, comprising: receiving a plurality of command address bits corresponding to a command at the memory device; decoding a subset of the plurality of command address bits in a command decoder to determine whether the command contains a bit pattern corresponding to a command set; and based at least in part on determining that the command corresponds to the bit pattern: transmitting a latch signal from the command decoder to a latch, the latch being configured to capture at least some of the plurality of command address bits based on the latch signal; and transmitting bits of the command from the command decoder to a combinational circuit system, wherein the bits are different between at least two commands in the command set; and generating a command signal in the combinational circuit system based on the latch signal and the bits of the command. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a simplified block diagram illustrating certain features of a memory device according to an embodiment of the present disclosure;

[0008] Figure 2 is a table of encoded commands having a common bit pattern between commands according to an embodiment of the present disclosure; and

[0009] Figure 3 is a block diagram of circuitry to decode and capture common bit patterns using a centralized command decoder according to an embodiment of the present disclosure.

[0010] Figure 4 is a block diagram of circuitry for combining a decoded signal with corresponding distinguished bits using combining circuitry to form a corresponding decoded command according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0011] One or more specific embodiments will be described below. In order to provide a brief description of these embodiments, not all features of the actual implementation will be described in this specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, many implementation-specific decisions must be made to achieve the specific goals of the developer, such as consistency with system-related and enterprise-related constraints, which may vary from one implementation to another. In addition, it should be understood that such development efforts may be complex and time-consuming, but will be a routine of design, construction, and manufacturing undertaken by those skilled in the art who benefit from this disclosure.

[0012] As previously described, some memory devices utilize a separate decoder for each command, which can increase the pipeline circuitry, cost, and size of the memory device. To reduce the necessity of this additional pipeline circuitry, some memory devices may fold certain circuitry (e.g., a command decoder) to decode a single result from a common bit pattern that is common between several commands to mark that one of the several commands has been received. In other words, any number of commands share a pattern in all but one (or more) of the command address bits. The decoder determines that one of the several commands has been received and captures the common command bits in a second cycle. The remaining bits that differ between the several commands (e.g., CA <4> ) may also be captured and used to distinguish the number of commands downstream of the second cycle bit. For example, a circuit system that may normally receive only decoded commands in an embodiment with a decoder for each command type may instead receive a decoded signal indicating that one of the commands corresponding to the command decoder has been received. The circuit system may receive one or more bits and combine those bits with the decoded signal. For example, if the circuit system corresponds to 0s and 1s in the bits transmitted downstream, the circuit system may invert the 0 using an inverter and combine the decoded signal, inverted 0 bits (i.e., 1), and 1 bits using an AND gate to output a signal that is logically equivalent to the individually decoded commands.

[0013] Turning now to the accompanying drawings, Figure 1 is a simplified block diagram illustrating certain features of memory device 10. Specifically, Figure 1 The block diagram of FIG. 1 is a functional block diagram illustrating certain functionality of the memory device 10. According to one embodiment, the memory device 10 may be a fifth generation double data rate synchronous dynamic random access memory (DDR5 SDRAM) device. Various features of the DDR5 SDRAM enable reduced power consumption, more bandwidth, and more storage capacity than previous generations of DDR SDRAM.

[0014] The memory device 10 may include several memory banks 12. The memory banks 12 may be, for example, DDR5 SDRAM memory banks. The memory banks 12 may be disposed on one or more chips (e.g., SDRAM chips) arranged on dual in-line memory modules (DIMMs). It should be understood that each DIMM may include several SDRAM memory chips (e.g., x4, x8, or x16 memory chips). Each SDRAM memory chip may include one or more memory banks 12. The memory device 10 represents a portion of a single memory chip (e.g., an SDRAM chip) having several memory banks 12. For DDR5, the memory banks 12 may be further arranged to form groups. For example, for an 8-gigabit (Gb) DDR5 SDRAM, the memory chip may include 16 memory banks 12, arranged in 8 groups, each group including 2 memory banks. For example, for a 16Gb DDR5 SDRAM, the memory chip may include 32 memory banks 12, arranged in 8 groups, each group including 4 memory banks. Various other configurations, organizations, and sizes of memory banks 12 on memory device 10 may be utilized depending on the application and design of the overall system.

[0015] The memory device 10 may include a command interface 14 and an input / output (I / O) interface 16. The command interface 14 is configured to provide a plurality of signals (e.g., signal 15) from an external device (not shown), such as a processor or controller. The processor or controller may provide various signals 15 to the memory device 10 to facilitate the transmission and reception of data to be written to or read from the memory device 10.

[0016] As will be appreciated, the command interface 14 may include several circuits, such as a clock input circuit 18 and a command address input circuit 20, to ensure proper handling of the signal 15. The command interface 14 may receive one or more clock signals from an external device. In general, a double data rate (DDR) memory utilizes a differential pair of system clock signals, referred to herein as a true clock signal (Clk_t) and a complementary clock signal (Clk_c). The positive clock edge of DDR refers to the point where the rising true clock signal Clk_t crosses the falling complementary clock signal Clk_c, while the negative clock edge indicates the transition of the falling true clock signal Clk_t and the rise of the complementary clock signal Clk_c. Commands (e.g., read commands, write commands, etc.) are typically input at the positive edge of the clock signal, and data is transmitted or received on both the positive and negative clock edges.

[0017] The clock input circuit 18 receives the true clock signal (Clk_t / ) and the complementary clock signal (Clk_c) and generates an internal clock signal CLK. The internal clock signal CLK is supplied to an internal clock generator 30, such as a delay locked loop (DLL) circuit. The internal clock generator 30 generates a phase-controlled internal clock signal LCLK based on the received internal clock signal CLK. The phase-controlled internal clock signal LCLK is supplied to, for example, the I / O interface 16 and is used as a timing signal for determining the output timing of the read data.

[0018] The internal clock signal CLK may also be provided to various other components within the memory device 10 and may be used to generate various additional internal clock signals. For example, the internal clock signal CLK may be provided to a command decoder 32. The command decoder 32 may receive command signals from a command bus 34 and may decode the command signals to provide various internal commands. For example, the command decoder 32 may provide the command signal to the internal clock generator 30 via a bus 36 to coordinate the generation of the phase-controlled internal clock signal LCLK. The phase-controlled internal clock signal LCLK may be used to clock data, such as through the IO interface 16.

[0019] In addition, the command decoder 32 may decode commands such as read commands, write commands, mode register set commands, activate commands, etc., and provide access to a specific memory bank 12 corresponding to the command via the bus path 40. As will be appreciated, the memory device 10 may include various other decoders, such as row decoders and column decoders, to facilitate access to the memory banks 12. In one embodiment, each memory bank 12 includes a bank control block 22 that provides the necessary decoding (e.g., row decoders and column decoders) and other features, such as timing control and data control, to facilitate execution of commands to and from the memory banks 12.

[0020] The memory device 10 performs operations such as read commands and write commands based on command / address signals received from an external device such as a processor. In one embodiment, the command / address bus may be a 14-bit bus for accommodating command / address signals (CA<13:0>). The command / address signals are clocked to the command interface 14 using clock signals (Clk_t / and Clk_c). The command interface may include a command address input circuit 20 configured to receive and transmit commands to provide access to the memory bank 12 through, for example, a command decoder 32. In addition, the command interface 14 may receive a chip select signal (CS_n). The CS_n signal enables the memory device 10 to process commands on the incoming CA<13:0> bus. Access to a specific bank 12 within the memory device 10 is encoded on the CA<13:0> bus by a command. As previously discussed, the command decoder 32 may include at least one centralized command decoder 48 that decodes multiple commands (e.g., WR, RD, WRA, RDA) using common command address bits when using 2-cycle commands to reduce pipeline redundancy.

[0021] In addition, the command interface 14 may be configured to receive a number of other command signals. For example, a command / address on-die termination (CA_ODT) signal may be provided to facilitate proper impedance matching within the memory device 10. A reset command (RESET_n) may be used to reset the command interface 14, a status register, a state machine, etc., for example, during power-up. The command interface 14 may also receive a command / address inversion (CAI) signal, which may be provided to invert the state of the command / address signal CA<13:0> on the command / address bus. A mirror (MIR) signal may also be provided to facilitate mirroring functionality. Based on the configuration of multiple memory devices in a particular application, the MIR signal may be used to multiplex signals so that they may be swapped for implementing certain routing of signals to the memory device 10. Various signals for facilitating testing of the memory device 10, such as a test enable (TEN) signal, may also be provided. For example, the TEN signal may be used to place the memory device 10 in a test mode for connectivity testing.

[0022] The command interface 14 may also be used to provide an alert signal (ALERT_n) to a system processor or controller for certain errors that may be detected. For example, an alert signal (ALERT_n) may be transmitted from the memory device 10 if a cyclic redundancy check (CRC) error is detected. Other alert signals may also be generated. In addition, the bus and pins used to transmit the alert signal (ALERT_n) from the memory device 10 may be used as input pins during certain operations, such as the connectivity test mode performed using the TEN signal as described above.

[0023] Utilizing the command and timing signals discussed above, data may be sent to and from the memory device 10 by transmitting and receiving data signals 44 via the IO interface 16. More specifically, data may be sent to or retrieved from the memory bank 12 via a data path 46 comprising a plurality of bidirectional data buses. Data IO signals, generally referred to as DQ signals, are generally transmitted and received in one or more bidirectional data buses. For certain memory devices, such as DDR5 SDRAM memory devices, the IO signals may be divided into upper and lower bytes. For example, for a x16 memory device, the IO signals may be divided into upper and lower IO signals (e.g., DQ<15:8> and DQ<7:0>) corresponding to, for example, the upper and lower bytes of the data signals.

[0024] To allow for higher data rates within the memory device 10, certain memory devices, such as DDR memory devices, may utilize a data strobe signal, commonly referred to as a DQS signal. The DQS signal is driven by an external processor or controller that sends data (e.g., for a write command) or by the memory device 10 (e.g., for a read command). For a read command, the DQS signal is actually an additional data output (DQ) signal with a predetermined pattern. For a write command, the DQS signal is used as a clock signal to capture the corresponding input data. Like the clock signals (Clk_t / and Clk_c), the data strobe (DQS) signal may be provided as a data strobe signal (DQS_t / and DQS_c) of a differential pair to provide differential pair signaling during read and write. For certain memory devices, such as DDR5 SDRAM memory devices, the differential pair of DQS signals can be divided into upper data select signals and lower data select signals (e.g., UDQS_t / and UDQS_c; LDQS_t / and LDQS_c), which correspond to, for example, upper bytes and lower bytes of data sent to and from the memory device 10.

[0025] An impedance (ZQ) calibration signal may also be provided to the memory device 10 through the IO interface 16. The ZQ calibration signal may be provided to a reference pin and used to tune the output driver and ODT values ​​by adjusting the pull-up and pull-down resistors of the memory device 10 across variations in process, voltage, and temperature (PVT) values. Because PVT characteristics may affect the ZQ resistor value, the ZQ calibration signal may be provided to the ZQ reference pin for adjusting the resistance to calibrate the input impedance to a known value. As will be appreciated, a precision resistor is generally coupled between the ZQ pin on the memory device 10 and GND / VSS external to the memory device 10. This resistor acts as a reference for adjusting the internal ODT and drive strength of the IO pins.

[0026] In addition, a loopback signal (LOOPBACK) may be provided to the memory device 10 through the IO interface 16. The loopback signal may be used during a test or debug phase to set the memory device 10 into a mode where a signal is looped back through the memory device 10 through the same pin. For example, the loopback signal may be used to set up the memory device 10 to test the data output (DQ) of the memory device 10. The loopback may include both data and strobe or perhaps only the data pin. This is generally intended to monitor the data captured by the memory device 10 at the IO interface 16.

[0027] As will be appreciated, various other components such as power supply circuits (for receiving external VDD and VSS signals), mode registers (for defining various modes of programmable operation and configuration), read / write amplifiers (for amplifying signals during read / write operations), temperature sensors (for sensing the temperature of the memory device 10), etc. may also be incorporated into the memory device 10. Therefore, it should be understood that only the memory device 10 is provided. Figure 1 1 is a block diagram to highlight certain functional features of the memory device 10 to facilitate the subsequent detailed description.

[0028] As previously discussed, the centralized command decoder 48 may be used to decode whether any one of the commands in the command group has been received. For example, the command group may include any command that utilizes the second cycle to capture command address bits. For example, the commands may include at least those commands that receive an address or option in some bits indicating that such bits should be captured (e.g., at least some of CA<13:5>). With the foregoing in mind, Figure 2 Table 50 is shown with six commands 52, 54, 56, 58, 60, 62 that share a common bit 64 that is captured in a first cycle. Decoding any of these commands 52, 54, 56, 58, 60, 62 indicates that additional bits (e.g., any of the bits of CA<13:0>) are to be captured from the command address bus. For example, during the first cycle (e.g., when the chip select signal (CS_n) is low), additional bits (e.g., CA<10:6> or CA<10:5>) are captured from the command address bus. Additionally or alternatively, any of the bits (e.g., CA<13:0>) are captured from the command address bus during the second cycle. Thus, a single centralized command decoder can be used to quickly determine whether to capture a command in a first cycle. Figure 1 The second cycle of Clk_t captures bits from the command address bus for any of the commands. For example, the latch can capture command address bits based on any of the decoded commands 52, 54, 56, 58, 60, 62 and / or the chip select signal (CS_n).

[0029] As shown in Table 50, CS_n may be high for the second cycle of commands 52, 54, 58, 60 and may be low for the second cycle of commands 56, 62. The low value of CS_n in the second cycle indicates that no additional bits are captured from the command address bus corresponding to commands 56, 62. The first command set (e.g., commands 52, 54, 56) may differ from the second command set (e.g., 58, 60, 62) at a single bit (e.g., bit 66). In certain embodiments, the first command set may be a write command set (e.g., write command type) and the second command set may be a read command set (e.g., read command type). For example, command 52 may be a write command, command 54 may be a write auto-precharge command, and command 56 may be a write non-target (NT) command, a read command, a read auto-precharge command, or a read NT command. In some embodiments, fewer commands, more commands, or different commands may be centralized into the centralized command decoder 48 as long as some bits are common to the centralized commands. In some embodiments, the number of different bits (e.g., bit 66) may be greater than a single bit, such as 2 or 3 bits. Additionally, to maintain separation between commands, a bit (e.g., bit 66) may be sent downstream to distinguish commands 52, 54, 56, 58, 60, 62 from each other later in a pipeline where a single decoded signal from centralized command decoder 48 is logically combined with the bits delivered downstream to downstream circuitry. For example, if the downstream circuitry corresponds to a command having an H value and an L value in the bits delivered downstream, the circuitry may invert the bit using an inverter to correspond to an L value and combine the decoded signal, the inverted bit (i.e., previously L), and the H bit using an AND gate to output a signal that is logically equivalent to the individual decoded command corresponding to the command.

[0030] Figure 370 is a block diagram of a circuit system for decoding and capturing command address bits using a centralized command decoder. The centralized command decoder 48 receives bits of a first portion 72 of CA bits (e.g., 4 of 13 bits). The centralized command decoder 48 decodes the first portion of an incoming command (e.g., WR, RD, WRA, RDA command) to match a pattern (e.g., HLHH in the corresponding bits of the portion). For example, all but a few (e.g., 1, 2, 3, or more) of the incoming command bits (e.g., bit 66) match a particular bit pattern. The bit pattern may include additional bits and / or signals. For example, the centralized command decoder 48 may receive CS_n 86 to determine whether the latch signal 76 or the decoded signal is to be asserted. When the bit pattern is detected, the centralized command decoder 48 indicates that the incoming command is one of the commands corresponding to the pattern. Furthermore, since commands corresponding to the pattern indicate that additional bits are to be captured from the command bus, centralized command decoder 48 outputs latch signal 76 which generates latch 78 to capture bit (e.g., CA<12:0> or CA<13:0>) 80 in a subsequent (e.g., second) clock cycle.

[0031] The latest value latched in the latch 78 is output as the output column address bit 82. However, since the latch signal 76 output from the centralized command decoder 48 is common to at least two commands, a distinguishing bit 84 may be sent downstream via a transmission line or transmission path to distinguish the command when the resulting operation of the command is to be performed. In some embodiments, when the latch signal 76 is asserted, the centralized command decoder 48 may drive the distinguishing bit 84 based on the received value. Otherwise, the centralized command decoder 48 may maintain its output at a predetermined value indicating that the output is not transmitted. Alternatively, the distinguishing bit 84 may be driven by a logic gate that is used to gate its output by ORing the distinguishing bit 84 with the latch signal 76 and ORing the result of the OR gate as the transmitted OR output. Although the distinguishing bit 84 is shown as being transmitted from the centralized command decoder 48, other embodiments of the memory device 10 may derive the distinguishing bit 84 from other locations in the pipeline. For example, the distinguishing bit 84 may be hardwired to a corresponding bit of the incoming portion 72 which may be distinct in the command corresponding to the centralized command decoder 48 .

[0032] Figure 41 is a block diagram 100 of a circuit system for combining a decoded signal with a corresponding discrimination bit to form a corresponding decoded command using a combinational circuit system. Command circuit system 102 may include combinational circuit system 104 and may receive a decoded command and output a command signal 106. For example, combinational circuit system 104 receives a decoded signal (e.g., latch signal 76) output from a centralized command decoder 48 and receives discrimination bit 84 from centralized command decoder 48. Combinational circuit system 104 may combine latch signal 76 and discrimination bit 84 and output a command signal 106 that is logically equivalent to the decoded command associated with latch signal 76 and / or discrimination bit 84. For example, command signal 106 output by combinational circuit system 104 may correspond to a write command, a write auto-precharge command, a write NT command, a read command, a read auto-precharge command, or a read NT command. In some embodiments, combinational circuit system 104 and / or command circuit system 102 may output fewer commands, more commands, or different commands. In some embodiments, combinational circuitry 104 may include any number of logic gates (e.g., AND gates, NAND gates) and / or any number of inverters. For example, if command circuitry 102 corresponds to a command having an H value and an L value in discrimination bit 84, combinational circuitry 104 may invert the bit corresponding to the L value using an inverter and use a gate combination to latch signal 76, the inverted bit, and the bit corresponding to the H value to output command signal 106.

[0033] Although various modifications and alternative forms may occur in the present disclosure, specific embodiments have been shown by way of example in the accompanying drawings and described in detail herein. However, it should be understood that the present disclosure is not intended to be limited to the specific forms disclosed. In fact, the present disclosure is intended to cover all modifications, equivalents and alternatives that fall within the spirit and scope of the present disclosure as defined by the appended claims.

[0034] The techniques presented and claimed herein are cited and applied to substantial objects and specific examples of a practical nature that improve the art in a demonstrable manner and are therefore not abstract, intangible, or purely theoretical. In addition, if any claim appended at the end of this specification contains one or more elements designated as "means for [performing] [a function] ..." or "steps for [performing] [a function] ...", it is expected that such elements should be interpreted in accordance with 35 U.S.C. 112(f). However, for any claim containing elements designated in any other manner, it is expected that such elements will not be interpreted in accordance with 35 U.S.C. 112(f).

Claims

1. A memory device, comprising: a command interface configured to receive commands from a host device via a plurality of command address bits; and A centralized command decoder configured to: receiving the command; determining whether the command matches a bit pattern corresponding to a plurality of command types, wherein the plurality of command types include a write command and a read command; and In response to the command matching the bit pattern: Assert the latch signal; and transmitting at least one bit of the command that is not in the bit pattern; and Combinatorial circuitry is configured to output a command signal based on the latch signal and the at least one bit of the command.

2. The memory device of claim 1 , comprising a latch configured to capture the plurality of command address bits, wherein the latch is configured to capture the plurality of command address bits in a subsequent cycle of the system clock after a cycle of the system clock used to receive the command.

3. The memory device of claim 1, wherein the plurality of command types include a write auto-precharge command and a read auto-precharge command, and the command is the write command.

4. The memory device of claim 1, wherein the plurality of command types include a write auto-precharge command and a read auto-precharge command, and the command is the read command.

5. The memory device of claim 1, wherein the plurality of command types include a write auto-precharge command and a read auto-precharge command, and the command is the write auto-precharge command.

6. The memory device of claim 1, wherein the plurality of command types include a write auto-precharge command and a read auto-precharge command, and the command is the read auto-precharge command.

7. The memory device of claim 1, comprising an issue path configured to issue the at least one bit of the command that is not in the bit pattern down a pipeline to enable the memory device to distinguish between the multiple command types.

8. The memory device of claim 7, wherein the bit is different between the read command and the write command.

9. A memory device comprising: a command interface configured to receive commands from a host device via a plurality of command address bits; and A centralized command decoder configured to: receiving the command; determining whether the command matches a bit pattern corresponding to a first command type and a second command type; and in response to the command matching the bit pattern, asserting a latch signal; and Combinatorial circuitry is configured to combine the latch signal and bits of the command that are not in the bit pattern and to output a command signal corresponding to the command.

10. The memory device of claim 9, comprising a latch configured to capture the plurality of command address bits based at least in part on assertion of the latch signal, wherein the latch is configured to capture the plurality of command address bits in a subsequent cycle of the system clock after a cycle of the system clock used to receive the command.

11. The memory device of claim 9, wherein the first command type is a read command type.

12. The memory device of claim 11, wherein the first command type comprises read and read auto-precharge commands.

13. The memory device of claim 9, wherein the second command type is a write command type.

14. The memory device of claim 13, wherein the second command type comprises write and write auto-precharge commands.

15. The memory device of claim 13, comprising a transmit line configured to transmit the bits of the command that are not in the bit pattern, wherein the bits are different between the first command type and the second command type.

16. A method of capturing bits in a memory device, comprising: receiving a plurality of command address bits corresponding to a command at the memory device; decoding a subset of the plurality of command address bits in a command decoder to determine whether the command contains a bit pattern corresponding to a command set; and Based at least in part on determining that the command corresponds to the bit pattern: transmitting a latch signal from the command decoder to a latch, the latch configured to capture at least some of the plurality of command address bits based on the latch signal; and transmitting a bit of the command from the command decoder to combinatorial circuitry, wherein the bit is different between at least two commands in the command set; and A command signal is generated in the combinatorial circuitry based on the latch signal and the bits of the command.

17. The method of claim 16, wherein the command set includes a write command and a write auto-precharge command.

18. The method of claim 16, wherein the command set includes a read command and a read auto-precharge command.

19. The method of claim 16, wherein the command signal corresponds to the command but not to an entire command set.

20. The method of claim 16, wherein receiving the plurality of command address bits comprises capturing a first portion of the plurality of command address bits in one cycle of a system clock and capturing a second portion of the plurality of command address bits in a subsequent cycle of the system clock after the cycle of the system clock.

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