A low-power negative capacitance field effect transistor for unidirectional electric field and a preparation method and application thereof

Abstract

The application relates to a low-power negative capacitance field effect transistor for unidirectional electric field and a preparation method thereof, and belongs to the field of microelectronic devices. The negative capacitance field effect transistor provided by the application uses a ferroelectric thin film material with multiple-stage negative capacitance effect as a gate dielectric layer, thereby not only overcoming the problem that a traditional negative capacitance field effect transistor can only work under alternating working voltage, but also reducing the polarization reversal barrier and further reducing the power consumption of the transistor. Compared with similar devices, the application has the outstanding advantages of low power consumption, small hysteresis and high process compatibility, and has important academic and application values in the field of microelectronic devices.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of microelectronic devices, in particular to a low-power negative-capacitance field effect transistor for unidirectional electric field and a preparation method thereof and application thereof in microelectronics. BACKGROUND

[0002] In the post-Moore era, the feature size of chips is continuously reduced, and the integration and performance are continuously improved, but the power consumption problem is increasingly serious, and has become a key factor restricting the further improvement of chip performance. For traditional CMOS devices, because of the existence of Boltzmann electron distribution limit, the theoretical lower limit of subthreshold swing (SS) is 60 mV / dec. In order to further reduce the power consumption of the chip, it is necessary to reduce the subthreshold swing of the device as much as possible. Therefore, how to effectively break through the Boltzmann electron distribution limit has become a key scientific problem in the field.

[0003] For this reason, people have proposed various new low-power transistors such as quantum tunneling transistors, two-dimensional material-based transistors, and negative capacitance field effect transistors (NC-FET). Among them, NC-FET has attracted much attention because of its low power consumption, process compatibility and other advantages. Specifically, by using ferroelectric thin film material with negative capacitance effect as gate dielectric layer, the amplification of gate voltage can be realized without changing the channel transport mechanism of traditional field effect transistor, and the subthreshold slope (SS) can be reduced to below 60 mV / dec, which significantly reduces the power consumption of the transistor and circuit.

[0004] Although NC-FET has good application potential, NC-FET uses the polarization charge released by the polarization reversal of ferroelectric material to realize voltage amplification, which fundamentally leads to the fact that NC-FET needs alternating voltage to work normally and causes serious hysteresis effect, which seriously restricts the practical application of NC-FET. In addition, because the free energy barrier of ferroelectric bipolar switching is generally high, it requires a large external voltage for polarization switching, so the gate voltage amplification and the reduced power consumption are limited.

[0005] Therefore, how to break through the fixed limitation of bipolar reversal of ferroelectric material, reduce the polarization reversal barrier of ferroelectric material, and overcome the dependence of NC-FET on alternating working voltage is a problem that researchers in the field urgently need to solve. SUMMARY

[0006] In view of the above, the application provides a low-power negative capacitance field effect transistor for unidirectional electric field and a preparation method thereof.

[0007] In order to achieve the above-mentioned purpose, the application provides the following technical scheme.

[0008] A low-power negative capacitance field effect transistor for unidirectional electric field comprises a substrate, a channel layer formed on the substrate, a buffer layer, a source region and a drain region formed on the channel layer, a gate dielectric layer formed on the buffer layer, and a gate electrode formed on the gate dielectric layer.

[0009] The source region and the drain region are respectively arranged on two sides of the buffer layer, and a source electrode and a drain electrode are respectively formed on the source region and the drain region.

[0010] The low-power negative capacitance field effect transistor for unidirectional electric field is as shown in the accompanying drawings. Figure 1

[0011] Optionally, the material of the gate dielectric layer is at least one of PbZr x Ti 1-x O3, BiFeO3, BaTiO3, PbTiO3 and PbZrO3, wherein 0 1 ~10 8 V / m, the number of potential wells is 1-7, the number of potential barriers is 1-5, the height of the potential barrier is 0.0001-50 J·cm -3 , and the thickness of the gate dielectric layer is 1 nm-1000 nm.

[0012] Further, the material of the gate dielectric layer is PbZr x Ti 1-x O3, wherein 0 4 ~10 8 V / m, the number of potential wells is 2-5, the number of potential barriers is 1-3, the height of the potential barrier is 0.001-3 J·cm -2 , and the thickness of the gate dielectric layer is 1 nm-200 nm.

[0013] ​Furthermore, the absolute value of the working electrical signal of the gate electrode is 0.01~5 V, the frequency is 50~3 GHz, and the electrical signal is unidirectional or alternating positive and negative signals.

[0014] The working electrical signal of the gate electrode is a unidirectional or alternating electrical pulse signal. The absolute value of the pulse signal is 0.1~4 V and the frequency is 1 kHz~1 GHz. The electrical signal can be a square wave, sine wave, trapezoidal wave or triangular wave. This invention does not limit the type of signal.

[0015] Optionally, the substrate is made of at least one of mica, Si, Ge, SiGe, SOI, GOI, and GaAs.

[0016] Furthermore, the substrate is made of at least one of mica, Si, and Ge.

[0017] Optionally, the channel layer is at least one of ZnO, SnO2, β-Ga2O3, In2O3, SiO2, and GeO2, and the thickness of the channel layer is 10~500 nm.

[0018] Furthermore, the channel layer is at least one of ZnO, SnO2, and β-Ga2O3, wherein the thickness of the channel layer is 10~200 nm.

[0019] Optionally, the gate electrode, source electrode, or drain electrode is at least Au, Ag, Pt, Ti, Ta2O5, TaN, or TiN. x It is one of SrRuO3, and the thickness of the electrode is 1~200 nm.

[0020] Furthermore, the gate electrode, source electrode, or drain electrode is at least one of Au, Pt, Ti, and SrRuO3, wherein the thickness of the electrode is 10~100 nm.

[0021] Optionally, the buffer layer is at least one of CoFe2O4, SrTiO3, PbTiO3, PbZrO3, and HfO2, and the thickness of the buffer layer is 1~200 nm.

[0022] Furthermore, the buffer layer is at least one of CoFe2O4, SrTiO3, and PbTiO3, wherein the thickness of the buffer layer is 1~50 nm.

[0023] It should be noted that a buffer layer of appropriate thickness can provide better growth conditions for the gate dielectric layer (epitaxy) to ensure that a high-quality gate dielectric layer with multiple barrier free energy curves can be grown.

[0024] The second objective of this invention is to claim protection for the method for fabricating the aforementioned low-power negative capacitance field-effect transistor, specifically including the following steps:

[0025] (1) Deposit a channel layer and a buffer layer sequentially on the upper surface of the substrate for later use;

[0026] (2) Deposit a gate dielectric layer on the buffer layer deposited in step (1) using pulsed laser physical deposition, radio frequency magnetron sputtering or atomic layer deposition, for later use;

[0027] (3) Deposit a gate electrode on the gate dielectric layer deposited in step (2), and deposit a source electrode and a drain electrode on the channel layer deposited in step (1), and then perform annealing to obtain the low-power negative capacitance field-effect transistor.

[0028] Optionally, in step (2), the operating conditions for the pulsed laser deposition method are: the vacuum degree of the sample deposition chamber is 1×10⁻⁶. -10 ~1×10 -5 Pa, deposition temperature 200–900 °C, deposition oxygen pressure 0–500 mtorr, laser energy density 0.01–10 J·cm⁻¹ -3 The laser pulse frequency is 1~100 Hz.

[0029] Furthermore, the vacuum level of the sample deposition chamber is 1×10⁻⁶. -10 ~1×10 -5 Pa; deposition temperature: 400–700 °C; deposition oxygen pressure: 10–200 mtorr; laser energy density: 0.02–0.5 J·cm⁻¹ -3 The laser pulse frequency is 10~30 Hz.

[0030] Furthermore, in this invention, the deposition of the channel layer, buffer layer, gate electrode, source electrode, and drain electrode can be carried out by pulsed laser physical deposition, radio frequency magnetron sputtering, or other common practices in the industry, and this invention does not limit the method.

[0031] Furthermore, a third objective of this invention is to seek protection for the application of the aforementioned low-power negative capacitance field-effect transistor or a low-power negative capacitance field-effect transistor prepared by the aforementioned method in microelectronics.

[0032] As can be seen from the above technical solutions, compared with the prior art, the low-power negative capacitance field-effect transistor for unidirectional electric fields, its fabrication method, and its application provided by the present invention have the following superior effects:

[0033] This invention overcomes the alternating operating voltage dependence of NC-FETs by using a ferroelectric thin film material with multi-level negative capacitance characteristics, a free energy curve with multiple potential barriers, and a smaller barrier height as the gate dielectric layer in the NC-FET. This not only enables the device to operate normally under a unidirectional electric field, but also further reduces the power consumption of the device. It has outstanding advantages such as low power consumption, high integration, simple structure, low cost, and process compatibility, and has important application value in the field of microelectronics.

[0034] The present invention also provides a method for fabricating the low-power negative capacitance field-effect transistor. The method is simple to operate and can effectively control the potential well curve inside the functional material of the gate dielectric layer by changing the process parameters in methods such as pulsed laser physical deposition, thereby fabricating a high-quality ferroelectric thin film material with multi-level negative capacitance characteristics and a low-power negative capacitance field-effect transistor. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the structure of the low-power negative capacitance field-effect transistor provided by the present invention.

[0037] Figure 2 In Embodiment 1 of the present invention, (111)-PbZr 0.2 Ti 0.8 Voltage-time curves of O3 thin films.

[0038] Figure 3 In Embodiment 1 of the present invention, (111)-PbZr 0.2 Ti 0.8 Free potential trap curve of O3 thin film under a 1.7 V pulsed electrical signal. Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] This invention discloses a method for fabricating a low-power negative capacitance field-effect transistor for unidirectional electric fields.

[0041] To better understand the present invention, the following embodiments are provided for further detailed description of the present invention, but they should not be construed as limiting the present invention. Any non-essential improvements and adjustments made by those skilled in the art based on the above-described invention are also considered to fall within the protection scope of the present invention.

[0042] The technical solution of the present invention will be further described below with reference to specific embodiments. Example 1

[0043] In this embodiment, a thickness of 1 mm and a size of 1 cm are selected. 2 A Si wafer was used as the substrate; firstly, a β-Ga2O3 layer with a thickness of about 100 nm was epitaxially grown on the substrate using a low-temperature solid-source molecular beam epitaxy process, with an epitaxial temperature of 500℃ and a deposition rate of 0.6 μm / h.

[0044] Next, using standard photolithography, an active layer (including a source layer, a drain layer, and a channel) is formed on the β-Ga2O3 layer, with the source layer and channel layer located on opposite sides of the channel; then, using ion implantation, an active layer is formed on the N-type surface. + The source and drain regions were injected with an energy of 25 keV and a dose of 10. 19 cm -3 Si + Ions are used to form source and drain regions; then the source and drain regions are activated by thermal annealing at 950℃ for 20 min to obtain activated source and drain regions.

[0045] In this embodiment, a CoFe2O4 buffer layer is deposited on the active layer using pulsed laser deposition technology. The operating conditions for pulsed laser deposition include: the sample deposition chamber is first continuously evacuated to 1×10⁻⁶. -7 Pa, deposition chamber temperature 600℃, deposition oxygen pressure 50 mtorr, laser energy density 0.4 J·cm⁻¹ -2 The deposition time was 10 min, the laser pulse frequency was 10 Hz, and a CoFe2O4 buffer layer with a thickness of about 10 nm was obtained.

[0046] Then, using the same pulsed laser deposition technique, (111)-PbZr was deposited on the buffer layer. 0.2 Ti 0.8 O3 gate dielectric layer, wherein the operating conditions for pulsed laser deposition include: the sample deposition chamber is first continuously evacuated to 1×10 -7 The deposition chamber temperature was 690℃, the deposition oxygen pressure was 200 mtorr, and the laser energy density was 0.35 J·cm⁻¹. -2The deposition time was 60 min, and the laser pulse frequency was 10 Hz, resulting in a (111)-PbZr layer with a thickness of approximately 180 nm. 0.2 Ti 0.8 O3 gate dielectric layer;

[0047] Finally, using photolithography and magnetron sputtering technology, Au electrodes of approximately 80 nm thickness were grown on the gate dielectric layer, source region, and drain region, respectively, and a low-power negative capacitance field-effect transistor capable of operating under a unidirectional electric field was finally obtained.

[0048] In this embodiment, (111)-PbZr 0.2 Ti 0.8 The negative capacitance of the O3 gate dielectric layer is a key feature of transistors to achieve unidirectional electric field and low-voltage operation. Therefore, it is necessary to study the (111)-PbZr... 0.2 Ti 0.8 The negative capacitance characteristics and potential well curves of the O3 gate dielectric layer were tested and analyzed.

[0049] In this embodiment, an ultrafast polarization kinetics characterization system is used to characterize (111)-PbZr. 0.2 Ti 0.8 The negative capacitance effect of the O3 gate dielectric layer was tested and analyzed. The experimental results are as follows: Figure 2 and 3 As shown.

[0050] from Figure 2 As can be seen from the data, the gate dielectric layer exhibits two transient voltage drops under square wave pulse excitation of less than 2V, which is equivalent to two negative capacitance effects. Furthermore, the second transient voltage drop occurs during the unidirectional electric field stage, which also indicates that (111)-PbZr 0.2 Ti 0.8 The O3 gate dielectric layer can exhibit a negative capacitance effect under a unidirectional electric field.

[0051] from Figure 3 From this, we can see that (111)-PbZr 0.2 Ti 0.8 The O3 gate dielectric layer exhibits a multi-barrier free energy curve that differs from that of traditional bipolar ferroelectrics. Under excitation pulses less than 2V, the number of potential barriers observed experimentally is two, with an energy barrier of only 0.1 J·cm⁻¹. -3 .

[0052] In summary, (111)-PbZr 0.2 Ti 0.8 Compared to common ferroelectric materials, the energy barrier of the O3 gate dielectric layer is reduced by more than 50 times (for PbZr of the same thickness). 0.2 Ti 0.8 The energy barrier of the O3 thin film is approximately 4 J·cm⁻¹. -3Furthermore, and more importantly, the gate dielectric layer also exhibits a negative capacitance effect under a unidirectional electric field. Therefore, based on (111)-PbZr 0.2 Ti 0.8 The negative capacitance field-effect transistor with an O3 gate dielectric layer has outstanding advantages such as unidirectional electric field operation, low power consumption, and high integration, resulting in significant benefits. Example 2

[0053] In this embodiment, a thickness of 1 mm and a size of 1 cm are selected. 2 The Ge wafer was used as the substrate; firstly, a ZnO layer with a thickness of about 100 nm was epitaxially grown on the substrate using a low-temperature solid-source molecular beam epitaxy process, with an epitaxial temperature of 400℃ and a deposition rate of 1μm / h.

[0054] Next, using standard photolithography, an active layer (including a source layer, a drain layer, and a channel) is formed on the ZnO layer, with the source layer and channel layer located on opposite sides of the channel; then, using ion implantation, an active layer is formed on the N-type ZnO layer. + The source and drain regions were injected with an energy of 25 keV and a dose of 10. 19 cm -3 Si + Ions are used to form source and drain regions; then the source and drain regions are activated by thermal annealing at 950℃ for 20 min to obtain activated source and drain regions.

[0055] In this embodiment, a PbTiO3 buffer layer is deposited on the active layer using pulsed laser deposition technology. The operating conditions for pulsed laser deposition include: the sample deposition chamber is first continuously evacuated to 1×10⁻⁶. -7 Pa, deposition chamber temperature 690℃, deposition oxygen pressure 100 mtorr, laser energy density 0.4 J·cm⁻¹ -2 The deposition time was 10 min, the laser pulse frequency was 10 Hz, and a PbTiO3 buffer layer with a thickness of about 10 nm was obtained.

[0056] Then, using the same pulsed laser deposition technique, (111)-PbZr was deposited on the buffer layer. 0.1 Ti 0.9 O3 gate dielectric layer, wherein the operating conditions for pulsed laser deposition include: the sample deposition chamber is first continuously evacuated to 1×10 -7 The deposition chamber temperature was 690℃, the deposition oxygen pressure was 200 mtorr, and the laser energy density was 0.35 J·cm⁻¹. -2 The deposition time was 60 min, and the laser pulse frequency was 10 Hz, resulting in a (111)-PbZr layer with a thickness of approximately 180 nm. 0.1Ti 0.9 O3 gate dielectric layer;

[0057] Finally, using photolithography and magnetron sputtering technology, TiN electrodes of approximately 80 nm thickness were grown on the gate dielectric layer, source region, and drain region, respectively, and a low-power negative capacitance field-effect transistor capable of operating under a unidirectional electric field was finally obtained.

[0058] According to the test method of Example 1, the results show that the effect of Example 2 is roughly the same as that of Example 1.

[0059] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A low-power negative capacitance field-effect transistor for unidirectional electric fields, characterized in that, Includes a substrate; a channel layer formed on the substrate; a buffer layer, a source region, and a drain region formed on the channel layer; a gate dielectric layer formed on the buffer layer; and a gate electrode formed on the gate dielectric layer; wherein, The source region and the drain region are respectively disposed on both sides of the buffer layer, and the source electrode and the drain electrode are respectively formed on the source region and the drain region; The gate dielectric layer is made of (111)-PbZr. 0.2 Ti 0.8 O3, and possesses multi-stage negative capacitance characteristics; and the free potential well curve of the gate dielectric layer under the action of an external electric field is a multi-potential well curve, wherein the absolute value of the electric field strength is 10. 4 ~10 8 V / m, number of potential wells is 3, number of potential barriers is 2, and barrier height is 0.1 J·cm. -3 Furthermore, the thickness of the gate dielectric layer is 1 nm to 1000 nm; when the polarization intensity is 0, there is a potential well. The buffer layer is at least one of CoFe2O4, SrTiO3, PbTiO3, PbZrO3, and HfO2, and the thickness of the buffer layer is 1~200 nm.

2. The low-power negative capacitance field-effect transistor for unidirectional electric fields according to claim 1, characterized in that, The absolute value of the working electrical signal of the gate electrode is 0.01~5 V, the frequency is 50~3 GHz, and the electrical signal is unidirectional or alternating positive and negative signals.

3. A low-power negative capacitance field-effect transistor for unidirectional electric fields according to claim 1, characterized in that, The substrate is made of one of the following materials: mica, Si, Ge, SiGe, SOI, GOI, and GaAs.

4. A low-power negative capacitance field-effect transistor for unidirectional electric fields according to claim 1, characterized in that, The channel layer is one of ZnO, SnO2, β-Ga2O3, In2O3, SiO2, and GeO2, and the thickness of the channel layer is 10~500nm.

5. A low-power negative capacitance field-effect transistor for unidirectional electric fields according to claim 1, characterized in that, The gate electrode, source electrode, or drain electrode is at least Au, Ag, Pt, Ti, Ta2O5, TaN, or TiN. x It is one of SrRuO3, and the thickness of the electrode is 1~200 nm.

6. A method for fabricating a low-power negative capacitance field-effect transistor for unidirectional electric fields as described in any one of claims 1 to 5, characterized in that, Includes the following steps: (1) Deposit a channel layer and a buffer layer sequentially on the upper surface of the substrate for later use; (2) Deposit a gate dielectric layer on the buffer layer deposited in step (1) using pulsed laser physical deposition, radio frequency magnetron sputtering or atomic layer deposition, for later use; (3) Deposit a gate electrode on the gate dielectric layer deposited in step (2), and deposit a source electrode and a drain electrode on the channel layer deposited in step (1), and then perform annealing to obtain the low-power negative capacitance field-effect transistor.

7. The method for fabricating a low-power negative capacitance field-effect transistor for unidirectional electric fields according to claim 6, characterized in that, In step (2), the operating conditions for the pulsed laser physical deposition method are: the vacuum degree of the sample deposition chamber is 1×10⁻⁶. -10 ~1×10 -5 Pa, deposition temperature 200–900 °C, deposition oxygen pressure 0–500 mtorr, laser energy density 0.01–10 J·cm⁻¹ -3 The laser pulse frequency is 1~100 Hz.

8. The application of a low-power negative capacitance field-effect transistor for unidirectional electric fields as described in claim 1 or a low-power negative capacitance field-effect transistor for unidirectional electric fields prepared by the method described in claim 6 in microelectronics.

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