Method of manufacturing a semiconductor structure
By first forming a lower electrode film to fill the via in semiconductor structure manufacturing and then removing the mask layer, the etching defect problem is solved, and the stability and accuracy of the etching process are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2023-02-02
- Publication Date
- 2026-05-29
AI Technical Summary
Existing semiconductor structure manufacturing methods are prone to etching defects during the etching process, especially when vertically etching high-hardness and high-film-thickness semiconductor structures, which can lead to enlarged and interconnected vias and cause semiconductor structure abnormalities.
The method of first forming a lower electrode film to fill the via and then removing the mask layer is adopted to ensure that the second dielectric layer is not affected, avoid the hole expansion effect, and reduce etching defects.
By forming the lower electrode film first and then removing the mask layer, etching defects in the semiconductor structure are reduced, and the stability and precision of the manufacturing process are improved.
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Figure CN115996569B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductors, and in particular to a method for manufacturing a semiconductor structure. Background Technology
[0002] Dynamic Random Access Memory (DRAM) cells consist of capacitors for storing charge and transistors that act as switches. As the geometry of DRAM cells continues to decrease according to Moore's Law, the aspect ratio of the capacitors gradually increases.
[0003] Existing etching processes are prone to forming etching defects when vertically etching semiconductor structures with high hardness and high film thickness. Summary of the Invention
[0004] This disclosure provides a method for manufacturing a semiconductor structure, which at least helps to reduce etching defects in the semiconductor structure.
[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, a first dielectric layer, a second dielectric layer, and a mask layer sequentially stacked, wherein the material of the first dielectric layer is different from the material of the second dielectric layer, and the substrate has a plurality of discrete landing pads, and the mask layer has a plurality of openings penetrating the mask layer; using the mask layer as a mask, etching the second dielectric layer and the first dielectric layer along the openings until the landing pads are exposed, forming a plurality of first vias penetrating the second dielectric layer and the first dielectric layer, and each first via exposing a corresponding landing pad; forming a lower electrode film, the lower electrode film at least filling the openings and the first vias; removing the mask layer and the lower electrode film above the top surface of the second dielectric layer, the remaining lower electrode film serving as the lower electrode layer.
[0006] According to other embodiments of this disclosure, in the same process step, the mask layer and the lower electrode film above the top surface of the second dielectric layer are removed.
[0007] According to other embodiments of this disclosure, a chemical mechanical polishing process is used to remove the mask layer and the lower electrode film above the top surface of the second dielectric layer.
[0008] According to other embodiments of this disclosure, removing the mask layer and the lower electrode film above the top surface of the second dielectric layer includes: using a chemical mechanical polishing process to remove the mask layer and the lower electrode film above the top surface of the second dielectric layer until the top surface of the second dielectric layer is exposed; and cleaning the top surface of the second dielectric layer.
[0009] According to other embodiments of this disclosure, removing the mask layer and the lower electrode film above the top surface of the second dielectric layer includes: etching the mask layer and the lower electrode film above the top surface of the second dielectric layer until the top surface of the second dielectric layer is exposed; and performing chemical mechanical polishing on the top surface of the second dielectric layer.
[0010] According to other embodiments of this disclosure, the gas introduced in the etching step includes one or more of CL2 or NF3.
[0011] According to other embodiments of this disclosure, before performing chemical mechanical polishing on the top surface of the second dielectric layer, the method further includes cleaning the top surface of the second dielectric layer.
[0012] According to other embodiments of this disclosure, the cleaning solution used for cleaning the top surface of the second dielectric layer includes one or more of HF, H2SO4, H2O2, and NH3·H2O.
[0013] According to other embodiments of this disclosure, the cleaning process on the top surface of the second dielectric layer includes: a first cleaning step, wherein the cleaning solution used in the first cleaning step includes one or more of NH3·H2O and H2O2, and the cleaning time of the first cleaning step is 50-90 seconds; a second cleaning step, wherein the cleaning solution used in the second cleaning step includes one or more of H2SO4 and H2O2; and a third cleaning step, wherein the cleaning solution used in the third cleaning step includes HF, and the cleaning time of the third cleaning step is 30-60 seconds.
[0014] According to other embodiments of this disclosure, the ratio of HF to H2O in the cleaning solution used in the third cleaning step is 25:1 to 35:1.
[0015] According to other embodiments of this disclosure, forming the first dielectric layer includes: forming a first isolation layer located on the surface of the substrate; forming a support layer located on the surface of the first isolation layer away from the substrate; and forming a second isolation layer located on the surface of the support layer away from the substrate, wherein the first isolation layer and the second isolation layer are made of the same material, and the second isolation layer, the support layer, and the first isolation layer constitute the first dielectric layer.
[0016] According to other embodiments of this disclosure, the material of the mask layer includes polycrystalline silicon.
[0017] According to other embodiments of this disclosure, the step of forming the second dielectric layer includes: forming a silicon nitride layer located on the surface of the first dielectric layer; and forming a silicon oxynitride layer located on the surface of the silicon nitride layer, wherein the thickness of the silicon oxynitride layer is less than the thickness of the silicon nitride layer.
[0018] According to other embodiments of this disclosure, after forming the lower electrode layer, the method further includes: patterning the second dielectric layer located between adjacent lower electrode layers to form a second via, wherein the second via exposes the side surface of the lower electrode layer.
[0019] According to other embodiments of this disclosure, the etching selectivity ratio for the first dielectric layer and the second dielectric layer is greater than or equal to 10:1.
[0020] The technical solutions provided in this disclosure have at least the following advantages:
[0021] In the semiconductor structure manufacturing method provided in this disclosure, a substrate, a first dielectric layer, a second dielectric layer, and a mask layer are first provided in sequence. The material of the first dielectric layer is different from that of the second dielectric layer, and the substrate has multiple discrete landing pads. The mask layer has multiple openings penetrating the mask layer. Then, using the mask layer as a mask, the second dielectric layer and the first dielectric layer are etched along the openings until the landing pads are exposed, forming multiple first vias penetrating the second dielectric layer and the first dielectric layer. Each first via exposes a corresponding landing pad, forming a lower electrode film. The lower electrode film at least fills the openings and the first vias. The mask layer and the lower electrode film above the top surface of the second dielectric layer are removed, and the remaining lower electrode film serves as the lower electrode layer. In related technologies, after etching the first dielectric layer and the second dielectric layer using the mask layer as a mask, the mask layer is removed first, and then a lower electrode film filling the first vias penetrating the first dielectric layer and the second dielectric layer is formed. This manufacturing method may result in the removal of a portion of the second dielectric layer beneath the mask layer during the mask layer removal process, creating abnormal connectivity between different first vias and causing a via enlargement effect, thus enlarging the diameter of the first vias. Consequently, when forming the lower electrode film in subsequent steps, the lower electrode film fills the enlarged and interconnected first vias, causing semiconductor structure abnormalities and etching defects. In the semiconductor structure manufacturing method provided in this disclosure, after etching the first dielectric layer and the second dielectric layer using the mask layer as a mask, a lower electrode film is first formed that fills the openings and first vias. Then, the mask layer and the portion of the lower electrode film located in the mask layer openings are removed. This ensures that the second dielectric layer is not affected by the mask layer removal process, preventing the first vias from experiencing an enlargement effect, ensuring that the first vias are not enlarged and interconnected, and preventing abnormalities in the lower electrode film filling the first vias, thereby reducing etching defects in the semiconductor structure. Attached Figure Description
[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0023] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step of a semiconductor structure manufacturing method;
[0024] Figures 5 to 13 This is a schematic diagram of the steps in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. Detailed Implementation
[0025] As can be seen from the background technology, current semiconductor structure manufacturing methods produce semiconductor structures with etching defects.
[0026] refer to Figures 1 to 4 , Figures 1 to 4 This is a cross-sectional structural diagram of each step in a semiconductor structure manufacturing method. The semiconductor structure includes a substrate 10, a first dielectric layer 20, a second dielectric layer 30, and a mask layer 40 stacked sequentially. The substrate 10 has multiple discrete landing pads 11.
[0027] refer to Figure 1 Using the mask layer 40 as a mask, the second dielectric layer 30 and the first dielectric layer 20 are etched along the opening penetrating the mask layer 40 until the pad 11 is exposed, forming multiple first vias penetrating the first dielectric layer 20 and the second dielectric layer 30. (Reference) Figure 2 When removing the mask layer 40, since the openings in the mask layer 40 and the first vias in the second dielectric layer 30 do not have other structures, the second dielectric layer 30 is very likely to be exposed to the etching environment during the removal of the mask layer 40, and may be partially removed. (Reference) Figure 3 This forms a lower electrode layer 50 that fills the first through-hole. Since the second dielectric layer 30 was partially removed in the preceding steps, and the first through-hole was enlarged and connected, the lower electrode layer 50 formed at this time will completely fill the first through-hole at the original location of the second dielectric layer 30. (Reference) Figure 4The second dielectric layer 30 between adjacent lower electrode layers 50 is patterned to form a second via. Since the lower electrode layer 50 filled the first via at the original second dielectric layer 30 in the previous step, this step will not be able to form a second via at the original second dielectric layer 30, resulting in an abnormality in the semiconductor structure and etching defects in the semiconductor structure.
[0028] Analysis revealed that in the aforementioned semiconductor structure manufacturing method, after etching the first via through the first dielectric layer 20 and the second dielectric layer 30 using the mask layer 40 as a mask, the mask layer 40 is removed first, and then the lower electrode layer 50 through the first via is formed. This results in a problem where the second dielectric layer 30 is partially removed during the removal of the mask layer 40, causing the first via to be enlarged and connected, leading to an enlarged via effect. Consequently, the semiconductor structure manufactured using this method has etching defects. If a semiconductor structure manufacturing method could be provided in which the second dielectric layer 30 is not affected and the first via is not enlarged and connected during the removal of the mask layer 40, the aforementioned problem could be improved.
[0029] This disclosure provides a method for manufacturing a semiconductor structure. First, a substrate, a first dielectric layer, a second dielectric layer, and a mask layer are sequentially stacked. Using the mask layer as a mask, the second dielectric layer and the first dielectric layer are etched to form a plurality of first vias penetrating the first and second dielectric layers. Then, the mask layer is not removed immediately; a lower electrode film is formed to at least fill the openings and the first vias. Finally, the mask layer and the lower electrode film above the top surface of the second dielectric layer are removed together, and the remaining lower electrode film serves as the lower electrode layer. This method ensures that the second dielectric layer is not partially removed during the mask layer removal process, and the first vias are not enlarged or connected, reducing etching defects in the semiconductor structure.
[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of the present disclosure to enable the reader to better understand the present disclosure. However, the technical solutions claimed in the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments.
[0031] Figures 5 to 13 The diagram shows the structural schematics corresponding to each step of the semiconductor structure manufacturing method provided in the embodiments of this disclosure.
[0032] refer to Figure 5The system provides a substrate 100, a first dielectric layer 110, a second dielectric layer 120, and a mask layer 130 stacked sequentially. The material of the first dielectric layer 110 is different from that of the second dielectric layer 120. The substrate 100 has a plurality of discrete landing pads 101, and the mask layer 130 has a plurality of openings penetrating the mask layer 130.
[0033] Landing pads 101 are located on top of the substrate 100, and multiple landing pads 101 are discretely positioned relative to each other. During subsequent etching steps, the landing pads 101 can serve as etching termination points to effectively prevent over-etching. After the lower electrode layer is formed in a subsequent step, the landing pads 101 can contact the lower electrode layer to form capacitive contact windows with conductive properties. In some embodiments, the material of the landing pads 101 may include tungsten.
[0034] The first dielectric layer 110 and the second dielectric layer 120 are made of different materials, and the thickness of the first dielectric layer 110 can be greater than the thickness of the second dielectric layer 120. In some embodiments, the etching selectivity ratio of the first dielectric layer 110 to the second dielectric layer 120 can be greater than or equal to 10:1. For example, the etching selectivity ratio of the first dielectric layer 110 to the second dielectric layer 120 can be 10:1, 20:1, 40:1, 50:1, 70:1, 100:1, etc. If the etching selectivity ratio of the first dielectric layer 110 to the second dielectric layer 120 is too small, the first dielectric layer 110 and the second dielectric layer 120 may interfere with each other during the etching process, resulting in a large difference in the aperture of the etched first via at different locations, producing a hole enlargement effect, and causing etching defects in the semiconductor structure. Therefore, the etching selectivity ratio of the first dielectric layer 110 to the second dielectric layer 120 needs to be selected within an appropriate range. When the etching selectivity ratio of the first dielectric layer 110 to the second dielectric layer 120 is greater than or equal to 10:1, no hole expansion effect will occur, and etching defects in the semiconductor structure can be reduced. The material of the first dielectric layer 110 may include one or more of silicon oxide and silicon nitride, and the material of the second dielectric layer 120 may include one or more of silicon nitride and silicon oxynitride.
[0035] In some embodiments, the material of the mask layer 130 may include polysilicon. Polysilicon is chemically inert at room temperature and can maintain high stability when etching other film layers using the mask layer 130 as a mask, ensuring the smooth progress of the etching step. The locations of the multiple openings penetrating the mask layer 130 are the locations where the lower electrode layer needs to be formed in subsequent steps.
[0036] The substrate 100 may include multiple mutually discrete active regions 102 and isolation regions 103 that separate adjacent active regions 102. The active regions 102 may be made of silicon, and the isolation regions 103 may use an insulating material. The substrate 100 may also have a word line structure 104, which includes a first conductive layer 1041, a second conductive layer 1042, and a word line capping layer 1043. The second conductive layer 1042 is located above the first conductive layer 1041, and the word line capping layer 1043 is located above the second conductive layer 1042 away from the first conductive layer 1041. A protective layer 105 may also be provided between the word line structure 104 and the active regions 102. The protective layer 105 may surround the word line structure 104 to make the performance of the word line structure 104 more stable.
[0037] Additionally, each landing pad 101 may have a barrier layer 106 and a capacitive contact layer 107 below it near the word line structure 104, wherein the barrier layer 106 is located above the capacitive contact layer 107, and the landing pad 101 is located above the barrier layer 106. The material of the barrier layer 106 may include TiN, and the material of the capacitive contact layer 107 may include polysilicon.
[0038] refer to Figure 6 In some embodiments, the step of forming the first dielectric layer 110 may include: forming a first isolation layer 111, the first isolation layer 111 being located on the surface of the substrate 100; forming a support layer 112, the support layer 112 being located on the surface of the first isolation layer 111 away from the substrate 100; and forming a second isolation layer 113, the second isolation layer 113 being located on the surface of the support layer 112 away from the substrate 100. The first isolation layer 111 and the second isolation layer 113 are made of the same material, and the second isolation layer 113, the support layer 112, and the first isolation layer 111 constitute the first dielectric layer 110. The materials of the first isolation layer 111 and the second isolation layer 113 may include silicon oxide, which is used in the semiconductor structure to isolate the lower electrode layer formed in subsequent steps. The material of the support layer 112 may be silicon nitride, and the support layer 112 is used to support the semiconductor structure, ensuring that the semiconductor structure has high stability and mechanical strength. The thickness of the support layer 112 may be less than the thickness of the first isolation layer 111, and the thickness of the support layer 112 may be less than the thickness of the second isolation layer 111.
[0039] In some embodiments, the step of forming the second dielectric layer 120 may include: forming a silicon nitride layer 121, the silicon nitride layer 121 being located on the surface of the first dielectric layer 110; and forming a silicon oxynitride layer 122, the silicon oxynitride layer 122 being located on the surface of the silicon nitride layer 121, and the thickness of the silicon oxynitride layer 122 may be less than the thickness of the silicon nitride layer 121. Both the silicon nitride layer 121 and the silicon oxynitride layer 122 can provide support for the semiconductor structure, ensuring that the semiconductor structure has high stability and mechanical strength. The combined arrangement of the silicon nitride layer 121 and the silicon oxynitride layer 122 can further enhance the support effect and further improve the stability of the semiconductor structure.
[0040] refer to Figure 7 Using the mask layer 130 as a mask, the second dielectric layer 120 and the first dielectric layer 110 are etched along the opening until the landing pad 101 is exposed, forming multiple first vias penetrating the second dielectric layer 120 and the first dielectric layer 110, with each first via exposing a corresponding landing pad 101. At this point, the landing pad 101 serves as the etching stop layer, and the etching ends after the surface of the landing pad 101 is exposed. Since the position of the opening in the mask layer 130 is the position where the lower electrode layer needs to be formed in the subsequent step, and the aperture of the opening in the mask layer 130 is the diameter of the lower electrode layer to be formed in the subsequent step, the position of the multiple first vias etched along the opening is the position of the lower electrode layer, and the aperture of the first via is the diameter of the lower electrode layer. In the subsequent step of forming the lower electrode layer, the lower electrode layer simply fills the first vias. Both the first dielectric layer 110 and the second dielectric layer 120 can serve as isolation structures for the multiple lower electrode layers.
[0041] refer to Figure 8 A lower electrode film 140 is formed, which at least fills the opening and the first via. In some embodiments, the material of the lower electrode film 140, serving as an electrode in a capacitor structure within a semiconductor structure, may include TiN. The top surface of the lower electrode film 140 may be flush with the top surface of the mask layer 130, or it may be higher than the top surface of the mask layer 130. This ensures that removing the mask layer 130 in subsequent steps will not affect the second dielectric layer 120 located below the mask layer 130 or the lower electrode film 140 located within the first via in the second dielectric layer 120. The lower electrode film 140 undergoes certain processing in subsequent steps to form a lower electrode layer.
[0042] refer to Figures 9 to 12 The mask layer 130 and the lower electrode film 140 above the top surface of the second dielectric layer 120 are removed, and the remaining lower electrode film 140 serves as the lower electrode layer 141. Various methods can be used to remove the mask layer 130 and the lower electrode film 140 above the top surface of the second dielectric layer 120, which will be described in detail below.
[0043] It should be noted that, in order to ensure that the mask layer 130 is completely removed, in the actual production process, a portion of the second dielectric layer 120 and a portion of the lower electrode film 140 located within the second dielectric layer 120 may be removed, resulting in a thinner second dielectric layer 120.
[0044] refer to Figure 9 In some embodiments, the mask layer 130 and the lower electrode film 140 above the top surface of the second dielectric layer 120 can be removed in the same process step. Removing the mask layer 130 and the lower electrode film 140 above the top surface of the second dielectric layer 120 in the same process step can make the semiconductor structure manufacturing method more efficient, and can quickly and easily remove the mask layer 130 and the lower electrode film 140 above the top surface of the second dielectric layer 120.
[0045] In some embodiments, chemical mechanical polishing (CMP) can be used to remove the mask layer 130 and the lower electrode film 140 above the top surface of the second dielectric layer 120. CMP combines chemical etching and mechanical removal to achieve global surface planarization. It combines the advantages of both chemical and mechanical polishing. Chemical polishing alone yields a high-precision surface with low damage and good integrity, but at a slow rate; mechanical polishing alone offers a fast rate, good consistency, and high surface flatness, but is prone to damage. CMP removal of the mask layer 130 and the lower electrode film 140 above the top surface of the second dielectric layer 120 achieves a high polishing rate while maintaining high surface flatness and minimizing damage to the second dielectric layer 120.
[0046] refer to Figure 10 Since a large amount of residue may remain on the surface of the second dielectric layer 120 after chemical mechanical polishing, in some embodiments, the step of removing the mask layer 130 and the lower electrode film 140 above the top surface of the second dielectric layer 120 may include: using a chemical mechanical polishing process to remove the mask layer 130 and the lower electrode film 140 above the top surface of the second dielectric layer 120 until the top surface of the second dielectric layer 120 is exposed, and then cleaning the top surface of the second dielectric layer 120. The cleaning process may use a certain cleaning solution for wet etching, and the cleaning solution can remove the residue of the mask layer 130 and the lower electrode film 140 on the surface of the second dielectric layer 120.
[0047] Because it is difficult to control the thickness of the film layers to be removed during chemical mechanical polishing (CMP) of the mask layer 130 and the lower electrode film 140 above the top surface of the second dielectric layer 120, it is also difficult to control the duration of the CMP process in actual production. If the mask layer 130 and the lower electrode film 140 above the top surface of the second dielectric layer 120 are to be completely removed, a large portion of the second dielectric layer 120 may be removed, resulting in over-polishing.
[0048] refer to Figure 11 In some embodiments, removing the mask layer 130 and the lower electrode film 140 above the top surface of the second dielectric layer 120 may include: etching the mask layer 130 and the lower electrode film 140 above the top surface of the second dielectric layer 120 until the top surface of the second dielectric layer 120 is exposed; and then performing chemical mechanical polishing on the top surface of the second dielectric layer 120. In this process, the mask layer 130 and the lower electrode film 140 above the top surface of the second dielectric layer 120 are first removed by etching, and then the top surface of the second dielectric layer 120 is further processed by chemical mechanical polishing. Compared with the chemical mechanical polishing process described above, the etching process can more accurately control the etching time, avoid over-etching, and more completely preserve the second dielectric layer 120 and the lower electrode film 140 located within the second dielectric layer 120.
[0049] The etching of the mask layer 130 and the lower electrode film 140 above the top surface of the second dielectric layer 120 can be performed using a dry etching process. In some embodiments, the gas introduced during the dry etching step may include one or more of CL2 or NF3. This dry etching process can remove both the mask layer 130 and the lower electrode film 140 simultaneously. CL2 or NF3 are both highly chemically active gases, enabling this etching step to achieve both a high etching rate and precise control of the etching time. This allows for the removal of the mask layer 130 and the lower electrode film 140 above the top surface of the second dielectric layer 120 while minimizing etching loss on the second dielectric layer 120.
[0050] refer to Figure 12 Because certain residues remain on the surface of the second dielectric layer 120 after etching the mask layer 130 and the lower electrode film 140 above the surface of the second dielectric layer 120, in some embodiments, before chemical mechanical polishing of the top surface of the second dielectric layer 120, a cleaning process may be included. The cleaning step may employ a wet etching process, which can effectively remove the residues of the mask layer 130 and the lower electrode film 140 located on the top surface of the second dielectric layer 120.
[0051] In some embodiments, the cleaning solution used to clean the top surface of the second dielectric layer 120 may include one or more of HF, H2SO4, H2O2, and NH3·H2O. NH3·H2O and H2O2 can form an SCl solution, and H2SO4 and H2O2 can form an SPM solution. Using a combination of these solutions to clean the top surface of the second dielectric layer 120 can achieve a better cleaning effect, removing residues from the mask layer 130 and the lower electrode film 140 while minimizing the impact on the second dielectric layer 120 and the lower electrode film 140 located within it.
[0052] In some embodiments, the specific steps for cleaning the top surface of the second dielectric layer 120 may include three step-by-step cleaning steps.
[0053] The cleaning solution used in the first cleaning step can be an SC1 solution, which includes one or more of NH3·H2O and H2O2. The cleaning time for the first cleaning step can be 50-90 seconds. For example, the cleaning time for the first cleaning step can be 50 seconds, 53 seconds, 60 seconds, 65 seconds, 70 seconds, 77 seconds, 80 seconds, 86 seconds, 90 seconds, etc. If the cleaning time of the first cleaning step is too long, it may cause partial etching of the second dielectric layer 120 and the lower electrode film 140 within the second dielectric layer 120. If the cleaning time of the first cleaning step is too short, it may not be able to completely remove the residue of the mask layer 130 and the lower electrode film 140. Therefore, the cleaning time of the first cleaning step needs to be selected within an appropriate range, which can be 50-90 seconds.
[0054] The second cleaning step uses an SPM solution, which includes one or more of H2SO4 and H2O2.
[0055] The cleaning solution used in the third cleaning step includes HF. In some embodiments, the ratio of HF to H2O in the cleaning solution used in the third cleaning step is 25:1-35:1. For example, the ratio of HF to H2O in the cleaning solution used in the third cleaning step can be 25:1, 27:1, 30:1, 33:1, 35:1, etc. If the ratio of HF to H2O in the cleaning solution used in the third cleaning step is too high, the concentration of the cleaning solution will be too high, which may cause partial etching of the second dielectric layer 120 and the lower electrode film 140 located in the second dielectric layer 120. If the ratio of HF to H2O in the cleaning solution used in the third cleaning step is too low, the concentration of the cleaning solution will be too low, and it may not be possible to completely clean and remove the residue of the mask layer 130 and the lower electrode film 140. Therefore, the ratio of HF to H2O in the cleaning solution used in the third cleaning step needs to be selected within an appropriate range, which can be 25:1-35:1. The cleaning time of the third cleaning step is 30-60 seconds. For example, the cleaning time for the third cleaning step can be 30 seconds, 35 seconds, 40 seconds, 44 seconds, 50 seconds, 56 seconds, 60 seconds, etc. If the cleaning time of the third cleaning step is too long, it may cause partial etching of the second dielectric layer 120 and the lower electrode film 140 within the second dielectric layer 120. If the cleaning time of the third cleaning step is too short, it may not be able to completely remove the residue of the mask layer 130 and the lower electrode film 140. Therefore, the cleaning time of the third cleaning step needs to be selected within an appropriate range, which can be 30-60 seconds.
[0056] The combination of the above three cleaning steps can further improve the cleaning efficiency, and make the cleaning steps remove the residual mask layer 130 and the lower electrode film 140 while further reducing the etching of the second dielectric layer 120 and the lower electrode film 140 located in the second dielectric layer 120.
[0057] refer to Figure 13 In some embodiments, after forming the lower electrode layer 141, the second dielectric layer 120 located between adjacent lower electrode layers 141 can be patterned to form a second via, with the second via exposed on the side of the lower electrode layer 141. The process for patterning the second dielectric layer 120 located between adjacent lower electrode layers 141 can be an etching process. The second via can be used to fill high-k dielectric material in subsequent steps, resulting in better performance of the capacitor structure in the semiconductor structure. Since the second dielectric layer 120 is not affected by the removal of the mask layer 130 in the aforementioned steps, and there is no situation where the location of the second dielectric layer 120 is filled by the lower electrode layer 141, the second dielectric layer 120 can be patterned normally at this time, and there will be no situation where some locations cannot form the second via, reducing etching defects in the semiconductor structure.
[0058] This disclosure provides a method for manufacturing a semiconductor structure. First, a substrate 100, a first dielectric layer 110, a second dielectric layer 120, and a mask layer 130 are sequentially stacked. The material of the first dielectric layer 110 is different from that of the second dielectric layer 120. The substrate 100 has a plurality of discrete landing pads 101, and the mask layer 130 has a plurality of openings penetrating the mask layer 130. Then, using the mask layer 130 as a mask, the second dielectric layer 120 and the first dielectric layer 110 are etched along the openings until the landing pads 101 are exposed, forming a plurality of first vias penetrating the second dielectric layer 120 and the first dielectric layer 110. Each first via exposes a corresponding landing pad 101, forming a lower electrode film 140 that at least fills the openings and the first vias. Then, the mask layer 130 and the lower electrode film 140 above the top surface of the second dielectric layer 120 are removed, and the remaining lower electrode film 140 serves as the lower electrode layer 141. This can avoid affecting the second dielectric layer 120 during the removal of the mask layer 130, avoid the hole expansion effect, and thus reduce etching defects in the semiconductor structure.
[0059] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate, a first dielectric layer, a second dielectric layer, and a mask layer are provided in sequence. The material of the first dielectric layer is different from that of the second dielectric layer. The substrate has multiple discrete landing pads, and the mask layer has multiple openings penetrating the mask layer. Using the mask layer as a mask, the second dielectric layer and the first dielectric layer are etched along the opening until the landing pad is exposed, forming a plurality of first through holes penetrating the second dielectric layer and the first dielectric layer, and each first through hole exposes a corresponding landing pad; A lower electrode film is formed, wherein the lower electrode film at least fills the opening and the first through hole; Dry etching is used to simultaneously etch the mask layer and the lower electrode film above the top surface of the second dielectric layer until the top surface of the second dielectric layer is exposed; The surface of the second dielectric layer and the remaining surface of the lower electrode film are cleaned by wet etching. The surface of the cleaned second dielectric layer and the surface of the remaining lower electrode film are subjected to chemical mechanical polishing treatment, and the polished lower electrode film serves as the lower electrode layer. The polished second dielectric layer is patterned between adjacent lower electrode layers to form a second via, and the second via exposes the side of the lower electrode layer.
2. The manufacturing method as described in claim 1, characterized in that, The gas introduced during the etching process includes one or more of CL2 or NF3.
3. The manufacturing method as described in claim 1, characterized in that, The cleaning solution used for the cleaning process includes one or more of HF, H2SO4, H2O2, and NH3·H2O.
4. The manufacturing method as described in claim 1, characterized in that, The cleaning process includes: The first cleaning step uses a cleaning solution including one or more of NH3·H2O and H2O2, and the cleaning time of the first cleaning step is 50-90 seconds. The second cleaning step uses a cleaning solution that includes one or more of H2SO4 and H2O2. The third cleaning step uses a cleaning solution including HF, and the cleaning time for the third cleaning step is 30-60 seconds.
5. The manufacturing method as described in claim 4, characterized in that, The third cleaning step uses a cleaning solution with a HF to H2O ratio of 25:1 to 35:
1.
6. The manufacturing method as described in claim 1, characterized in that, Forming the first dielectric layer includes: A first isolation layer is formed, the first isolation layer being located on the surface of the substrate; A support layer is formed on the surface of the first isolation layer away from the substrate; A second isolation layer is formed on the surface of the support layer away from the substrate, wherein the first isolation layer and the second isolation layer are made of the same material, and the second isolation layer, the support layer and the first isolation layer constitute the first dielectric layer.
7. The manufacturing method as described in claim 1, characterized in that, The material of the mask layer includes polycrystalline silicon.
8. The manufacturing method as described in claim 1, characterized in that, The steps for forming the second dielectric layer include: A silicon nitride layer is formed, wherein the silicon nitride layer is located on the surface of the first dielectric layer; A silicon oxynitride layer is formed, the silicon oxynitride layer being located on the surface of the silicon nitride layer, and the thickness of the silicon oxynitride layer being less than the thickness of the silicon nitride layer.
9. The manufacturing method as described in claim 1, characterized in that, The etching selectivity ratio between the first dielectric layer and the second dielectric layer is greater than or equal to 10:1.