Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: providing a substrate, forming a gate structure on the substrate, forming dummy sidewalls on the sidewalls of the gate structure, forming contact hole etch stop layers on the sidewalls of the dummy sidewalls, and forming source and drain doped regions within the substrate on both sides of the gate structure; forming a sacrificial dielectric layer above the source and drain doped regions and the top of the gate structure; forming source and drain plugs that penetrate the sacrificial dielectric layer above the top of the source and drain doped regions and contact the source and drain doped regions; etching the sacrificial dielectric layer until the top of the dummy sidewalls is exposed; after the top of the dummy sidewalls is exposed, removing the dummy sidewalls to form a gap between the contact hole etch stop layer and the sidewalls of the gate structure; forming a top dielectric layer to fill the gap between the source and drain plugs, the top dielectric layer also filling the gap, or the top dielectric layer sealing the top of the gap, the dielectric constant of the material of the top dielectric layer being less than the dielectric constant of the material of the dummy sidewalls. The present invention can reduce the effective capacitance between the gate structure and the source and drain plugs.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the continuous advancement of integrated circuit manufacturing technology, the requirements for integrated circuit integration and performance are becoming increasingly stringent. To increase integration and reduce costs, the critical dimensions of components are constantly shrinking, and the circuit density within integrated circuits is increasing. This development has resulted in insufficient surface area on the wafer to produce the required interconnects.

[0003] To meet interconnect requirements after critical dimensions have been reduced, interconnect structures are currently used to connect different metal layers, or between a metal layer and the substrate. These structures consist of interconnect lines and contact plugs formed within contact openings. The contact plugs connect to semiconductor devices, while the interconnect lines connect the contact plugs to each other, thus forming a circuit.

[0004] The contact plugs in the transistor structure include a gate contact plug located on the surface of the gate structure, which is used to connect the gate structure with an external circuit, and a source-drain contact plug located on the surface of the source-drain doped region, which is used to connect the source-drain doped region with an external circuit. SUMMARY OF THE INVENTION

[0006] Technical issues

[0007] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0008] Solution to the problem

[0009] Technical Solutions

[0010] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, on which a gate structure is formed, dummy sidewalls are formed on sidewalls of the gate structure, contact hole etch stop layers are formed on the sidewalls of the dummy sidewalls, and source and drain doped regions are formed in the substrate on both sides of the gate structure; forming a sacrificial dielectric layer above the source and drain doped regions and the gate structure; forming source and drain plugs that penetrate the sacrificial dielectric layer above the tops of the source and drain doped regions and contact the source and drain doped regions; after forming the source and drain plugs, etching the sacrificial dielectric layer until the tops of the dummy sidewalls are exposed; after the tops of the dummy sidewalls are exposed, removing the dummy sidewalls to form a gap between the contact hole etch stop layer and the sidewalls of the gate structure; forming a top dielectric layer filling between the source and drain plugs, the top dielectric layer also filling the gap to form sidewalls located in the gap, or the top dielectric layer sealing the top of the gap to form an air gap, the material dielectric constant of the top dielectric layer being smaller than the material dielectric constant of the dummy sidewalls.

[0011] Correspondingly, an embodiment of the present invention also provides a semiconductor structure, comprising: a substrate; a gate structure located on the substrate; a source-drain doped region located in the substrate on both sides of the gate structure; a contact hole etch stop layer located on the substrate between the source-drain doped region and the gate structure and arranged opposite to the side wall of the gate structure, with a gap between the contact hole etch stop layer and the side wall of the gate structure; a source-drain plug located on top of the source-drain doped region and in contact with the source-drain doped region; a top dielectric layer filled between the source-drain plugs, the top dielectric layer also filled in the gap, the top dielectric layer located in the gap serves as a sidewall, or the top dielectric layer seals the top of the gap to form an air gap, and the material of the top dielectric layer is a low-k dielectric material or an ultra-low-k dielectric material.

[0012] Advantageous Effects of the Invention

[0013] Beneficial effects

[0014] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages: In the formation method provided by the embodiments of the present invention, dummy sidewalls are formed on the sidewalls of the gate structure, and a sacrificial dielectric layer is formed above the source / drain doped regions and the top of the gate structure, as well as a source / drain plug that penetrates the sacrificial dielectric layer above the top of the source / drain doped regions and contacts the source / drain doped regions. After forming the source / drain plug, the sacrificial dielectric layer is etched until the top of the dummy sidewall is exposed, and the dummy sidewall is removed to form a gap between the contact hole etch stop layer and the sidewall of the gate structure. Then, a top dielectric layer is formed to fill the gap between the source / drain plug and the top dielectric layer also fills the gap to form a sidewall located in the gap, or seals the top of the gap to form an air gap. The dielectric constant of the material of the top dielectric layer is lower than that of the material of the dummy sidewall. By removing the dummy sidewall and forming the top dielectric layer with a lower dielectric constant, the sidewall or air gap with a lower dielectric constant is formed, thereby reducing the effective capacitance between the gate structure and the source / drain plug, thereby improving the performance of the semiconductor structure. Moreover, since the dummy sidewalls will be removed later, the material of the dummy sidewalls can be flexibly selected so that the material of the dummy sidewalls is compatible with the subsequent process flow, which is beneficial to improving the performance of the semiconductor structure.

[0015] Brief description of the accompanying drawings BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figures 1 to 4 The present invention is a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure.

[0017] Figures 5 to 16 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0018] Invention Embodiments

[0019] Modes for Carrying Out the Invention

[0020] The performance of current semiconductor structures needs to be improved. The reasons why the performance needs to be improved are analyzed in conjunction with a method for forming a semiconductor structure.

[0021] Figures 1 to 4 The present invention is a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure.

[0022] refer to Figure 1 A substrate 10 is provided, a dummy gate structure 20 is formed on the substrate 10, sidewalls 22 are formed on the sidewalls of the dummy gate structure 20, source and drain doped regions 11 are formed in the substrate 10 on both sides of the dummy gate structure 20, and a bottom dielectric layer 12 covering the source and drain doped regions 11 is formed on the substrate 10 on the side of the dummy gate structure 20.

[0023] refer to Figure 2, the dummy gate structure 20 is removed, and a gate opening 25 is formed in the bottom dielectric layer 12 .

[0024] refer to Figure 3 , in the gate opening 25 (such as Figure 2 A gate structure 30 is formed in the embodiment shown in FIG.

[0025] refer to Figure 4 A top dielectric layer 40 is formed above the source / drain doped region 11 and the top of the gate structure 30 ; a source / drain plug 50 is formed, penetrating the top dielectric layer 40 and the bottom dielectric layer 12 above the top of the source / drain doped region 11 and contacting the source / drain doped region 11 .

[0026] During the formation of the semiconductor structure, the steps for forming the source-drain doped region 11 generally include: using the sidewalls 22 as a mask, etching the substrate 10 on both sides of the dummy gate structure 20 to form a groove (not shown) in the substrate 10; performing a pre-cleaning treatment on the groove; after the pre-cleaning treatment, forming an epitaxial layer in the groove, and in the process of forming the epitaxial layer, in-situ self-doping ions, and the epitaxial layer doped with ions serves as the source-drain doped region 11. In order to reduce the damage to the sidewalls 22 caused by the pre-cleaning treatment, the sidewalls 22 have a high hardness and density, which makes the sidewalls 22 have a high etching resistance. In addition, the process of removing the dummy gate structure 20 generally includes a wet etching process. Similarly, in order to reduce the probability of damage to the sidewalls 22 during the removal of the dummy gate structure 20, the etching resistance of the sidewalls 20 is also required. Therefore, in the current semiconductor structure formation process, the material dielectric constant of the spacer 20 is usually high (for example, the material of the spacer 20 is silicon nitride), resulting in a large effective capacitance between the gate structure 30 and the source / drain plug 50 .

[0027] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: forming a contact hole etch stop layer on the sidewalls of a dummy sidewall, and forming source and drain doped regions in the substrate on both sides of the gate structure; forming a sacrificial dielectric layer above the source and drain doped regions and the top of the gate structure; forming a source and drain plug, penetrating the sacrificial dielectric layer above the top of the source and drain doped regions and contacting the source and drain doped regions; after forming the source and drain plug, etching the sacrificial dielectric layer until the top of the dummy sidewall is exposed; after the top of the dummy sidewall is exposed, removing the dummy sidewall to form a gap between the contact hole etch stop layer and the sidewall of the gate structure; forming a top dielectric layer filling between the source and drain plugs, the top dielectric layer also filling the gap to form a sidewall located in the gap, or the top dielectric layer seals the top of the gap to form an air gap, and the material dielectric constant of the top dielectric layer is smaller than the material dielectric constant of the dummy sidewall.

[0028] In the formation method provided by the embodiments of the present invention, by removing the dummy sidewalls and forming a top dielectric layer with a lower dielectric constant, a sidewall or air gap with a lower dielectric constant is formed, thereby reducing the effective capacitance between the gate structure and the source / drain plugs, thereby improving the performance of the semiconductor structure. Furthermore, since the dummy sidewalls are subsequently removed, the material of the dummy sidewalls can be flexibly selected, making them compatible with subsequent process steps, which in turn improves the performance of the semiconductor structure.

[0029] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0030] Figures 5 to 16 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0031] Combined with reference Figures 5 to 10 A substrate 100 is provided, a gate structure 400 is formed on the substrate 100, a dummy sidewall 220 is formed on the sidewall of the gate structure 400, a contact hole etch stop layer 300 is formed on the sidewall of the dummy sidewall 220, and a source-drain doped region 110 is formed in the substrate 100 on both sides of the gate structure 400.

[0032] The substrate 100 is used to provide a process platform for subsequent process steps. In this embodiment, the substrate 100 is used to form a planar field-effect transistor as an example, and the substrate 100 is a planar substrate. In other embodiments, the substrate is used to form a fin field-effect transistor (FinFET), and accordingly, the substrate includes a substrate and a fin protruding from the substrate.

[0033] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may be a substrate of other materials. For example, the substrate may be made of germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0034] like Figure 5 As shown, Figure 5 This is a top view. In this embodiment, the substrate 100 includes a device region 100b and an isolation region 100a. The device region 100b is used to form transistors, and the remaining area outside the device region 100b is the isolation region 100a. In this embodiment, the device region 100b is the active area (AA). Subsequently, a contact over active gate (COAG) is formed on top of the gate structure 400 in the active area to save chip area.

[0035] In this embodiment, the gate structure 400 is formed by forming a high-k gate dielectric layer and then forming a gate electrode layer (high klast metal gate last). Figure 5 and Figure 6 Before forming the gate structure 400 , the forming method further includes: forming a dummy gate structure 200 on the substrate 100 .

[0036] in, Figure 5 It is a top view, and for the convenience of illustration, only the substrate 100, the dummy gate structure 200 and the source and drain doped regions 110 are shown. Figure 6 yes Figure 5 Cross-sectional view along the A1A2 cut line. Specifically, the dummy gate structure 200 is formed on the substrate 100 in the device region 100b. The dummy gate structure 200 is used to occupy a space for the subsequent formation of the gate structure 400.

[0037] In this embodiment, the dummy gate structure 200 is a polysilicon gate structure, that is, the dummy gate structure 200 includes a dummy gate layer, and the material of the dummy gate layer is polysilicon. In other embodiments, the material of the dummy gate layer may also include other materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride or amorphous carbon. As an example, the dummy gate structure 200 is a single-layer structure, and the dummy gate structure 200 only includes a dummy gate layer. In other embodiments, the dummy gate structure may also be a stacked structure, correspondingly including a dummy gate oxide layer and a dummy gate layer located on the dummy gate oxide layer, wherein the material of the dummy gate oxide layer may be silicon oxide.

[0038] Continue to refer Figure 6 A dummy sidewall spacer 220 is formed on the sidewall of the dummy gate structure 200. The dummy sidewall spacer 220 is used to protect the sidewall of the dummy gate structure 200 and also to define the formation position of the source and drain doped regions 110. The dummy sidewall spacer 220 and the source and drain doped regions 110 are located in the device region 100b.

[0039] It should be noted that the subsequent steps also include: removing the pseudo sidewall 220, forming a gap at the position of the pseudo sidewall 220, so that the pseudo sidewall 220 is used to occupy space for forming the gap. After the gap is formed, a top dielectric layer with a smaller dielectric constant will be formed. In order to make the material of the top dielectric layer have a lower dielectric constant, the material of the top dielectric layer is usually a material with a looser structure and lower density. Therefore, by first forming a pseudo sidewall 220 for occupying space for the gap, the material of the pseudo sidewall 220 can be flexibly selected, so that the material of the pseudo sidewall 220 is compatible with the subsequent process, which is correspondingly beneficial to improving the performance of the semiconductor structure. For example, the pseudo sidewall 220 has a high etching resistance. In the subsequent process of removing the pseudo gate structure 200, the probability of the pseudo sidewall 220 being damaged is low, or in the process of forming the source and drain doping region 110, the probability of the pseudo sidewall 220 being damaged is low. In addition, since the dummy side wall 220 will be removed later, the material of the dummy side wall 220 is selected as follows: during the process of removing the dummy side wall 220, the etching selectivity between the dummy side wall 220 and other film layers (for example, the gate structure or the contact hole etching stop layer 300, etc.) is relatively high, so that the process of removing the dummy side wall 220 causes less damage to other film layers.

[0040] The dummy sidewall 220 may be a single-layer structure or a stacked-layer structure, and the material of the dummy sidewall 220 may include one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, boron nitride, aluminum oxide, and aluminum nitride. In this embodiment, the dummy sidewall 220 is a single-layer structure, and the material of the dummy sidewall 220 is silicon oxide. Silicon oxide has high hardness and density, so subsequent processes cause less damage to the dummy sidewall 220, making the dummy sidewall 220 compatible with subsequent processes. Silicon oxide is also an easily removable material, facilitating subsequent removal of the dummy sidewall 220.

[0041] It should be noted that after the dummy sidewall 220 is subsequently removed, a gap is formed at the position of the dummy sidewall 220, and a sidewall is formed in the gap. When the width of the dummy sidewall 220 is too small, it is difficult for the sidewall material to fill the gap, resulting in poor effect of reducing the effective capacitance between the gate structure and the source / drain plug. When the width of the dummy sidewall 220 is too large, the distance between the source / drain doped region 110 and the subsequent gate structure is too large, resulting in an excessively large channel length, which in turn leads to an excessively large device size, making it difficult to meet the development needs of device miniaturization. To this end, in this embodiment, in a direction parallel to the surface of the substrate 100 and perpendicular to the sidewall of the dummy gate structure 200, the width of the dummy sidewall 220 is 2 nanometers to 12 nanometers. For example, the width of the dummy sidewall 220 is 5 nanometers, 7 nanometers, or 10 nanometers.

[0042] Specifically, the steps of forming the dummy spacer 220 include: forming a dummy spacer material layer (not shown) that conformally covers the dummy gate structure 200 and the substrate 100; removing the dummy spacer material layer on both sides of the dummy gate structure 200 to expose a portion of the substrate 100 on both sides of the dummy gate structure 200, with the remaining dummy spacer material layer serving as the dummy spacer 220. By removing the dummy spacer material layer on both sides of the dummy gate structure 200, a portion of the substrate 100 on both sides of the dummy gate structure 200 is exposed, thereby preparing for the subsequent formation of the source and drain doped regions 110. Accordingly, in this embodiment, the dummy spacer 220 also covers the top of the dummy gate structure 200.

[0043] It should also be noted that, before forming the dummy spacer material layer, the formation method further includes: forming an offset spacer 210 that conformally covers the dummy gate structure 200 and the substrate 100. The offset spacer 210 is used to increase the channel length of the formed transistor, thereby improving the short channel effect and the hot carrier effect caused by the short channel effect. Accordingly, in order to form the source and drain doped regions, after forming the dummy spacer 220, the offset spacer 210 exposed by the dummy spacer 220 is removed. Therefore, the remaining offset spacer 210 is located between the dummy spacer 220 and the dummy gate structure 200, and between the dummy spacer 220 and the substrate 100.

[0044] The offset spacer 210 is made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride oxynitride, silicon boron oxynitride, or silicon carbon boron oxynitride. In this embodiment, the offset spacer 210 is made of silicon nitride.

[0045] Continue to refer Figure 6 After forming the dummy sidewalls 220, source and drain doping regions 110 are formed in the substrate 100 on both sides of the dummy gate structure 200. Specifically, the source and drain doping regions 110 are located in the device region 100b (eg Figure 5 The source-drain doped region 110 serves as the source region or drain region of the formed transistor.

[0046] In this embodiment, an epitaxial process is used to form the source-drain doped regions 110. Specifically, the steps of forming the source-drain doped regions 110 include: using the dummy sidewalls 220 as a mask, etching the substrate 100 on both sides of the dummy gate structure 200 to form grooves; using an epitaxial process to form an epitaxial layer in the grooves, and in situ self-doping ions during the formation of the epitaxial layer, the epitaxial layer doped with ions serves as the source-drain doped regions 110. When forming an NMOS transistor, the epitaxial layer is made of Si or SiC, and the epitaxial layer provides tensile stress to the channel region of the NMOS transistor, thereby facilitating improvement of the carrier mobility of the NMOS transistor. The doped ions in the epitaxial layer are N-type ions, and the N-type ions include P ions, As ions, or Sb ions. When forming a PMOS transistor, the material of the epitaxial layer is Si or SiGe, and the epitaxial layer provides compressive stress for the channel region of the PMOS transistor, thereby facilitating improvement of the carrier mobility of the PMOS transistor. The doped ions in the epitaxial layer are P-type ions, and the P-type ions include B ions, Ga ions, or In ions.

[0047] refer to Figure 7 After forming the source and drain doped regions 110 , a contact etch stop layer (CESL) 300 is formed to conformally cover the dummy spacers 220 , the dummy gate structure 200 and the substrate 100 .

[0048] The subsequent process of forming source / drain plugs in contact with the source / drain doped regions 110 includes etching a bottom dielectric layer. During the etching of the bottom dielectric layer, the contact hole etch stop layer 300 is used to define the etching stop position, thereby preventing over-etching of the source / drain doped regions 110. Accordingly, a high etching selectivity is achieved between the contact hole etch stop layer 300 and the subsequently formed bottom dielectric layer. The material of the contact hole etch stop layer 300 includes a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6), or silicon nitride.

[0049] It should be noted that after source / drain plugs are subsequently formed on the source / drain doped regions 110, the contact etch stop layer 300 is also located between the source / drain plugs and the gate structure. Therefore, the contact etch stop layer 300 also affects the effective capacitance between the source / drain plugs and the gate structure. The smaller the dielectric constant of the contact etch stop layer 300, the smaller the effective capacitance between the source / drain plugs and the gate structure. Therefore, in this embodiment, to reduce the dielectric constant of the contact etch stop layer 300, the material of the contact etch stop layer 300 is a low-k dielectric material or an ultra-low-k dielectric material.

[0050] In this embodiment, an anti-diffusion layer 310 is further formed between the dummy sidewall spacer 220 and the contact hole etch stop layer 300. The anti-diffusion layer 310 is used to prevent easily diffusible ions in the dummy sidewall spacer 220 from diffusing into the contact hole etch stop layer 300, thereby preventing the dielectric constant of the contact hole etch stop layer 300 from increasing due to ion diffusion.

[0051] Specifically, the contact hole etch stop layer 300 is made of a low-k dielectric material or an ultra-low-k dielectric material, and the dummy sidewall spacer 220 is made of an oxygen-containing material (e.g., silicon oxide). When oxygen ions diffuse into the contact hole etch stop layer 300, the dielectric constant of the contact hole etch stop layer 300 increases. Therefore, forming an anti-diffusion layer 310 between the dummy sidewall spacer 220 and the contact hole etch stop layer 300 reduces the probability of the dielectric constant of the contact hole etch stop layer 300 increasing. As a result, the density of the anti-diffusion layer 310 is high. Furthermore, the anti-diffusion layer 310 is subsequently retained, and therefore, the material of the anti-diffusion layer 310 is an insulating material. Specifically, the material of the anti-diffusion layer 310 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, boron carbonitride, aluminum oxide, and aluminum nitride. As an example, the material of the anti-diffusion layer 310 is silicon nitride.

[0052] It should be noted that the anti-diffusion layer 310 is also located between the source-drain plug and the gate structure, and the anti-diffusion layer 310 will also affect the effective capacitance between the source-drain plug and the gate structure. The dielectric constant of the material of the anti-diffusion layer 310 is relatively large. Therefore, when the thickness of the anti-diffusion layer 310 is too large, it is easy to cause the effective capacitance between the source-drain plug and the gate structure to be too large. Moreover, it will also cause the distance between the source-drain doped region 110 and the gate structure to be too large, resulting in an excessively large channel length, which in turn leads to an excessively large device size, making it difficult to meet the development needs of device miniaturization. Therefore, while ensuring the anti-diffusion effect of the anti-diffusion layer 310 on ions, taking into account the above-mentioned effects, the thickness of the anti-diffusion layer 310 is less than or equal to 30Å.

[0053] In this embodiment, the thickness of the anti-diffusion layer 310 is less than or equal to 15 Å. This ensures that the anti-diffusion layer 310 can prevent ion diffusion while reducing the effective capacitance between the source / drain plug and the gate structure. However, if the thickness of the anti-diffusion layer 310 is too small, the anti-diffusion layer 310's ability to prevent ion diffusion may be impaired. Therefore, in this embodiment, the thickness of the anti-diffusion layer 310 is between 5 Å and 15 Å. For example, the thickness of the anti-diffusion layer 310 is 10 Å.

[0054] In this embodiment, after forming the source / drain doping region 110 and before forming the contact hole etch stop layer 300, an anti-diffusion layer 310 is formed to conformally cover the dummy sidewall 220, the dummy gate structure 200 and the substrate 100, and the contact hole etch stop layer 300 is correspondingly formed on the anti-diffusion layer 310.

[0055] The process for forming the anti-diffusion layer 310 includes an atomic layer deposition process, a chemical vapor deposition process, or a plasma-enhanced chemical vapor deposition process. In this embodiment, the anti-diffusion layer 310 is formed using the atomic layer deposition process. The thickness of the anti-diffusion layer 310 is relatively small. By using the atomic layer deposition process, it is easy to form the anti-diffusion layer 310 with a relatively small thickness, and the thickness uniformity of the anti-diffusion layer 310 is good. In addition, the anti-diffusion layer 310 has good step coverage.

[0056] refer to Figure 8 After forming the contact hole etching stop layer 300 , a bottom dielectric layer 101 is formed on the substrate 100 at the side of the dummy gate structure 200 .

[0057] The bottom dielectric layer 101 is used to isolate adjacent devices. In this embodiment, the bottom dielectric layer 101 is an interlayer dielectric (ILD). The material of the bottom dielectric layer 101 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. As an example, the material of the bottom dielectric layer 101 is silicon oxide.

[0058] Specifically, the bottom dielectric layer 101 is formed through a deposition and planarization process (e.g., a chemical mechanical polishing process) such that the bottom dielectric layer 101 exposes the top of the dummy gate structure 200. In this embodiment, the top of the bottom dielectric layer 101 is flush with the top of the dummy gate structure 200. During the formation of the bottom dielectric layer 101, the contact hole etch stop layer 300, the anti-diffusion layer 310, the dummy spacer 220, and the offset spacer 210 that are above the dummy spacer 220 and the top of the dummy gate structure 200 are removed.

[0059] Combined with reference Figure 9 and Figure 10 , remove the dummy gate structure 200, and form a gate opening 102 in the bottom dielectric layer 101 (eg Figure 9 As shown); a gate structure 400 is formed in the gate opening 102 (as shown Figure 10 shown).

[0060] Accordingly, the gate structure 400 is located in the device region 100b (eg Figure 5As shown in FIG, a bottom dielectric layer 101 is formed on the substrate 100 where the gate structure 400 is exposed, and the bottom dielectric layer 101 covers the source and drain doped regions 110.

[0061] When the transistor is operating, the gate structure 400 is used to control whether the conductive channel is turned on or off. Specifically, the gate structure 400 is a metal gate structure and includes a high-k gate dielectric layer (not shown) conformally covering the bottom and sidewalls of the gate opening 102, a work function layer (not shown) located on the high-k gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer.

[0062] The high-k gate dielectric layer is made of a high-k dielectric material, where a high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3. As an example, the material of the high-k gate dielectric layer is HfO2.

[0063] The work function layer is used to adjust the threshold voltage of the formed transistor. When forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN. When forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC.

[0064] The gate electrode layer is used to electrically lead out the gate structure 200. In this embodiment, the gate electrode layer is made of Al, Cu, Ag, Au, Pt, Ni, Ti or W.

[0065] It should be noted that the dummy spacer 220 has high density and hardness. Therefore, the process of removing the dummy gate structure 200 causes less damage to the dummy spacer 220 .

[0066] refer to Figure 11 After forming the gate structure 400, the forming method further includes: in the device region 100b (such as Figure 5 As shown in FIG, a bottom source-drain plug 120 is formed which penetrates the bottom dielectric layer 101 above the source-drain doped region 110 and contacts the source-drain doped region 110, and a source-drain capping layer 130 is located on the top surface of the bottom source-drain plug 120.

[0067] In this embodiment, a top source-drain plug contacting the bottom source-drain plug 120 is subsequently formed on the bottom source-drain plug 120 , and the top source-drain plug and the bottom source-drain plug 120 constitute a source-drain plug.

[0068] In this embodiment, the bottom source / drain plug 120 is made of copper. Copper has a low resistivity, which helps improve signal delay in the back-end RC circuit and increase chip processing speed. It also helps reduce the resistance of the bottom source / drain plug 120, thereby reducing power consumption. In other embodiments, the bottom source / drain plug can also be made of a conductive material such as tungsten or cobalt.

[0069] Subsequently, the bottom dielectric layer 101 (such as Figure 10 After forming a sacrificial dielectric layer on the substrate (as shown), a gate plug in contact with the gate structure 400 is formed in the sacrificial dielectric layer on top of the gate structure 400 in the active area (AA). The source / drain capping layer 130 is located on the top surface of the bottom source / drain plug 120 and is used to protect the bottom source / drain plug 120 during the formation of the gate plug, thereby reducing the probability of damage to the bottom source / drain plug 120 and short circuit between the gate plug and the bottom source / drain plug 120.

[0070] The source / drain capping layer 130 is made of a material having a high etching selectivity with respect to the gate capping layer, the dummy sidewall 220, the bottom dielectric layer 101, and the subsequently formed sacrificial dielectric layer, so as to ensure that the source / drain capping layer 130 can protect the bottom source / drain plug 120. In this embodiment, the material of the source / drain capping layer 130 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. Specifically, the material of the source / drain capping layer 130 is different from that of the gate capping layer, and the material of the source / drain capping layer 130 is different from that of the dummy sidewall 220. As an example, the material of the source / drain capping layer 130 is silicon carbide.

[0071] In this embodiment, the source / drain capping layer 130 is flush with the top surface of the bottom dielectric layer 101. Figure 11 This is a cross-sectional view at the device region 100b, and therefore, the isolation region 100a (eg, Figure 5 As shown in FIG. 1 ).

[0072] In this embodiment, the formation method further includes: forming a gate cap layer 410 located on the top surface of the gate structure 400. When the top source and drain plugs are subsequently formed, the gate cap layer 410 is used to protect the gate structure 400, thereby reducing the probability of damage to the gate structure 400 and short circuit between the top source and drain plugs and the gate structure 400 during the process of forming the top source and drain plugs. Specifically, the gate structure 400 is etched back to remove a portion of the thickness of the gate structure 400; after removing a portion of the thickness of the gate structure 400, a gate cap layer 410 is formed on the top of the remaining gate structure 400. In this embodiment, the gate cap layer 410 is flush with the top surface of the bottom dielectric layer 101.

[0073] The gate capping layer 410 is made of a material that has etching selectivity with the source / drain capping layer 130, the bottom dielectric layer 101, and the subsequently formed sacrificial dielectric layer, thereby ensuring that the gate capping layer 410 can protect the gate structure 400. In this embodiment, the material of the gate capping layer 410 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the gate capping layer 410 is silicon nitride.

[0074] refer to Figure 12 A sacrificial dielectric layer 140 is formed on top of the source / drain doped region 110 and the gate structure 400 .

[0075] Specifically, the sacrificial dielectric layer 140 is formed on the bottom dielectric layer 101. The sacrificial dielectric layer 140 is used to provide a process basis for the subsequent formation of top source and drain plugs and gate plugs.

[0076] The material of the sacrificial dielectric layer 140 is an insulating material. Moreover, the sacrificial dielectric layer 140 will be etched later, so the sacrificial dielectric layer 140 is selected from a material that is easy to etch. The material of the sacrificial dielectric layer 140 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, boron nitride, aluminum oxide, and aluminum nitride. In this embodiment, the material of the sacrificial dielectric layer 140 is the same as the material of the dummy sidewall 220, which facilitates the subsequent etching of the sacrificial dielectric layer 140 and the dummy sidewall 220 in the same etching step. Accordingly, in this embodiment, the material of the sacrificial dielectric layer 140 is silicon oxide.

[0077] Combined with reference Figure 13 and Figure 14 , forming source-drain plugs 180 (such as Figure 14 As shown), it penetrates the sacrificial dielectric layer 140 above the top of the source / drain doped region 110 and contacts the source / drain doped region 110.

[0078] Source / drain plugs 180 are used to electrically connect the source / drain doped regions 110 to external circuits or other interconnect structures. In this embodiment, the steps of forming source / drain plugs 180 include: forming a top source / drain plug 122 that penetrates the sacrificial dielectric layer 140 and the source / drain capping layer 130 above the top of the source / drain doped regions 110; forming a top source / drain plug 125 that contacts the bottom source / drain plug 120; and forming the top source / drain plug 122 and the bottom source / drain plug 120 to form the source / drain plug 180.

[0079] Specifically, if Figure 13 As shown, the sacrificial dielectric layer 140 and the source / drain capping layer 130 on the top of the source / drain doped region 110 are sequentially etched to form source / drain contact holes 160 exposing the bottom source / drain plugs 120; Figure 14As shown, a top source-drain plug 122 is formed in the source-drain contact hole 160. The detailed description of the material of the top source-drain plug 122 can be combined with the above description of the bottom source-drain plug 120, which will not be repeated here.

[0080] In this embodiment, the forming method further includes: forming a gate plug 170 (such as Figure 14 As shown), the sacrificial dielectric layer 140 and the gate cap layer 410 (as shown) on the top of the gate structure 400 are penetrated. Figure 12 ), and in contact with the gate structure 400.

[0081] Gate plug 170 is used to electrically connect gate structure 400 to external circuits or other interconnect structures. In this embodiment, gate plug 170 is formed above gate structure 400 in the active region. Gate plug 170 is a contact over active gate (COAG). Compared to solutions where the gate plug contacts the gate structure located in the isolation region, this embodiment omits the portion of gate structure 400 located in the isolation region, which helps save chip area and further reduce chip size. A detailed description of the materials used for gate plug 170 can be found in conjunction with the aforementioned description of bottom source and drain plug 120 and is not repeated here.

[0082] Specifically, if Figure 13 As shown, the sacrificial dielectric layer 140 and the gate cap layer 410 on the top of the gate structure 400 are sequentially etched to form a gate contact hole 150 exposing the top of the gate structure 400; Figure 14 As shown, a gate plug 170 is formed in the gate contact hole 150 .

[0083] In this embodiment, after forming the source / drain contact holes 160 and the gate contact holes 150, the top source / drain plugs 125 and the gate plug 170 are formed in the same step. It should be noted that in this embodiment, the gate plug 170 is formed before etching the sacrificial dielectric layer 140, thereby reducing the modification of the current process and improving the process compatibility of the formation method.

[0084] refer to Figure 15 After forming the source / drain plugs 180, the sacrificial dielectric layer 140 is etched until the dummy sidewalls 220 are exposed (eg Figure 13 after exposing the top of the dummy sidewall 220, the dummy sidewall 220 is removed to form a gap 190 between the contact hole etch stop layer 300 and the sidewall of the gate structure 400.

[0085] The gap 190 is used to provide a space for the subsequent formation of sidewalls.

[0086] In this embodiment, the step of etching the sacrificial dielectric layer 140 until the top of the dummy sidewall 220 is exposed includes: removing the device region 100b (eg Figure 5 By removing only the sacrificial dielectric layer 140 of the device region 100b, the impact on the isolation region 100a (as shown) is reduced. Figure 5 The top dielectric layer filling the space between the source and drain plugs 180 is subsequently formed. In this embodiment, only the sacrificial dielectric layer 140 is etched, and the bottom dielectric layer 101 is not etched. Accordingly, the top dielectric layer fills the space between the top source and drain plugs 125. The depth-to-width ratio of the space filled by the top dielectric layer is small, which reduces the process difficulty of forming the top dielectric layer and is conducive to improving the formation quality of the top dielectric layer.

[0087] In this embodiment, an isotropic etching process is used to remove the sacrificial dielectric layer 140 and the dummy sidewall spacer 220 in the device region 100b. By using the isotropic etching process, the sacrificial dielectric layer 140 and the dummy sidewall spacer 220 in the device region 100b can be completely removed, and the etching rate is relatively fast.

[0088] In this embodiment, the isotropic etching process is a remote plasma etching process. The remote plasma etching process has isotropic etching characteristics, and the remote plasma etching process also has good etching selectivity, thereby reducing the loss of other film layers during the etching process. The principle of the remote plasma etching process is to form plasma outside the etching chamber (for example, by generating plasma through a remote plasma generator), and then introduce it into the etching chamber and use the chemical reaction between the plasma and the etched layer to etch, thereby achieving an isotropic etching effect, and because there is no ion bombardment, other film layers will not be damaged. In other embodiments, the isotropic etching process may also be a wet etching process.

[0089] It should be noted that the sacrificial dielectric layer 140 and the dummy sidewall spacer 220 are made of the same material. Therefore, the sacrificial dielectric layer 140 and the dummy sidewall spacer 220 in the device region 100 b can be removed in the same etching step, thereby simplifying the process steps.

[0090] refer to Figure 16 , forming a top dielectric layer 500 filled between the source and drain plugs 180, and the top dielectric layer 500 also fills the gap 190 to form a sidewall 510 located in the gap 190, and the dielectric constant of the material of the top dielectric layer 500 is smaller than that of the dummy sidewall 220 (such as Figure 14 Specifically, the top dielectric layer 500 is filled between the source / drain plug 180 and the gate plug 170.

[0091] By removing the dummy sidewall spacer 220 and forming a top dielectric layer 500 with a material having a lower dielectric constant, a sidewall spacer 510 with a material having a lower dielectric constant is formed, thereby reducing the effective capacitance between the gate structure 400 and the source / drain plug 180 (specifically, the bottom source / drain plug 120), thereby improving the performance of the semiconductor structure.

[0092] In this embodiment, the material of the top dielectric layer 500 includes a low-k dielectric material or an ultra-low-k dielectric material. Therefore, the dielectric constant of the material of the spacer 510 is relatively low, thereby reducing the effective capacitance between the gate structure 400 and the source / drain plug 180. Moreover, in this embodiment, to further reduce the transistor area, a contact over active gate (COAG) process is introduced. The distance between the gate plug 170 and the source / drain plug 180 is correspondingly reduced, and the top dielectric layer 500 is filled between the source / drain plug 180. Therefore, by forming the top dielectric layer 500 with a material having a low dielectric constant, the parasitic capacitance between the gate plug 170 and the source / drain plug 180 is also reduced. Furthermore, by forming the top dielectric layer 500 with a material having a low dielectric constant, the RC delay of the interconnect structure in the integrated circuit is also reduced.

[0093] In other embodiments, when the aspect ratio (AR) of the gap is large, the top dielectric layer seals the top of the gap to form an air gap. Air has a small dielectric constant, which can correspondingly reduce the effective capacitance between the gate structure and the source / drain plug.

[0094] In this embodiment, a spin coating process is used to form the top dielectric layer 500. The spin coating process has a relatively low process temperature, thereby avoiding the channel degradation problem caused by high temperatures, which is beneficial for improving the performance of the semiconductor structure. In other embodiments, the top dielectric layer may also be formed using chemical vapor deposition, fluid chemical vapor deposition, or atomic layer deposition.

[0095] In this embodiment, the top dielectric layer 500 covers the top of the source / drain plug 180. Subsequent processes also include forming a metal interconnect electrically connected to the source / drain plug 180 on top of the source / drain plug 180. The metal interconnect is formed in an intermetallic dielectric (IMD) layer. By having the top dielectric layer 500 cover the top of the source / drain plug 180, the top dielectric layer 500 above the top of the source / drain plug 180 serves as an intermetallic dielectric layer, thereby simplifying the back-end-of-line (BEOL) process steps. In other embodiments, the top of the top dielectric layer is flush with the top of the source / drain plug, or the top of the top dielectric layer is lower than the top of the source / drain plug. This allows for flexible selection of the material of the intermetallic dielectric layer to meet the performance requirements of the semiconductor structure.

[0096] It should be noted that in this embodiment, the COAG process is used as an example for description. In other embodiments, when the gate plug is located on top of the gate structure in the isolation region, the method can still achieve the effect of reducing the effective capacitance between the source / drain plug and the gate structure.

[0097] Accordingly, the present invention also provides a semiconductor structure. Figure 16 , showing a structural schematic diagram of an embodiment of a semiconductor structure of the present invention.

[0098] The semiconductor structure includes: a substrate 100; a gate structure 400 located on the substrate 100; source-drain doped regions 110 located in the substrate 100 on both sides of the gate structure 400; a contact hole etch stop layer 300 located on the substrate 100 between the source-drain doped regions 110 and the gate structure 400 and disposed opposite to the sidewalls of the gate structure 400, with a gap 190 (such as Figure 14 As shown); source-drain plugs 180 are located on top of and in contact with the source-drain doped regions 110; a top dielectric layer 500 is filled between the source-drain plugs 180. The top dielectric layer 500 also fills the gap 190. The top dielectric layer 500 located in the gap 190 serves as a sidewall 510, or the top dielectric layer 500 seals the top of the gap 190 to form an air gap. The material of the top dielectric layer 500 is a low-k dielectric material or an ultra-low-k dielectric material.

[0099] In this embodiment, the substrate 100 is a planar substrate. In other embodiments, the substrate includes a substrate and a fin protruding from the substrate. In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate can also be a substrate of other material types. For example, the substrate material can be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0100] like Figure 5 As shown, Figure 5 This is a top view. In this embodiment, the substrate 100 includes a device region 100b and an isolation region 100a. The device region 100b is used to form a transistor, and the remaining area outside the device region 100b is the isolation region 100a. In this embodiment, the device region 100b is an active region.

[0101] in, Figure 16 is based on Figure 5 Cross-sectional view at the A1A2 secant line.

[0102] The gate structure 400 is located on the substrate 100 in the device region 100b and is used to control the on / off state of the conductive channel. Specifically, the gate structure 400 is a metal gate structure comprising a high-k gate dielectric layer (not shown), a work function layer (not shown) located on the high-k gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer. A detailed description of the gate structure 400 can be found in conjunction with the corresponding description of the preceding embodiments and will not be repeated here.

[0103] It should be noted that the semiconductor structure further includes an offset spacer 210 located on the sidewall of the gate structure 400 exposed in the gap 190. The offset spacer 210 is used to increase the channel length of the formed transistor, thereby improving the short channel effect and the hot carrier effect caused by the short channel effect. The material of the offset spacer 210 is silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride-carbon, silicon oxynitride-boron, or silicon oxynitride-carbon-boron. In this embodiment, the material of the offset spacer 210 is silicon nitride.

[0104] In this embodiment, in the method for forming the semiconductor structure, the gap 190 is formed by removing the dummy spacer, and the offset spacer 210 is formed before forming the dummy spacer. Therefore, the offset spacer 210 also extends to cover the bottom of the gap 190 .

[0105] The source-drain doped region 110 is located in the device region 100b, and the source-drain doped region 110 serves as the source region or drain region of the transistor being formed. The source-drain doped region 110 is formed by an epitaxial process, and the source-drain doped region 110 includes an epitaxial layer doped with ions. When the semiconductor structure is an NMOS transistor, the material of the epitaxial layer is Si or SiC, and the doped ions in the epitaxial layer are N-type ions, including P ions, As ions, or Sb ions. When the semiconductor structure is a PMOS transistor, the material of the epitaxial layer is Si or SiGe, and the doped ions in the epitaxial layer are P-type ions, including B ions, Ga ions, or In ions.

[0106] In this embodiment, the semiconductor structure further includes: a bottom dielectric layer 101 (such as Figure 9 As shown), the bottom dielectric layer 101 is located on the substrate 100 at the side of the gate structure 400 and covers the source and drain doped regions 110.

[0107] Bottom dielectric layer 101 is used to isolate adjacent devices. In this embodiment, bottom dielectric layer 110 is an interlayer dielectric layer. Bottom dielectric layer 101 is made of an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. As an example, bottom dielectric layer 101 is made of silicon oxide.

[0108] During the formation of the semiconductor structure, the contact hole etch stop layer 300 covers the sidewalls of the dummy sidewalls, and the gap 190 is formed by removing the dummy sidewalls. Therefore, the contact hole etch stop layer 300 is located on the substrate 100 between the source and drain doped regions 110 and the gate structure 400 and is arranged opposite to the sidewalls of the gate structure 400. There is a gap 190 between the contact hole etch stop layer 300 and the sidewalls of the gate structure 400.

[0109] The process of forming source / drain plugs 180 includes etching the bottom dielectric layer 101. During the etching of the bottom dielectric layer 101, a contact hole etch stop layer 300 is used to define the etching stop position, thereby preventing over-etching of the source / drain doped regions 110. Accordingly, a high etching selectivity is achieved between the contact hole etch stop layer 300 and the bottom dielectric layer 101. The material of the contact hole etch stop layer 300 includes a low-k dielectric material, an ultra-low-k dielectric material, or silicon nitride.

[0110] It should be noted that the contact hole etch stop layer 300 is also located between the source / drain plug 180 and the gate structure 400. Therefore, the contact hole etch stop layer 300 also affects the effective capacitance between the source / drain plug 180 and the gate structure 400. The smaller the dielectric constant of the material of the contact hole etch stop layer 300, the smaller the effective capacitance between the source / drain plug 180 and the gate structure 400. Therefore, in this embodiment, in order to reduce the dielectric constant of the material of the contact hole etch stop layer 300, the material of the contact hole etch stop layer 300 is a low-k dielectric material or an ultra-low-k dielectric material.

[0111] Therefore, in this embodiment, the semiconductor structure further includes: an anti-diffusion layer 310, which is located on the sidewalls of the contact hole etch stop layer 300 exposed by the gap 190. The anti-diffusion layer 310 is used to prevent easily diffusible ions in the dummy sidewalls from diffusing into the contact hole etch stop layer 300, thereby preventing the problem of an increase in the dielectric constant of the contact hole etch stop layer 300 due to ion diffusion. Specifically, the material of the contact hole etch stop layer 300 is a low-k dielectric material or an ultra-low-k dielectric material, and the material of the dummy sidewalls is generally an oxygen-containing material (e.g., silicon oxide). When oxygen ions diffuse into the contact hole etch stop layer 300, the dielectric constant of the contact hole etch stop layer 300 increases. Therefore, the anti-diffusion layer 310 can reduce the probability of the dielectric constant of the contact hole etch stop layer 300 increasing.

[0112] Therefore, the density of the diffusion prevention layer 310 is relatively high, and the material of the diffusion prevention layer 310 is an insulating material. Specifically, the material of the diffusion prevention layer 310 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon oxynitride, boron nitride, boron carbonitride, aluminum oxide, and aluminum nitride. As an example, the material of the diffusion prevention layer 310 is silicon nitride.

[0113] It should be noted that the anti-diffusion layer 310 is also located between the source / drain plug 180 and the gate structure 400. The anti-diffusion layer 310 also affects the effective capacitance between the source / drain plug 180 and the gate structure 400. The dielectric constant of the material of the anti-diffusion layer 310 is relatively large. Therefore, when the thickness of the anti-diffusion layer 310 is too large, it is easy to cause the effective capacitance between the source / drain plug 180 and the gate structure 400 to be too large. Moreover, it will also cause the distance between the source / drain doped region 110 and the gate structure 400 to be too large, resulting in an excessively large channel length, which in turn leads to an excessively large device size, making it difficult to meet the development needs of device miniaturization. Therefore, while ensuring the anti-diffusion layer 310's anti-diffusion effect on ions, taking into account the above-mentioned effects, the thickness of the anti-diffusion layer 310 is less than or equal to 30 Å.

[0114] In this embodiment, the thickness of the anti-diffusion layer 310 is less than or equal to 15 Å, thereby ensuring that the anti-diffusion layer 310 can prevent ion diffusion while reducing the effective capacitance between the source-drain plug 180 and the gate structure 400. However, if the thickness of the anti-diffusion layer 310 is too small, the anti-diffusion layer 310's ability to prevent ion diffusion may be impaired. Therefore, the thickness of the anti-diffusion layer 310 is preferably between 5 Å and 15 Å.

[0115] In this embodiment, the width of the gap 190 in a direction parallel to the surface of the substrate 100 and perpendicular to the sidewalls of the gate structure 400 should not be too small or too large. If the width of the gap 190 is too small, the material of the top dielectric layer 500 is difficult to fill into the gap 190, resulting in poor effect in reducing the parasitic capacitance between the gate structure 400 and the source / drain plug 180. If the width of the gap 190 is too large, the distance between the source / drain doped region 110 and the gate structure 400 is too large, resulting in an excessively large channel length, which in turn leads to an excessively large device size, making it difficult to meet the development requirements of device miniaturization. To this end, in this embodiment, the width of the gap 190 is 2 nanometers to 12 nanometers.

[0116] In this embodiment, during the formation of the semiconductor structure, the anti-diffusion layer 310 is formed after the source-drain doped region 110 is formed and before the contact hole etch stop layer 300 is formed. Therefore, the anti-diffusion layer 310 is also located between the bottom of the contact hole etch stop layer 300 and the substrate 100.

[0117] The source / drain plugs 180 are used to achieve electrical connection between the source / drain doped regions 110 and external circuits or other interconnect structures. In this embodiment, the source / drain plugs 180 are made of copper. In other embodiments, the source / drain plugs may be made of a conductive material such as tungsten or cobalt.

[0118] In this embodiment, the gate plug in the semiconductor structure is a contact over active gate (COAG). Therefore, the source and drain plugs 180 include: a bottom source and drain plug 120, which penetrates the bottom dielectric layer 101 above the source and drain doped region 110 and contacts the source and drain doped region 110; and a top source and drain plug 122, which is located on the bottom source and drain plug 120 and contacts the bottom source and drain plug 120.

[0119] Accordingly, the semiconductor structure further includes a source / drain capping layer 130 located between the top of the bottom source / drain plug 120 and the top dielectric layer 500. The semiconductor structure generally also includes a gate plug located in the top dielectric layer 500 on top of the gate structure 400 in the active region and in contact with the gate structure 400. The source / drain capping layer 130 is located on the top surface of the bottom source / drain plug 120 and is used to protect the bottom source / drain plug 120 during the formation of the gate plug, thereby reducing the probability of damage to the bottom source / drain plug 120 and shorting between the gate plug and the bottom source / drain plug 120.

[0120] The source / drain capping layer 130 is made of a material having a high etch selectivity with the gate capping layer, the dummy sidewall spacer 220, the bottom dielectric layer 101, and the top dielectric layer 500, thereby ensuring that the source / drain capping layer 130 can protect the bottom source / drain plugs 120. In this embodiment, the material of the source / drain capping layer 130 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the source / drain capping layer 130 is silicon carbide.

[0121] In this embodiment, the top surfaces of the source / drain capping layer 130 and the bottom dielectric layer 101 are flush with each other.

[0122] In this embodiment, the semiconductor structure further includes a gate plug 170 located on top of and in contact with the gate structure 400. The gate plug 170 is used to electrically connect the gate structure 400 to an external circuit or other interconnect structure. In this embodiment, the gate plug 170 is located above the gate structure 400 in the active region. In other words, the gate plug 170 is an active gate contact plug. Compared to a solution in which the gate plug contacts the gate structure located in the isolation region, this embodiment omits the portion of the gate structure 400 located in the isolation region, thereby saving chip area and further reducing chip size.

[0123] Accordingly, the semiconductor structure further includes: a gate cap layer 410 (such as Figure 12), located between the top of the gate structure 400 and the top dielectric layer 500. When forming the top source-drain plug 122, the gate cap layer 410 is used to protect the gate structure 400, thereby reducing the probability of damage to the gate structure 400 and short circuit between the top source-drain plug 122 and the gate structure 400 during the process of forming the top source-drain plug 122.

[0124] The gate capping layer 410 is made of a material that has etching selectivity with the source / drain capping layer 130, the bottom dielectric layer 101, and the top dielectric layer 500, thereby ensuring that the gate capping layer 410 can protect the gate structure 400. In this embodiment, the material of the gate capping layer 410 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the gate capping layer 410 is silicon nitride.

[0125] In this embodiment, the top surfaces of the gate cap layer 410 and the bottom dielectric layer 101 are flush with each other.

[0126] In this embodiment, the semiconductor structure further includes: a sacrificial dielectric layer 101 (such as Figure 10 ), located in the isolation area 100a (as shown Figure 5 On the substrate 100 (as shown), the top of the sacrificial dielectric layer 101 is flush with the top of the source / drain plug 180.

[0127] in, Figure 16 This is a cross-sectional view of the device region 100b; therefore, the bottom dielectric layer 101 in the isolation region 100a is not shown. Specifically, the sacrificial dielectric layer 140 is located on the bottom dielectric layer 101. The sacrificial dielectric layer 140 is used to provide a process foundation for forming the top source and drain plugs 122 and the gate plug 170.

[0128] The sacrificial dielectric layer 140 is made of an insulating material. Furthermore, during the formation of the semiconductor structure, etching the bottom dielectric layer 101 provides space for the formation of the top dielectric layer 500. Therefore, the sacrificial dielectric layer 140 is made of a material that is easily etched. The material of the sacrificial dielectric layer 140 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, boron nitride, aluminum oxide, and aluminum nitride. In this embodiment, the sacrificial dielectric layer 140 is made of silicon oxide.

[0129] Accordingly, in this embodiment, the top dielectric layer 500 is located in the device region 100. Therefore, during the formation of the semiconductor structure, only the sacrificial dielectric layer 140 in the device region 100b is removed, thereby reducing the impact on the isolation region 100a (eg, Figure 5 shown).

[0130] In this embodiment, the top dielectric layer 500 is filled between the source / drain plug 180 and the gate plug 170 . Specifically, the top dielectric layer 500 is also filled in the gap 190 , and the top dielectric layer 500 in the gap 190 serves as a spacer 510 .

[0131] The material of the top dielectric layer 500 includes a low-k dielectric material or an ultra-low-k dielectric material. Therefore, the dielectric constant of the material of the spacer 510 is relatively low, thereby reducing the effective capacitance between the gate structure 400 and the source / drain plug 180 (specifically, the bottom source / drain plug 120), thereby improving the performance of the semiconductor structure. Furthermore, in this embodiment, the semiconductor structure utilizes a contact over active gate (COAG), and the distance between the gate plug 170 and the source / drain plug 180 is correspondingly relatively small. The top dielectric layer 500 fills the gap between the source / drain plug 180. Therefore, the use of a top dielectric layer 500 with a relatively low dielectric constant further reduces the parasitic capacitance between the gate plug 170 and the source / drain plug 180. Furthermore, the use of a top dielectric layer 500 with a relatively low dielectric constant can also reduce the RC delay of the interconnect structure in the integrated circuit.

[0132] In other embodiments, when the gap has a large depth-to-width ratio, the top dielectric layer seals the top of the gap to form an air gap. Air has a smaller dielectric constant, which can correspondingly reduce the effective capacitance between the gate structure and the source / drain plug.

[0133] In this embodiment, the top dielectric layer 500 covers the top of the source / drain plug 180. Subsequent processes also include: forming a metal interconnection line electrically connected to the source / drain plug 180 on the top of the source / drain plug 180, the metal interconnection line is formed in the intermetallic dielectric layer. By making the top dielectric layer 500 cover the top of the source / drain plug 180, the top dielectric layer 500 above the top of the source / drain plug 180 serves as the intermetallic dielectric layer, thereby simplifying the process steps of the back-end process. In other embodiments, the top of the top dielectric layer is flush with the top of the source / drain plug, or the top of the top dielectric layer is lower than the top of the source / drain plug, so that the material of the intermetallic dielectric layer can be flexibly selected to meet the performance requirements of the semiconductor structure.

[0134] The semiconductor structure can be formed by the formation method described in the above embodiment, or by other formation methods. For the detailed description of the semiconductor structure of this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0135] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: substrate; a gate structure, located on the substrate; Source and drain doped regions are located in the substrate on both sides of the gate structure; a source-drain plug, located on top of the source-drain doped region and in contact with the source-drain doped region; a contact hole etch stop layer, located on the substrate between the source and drain doped regions and the gate structure and arranged opposite to the sidewall of the gate structure, wherein the top of the contact hole etch stop layer is lower than the top of the source and drain plugs, and a gap is formed between the sidewall of the contact hole etch stop layer and the sidewall of the gate structure; A top dielectric layer is filled between the source and drain plugs. The top dielectric layer also fills the gap. The top dielectric layer in the gap serves as a sidewall. Alternatively, the top dielectric layer seals the top of the gap to form an air gap. The material of the top dielectric layer is a low-k dielectric material or an ultra-low-k dielectric material.

2. The semiconductor structure according to claim 1, wherein The semiconductor structure further includes an anti-diffusion layer located on a sidewall of the contact hole etching stop layer exposed in the gap.

3. The semiconductor structure according to claim 1, wherein: The substrate includes a device region and an isolation region; The gate structure, source and drain doped regions and top dielectric layer are all located in the device region; The semiconductor structure further includes a sacrificial dielectric layer located on the substrate of the isolation region, wherein the top of the sacrificial dielectric layer is flush with the top of the source / drain plug.

4. The semiconductor structure according to claim 1, wherein: The semiconductor structure further comprises: a bottom dielectric layer located on the substrate at the side of the gate structure, the bottom dielectric layer covering the source and drain doped regions; The source-drain plugs include: a bottom source-drain plug, which penetrates the bottom dielectric layer above the source-drain doped region and contacts the source-drain doped region; and a top source-drain plug, which is located on the bottom source-drain plug and contacts the bottom source-drain plug. The semiconductor structure further includes: a source-drain capping layer located between the top of the bottom source-drain plug and the top dielectric layer; a gate plug located on the top of the gate structure and in contact with the gate structure; and a gate capping layer located between the top of the gate structure and the top dielectric layer. The top dielectric layer is filled between the source / drain plugs and the gate plug.

5. The semiconductor structure according to claim 1, wherein The top dielectric layer covers the top of the source / drain plug; Alternatively, the top of the top dielectric layer is flush with the top of the source / drain plug; Alternatively, the top of the top dielectric layer is lower than the top of the source / drain plug.

6. The semiconductor structure according to claim 1, wherein In a direction parallel to the substrate surface and perpendicular to the sidewall of the gate structure, the width of the gap is 2 nanometers to 12 nanometers.

7. The semiconductor structure according to claim 1, wherein: The material of the contact hole etch stop layer is a low-k dielectric material, an ultra-low-k dielectric material or silicon nitride.

8. The semiconductor structure according to claim 2, wherein: The material of the diffusion prevention layer includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride, boron carbonitride, aluminum oxide and aluminum nitride.

9. The semiconductor structure according to claim 2, wherein: The thickness of the diffusion prevention layer is less than or equal to 10. The semiconductor structure according to claim 9, wherein: The thickness of the diffusion prevention layer is to 11. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein a gate structure is formed on the substrate, dummy sidewalls are formed on the sidewalls of the gate structure, contact hole etching stop layers are formed on the sidewalls of the dummy sidewalls, and source and drain doped regions are formed in the substrate on both sides of the gate structure; forming a sacrificial dielectric layer above the source / drain doped regions and the top of the gate structure, wherein the sacrificial dielectric layer also covers the top of the dummy sidewalls and the contact hole etching stop layer; forming source-drain plugs penetrating the sacrificial dielectric layer above the top of the source-drain doped region and contacting the source-drain doped region; After forming the source / drain plugs, etching the sacrificial dielectric layer until the top of the dummy sidewall is exposed; After exposing the top of the dummy sidewall, removing the dummy sidewall to form a gap between the contact hole etch stop layer and the sidewall of the gate structure; A top dielectric layer is formed to fill between the source and drain plugs. The top dielectric layer also fills the gap to form a sidewall in the gap. Alternatively, the top dielectric layer seals the top of the gap to form an air gap. The material dielectric constant of the top dielectric layer is smaller than the material dielectric constant of the dummy sidewall.

12. The method for forming a semiconductor structure according to claim 11, wherein: In the step of providing a substrate, an anti-diffusion layer is formed between the dummy sidewalls and the contact hole etching stop layer.

13. The method for forming a semiconductor structure according to claim 11, wherein: The substrate includes a device region and an isolation region, and the gate structure, dummy sidewalls and source / drain doping regions are located in the device region; In the step of etching the sacrificial dielectric layer until the top of the dummy sidewall spacer is exposed, the sacrificial dielectric layer located in the device area is removed.

14. The method for forming a semiconductor structure according to claim 11, wherein: In the step of providing a substrate, a bottom dielectric layer is formed on the substrate where the gate structure is exposed, and the bottom dielectric layer covers the source and drain doped regions; Before forming the sacrificial dielectric layer, the formation method further includes: forming a bottom source-drain plug penetrating the bottom dielectric layer above the source-drain doped region and contacting the source-drain doped region, and a source-drain capping layer located on top of the bottom source-drain plug; removing a portion of the thickness of the gate structure and forming a gate capping layer on top of the remaining gate structure; The step of forming the source-drain plug includes: forming a top source-drain plug penetrating the sacrificial dielectric layer and the source-drain cap layer above the top of the source-drain doped region, wherein the top source-drain plug contacts the bottom source-drain plug, and the top source-drain plug and the bottom source-drain plug constitute a source-drain plug; After forming the sacrificial dielectric layer, etching the sacrificial dielectric layer until the top of the dummy sidewall is exposed, the forming method further includes: forming a gate plug that penetrates the sacrificial dielectric layer and the gate cap layer above the top of the gate structure and contacts the gate structure; In the step of forming the top dielectric layer, the top dielectric layer is filled between the source / drain plugs and the gate plug.

15. The method for forming a semiconductor structure according to claim 11, wherein: In the step of providing a substrate, a bottom dielectric layer is formed on the substrate where the gate structure is exposed, and the bottom dielectric layer covers the source and drain doped regions; Before forming the gate structure, the forming method further includes: forming a dummy gate structure on the substrate; In the step of forming the dummy sidewall spacer, the dummy sidewall spacer is formed on the sidewall of the dummy gate structure; The steps of forming the gate structure include: removing the dummy gate structure, forming a gate opening in the bottom dielectric layer; and forming a gate structure in the gate opening.

16. The method for forming a semiconductor structure according to claim 11, wherein: The material of the sacrificial dielectric layer is the same as that of the dummy sidewall spacer.

17. The method for forming a semiconductor structure according to claim 11, wherein: The material of the dummy sidewall spacer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, boron nitride, aluminum oxide and aluminum nitride.

18. The method for forming a semiconductor structure according to claim 11, wherein: The material of the contact hole etch stop layer is a low-k dielectric material, an ultra-low-k dielectric material or silicon nitride.

19. The method for forming a semiconductor structure according to claim 11, wherein: The material of the sacrificial dielectric layer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, boron nitride, aluminum oxide and aluminum nitride.

20. The method for forming a semiconductor structure according to claim 11, wherein: The sacrificial dielectric layer is etched by an isotropic etching process until the top of the dummy sidewall is exposed and the dummy sidewall is removed. The isotropic etching process includes a remote plasma etching process or a wet etching process.

21. The method for forming a semiconductor structure according to claim 11, wherein: The top dielectric layer is formed by using a spin coating process, a chemical vapor deposition process, a fluid chemical vapor deposition process or an atomic layer deposition process.

22. The method for forming a semiconductor structure according to claim 11, wherein: The material of the top dielectric layer includes a low-k dielectric material or an ultra-low-k dielectric material.

23. The method for forming a semiconductor structure according to claim 12, wherein: The process of forming the anti-diffusion layer includes an atomic layer deposition process, a chemical vapor deposition process or a plasma enhanced chemical vapor deposition process.

24. The method for forming a semiconductor structure according to claim 12, wherein: The material of the diffusion prevention layer includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride, boron carbonitride, aluminum oxide and aluminum nitride.

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