Image processing device

Abstract

This invention provides an image processing apparatus. Even in the event of data anomalies caused by external factors in the transmission path, it prevents image display corruption. In the image processing apparatus comprising an image control unit and an image display unit, the image control unit includes: a detection circuit that detects whether the input signal meets a predetermined value based on the length and order of a synchronization signal and an image recognition signal included in the input signal, and an error detection code of the image data; and a synchronization signal control circuit that generates a signal for displaying an image on the image display unit and outputs the generated signal to the image display unit. The detection circuit stops the synchronization signal control circuit from outputting a signal to the image display unit when the input signal does not meet the predetermined value, and enables the synchronization signal control circuit to output a signal to the image display unit when the input signal meets the predetermined value.

Description

Technical Field

[0001] The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus that does not present disordered images to the user. Background Technology

[0002] In devices that display still images on a screen, such as user interface units for printing devices, if the image transmission path is affected by static electricity, noise, or other factors, it can sometimes lead to abnormal image data and adverse effects such as image distortion on the screen display unit.

[0003] Patent Document 1 proposes a method in which, in the event of an anomaly in the data to be displayed on the screen display unit, an image is read from a frame memory that stores an image of a screen, and an error in the image data is detected.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2007-72394 Summary of the Invention

[0007] The problem the invention aims to solve

[0008] Here, if there is an error in the synchronization signal other than the image data, the image displayed on the screen display unit will also become disordered.

[0009] However, in cases where data abnormalities occur due to external factors in the transmission path, such as errors in the synchronization signal other than image data, the method described in Patent Document 1 is insufficient to prevent image disorder.

[0010] Furthermore, the method described in Patent Document 1 uses a frame memory, which requires a large memory, thus increasing product costs.

[0011] The present invention was made in view of the following problem, and its object is to provide an image processing apparatus that can prevent the display of images from being disordered even when data abnormalities occur in the transmission path due to external factors.

[0012] Solution for solving the problem

[0013] To achieve the above objectives, the image processing apparatus of the present invention is characterized in that...

[0014] An image processing apparatus includes an image control unit and an image display unit.

[0015] The image control unit includes:

[0016] The detection circuit detects whether the input signal meets the specified value; and

[0017] A synchronization signal control circuit generates a signal for displaying an image on the image display unit and outputs the generated signal to the image display unit.

[0018] If the input signal does not meet the specified value, the detection circuit causes the synchronization signal control circuit to stop outputting signals to the image display unit; if the input signal meets the specified value, the detection circuit causes the synchronization signal control circuit to output signals to the image display unit.

[0019] The input signal includes at least one of the following: a vertical synchronization signal, a horizontal synchronization signal, an image recognition signal, an image signal, the length and order of the vertical synchronization signal, the length and order of the horizontal synchronization signal, the length and order of the image recognition signal, and an error detection code for the image signal.

[0020] The effects of the invention

[0021] According to the features of the image processing apparatus of the present invention, even in the event of data abnormality caused by external factors in the transmission path, it is possible to prevent the display of images from becoming disordered. Attached Figure Description

[0022] Figure 1 This is a block diagram illustrating the hardware structure of an image processing apparatus according to one embodiment of the present invention.

[0023] Figure 2 This is a diagram illustrating an example of parallel data output by a serial-to-parallel conversion circuit of an image processing apparatus according to an embodiment of the present invention.

[0024] Figure 3 This is a diagram illustrating an example of an error occurring in the parallel data output by the serial-to-parallel conversion circuit of an image processing apparatus according to an embodiment of the present invention.

[0025] Figure 4 This is a flowchart illustrating a process in an image processing apparatus according to an embodiment of the present invention for determining whether the order of the vertical synchronization signal, the horizontal synchronization signal, and the image recognition signal is appropriate. Detailed Implementation

[0026] The embodiments of the present invention will now be described with reference to the accompanying drawings. Identical or equivalent parts and components in each drawing are labeled with the same or equivalent reference numerals. However, it should be noted that the drawings are schematic and differ from actual figures. Furthermore, the drawings also include portions with different dimensional relationships and ratios.

[0027] Furthermore, the embodiments shown below are illustrative of apparatuses, etc., used to embody the technical concept of the present invention, and the technical concept of the present invention does not specifically define the arrangement of each component as described below. Various modifications can be made to the technical concept of the present invention within the scope of the claims.

[0028] Figure 1 This is a block diagram illustrating the hardware structure of an image processing apparatus 1 according to one embodiment of the present invention. As shown in this figure, the image processing apparatus 1 includes a printer main unit 2 and a user interface unit 3.

[0029] The printer main unit 2 has black (K), cyan (C), magenta (M), and yellow (Y) inkjet heads, and prints by spraying ink from the inkjet heads onto paper that is conveyed by a transport unit (not shown).

[0030] The printer main unit 2 includes a controller unit 21. The controller unit 21 controls the inkjet head and the conveying unit, and sends serial data (synchronization signal and data mixture) to the user interface unit 3.

[0031] User interface unit 3 has an image control unit 10 and an image display unit 30.

[0032] The image display unit 30 includes an image output device such as an organic EL (electroluminescence) display or a liquid crystal display, and displays images based on data provided by the image control unit 10.

[0033] The image control unit 10 generates data for the image display unit based on the serial data received from the printer main unit 2 and outputs it to the image display unit 30.

[0034] The image control unit 10 includes, in terms of its function, a serial-to-parallel conversion circuit 11, a detection circuit 12, and a synchronization signal control circuit 13.

[0035] The serial-to-parallel conversion circuit 11 generates parallel data by performing a serial-to-parallel conversion on the serial data received from the printer main unit 2, and outputs the generated parallel data to the detection circuit 12 and the synchronization signal control circuit 13. The generated parallel data includes vertical synchronization signals, horizontal synchronization signals, image recognition signals, image signals, the length and order of the vertical synchronization signals, the length and order of the horizontal synchronization signals, the length and order of the image recognition signals, and error detection codes for the image signals.

[0036] The detection circuit 12 detects whether the parallel data meets specified values ​​based on the length and order of the vertical synchronization signal, horizontal synchronization signal, and image recognition signal contained in the parallel data, as well as the error detection code of the image data. The vertical synchronization signal, horizontal synchronization signal, and image recognition signal have a predetermined order and a specified length. Therefore, if the order and length of the vertical synchronization signal, horizontal synchronization signal, and image recognition signal differ from the predetermined order and specified length, the detection circuit 12 detects that the parallel data does not meet the specified values. Furthermore, if the image data contains error detection codes such as Cyclic Redundancy Check (CRC), and these error detection codes are inconsistent with the error detection codes generated based on the received image data, the detection circuit 12 also detects that the parallel data does not meet the specified values.

[0037] Furthermore, when the parallel data does not meet the specified value, the detection circuit 12 causes the synchronization signal control circuit 13 to stop outputting the signal (data for image display unit) to the image display unit 30, and when the parallel data meets the specified value, the synchronization signal control circuit 13 causes the synchronization signal control circuit 13 to output the signal (data for image display unit) to the image display unit 30.

[0038] If the detection circuit 12 determines that the parallel data does not meet the specified value, the synchronization signal control circuit 13 stops outputting signals to the image display unit 30. If the detection circuit 12 determines that the parallel data meets the specified value, the synchronization signal control circuit 13 outputs signals to the image display unit 30.

[0039] Figure 2 This is a diagram illustrating an example of parallel data output by the serial-to-parallel conversion circuit 11 of an image processing apparatus 1 according to an embodiment of the present invention. Figure 2 The parallel data shown represents a signal in a normal state without errors.

[0040] like Figure 2 As shown, the parallel data includes a vertical synchronization signal 101, a horizontal synchronization signal 102, an image recognition signal 103, and an image signal 104.

[0041] Furthermore, the vertical synchronization signal 101, the horizontal synchronization signal 102, and the image recognition signal 103 become asserted (on) in this sequence, and the vertical synchronization signal 101 remains asserted (on) until the specified number of scan lines is met. During the period when the vertical synchronization signal 101 is asserted, the operation is repeated for a specified length in the order of horizontal synchronization signal 102 asserted, image recognition signal 103 asserted, image recognition signal 103 negated (off), and horizontal synchronization signal 102 negated.

[0042] During the active state of the vertical synchronization signal 101, the image signal 104 is repeatedly active and inactive at predetermined intervals. Error detection codes such as Cyclic Redundancy Check (CRC) are appended to the image signal 104.

[0043] Figure 3 This is a diagram illustrating an example of an error occurring in the parallel data output by the serial-to-parallel conversion circuit 11 of the image processing apparatus 1 according to an embodiment of the present invention.

[0044] like Figure 3 As shown, the detection circuit 12 detects whether the parallel data meets the specified values ​​based on the length and order of the vertical synchronization signal 101, the horizontal synchronization signal 102, and the image recognition signal 103 contained in the parallel data, as well as the error detection code of the image signal 104.

[0045] exist Figure 3 In the example shown, at time point t1, the detection circuit 12 detects that the parallel data does not meet the specified value.

[0046] Therefore, after time t1, the detection circuit 12 stops the synchronization signal control circuit 13 from outputting signals to the image display unit 30. At this time, the detection circuit 12 deletes the image after time point t1, which is determined to be the time point where the input signal does not meet the specified value. As a result, the image after time point t1, which is determined to be the time point where the input signal does not meet the specified value, is not displayed, and the image before time point t1 is displayed, thus reliably preventing image disorder.

[0047] Furthermore, after t1, the detection circuit 12 continues to detect whether the parallel data meets the specified values ​​based on the length and order of the vertical synchronization signal 101, the horizontal synchronization signal 102, and the image recognition signal 103 contained in the parallel data, as well as the error detection code of the image signal 104.

[0048] Then, at time point t2, the detection circuit 12 detects that the parallel data meets the specified value.

[0049] However, the detection circuit 12 goes into standby mode from time point t2 without restarting the signal output from the synchronization signal control circuit 13 to the image display unit 30.

[0050] Then, at time point t3, which is the effective time point of the vertical synchronization signal 101, the detection circuit 12 restarts the signal output from the synchronization signal control circuit 13 to the image display unit 30.

[0051] At this time, in the image of frame G101 before the error occurred displayed on the image display unit 30, the image up to the position where the error occurred is overlaid, but in the image of frame G102 after the error occurred, since no abnormal image is displayed, it appears that no disorder has occurred.

[0052] In this way, the image in the image display unit 30 remains in the residual state until time point t3 when the next normal vertical synchronization signal 101 arrives. At time point t3, the new next normal vertical synchronization signal 101 arrives and refreshes the display.

[0053] Figure 4 This is a flowchart illustrating the process of determining whether the order of the vertical synchronization signal 101, the horizontal synchronization signal 102, and the image recognition signal 103 is appropriate in an image processing apparatus 1 according to an embodiment of the present invention.

[0054] like Figure 4 As shown, in step S101, the detection circuit 12 determines whether the vertical synchronization signal 101 becomes valid.

[0055] In step S101, if other signals are generated and the order of the signals is inappropriate, then in step S115, the parallel data is considered not to meet the specified value, and the detection circuit 12 generates an error signal.

[0056] In step S101, if it is determined that the vertical synchronization signal 101 has become valid ("Yes"), the order of the signals is appropriate. Therefore, in step S103, the detection circuit 12 determines whether the horizontal synchronization signal 102 has become valid.

[0057] In step S103, if other signals are generated and the order of the signals is inappropriate, then in step S115, the parallel data is considered not to meet the specified value, and the detection circuit 12 generates an error signal.

[0058] In step S103, if it is determined that the horizontal synchronization signal 102 has become valid ("Yes"), the order of the signals is appropriate. Therefore, in step S105, the detection circuit 12 determines whether the image recognition signal 103 has become valid.

[0059] In step S105, if other signals are generated and the order of the signals is inappropriate, then in step S115, the parallel data is considered not to meet the specified value, and the detection circuit 12 generates an error signal.

[0060] In step S105, if it is determined that the image recognition signal 103 has become valid ("Yes"), the order of the signals is appropriate. Therefore, in step S107, the detection circuit 12 determines whether the image recognition signal 103 has become invalid.

[0061] In step S107, if other signals are generated and the order of the signals is inappropriate, then in step S115, the parallel data is considered not to meet the specified value, and the detection circuit 12 generates an error signal.

[0062] In step S107, if it is determined that the image recognition signal 103 has become invalid ("yes"), the order of the signals is appropriate. Therefore, in step S109, the detection circuit 12 determines whether the horizontal synchronization signal 102 has become invalid.

[0063] In step S109, if other signals are generated and the order of the signals is inappropriate, then in step S115, the parallel data is considered not to meet the specified value, and the detection circuit 12 generates an error signal.

[0064] In step S109, if it is determined that the horizontal synchronization signal 102 has become invalid ("yes"), the signal sequence is appropriate, so in step S111, the detection circuit 12 determines whether the specified number of scan lines has been reached.

[0065] In step S111, if it is determined that the specified number of scan lines has not been reached, the detection circuit 12 causes the processing to proceed to step S103.

[0066] In step S111, if it is determined that the specified number of scan lines has been reached, in step S113, the detection circuit 12 determines whether the vertical synchronization signal 101 has become invalid.

[0067] In this way, the detection circuit 12 determines whether the order of the vertical synchronization signal 101, the horizontal synchronization signal 102, and the image recognition signal 103 is appropriate.

[0068] Furthermore, in an embodiment of the image processing apparatus 1 of the present invention, the detection circuit 12 detects whether the parallel data meets the specified value based on the length and order of the vertical synchronization signal, the horizontal synchronization signal and the image recognition signal contained in the parallel data, and the error detection code of the image data, but is not limited thereto.

[0069] Alternatively, the parallel data may be detected to meet the specified value based on at least one of the following: the length and order of the vertical synchronization signal, the length and order of the horizontal synchronization signal, the length and order of the image recognition signal, and the error detection code of the image data.

[0070] (Postscript)

[0071] This application discloses the following invention.

[0072] (Postscript 1)

[0073] An image processing apparatus includes an image control unit and an image display unit, characterized in that...

[0074] The image control unit includes:

[0075] The detection circuit detects whether the input signal meets the specified value; and

[0076] A synchronization signal control circuit generates a signal for displaying an image on the image display unit and outputs the generated signal to the image display unit.

[0077] If the input signal does not meet the specified value, the detection circuit causes the synchronization signal control circuit to stop outputting signals to the image display unit; if the input signal meets the specified value, the detection circuit causes the synchronization signal control circuit to output signals to the image display unit.

[0078] The input signal includes at least one of the following: a vertical synchronization signal, a horizontal synchronization signal, an image recognition signal, an image signal, the length and order of the vertical synchronization signal, the length and order of the horizontal synchronization signal, the length and order of the image recognition signal, and an error detection code for the image signal.

[0079] Therefore, even in cases where data abnormalities occur due to external factors, such as errors in the synchronization signal other than image data, the input signal can be detected to prevent image distortion from being displayed on the screen or other image display unit of the printing device, thereby improving operability.

[0080] Furthermore, when a frame memory structure is used, new hardware memory needs to be added, which increases the cost. However, in the image processing apparatus 1 according to one embodiment of the present invention, when the detection circuit and the synchronization control signal circuit are added by the program of FPGA (field-programmable gate array), the manufacturing cost can be reduced since no new hardware is added.

[0081] (Postscript 2)

[0082] The image processing apparatus according to Appendix 1 is characterized in that,

[0083] The input signal includes a vertical synchronization signal.

[0084] Therefore, by detecting the vertical synchronization signal, the image displayed on the panel or other image display unit of the printing device is not disturbed, thereby improving operability.

[0085] (Note 3)

[0086] The image processing apparatus according to Appendix 1 is characterized in that,

[0087] The detection circuit detects whether the input signal meets the specified value based on at least one of the length and order of the horizontal synchronization signal contained in the input signal and the length and order of the image recognition signal contained in the input signal.

[0088] Therefore, by detecting at least one of the length and sequence of the horizontal synchronization signal and the length and sequence of the image recognition signal, the disorder of the image displayed on the image display unit such as the panel of the printing device is not presented to the user, thereby improving operability.

[0089] (Postscript 4)

[0090] The image processing apparatus according to Appendix 1 is characterized in that,

[0091] The detection circuit detects whether the error detection code of the image data contained in the input signal meets the specified value.

[0092] Therefore, by detecting error detection codes, the disorder of the image displayed on the panel or other image display section of the printing device is not presented to the user, thereby improving operability.

[0093] In particular, it can prevent image distortion from being presented to the user without increasing hardware resources such as memory by detecting error detection codes, thus suppressing the increase in manufacturing costs. Furthermore, it can detect whether the error detection code meets the specified value at the time of detection, thus identifying errors before image updates and enabling display without image distortion.

[0094] (Note 5)

[0095] The image processing apparatus according to Appendix 1 is characterized in that,

[0096] If the input signal does not meet the specified value, the detection circuit will delete the image after the time point when the input signal is determined to not meet the specified value.

[0097] Therefore, it is possible to prevent image corruption by displaying images after the time point when the input signal is determined to be non-compliant with the specified value, and to maintain the display of images before the time point when the input signal is determined to be non-compliant with the specified value.

[0098] (Note 6)

[0099] The image processing apparatus according to Appendix 1 is characterized in that,

[0100] When the input signal does not meet the specified value, the detection circuit stops the synchronization signal control circuit from outputting signals to the image display unit. After detecting that the input signal of the detection circuit meets the specified value, the restart timing for resuming signal output to the image display unit is set to the timing when the start of the next vertical synchronization signal is detected.

[0101] Therefore, after the input signals, such as the length and sequence of the synchronization signal, the length and sequence of the image recognition signal, or the signal associated with the error detection code of the image data, meet the specified values, the image on the image display unit is updated by an amount of one frame starting from the beginning of the vertical synchronization signal detection timing, thus enabling display without image distortion. That is, although the timing of the image update is delayed by an amount of one frame on the image display unit, the image can be updated reliably.

[0102] Explanation of reference numerals in the attached figures

[0103] 1: Image processing device; 2: Printer main unit; 3: User interface unit; 10: Image control unit; 11: Serial-to-parallel conversion circuit; 12: Detection circuit; 13: Synchronization signal control circuit; 21: Controller unit; 30: Image display unit; 101: Vertical synchronization signal; 102: Horizontal synchronization signal; 103: Image recognition signal; 104: Image signal.

Claims

1. An image processing apparatus comprising an image control unit and an image display unit, characterized in that, The image control unit includes: The detection circuit detects whether the input signal meets the specified value; and A synchronization signal control circuit generates a signal for displaying an image on the image display unit and outputs the generated signal to the image display unit. in, Detecting whether the input signal meets the specified values ​​includes: determining whether the length and order of the horizontal synchronization signal contained in the input signal and the length and order of the image recognition signal contained in the input signal meet the specified length and predetermined order. Specifically, if it is determined that at least one of the length and order of the horizontal synchronization signal included in the input signal, and the length and order of the image recognition signal included in the input signal, does not meet the specified length and predetermined order, the detection circuit causes the synchronization signal control circuit to stop outputting signals to the image display unit. Conversely, if it is determined that the length and order of the horizontal synchronization signal included in the input signal, and the length and order of the image recognition signal included in the input signal, meet the specified length and predetermined order, the detection circuit causes the synchronization signal control circuit to output signals to the image display unit. The input signal includes a vertical synchronization signal, and determining whether the length and order of the horizontal synchronization signal and the image recognition signal included in the input signal meet the specified length and predetermined order includes: during the period when the vertical synchronization signal is valid, determining whether the horizontal synchronization signal and the image recognition signal repeat for a specified length in the order of the horizontal synchronization signal being valid, the image recognition signal being valid, the image recognition signal being invalid, and the horizontal synchronization signal being invalid.

2. The image processing apparatus according to claim 1, characterized in that, The detection circuit detects whether the error detection code of the image data contained in the input signal meets the specified value.

3. The image processing apparatus according to claim 1, characterized in that, If the input signal does not meet the specified value, the detection circuit will delete the image after the time point when the input signal is determined to not meet the specified value.

4. The image processing apparatus according to claim 1, characterized in that, When the input signal does not meet the specified value, the detection circuit stops the synchronization signal control circuit from outputting signals to the image display unit. After detecting that the input signal of the detection circuit meets the specified value, the restart timing for resuming signal output to the image display unit is set to the timing when the start of the next vertical synchronization signal is detected.

Images