A sequence generator and semiconductor chip
By inserting an all-zero state under the condition of the shift register output signal, a sequence generator period of 2n was achieved, which solves the problem of unbalanced number of 0s and 1s in the prior art and improves applicability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-12-14
- Publication Date
- 2026-03-20
AI Technical Summary
The existing m-sequence generator has a period of 2n-1, which results in a different number of 0s and 1s, and cannot meet the needs of some application scenarios.
A sequence generator is designed that uses combinational logic circuits to insert an all-zero state when the output signal of the shift register meets a specific condition, thereby generating a sequence with a period of 2n and ensuring that the number of 0s and 1s is the same.
This improves the applicability of the sequence generator, ensuring that it generates the same number of 0s and 1s within a single cycle, thus enhancing the flexibility of the application.
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Figure CN116009816B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The embodiment of the present application relates to the technical field of integrated circuits, in particular to a sequence generator and a semiconductor chip. BACKGROUND
[0002] The m sequence is the abbreviation of the longest linear shift register sequence, which is the longest code sequence generated by n-stage shift register and its delay element through linear feedback, wherein n is an integer greater than or equal to 2. In the binary shift register, the n-stage shift register has 2 n states, and there are 2 n -1 states except for the all-0 state, therefore, the maximum length of the code sequence generated by the n-stage shift register is 2 n -1 bits, that is, the longest period of an n-stage m sequence is equal to 2 n -1.
[0003] The period of the existing m sequence generator is 2 n -1, that is, the number of 0 and the number of 1 generated in a period are different, and therefore the m sequence generator is not applicable in some application scenarios, and therefore, it is urgent to propose a sequence generator capable of realizing a period of 2 n -1. SUMMARY
[0004] In view of the above problems, the embodiment of the present application provides a sequence generator and a semiconductor chip, which can realize a period of 2 n -1, so that the number of 0 and the number of 1 generated in a period are the same, thereby improving the applicability of the sequence generator.
[0005] In a first aspect, the embodiment of the present application provides a sequence generator, comprising: n cascaded shift registers and a combinational logic circuit, wherein n is an integer greater than or equal to 2;
[0006] n first input ends of the combinational logic circuit are electrically connected with the output ends of the n cascaded shift registers one by one, a second input end of the combinational logic circuit is electrically connected with a first state signal, a third input end of the combinational logic circuit is electrically connected with a second state signal, an output end of the combinational logic circuit is electrically connected with an input end of a first shift register, and clock signal ends of the n cascaded shift registers are all electrically connected with a clock signal;
[0007] The combinational logic circuit is configured to output the first state signal when the output signals of the first shift register to the n-1th shift register are all the first state signal and the output signal of the nth shift register is the second state signal; wherein the first state signal is used to represent a digital signal 0, and the second state signal is used to represent a digital signal 1.
[0008] In some embodiments, the combinational logic circuit comprises a logic circuit and a selection circuit;
[0009] n inputs of the logic circuit are electrically connected to outputs of n cascaded shift registers one by one, a first output of the logic circuit is electrically connected to a first control end of the selection circuit, a second output of the logic circuit is electrically connected to a second control end of the selection circuit, a first input of the selection circuit is electrically connected to the first state signal, and a second input of the selection circuit is electrically connected to the second state signal;
[0010] the logic circuit is configured to control the selection circuit to output the first state signal when the output signals of the first to the n-1th shift registers are all the first state signal and the output signal of the nth shift register is the second state signal.
[0011] In some embodiments, the logic circuit is further configured to control the selection circuit to output the second state signal when the output signals of the first to the nth shift registers are all the first state signal.
[0012] In some embodiments, the combinational logic circuit further comprises an adder;
[0013] m inputs of the adder are electrically connected to outputs of m shift registers one by one, and an output of the adder is electrically connected to a third input of the selection circuit; wherein 1≤m≤n, and m is an integer;
[0014] the adder is configured to perform addition operation on the output signals of the m shift registers and output the least significant data in the addition operation result;
[0015] the logic circuit is further configured to control the selection circuit to output the output signal of the adder based on the output signals of the n cascaded shift registers.
[0016] In some embodiments, the logic circuit comprises a first logic sub-circuit and a second logic sub-circuit;
[0017] n inputs of the first logic sub-circuit are electrically connected to outputs of n cascaded shift registers one by one, n inputs of the second logic sub-circuit are electrically connected to the outputs of the n cascaded shift registers one by one, an output of the first logic sub-circuit is electrically connected to a first control end of the selection circuit, and an output of the second logic sub-circuit is electrically connected to a second control end of the selection circuit;
[0018] The first logic sub-circuit is configured to generate a first control signal based on output signals of the n cascaded shift registers; wherein when the output signals of the first shift register to the n-1th shift register are all the first state signal and the output signal of the n th shift register is the second state signal, the first control signal is the second state signal;
[0019] The second logic sub-circuit is configured to generate a second control signal based on the output signals of the n cascaded shift registers; wherein when the output signals of the first shift register to the n-1th shift register are all the first state signal and the output signal of the n th shift register is the second state signal, the second control signal is the first state signal.
[0020] The selection circuit is configured to output the first state signal when the first control signal is the second state signal and the second control signal is the first state signal.
[0021] In some embodiments, the first logic sub-circuit comprises a first OR gate, a first NOT gate and a second NOT gate.
[0022] The n-1 inputs of the first OR gate are electrically connected to the outputs of the first shift register to the n-1th shift register respectively, the output of the n th shift register is electrically connected to the input of the first NOT gate, the output of the first NOT gate is electrically connected to the n th input of the first OR gate, and the output of the first OR gate is electrically connected to the first control terminal of the selection circuit through the second NOT gate.
[0023] In some embodiments, the second logic sub-circuit comprises a second OR gate and a third NOT gate.
[0024] The n inputs of the second OR gate are electrically connected to the outputs of the n cascaded shift registers respectively, and the output of the second OR gate is electrically connected to the second control terminal of the selection circuit through the third NOT gate.
[0025] In some embodiments, the selection circuit comprises a first selector and a second selector.
[0026] The first input end of the first selector is electrically connected with the output end of the adder, the second input end of the first selector is electrically connected with the first state signal, the control end of the first selector is electrically connected with the first output end of the logic circuit, the output end of the first selector is electrically connected with the first input end of the second selector, the second input end of the second selector is electrically connected with the second state signal, the control end of the second selector is electrically connected with the second output end of the logic circuit, and the output end of the second selector is electrically connected with the input end of the first stage of the shift register.
[0027] In some embodiments, the first selector is configured to output the output signal of the adder when the first control signal output by the logic circuit is the first state signal, and output the first state signal when the first control signal is the second state signal.
[0028] The second selector is configured to output the output signal of the first selector when the second control signal output by the logic circuit is the first state signal, and output the second state signal when the second control signal is the second state signal.
[0029] In a second aspect, the embodiments of the present application provide a semiconductor chip, comprising any sequence generator provided in the first aspect.
[0030] In the technical scheme of the embodiments of the present application, the sequence generator comprises n cascaded shift registers and a combinational logic circuit, wherein n is an integer greater than or equal to 2, the n first input ends of the combinational logic circuit are electrically connected with the output ends of the n cascaded shift registers one by one, the second input end of the combinational logic circuit is electrically connected with the first state signal, the third input end of the combinational logic circuit is electrically connected with the second state signal, the output end of the combinational logic circuit is electrically connected with the input end of the first stage of the shift register, and the clock signal ends of the n cascaded shift registers are all electrically connected with the clock signal; the combinational logic circuit can output the first state signal when the output signals of the first stage of the shift register to the (n-1)th stage of the shift register are all the first state signal and the output signal of the nth stage of the shift register is the second state signal; wherein the first state signal is used to represent the digital signal 0, and the second state signal is used to represent the digital signal 1, so that a full 0 state can be inserted in the sequence generator, that is, an additional state is inserted on the 2 n -1 states, so that the period of the sequence generator can be 2 n So that the number of 0 and 1 generated in one period is the same, thereby improving the applicability of the sequence generator.
[0031] The above description is only a summary of the technical solutions of the embodiments of the present application. In order to make the technical means of the embodiments of the present application more clearly understood, and to be implemented according to the content of the description, and in order to make the above and other purposes, characteristics and advantages of the embodiments of the present application more obvious and easy to understand, the specific embodiments of the present application will be described below. BRIEF DESCRIPTION OF DRAWINGS
[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor on the basis of these drawings.
[0033] Figure 1 A structural schematic diagram of a sequence generator provided by the embodiments of the present application is shown in the figure.
[0034] Figure 2 A structural schematic diagram of another sequence generator provided by the embodiments of the present application is shown in the figure.
[0035] Figure 3 A structural schematic diagram of another sequence generator provided by the embodiments of the present application is shown in the figure.
[0036] Figure 4 A schematic diagram of the sequence state of a three-stage shift register in the prior art is shown in the figure.
[0037] Figure 5 A schematic diagram of the sequence state of a three-stage shift register provided by the embodiments of the present application is shown in the figure.
[0038] Figure 6 A structural schematic diagram of another sequence generator provided by the embodiments of the present application is shown in the figure.
[0039] Figure 7 A structural schematic diagram of another sequence generator provided by the embodiments of the present application is shown in the figure.
[0040] Figure 8 A structural schematic diagram of a first logic sub-circuit provided by the embodiments of the present application is shown in the figure.
[0041] Figure 9 A structural schematic diagram of a second logic sub-circuit provided by the embodiments of the present application is shown in the figure. DETAILED DESCRIPTION
[0042] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will be combined with the accompanying drawings to make a clear and complete description of the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.
[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description herein is for describing the specific embodiments only and is not intended to be limiting of the application; the use of the terms "including", "comprising" and "having" and any variations thereof in the specification and claims and the description herein are intended to cover both the inclusive and exclusive cases.
[0044] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase "an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive or alternative embodiments. It is expressly understood that the embodiments described herein are merely examples from a whole class of comparable embodiments which those skilled in the art will readily appreciate.
[0045] In addition, the terms "first", "second", and the like in the description and claims of this application or above accompanying drawings are used to distinguish different objects, and are not used to describe a particular order, and can explicitly or implicitly include one or more of the features.
[0046] In the description of the present application, unless otherwise explicitly specified and limited, the terms "connected", "connected" should be understood in a broad sense, for example, the "connected" or "connected" of the circuit structure can mean physical connection, but also means electrical connection or signal connection, for example, it can be directly connected, that is, physically connected, or indirectly connected through at least one intermediate element, as long as the circuit is connected, it can also be the internal connection of two elements; signal connection can be signal connection through circuit, but also means signal connection through media medium, for example, radio wave.
[0047] The term "and / or" herein is only a description of the association relationship between the associated objects, which means that there can be three relationships, for example, A and / or B, which means that there are A, A and B, and B. In addition, the character " / " herein generally means that the front and rear associated objects are in an "or" relationship.
[0048] In the description of the present application, unless otherwise specified, the meaning of "a plurality of" and "at least two" is two or more (including two), and similarly, "a plurality of groups" and "at least two groups" means two groups or more (including two groups).
[0049] In order for those skilled in the art to better understand the scheme of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in combination with the drawings.
[0050] Figure 1 A structural schematic diagram of a sequence generator provided by the embodiments of the present application is shown in Figure 1 The sequence generator 100 includes a combinational logic circuit 10 and n cascaded shift registers Di, where 1≤i≤n, and n is an integer greater than or equal to 2.
[0051] The n first input terminals of the combinational logic circuit 10 are electrically connected one by one with the output terminals of the n cascaded shift registers Di, the second input terminal of the combinational logic circuit 10 is electrically connected with the first state signal S1, the third input terminal of the combinational logic circuit 10 is electrically connected with the second state signal S2, the output terminal of the combinational logic circuit 10 is electrically connected with the input terminal of the first-stage shift register D1, and the clock signal terminals of the n cascaded shift registers Di are all electrically connected with the clock signal CLK.
[0052] The combinational logic circuit 10 is configured to output the first state signal S1 when the output signals of the first-stage shift register D1 to the (n-1)th-stage shift register Dn-1 are all the first state signal S1, and the output signal of the nth-stage shift register Dn is the second state signal S2. The first state signal S1 is used to represent the number 0, and the second state signal S2 is used to represent the number 1.
[0053] For example, as shown in Figure 1 The sequence generator 100 includes four cascaded shift registers, i.e., the first-stage shift register D1, the second-stage shift register D2, the third-stage shift register D3, and the fourth-stage shift register D4. The clock signal terminals of the first-stage shift register D1, the second-stage shift register D2, the third-stage shift register D3, and the fourth-stage shift register D4 are all electrically connected with the clock signal CLK. The input terminal of the first-stage shift register D1 is electrically connected with the output terminal of the combinational logic circuit 10, the output terminal of the first-stage shift register D1 is electrically connected with the input terminal of the second-stage shift register D2, the output terminal of the second-stage shift register D2 is electrically connected with the input terminal of the third-stage shift register D3, and the output terminal of the third-stage shift register D3 is electrically connected with the input terminal of the fourth-stage shift register D4.
[0054] The output signal C1 of the first stage shift register D1 is determined by the input signal C0 of the first stage shift register D1; the output signal C2 of the second stage shift register D2 is determined by the input signal of the second stage shift register D2, i.e. the output signal C1 of the first stage shift register D1; the output signal C3 of the third stage shift register D3 is determined by the input signal of the third stage shift register D3, i.e. the output signal C2 of the second stage shift register D2; the output signal C4 of the fourth stage shift register D4 is determined by the input signal of the fourth stage shift register D4, i.e. the output signal C3 of the third stage shift register D3. In addition, the output signal C1 of the first stage shift register D1, the output signal C2 of the second stage shift register D2, the output signal C3 of the third stage shift register D3 and the output signal C4 of the fourth stage shift register D4 are synchronized by the clock signal CLK.
[0055] For example, if the output signal C2 of the second stage shift register D2 is 0, i.e. the input signal of the third stage shift register D3 is 0, when the rising edge of the clock signal CLK comes, the output signal C3 of the third stage shift register D3 = C2 = 0; if the output signal C2 of the second stage shift register D2 is 1, when the rising edge of the clock signal CLK comes, the output signal C3 of the third stage shift register D3 = C2 = 1.
[0056] Continuing to refer to Figure 1 , the output end of the first stage shift register D1, the output end of the second stage shift register D2, the output end of the third stage shift register D3 and the output end of the fourth stage shift register D4 are electrically connected with the four first input ends of the combinational logic circuit 10 one by one, and at least part of the output signals of the input signal C0 of the first stage shift register D1, the output signal C1 of the first stage shift register D1, the output signal C2 of the second stage shift register D2, the output signal C3 of the third stage shift register D3 and the output signal C4 of the fourth stage shift register D4 can participate in feedback. Among them, the output signal C4 of the fourth stage shift register D4 and the input signal C0 of the first stage shift register D1 must be 1, i.e. the input signal C0 of the first stage shift register D1 and the output signal C4 of the fourth stage shift register D4 must participate in feedback. The output signal C1 of the first stage shift register D1, the output signal C2 of the second stage shift register D2 and the output signal C3 of the third stage shift register D3 may be 1 or 0 according to different algorithms, if it is 1, it means that the corresponding output signal participates in feedback, if it is 0, it means that the corresponding output signal does not participate in feedback, i.e. the corresponding feedback line is open circuit.
[0057] As Figure 1The main parameters of the sequence generator 100 shown are the number of stages 4, the output signal C1 of the first stage shift register D1, the output signal C2 of the second stage shift register D2, and the output signal C3 of the third stage shift register D3. Since the feedback coefficient of the sequence generator 100 is (23)8, the corresponding binary code is (10011)2, it can be obtained that C0=1, C1=0, C2=0, C3=1, and C4=1. Thus, the feedback line corresponding to the output signal C1 of the first stage shift register D1 and the feedback line corresponding to the output signal C2 of the second stage shift register D2 in the combinational logic circuit 10 can be set as open circuits.
[0058] The combinational logic circuit 10 can receive the first state signal S1 and the second state signal S2 while receiving the output signal C1 of the first stage shift register D1, the output signal C2 of the second stage shift register D2, the output signal C3 of the third stage shift register D3, and the output signal C4 of the fourth stage shift register D4. The first state signal S1 can represent a digital signal 0, and the second state signal S2 can represent a digital signal 1. For example, the first state signal S1 is a low-level signal, and the second state signal is a high-level signal.
[0059] The combinational logic circuit 10 can perform a one-bit addition operation on the output signals involved in the feedback, that is, perform a one-bit addition operation on the output signal C3 of the third stage shift register D3 and the output signal C4 of the fourth stage shift register D4 to obtain the least significant bit data of the addition operation result. The combinational logic circuit 10 can also select one output from the first state signal S1, the second state signal S2, and the least significant bit data of the addition operation result as a new input signal C0 of the first stage shift register D1 based on the output signal C1 of the first stage shift register D1, the output signal C2 of the second stage shift register D2, the output signal C3 of the third stage shift register D3, and the output signal C4 of the fourth stage shift register D4.
[0060] If the sequence generator 100 is in the 0001 state, the output signal C1 of the first stage shift register D1, the output signal C2 of the second stage shift register D2, and the output signal C3 of the third stage shift register D3 are all the first state signal S1, and the output signal C4 of the fourth stage shift register D4 is the second state signal S2, that is, the output signal C1=0, the output signal C2=0, the output signal C3=0, and the output signal C4=1. The combinational logic circuit 10 can output the first state signal S1 based on the output signal C1=0, the output signal C2=0, the output signal C3=0, and the output signal C4=1, that is, the input signal C0 of the first stage shift register D1 can be set to 0. At this time, the sequence generator 100 switches from the 0001 state to the 0000 state. Thus, the 0000 state can be inserted in the sequence generator 100, that is, the 0000 state can be inserted in the sequence generator 100 in the 24 -1 state, an additional state is inserted, and the period of the sequence generator 100 is 2 4 , so that the number of 0s and the number of 1s generated in one period of the sequence generator 100 are the same, thereby improving the applicability of the sequence generator 100.
[0061] It should be noted that Figure 1 The sequence generator 100 is exemplarily shown to include four cascaded shift registers. In other implementations, the sequence generator 100 can include two cascaded shift registers, or three cascaded shift registers; or n cascaded shift registers, where n is an integer greater than 4, such as Figure 2 as shown, Figure 2 Another structure diagram of a sequence generator provided by an embodiment of the present application is provided.
[0062] If the sequence generator 100 includes three cascaded shift registers, a 000 state can be inserted in the sequence generator 100, i.e., an additional state is inserted on the 2 3 -1 state, and the period of the sequence generator 100 is 2 3 If the sequence generator 100 includes n cascaded shift registers, where n is an integer greater than 4, such as Figure 2 as shown, a all-0 state can be inserted in the sequence generator 100, i.e., an additional state is inserted on the 2 n -1 state, and the period of the sequence generator 100 is 2 n .
[0063] Table 1 is a feedback coefficient table of the sequence generator provided by an embodiment of the present application, and through Table 1, the output signals participating in feedback in the combinational logic circuit 10 can be determined, and the feedback line in the combinational logic circuit 10 is simplified.
[0064] Table 1 Feedback coefficient table of the sequence generator
[0065]
[0066]
[0067] In the embodiment of the present application, the sequence generator comprises n cascaded shift registers and a combinational logic circuit, wherein n is an integer greater than or equal to 2, n first inputs of the combinational logic circuit are electrically connected to outputs of the n cascaded shift registers one by one, a second input of the combinational logic circuit is electrically connected to the first state signal, a third input of the combinational logic circuit is electrically connected to the second state signal, an output of the combinational logic circuit is electrically connected to an input of the first stage shift register, and clock signal ends of the n cascaded shift registers are all electrically connected to the clock signal; the first state signal is outputted by the combinational logic circuit when the output signals of the first stage shift register to the (n-1)th stage shift register are all the first state signal and the output signal of the nth stage shift register is the second state signal; wherein the first state signal is used to represent the digital signal 0, and the second state signal is used to represent the digital signal 1, so that a full 0 state can be inserted in the sequence generator, i.e. one additional state is inserted on the 2 n -1 states, so that the period of the sequence generator is 2 n , and the number of 0 and 1 generated in one period is the same, thereby improving the applicability of the sequence generator.
[0068] In some embodiments, Figure 3 a structure diagram of another sequence generator provided by the embodiment of the present application is provided, Figure 3 a structure diagram of another sequence generator provided by the embodiment of the present application is provided, Figure 1 As shown in the embodiment, the combinational logic circuit 10 comprises a logic circuit 110 and a selection circuit 120.
[0069] The n inputs of the logic circuit 110 are electrically connected to the outputs of the n cascaded shift registers Di one by one, the first output of the logic circuit 110 is electrically connected to the first control end of the selection circuit 120, the second output of the logic circuit 110 is electrically connected to the second control end of the selection circuit 120, the first input of the selection circuit 120 is electrically connected to the first state signal S1, and the second input of the selection circuit 120 is electrically connected to the second state signal S2.
[0070] The logic circuit 110 is configured to control the selection circuit 120 to output the first state signal S1 when the output signals of the first stage shift register D1 to the (n-1)th stage shift register Dn-1 are all the first state signal S1 and the output signal of the nth stage shift register Dn is the second state signal S2.
[0071] For example, Figure 3As shown, the output terminal of the first-stage shift register D1, the output terminal of the second-stage shift register D2, the output terminal of the third-stage shift register D3 and the output terminal of the fourth-stage shift register D4 are electrically connected to four input terminals of the logic circuit 110 one by one, and the logic circuit 110 can receive the output signal C1 of the first-stage shift register D1, the output signal C2 of the second-stage shift register D2, the output signal C3 of the third-stage shift register D3 and the output signal C4 of the fourth-stage shift register D4.
[0072] The logic circuit 110 can generate the first control signal SEL1 and the second control signal SEL2 based on the received output signal C1 of the first-stage shift register D1, the output signal C2 of the second-stage shift register D2, the output signal C3 of the third-stage shift register D3 and the output signal C4 of the fourth-stage shift register D4, and transmit the first control signal SEL1 to the first control terminal of the selection circuit 120 and the second control signal SEL2 to the second control terminal of the selection circuit 120. If the sequence generator is in the 0001 state, i.e., the output signal C1 = 0, the output signal C2 = 0, the output signal C3 = 0 and the output signal C4 = 1, the generated first control signal SEL1 is 1 and the second control signal SEL2 is 0.
[0073] The selection circuit 120 can receive the first control signal SEL1 and the second control signal SEL2, and select whether to output the first state signal S1 or the second state signal S2 based on the first control signal SEL1 and the second control signal SEL2. If the first control signal SEL1 is 1 and the second control signal SEL2 is 0, the selection circuit 120 selects to output 0, so that the input signal C0 of the first-stage shift register D1 can be set to 0.
[0074] In some embodiments, the logic circuit 110 is further configured to control the selection circuit 120 to output the second state signal S2 when the output signals of the first-stage shift register D1 to the n-th stage shift register Dn are all the first state signal S1.
[0075] For example, continuing to refer to Figure 3 , the sequence generator 100 is in the 0000 state, i.e., the output signal C1 = 0, the output signal C2 = 0, the output signal C3 = 0 and the output signal C4 = 0, the generated first control signal SEL1 is 0 and the second control signal SEL2 is 1. At this time, the selection circuit 120 selects to output 1, so that the input signal C0 of the first-stage shift register D1 can be set to 1, so that the sequence generator 100 switches from the 0000 state to the 1000 state, avoiding the sequence generator 100 from being locked in the 0000 state.
[0076] In other embodiments, the sequence generator 100 includes n cascaded shift registers, where n is an integer greater than 4. If the sequence generator 100 is in the all-0 state, i.e., Ci = 0, 1≤i≤n, the first control signal SEL1 is 0 and the second control signal SEL2 is 1. At this time, the selection circuit 120 selects the output 1, so that the input signal C0 of the first shift register D1 can be set to 1, so that the sequence generator switches from the all-0 state to the state where the input signal C1 is 1 and the input signals C2 to Cn are all 0, avoiding the sequence generator 100 from being locked in the all-0 state, thereby ensuring that the sequence generator 100 can enter the next working period.
[0077] In the embodiments of the present application, the logic circuit can control the selection circuit to output the second state signal when the output signals of the first shift register to the nth shift register are all the first state signal, so that the sequence generator can be prevented from being locked in the all-0 state and can enter the next working period.
[0078] As an embodiment of the present application, if the sequence generator includes three cascaded shift registers, Figure 4 A schematic diagram of the sequence state of the three shift registers in the prior art is shown in FIG. 1. Figure 4 As shown in FIG. 1, the number of sequence states of the sequence generator in one working period is 7, and the switching sequence of the sequence states in one working period is 100-010-101-110-111-011-001. Figure 5 A schematic diagram of the sequence state of the three shift registers provided by the embodiments of the present application is shown in FIG. 2. Figure 5 As shown in FIG. 2, the sequence generator inserts the sequence state 000 after the sequence state 001, and the sequence state 000 can switch to the sequence state 100. In this way, the number of sequence states of the sequence generator in one working period is 8, the switching sequence of the sequence states in one working period is 100-010-101-110-111-011-001-000, and the sequence state 000 can automatically switch to the sequence state 100 of the next working period.
[0079] In some embodiments, Figure 6 A schematic diagram of another structure of the sequence generator provided by the embodiments of the present application is shown in FIG. 3. Figure 6 As shown in FIG. 3, the sequence generator includes three cascaded shift registers, a selection circuit 120, and a combination logic circuit 10. Figure 3 Based on the embodiment shown in FIG. 3, the combination logic circuit 10 further includes an adder 130, the m input terminals of the adder 130 are electrically connected to the output terminals of the m shift registers one by one, and the output terminal of the adder 130 is electrically connected to the third input terminal of the selection circuit 120.
[0080] The adder 130 is configured to add the output signals of the m shift registers and output the least significant bit of the addition result. The logic circuit 110 is further configured to control the selection circuit to output the output signal of the adder 130 based on the output signals of the n cascaded shift registers.
[0081] For example, as shown in FIG. 1, the sequence generator 100 includes three cascaded shift registers, i.e., a first shift register D1, a second shift register D2 and a third shift register D3. The first shift register D1 is configured to receive the first control signal SEL1 and the second control signal SEL2, and output a first output signal C1. The second shift register D2 is configured to receive the first control signal SEL1 and the second control signal SEL2, and output a second output signal C2. The third shift register D3 is configured to receive the first control signal SEL1 and the second control signal SEL2, and output a third output signal C3. The selection circuit 120 is configured to output the output signal of the adder 130 based on the output signals of the n cascaded shift registers. Figure 6 For example, as shown in FIG. 1, the output signal C3 of the third shift register D3 and the output signal C4 of the fourth shift register D4 are respectively connected to two input terminals of the adder 130 through respective feedback lines, where the output signal C3 of the third shift register D3 and the output signal C4 of the fourth shift register D4 are the output signals of all the shift registers participating in feedback. The adder 130 can add the output signal C3 of the third shift register D3 and the output signal C4 of the fourth shift register D4, and output the least significant bit of the addition result.
[0082] For example, the adder 130 can be a one-bit adder. If the output signal C3 is 0 and the output signal C4 is 0, the addition result of the adder 130 is 0, i.e., the least significant bit of the addition result is 0. If the output signal C3 is 0 and the output signal C4 is 1, the addition result of the adder 130 is 1, i.e., the least significant bit of the addition result is 1. If the output signal C3 is 1 and the output signal C4 is 0, the addition result of the adder 130 is 1, i.e., the least significant bit of the addition result is 1. If the output signal C3 is 1 and the output signal C4 is 1, the addition result of the adder 130 is (10)2, i.e., the least significant bit of the addition result is 0.
[0083] If the sequence generator 100 is in neither the 0000 state nor the 0001 state, i.e., the sequence generator 100 is in any one of the 1000, 0010, 0100, 0011, 0101, 1001, 0110, 1010, 1100, 0111, 1011, 1101, 1110 and 1111 states, the first control signal SEL1 is 0 and the second control signal SEL2 is 0. At this time, the selection circuit 120 selects to output the least significant bit of the addition result, i.e., the output signal of the adder 130. In this way, the sequence generator 100 can switch between different states in the same working period.
[0084] In other embodiments, the sequence generator 100 includes n cascaded shift registers, where n is an integer greater than 4, and the number m of the output signals participating in feedback in the n cascaded shift registers is less than or equal to n. The specific output signals participating in feedback can be determined according to Table 1. The adder 130 can add the output signals participating in feedback and obtain the least significant bit of the addition result.
[0085] If the sequence generator 100 is in the all-0 state, and the input signal C1 is 1 and the input signals C2 to Cn are all 0, the generated first control signal SEL1 is 0, and the second control signal SEL2 is 0. At this time, the selection circuit 120 selects the output of the adder 130, that is, the output signal of the adder 130. In this way, it is ensured that the sequence generator 100 can switch between different states in the same working period.
[0086] In the embodiment of the present application, the combination logic circuit further comprises an adder, m input ends of the adder are electrically connected to the output ends of the m shift registers one by one, and an output end of the adder is electrically connected to a third input end of the selection circuit, where 1≤m≤n, and m is an integer; the logic circuit can control the selection circuit to output the output signal of the adder based on the output signals of the n cascaded shift registers, so as to ensure the switching between different states of the sequence generator in the same working period.
[0087] In some embodiments, Figure 7 Another structure diagram of a sequence generator provided in the embodiment of the present application is shown in FIG. 2. Figure 7 As shown in FIG. 2, the logic circuit comprises a first logic sub-circuit 111 and a second logic sub-circuit 112.
[0088] The n input ends of the first logic sub-circuit 111 are electrically connected to the output ends of the n cascaded shift registers one by one, the n input ends of the second logic sub-circuit 112 are electrically connected to the output ends of the n cascaded shift registers one by one, the output end of the first logic sub-circuit 111 is electrically connected to the first control end of the selection circuit 130, and the output end of the second logic sub-circuit 112 is electrically connected to the second control end of the selection circuit 130.
[0089] The first logic sub-circuit 111 is configured to generate a first control signal SEL1 based on the output signals of the n cascaded shift registers; when the output signals of the first shift register D1 to the n-1th shift register Dn-1 are all first state signals S1, and the output signal of the nth shift register Dn is a second state signal S2, the first control signal SEL1 is the first state signal S1. The second logic sub-circuit 112 is configured to generate a second control signal SEL2 based on the output signals of the n cascaded shift registers; when the output signals of the first shift register D1 to the n-1th shift register Dn-1 are all first state signals S1, and the output signal of the nth shift register Dn is a second state signal S2, the second control signal SEL2 is the first state signal S1.
[0090] Selection circuit 120 is used to output first state signal S1 when first control signal SEL1 is second state signal S2 and second control signal SEL2 is first state signal S1.
[0091] For example, Figure 8 This is a schematic diagram of the structure of a first logic sub-circuit provided in an embodiment of this application, combined with... Figure 7 and Figure 8 As shown, the first logic sub-circuit 111 includes a first OR gate OR1, a first NOT gate NOT1, and a second NOT gate NOT2; wherein, the n-1 input terminals of the first OR gate OR1 are electrically connected to the output terminals of the first-stage shift register D1 to the (n-1)th-stage shift register Dn-1 in a one-to-one correspondence, the output terminal of the nth-stage shift register Dn is electrically connected to the input terminal of the first NOT gate NOT1, the output terminal of the first NOT gate NOT1 is electrically connected to the nth input terminal of the first OR gate OR1, and the output terminal of the first OR gate OR1 is electrically connected to the first control terminal of the selection circuit 120 through the second NOT gate NOT2.
[0092] Combination Figure 7 and Figure 8 As shown, the outputs of the first-stage shift register D1, the second-stage shift register D2, and the third-stage shift register D3 are electrically connected to the first, second, and third inputs of the first OR gate OR1, respectively. The output of the fourth-stage shift register D4 is electrically connected to the fourth input of the first OR gate OR1 through the first NOT gate NOT1. The first, second, and third inputs of the first OR gate OR1 and the input of the first NOT gate NOT1 are the four inputs of the first logic sub-circuit 111.
[0093] The first NOT gate NOT1 can perform an inversion operation on the output signal C4 of the fourth shift register D4, the first OR gate OR1 can perform an OR operation on the inverted signals of the output signal C1 of the first shift register D1, the output signal C2 of the second shift register D2, the output signal C3 of the third shift register D3 and the output signal C4 of the fourth shift register D4, the second NOT gate NOT2 can perform an inversion operation on the OR operation result, and the first control signal SEL1 is obtained. In this way, the first logic sub-circuit 111 can generate the first control signal SEL1 based on the output signal C1 of the first shift register D1, the output signal C2 of the second shift register D2, the output signal C3 of the third shift register D3 and the output signal C4 of the fourth shift register D4. For example, if the output signal C1, the output signal C2 and the output signal C3 are all 0, and the output signal C4 is 1, the inverted signal of the output signal C4 is 0, the OR operation result of the output signal C1, the output signal C2, the output signal C3 and the inverted signal of the output signal C4 is 0, and the inverted signal of the OR operation result is 1, and the generated first control signal SEL1 is 1. If the output signal C1, the output signal C2, the output signal C3 and the output signal C4 are all 0, the inverted signal of the output signal C4 is 1, the OR operation result of the output signal C1, the output signal C2, the output signal C3 and the inverted signal of the output signal C4 is 1, and the inverted signal of the OR operation result is 0, and the generated first control signal SEL1 is 0.
[0094] In other embodiments, the sequence generator 100 includes n cascaded shift registers, n is an integer greater than 4, the output terminals of the first shift register D1 to the (n-1)th shift register Dn-1 are electrically connected to the n-1 input terminals of the first OR gate OR1 one by one, and the output terminal of the nth shift register Dn is electrically connected to the nth input terminal of the first OR gate OR1 through the first NOT gate NOT1. The n-1 input terminals of the first OR gate OR1 and the input terminal of the first NOT gate NOT1 are n input terminals of the first logic sub-circuit 111.
[0095] The first NOT gate (NOT1) inverts the output signal Cn of the nth-stage shift register Dn. The first OR gate (OR1) performs an OR operation on the output signals C1 of the first-stage shift register D1 to Cn-1 of the (n-1)th-stage shift register D1, and the inverted signals of the output signal Cn of the nth-stage shift register Dn. The second NOT gate (NOT2) inverts the result of the OR operation to obtain the first control signal SEL1. Thus, the first logic sub-circuit 111 can generate the first control signal SEL1 based on the output signals C1 of the first-stage shift register D1 to Cn of the nth-stage shift register Dn. For example, if the output signals C1 to Cn-1 are all 0, and the output signal Cn is 1, then the inverted signal of the output signal Cn is 0. The OR operation result of the output signals C1 to Cn-1, and the inverted signal of the output signal Cn is 0, and the inverted signal of the OR operation result is 1, then the generated first control signal SEL1 is 1. If all output signals C1 to Cn are 0, then the inverted signal of output signal Cn is 1. The OR operation result of output signals C1 to Cn-1 and the inverted signal of output signal Cn is 1, or the inverted signal of the OR operation result is 0, then the generated first control signal SEL1 is 0.
[0096] For example, Figure 9 This is a schematic diagram of the structure of a second logic sub-circuit provided in an embodiment of this application, combined with... Figure 7 and Figure 9 As shown, the second logic sub-circuit 112 includes a second OR gate OR2 and a third NOT gate NOT3. The n input terminals of the second OR gate OR2 are electrically connected to the output terminals of the n cascaded shift registers in a one-to-one correspondence. The output terminal of the second OR gate OR2 is connected to the second control terminal of the selection circuit 120 through the third NOT gate NOT3.
[0097] Combination Figure 7 and Figure 9 As shown, the output terminals of the first-stage shift register D1, the second-stage shift register D2, the third-stage shift register D3, and the fourth-stage shift register D4 are electrically connected to the first, second, third, and fourth input terminals of the second OR gate OR2, respectively. The first, second, third, and fourth input terminals of the second OR gate OR2 are the four input terminals of the second logic sub-circuit 112.
[0098] The second OR gate OR2 can perform an OR operation on the output signal C1 of the first stage shift register D1, the output signal C2 of the second stage shift register D2, the output signal C3 of the third stage shift register D3, and the output signal C4 of the fourth stage shift register D4, the third NOT gate NOT3 can perform an inversion operation on the OR operation result to obtain the second control signal SEL2. In this way, the second logic sub-circuit 112 can generate the second control signal SEL2 based on the output signal C1 of the first stage shift register D1, the output signal C2 of the second stage shift register D2, the output signal C3 of the third stage shift register D3, and the output signal C4 of the fourth stage shift register D4. For example, if the output signal C1, the output signal C2, the output signal C3, and the output signal C4 are all 0, the OR operation result of the output signal C1, the output signal C2, the output signal C3, and the output signal C4 is 0, and the inverted signal of the OR operation result is 1, the generated second control signal SEL2 is 1. If the output signal C1, the output signal C2, and the output signal C3 are all 0, the output signal C4 is 1, the OR operation result of the output signal C1, the output signal C2, the output signal C3, and the output signal C4 is 1, and the inverted signal of the OR operation result is 0, the generated second control signal SEL2 is 0.
[0099] In other embodiments, the sequence generator 100 includes n cascaded shift registers, n is an integer greater than 4, the output terminals of the first stage shift register D1 to the nth stage shift register Dn are electrically connected to the n input terminals of the second OR gate OR2, and the n input terminals of the second OR gate OR2 are the n input terminals of the second logic sub-circuit 111.
[0100] The second OR gate OR2 can perform an OR operation on the output signal C1 of the first stage shift register D1, the output signal C2 of the second stage shift register D2, the output signal C3 of the third stage shift register D3, and the output signal C4 of the fourth stage shift register D4, the third NOT gate NOT3 can perform an inversion operation on the OR operation result to obtain the second control signal SEL2. In this way, the second logic sub-circuit 112 can generate the second control signal SEL2 based on the output signal C1 of the first stage shift register D1, the output signal C2 of the second stage shift register D2, the output signal C3 of the third stage shift register D3, and the output signal C4 of the fourth stage shift register D4. For example, if the output signal C1, the output signal C2, the output signal C3, and the output signal C4 are all 0, the OR operation result of the output signal C1, the output signal C2, the output signal C3, and the output signal C4 is 0, and the inverted signal of the OR operation result is 1, the generated second control signal SEL2 is 1. If the output signal C1, the output signal C2, and the output signal C3 are all 0, the output signal C4 is 1, the OR operation result of the output signal C1, the output signal C2, the output signal C3, and the output signal C4 is 1, and the inverted signal of the OR operation result is 0, the generated second control signal SEL2 is 0.
[0101] The selection circuit 120 can select to output the first state signal S1, the second state signal S2 or the output signal of the adder 130 based on the first control signal SEL1 and the second control signal SEL2. If the first control signal SEL1 is 1 and the second control signal SEL2 is 0, the selection circuit 120 selects to output 0; if the first control signal SEL1 is 0 and the second control signal SEL2 is 1, the selection circuit 120 selects to output 1; if the first control signal SEL1 is 0 and the second control signal SEL2 is 0, the selection circuit 120 selects to output the output signal of the adder 130.
[0102] In some embodiments, referring to Figure 7 the selection circuit 120 comprises a first selector MUX1 and a second selector MUX2, a first input terminal of the first selector MUX1 is electrically connected to the output terminal of the adder 130, a second input terminal of the first selector MUX1 is electrically connected to the first state signal S1, a control terminal of the first selector MUX1 is electrically connected to the first output terminal of the logic circuit 110, an output terminal of the first selector MUX1 is electrically connected to a first input terminal of the second selector MUX2, a second input terminal of the second selector MUX2 is electrically connected to the second state signal S2, a control terminal of the second selector MUX2 is electrically connected to the second output terminal of the logic circuit 110, and an output terminal of the second selector MUX2 is electrically connected to the input terminal of the first stage shift register D1.
[0103] For example, the second selector MUX2 can receive the second control signal SEL2 outputted by the logic circuit 110 and select the output signal of the first selector MUX1 or the second state signal S2 as the new input signal C0 based on the second control signal SEL2. If the second control signal SEL2 is 1, the second selector MUX2 selects to output the second state signal S2 as the new input signal C0, i.e. the new input signal C0 is 0; if the second control signal SEL2 is 0, the second selector MUX2 selects to output the output signal of the first selector MUX1 as the new input signal C0. In this way, the second selector MUX2 can output the output signal of the first selector MUX1 when the second control signal SEL2 outputted by the logic circuit 110 is the first state signal S1, and output the second state signal S2 when the second control signal SEL2 is the second state signal S2.
[0104] The first selector MUX1 can receive the first control signal SEL1 output by the logic circuit 110, and select the output signal of the adder 130 or the first state signal S1 as the output signal of the first selector MUX1 based on the first control signal SEL1. If the first control signal SEL1 is 1, the first selector MUX1 selects the first state signal S1 as the output signal of the first selector MUX1; if the first control signal SEL1 is 0, the first selector MUX1 selects the output signal of the adder 130 as the output signal of the first selector MUX1. In this way, the first selector MUX1 can output the output signal of the adder 130 when the first control signal SEL1 output by the logic circuit 110 is the first state signal S1, and output the first state signal S1 when the first control signal SEL1 is the second state signal S2.
[0105] In summary, when the first control signal SEL1 is 1 and the second control signal SEL2 is 0, the output signal of the first selector MUX1 is the first state signal S1, the output signal of the second selector MUX2 is the first state signal S1, i.e., the new input signal C0 is 0; when the first control signal SEL1 is 0 and the second control signal SEL2 is 1, the output signal of the first selector MUX1 is the output signal of the adder 130, the output signal of the second selector MUX2 is the second state signal S2, i.e., the new input signal C0 is 1; when the first control signal SEL1 is 0 and the second control signal SEL2 is 0, the output signal of the first selector MUX1 is the output signal of the adder 130, the output signal of the second selector MUX2 is the output signal of the adder 130, i.e., the new input signal C0 is the output signal of the adder 130.
[0106] The embodiment of the present application further provides a semiconductor chip, which comprises the sequence generator 100 provided by any of the above embodiments.
[0107] For example, integrating the sequence generator 100 provided by any of the above embodiments into a chip can reduce the volume of the sequence generator 100, and facilitate the miniaturization development of the sequence generator 100.
[0108] The semiconductor chip provided by the embodiment of the present application comprises the sequence generator provided by any of the above embodiments, has the same functional modules and beneficial effects as the sequence generator, and thus is not described herein.
[0109] The above disclosure is merely specific embodiments of the present application, and the embodiments of the present application are not limited to this. Any changes that can be thought of by those skilled in the art shall fall within the protection scope of the present application.
[0110] The description of the application uses "comprising" rather than "consisting of" to describe the technical solutions of the application. This does not exclude that other elements can be included in the application. The word "one" or "an" preceding an element does not exclude the presence of a plurality of such elements. The application can be implemented by means of both hardware and software, and by means of a computer program specifically programmed to perform some of the steps. In a claim enumerating several means, the use of the language "comprising" should not be construed as using the exclusive "only" meaning. The use of indefinite articles "one" or "an" should not be construed as excluding the presence of several elements, nor should it be construed as excluding the presence of one and only one of these elements. The use of the word "first", "second" and "third", etc. does not denote any order. These words have been used to name the elements. The steps of the above-described embodiments should not be interpreted as a limitation on the order of execution, unless otherwise specified.
[0111] The above-described embodiments are only used to illustrate the technical solutions of the present application, but not limit the present application; even though the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. A sequence generator, characterized in that, include: n cascaded shift registers and combinational logic circuits, where n is an integer greater than or equal to 2; The n first input terminals of the combinational logic circuit are electrically connected one-to-one with the output terminals of the n cascaded shift registers. The second input terminal of the combinational logic circuit is electrically connected to the first state signal. The third input terminal of the combinational logic circuit is electrically connected to the second state signal. The output terminal of the combinational logic circuit is electrically connected to the input terminal of the first-stage shift register. The clock signal terminals of the n cascaded shift registers are all electrically connected to the clock signal. The combinational logic circuit is configured to output the first state signal when the output signals of the shift registers from the first stage to the (n-1)th stage are all the first state signal and the output signal of the nth stage shift register is the second state signal; wherein the first state signal is used to represent the digital signal 0 and the second state signal is used to represent the digital signal 1. The combinational logic circuit includes: logic circuit and selection circuit; The n input terminals of the logic circuit are electrically connected one-to-one with the output terminals of the n cascaded shift registers. The first output terminal of the logic circuit is electrically connected to the first control terminal of the selection circuit, and the second output terminal of the logic circuit is electrically connected to the second control terminal of the selection circuit. The first input terminal of the selection circuit is electrically connected to the first status signal, and the second input terminal of the selection circuit is electrically connected to the second status signal. The logic circuit is configured to control the selection circuit to output the first state signal when the output signals of the shift registers from the first stage to the (n-1)th stage are all the first state signal and the output signal of the shift register of the nth stage is the second state signal; and is further configured to control the selection circuit to output the second state signal when the output signals of the shift registers from the first stage to the nth stage are all the first state signal.
2. The sequence generator according to claim 1, characterized in that, The combinational logic circuit further includes: an adder; The m input terminals of the adder are electrically connected one-to-one with the output terminals of the m shift registers, and the output terminal of the adder is electrically connected to the third input terminal of the selection circuit; wherein, 1≤m≤n, and m is an integer; The adder is used to perform addition operations on the output signals of the m shift registers and output the least significant bit of the addition result; The logic circuit is also used to control the selection circuit to output the output signal of the adder based on the output signals of the n cascaded shift registers.
3. The sequence generator according to any one of claims 1-2, characterized in that, The logic circuit includes a first logic sub-circuit and a second logic sub-circuit; The n input terminals of the first logic sub-circuit are electrically connected one-to-one with the output terminals of the n cascaded shift registers. The n input terminals of the second logic sub-circuit are electrically connected one-to-one with the output terminals of the n cascaded shift registers. The output terminal of the first logic sub-circuit is electrically connected to the first control terminal of the selection circuit, and the output terminal of the second logic sub-circuit is electrically connected to the second control terminal of the selection circuit. The first logic sub-circuit is used to generate a first control signal based on the output signals of the n cascaded shift registers; wherein the output signals of the shift registers from the first stage to the (n-1)th stage are all the first state signal, and when the output signal of the nth stage shift register is the second state signal, the first control signal is the second state signal; The second logic sub-circuit is used to generate a second control signal based on the output signals of the n cascaded shift registers; wherein the output signals of the shift registers from the first stage to the (n-1)th stage are all the first state signal, and when the output signal of the nth stage shift register is the second state signal, the second control signal is the first state signal; The selection circuit is used to output the first status signal when the first control signal is the second status signal and the second control signal is the first status signal.
4. The sequence generator according to claim 3, characterized in that, The first logic sub-circuit includes a first OR gate, a first NOT gate, and a second NOT gate; The n-1 input terminals of the first OR gate are electrically connected one-to-one with the output terminals of the shift registers from the first stage to the (n-1)th stage. The output terminal of the nth stage shift register is electrically connected to the input terminal of the first NOT gate. The output terminal of the first NOT gate is electrically connected to the nth input terminal of the first OR gate. The output terminal of the first OR gate is electrically connected to the first control terminal of the selection circuit through the second NOT gate.
5. The sequence generator according to claim 3, characterized in that, The second logic sub-circuit includes a second OR gate and a third NOT gate; The n inputs of the second OR gate are electrically connected one-to-one with the outputs of the n cascaded shift registers, and the output of the second OR gate is electrically connected to the second control terminal of the selection circuit through the third NOT gate.
6. The sequence generator according to claim 2, characterized in that, The selection circuit includes a first selector and a second selector; The first input terminal of the first selector is electrically connected to the output terminal of the adder, the second input terminal of the first selector is electrically connected to the first status signal, the control terminal of the first selector is electrically connected to the first output terminal of the logic circuit, the output terminal of the first selector is electrically connected to the first input terminal of the second selector, the second input terminal of the second selector is electrically connected to the second status signal, the control terminal of the second selector is electrically connected to the second output terminal of the logic circuit, and the output terminal of the second selector is electrically connected to the input terminal of the first-stage shift register.
7. The sequence generator according to claim 6, characterized in that, The first selector is configured to output the output signal of the adder when the first control signal output by the logic circuit is the first state signal, and to output the first state signal when the first control signal is the second state signal. The second selector is used to output the output signal of the first selector when the second control signal output by the logic circuit is the first status signal, and to output the second status signal when the second control signal is the second status signal.
8. A semiconductor chip, characterized in that, Includes the sequence generator according to any one of claims 1-7.
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