A method for implementing a hard verification flow based on an FPGA cloud platform

Abstract

The application discloses a kind of based on FPGA cloud platform's hardware simulation verification process implementation method, client obtains the source code file of user design, compiles integrated source code file, generates instance tree and resource occupation situation;Global instance is specified, and the instance of user design is split into small instance module;According to the instance module of splitting, the signal flow graph between different modules is generated;User is divided into different FPGA under the operation of client by following certain principle and split instance module;The attribute of signal between different FPGA is specified by client, and connection port is configured, and probe is inserted;FPGA sub-project top file is generated, and sub-project bit stream is generated by compiling, and after encryption, it is sent to cloud platform server;Trigger condition is configured in client, and cloud platform deploys running simulation program, debugs and looks waveform data and sends to client display.Satisfy the verification demand of large-scale chip design hardware simulation, and protect the intellectual property right of user.

Description

Technical Field

[0001] This invention belongs to the field of electronic design automation technology, and in particular relates to a method for implementing a hardware simulation verification process based on an FPGA cloud platform. Background Technology

[0002] As chip designs become increasingly large-scale, single FPGAs, due to their resource limitations, cannot meet the verification needs of large-scale chip designs. Furthermore, the high cost of FPGAs has led to the emergence of FPGA-based hardware simulation cloud platforms (hereinafter referred to as cloud platforms). Cloud platforms can provide verification services for both large-scale and small-scale chip designs. A cloud platform manages multiple FPGAs, and these FPGAs work collaboratively through special links.

[0003] Because chip design involves intellectual property and software protection, users cannot upload the chip design source code to a server. Therefore, the only option is to generate multiple FPGA sub-projects in the customer's own environment and then upload encrypted bitstream files to a cloud platform to complete chip verification. This method describes the process of performing large-scale chip design hardware simulation verification in this scenario. Summary of the Invention

[0004] To address the above technical problems, this invention provides a method for implementing a hardware simulation verification process based on an FPGA cloud platform.

[0005] The technical solution adopted by this invention to solve its technical problem is:

[0006] A method for implementing a hardware simulation verification process based on an FPGA cloud platform, the method comprising the following steps:

[0007] S100: The client obtains the source code file designed by the user, compiles and synthesizes the source code file, generates an instance tree, and obtains the resource usage of each node in the instance tree;

[0008] S200: Receives global instance specification instructions and partitioning instructions input by the user based on the instance tree and the resource usage of each node in the instance tree; specifies the global instance according to the global instance specification instructions; and splits the instance tree into multiple instance modules according to the partitioning instructions.

[0009] S300: Generates a signal flow graph between different modules based on the global instance and multiple split instance modules;

[0010] S400: Obtain the resource usage of different FPGAs, receive configuration instructions input by the user based on the signal flow graph between different modules, the resource usage of each node in the instance tree, the resource usage of different FPGAs, and the preset signal transmission requirements, configure the multiple instance modules to different FPGAs according to the configuration instructions, specify the signal attributes between different FPGAs, configure the connection ports and insert probes according to the signal attributes between different FPGAs, and obtain intermediate files.

[0011] S500: Generates an FPGA sub-project top file based on the intermediate file, compiles the FPGA sub-project top file to generate a sub-project bit stream, and encrypts the sub-project bit stream before sending it to the cloud platform server;

[0012] S600: Receives the waveform data reading trigger conditions configured by the user and sends them to the cloud platform server. The cloud platform server deploys and runs the simulation program. When the waveform data reading trigger conditions are met, it debugs and views the waveform data and returns it to the client for display.

[0013] Preferably, S300 includes:

[0014] S310: Acquires signals from multiple instance modules and compiles them into a netlist using a preset compilation and synthesis tool;

[0015] S320: Determine the connection relationships of all signals between instance modules based on the netlist, and generate a signal flow graph between different modules.

[0016] Preferably, the configuration instructions include FPGA configuration instructions and signal attribute configuration instructions, and S400 includes:

[0017] S410: Obtain the resource usage of different FPGAs, receive FPGA configuration instructions input by the user based on the signal flow diagram between different modules, the resource usage of each node in the instance tree, and the resource usage of different FPGAs, and configure the split multiple instance modules into different FPGAs according to the FPGA configuration instructions.

[0018] S420: Receives signal attribute configuration instructions input by the user according to preset signal transmission requirements, specifies the signal attributes between different FPGAs according to the signal attribute configuration instructions, configures the connection ports and inserts probes according to the signal attributes between different FPGAs, and obtains intermediate files.

[0019] Preferably, the resource usage of the FPGA in S410 is greater than the total resource usage of all instance modules configured in the current FPGA.

[0020] Preferably, the attributes of the signal in S420 include a data signal, a valid signal, and a release signal.

[0021] Preferably, after S600, it further includes:

[0022] If the waveform data does not meet the expected requirements, the corresponding waveform data is analyzed, the source code is modified according to the analysis results, and S100 is returned until the waveform data meets the expected requirements.

[0023] The above-described method for implementing a hardware simulation verification process based on an FPGA cloud platform can meet the verification requirements of hardware simulation for large-scale chip designs. It breaks down large designs into smaller modules and deploys them on different FPGAs. The cloud platform can meet the needs of multiple users, provide services to different users, sample user-generated bitstream schemes, and effectively protect users' intellectual property rights. Attached Figure Description

[0024] Figure 1 This is a flowchart illustrating a method for implementing a hardware simulation verification process based on an FPGA cloud platform in one embodiment of the present invention.

[0025] Figure 2 This is a flowchart of a method for implementing a hardware simulation verification process based on an FPGA cloud platform in another embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of the partitioned instance tree in one embodiment of the present invention. Detailed Implementation

[0027] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings.

[0028] In one embodiment, such as Figure 1 and 2 As shown, a method for implementing a hardware simulation verification process based on an FPGA cloud platform is described, and the method includes the following steps:

[0029] S100: The client obtains the source code file designed by the user, compiles and synthesizes the source code file, generates an instance tree, and obtains the resource usage of each node in the instance tree.

[0030] Specifically, user-designed source code files refer to source code written in a hardware description language, such as a .v file written in Verilog, used to complete the functional design of the chip.

[0031] S200: Receives global instance specification instructions and partitioning instructions input by the user based on the instance tree and the resource usage of each node in the instance tree. Specifies the global instance according to the global instance specification instructions and splits the instance tree into multiple instance modules according to the partitioning instructions.

[0032] S300: Generates a signal flow graph between different modules based on the global instance and multiple split instance modules.

[0033] In one embodiment, S300 includes:

[0034] S310: Acquires signals from multiple instance modules and compiles them into a netlist using a preset compilation and synthesis tool;

[0035] S320: Determine the connection relationships of all signals between instance modules based on the netlist, and generate a signal flow graph between different modules.

[0036] Specifically, the connection relationships between all signals between instance modules include signal inputs and outputs, and the default compilation and synthesis tool is Verific software.

[0037] S400: Obtain the resource usage of different FPGAs, receive configuration instructions input by the user based on the signal flow graph between different modules, the resource usage of each node in the instance tree, the resource usage of different FPGAs, and the preset signal transmission requirements, configure the multiple instance modules to different FPGAs according to the configuration instructions, specify the signal attributes between different FPGAs, configure the connection ports and insert probes according to the signal attributes between different FPGAs, and obtain intermediate files.

[0038] In one embodiment, the configuration instructions include FPGA configuration instructions and signal attribute configuration instructions, and S400 includes:

[0039] S410: Obtain the resource usage of different FPGAs, receive FPGA configuration instructions input by the user based on the signal flow diagram between different modules, the resource usage of each node in the instance tree, and the resource usage of different FPGAs, and configure the split multiple instance modules into different FPGAs according to the FPGA configuration instructions.

[0040] S420: The client receives the signal attribute configuration command input by the user according to the preset signal transmission requirements, specifies the signal attributes between different FPGAs according to the signal attribute configuration command, configures the connection port and inserts probes according to the signal attributes between different FPGAs, and obtains the intermediate file.

[0041] Furthermore, the resource consumption of the FPGA in S410 is greater than the total resource consumption of all instance modules configured in the current FPGA. The signal attributes in S420 include data, valid, and release signals.

[0042] Specifically, the instance tree partitioning graph is as follows: Figure 3As shown, large designs may have hundreds, thousands, or even tens of thousands of instance nodes. Each node placed in an FPGA requires a certain amount of resources, so large designs cannot be verified on a single FPGA due to resource constraints. Therefore, they need to be divided into subtrees 1 to 6, or even finer subtrees such as 7 to 16. If subtrees are divided into 1 to 6, subtrees 1 and 2 can be placed in FPGA1, subtrees 3 and 4 in FPGA2, and subtrees 5 and 6 in FPGA3. The division and placement must meet resource limitations; that is, when a large design is divided into instance trees and placed on different FPGAs, the resource usage of the divided instances must not exceed the resources of a single FPGA. Of course, communication between different instances after division is also necessary, and the amount of data communication after division should be minimized.

[0043] S500: Generates an FPGA sub-project top file based on the intermediate file, compiles the FPGA sub-project top file to generate a sub-project bit stream, and encrypts the sub-project bit stream before sending it to the cloud platform server.

[0044] S600: Receives the waveform data reading trigger conditions configured by the user and sends them to the cloud platform server. The cloud platform server deploys and runs the simulation program. When the waveform data reading trigger conditions are met, it debugs and views the waveform data and returns it to the client for display.

[0045] Specifically, in this embodiment, the waveform data reading trigger condition refers to certain signals or combinations of signals that trigger waveform reading when certain conditions are met. For example, when signal A equals 1 and signal B equals 0, waveform reading begins. This can be configured according to the user's specific needs.

[0046] In one embodiment, S600 is followed by:

[0047] If the waveform data does not meet the expected requirements, the corresponding waveform data is analyzed, the source code is modified according to the analysis results, and S100 is returned until the waveform data meets the expected requirements.

[0048] The above-described method for implementing a hardware simulation verification process based on an FPGA cloud platform can meet the verification requirements of hardware simulation for large-scale chip designs. It breaks down large designs into smaller modules and deploys them on different FPGAs. The cloud platform can meet the needs of multiple users, provide services to different users, sample user-generated bitstream schemes, and effectively protect users' intellectual property rights.

[0049] The above provides a detailed description of a method for implementing a hardware simulation verification process based on an FPGA cloud platform, as provided by this invention. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this invention.

Claims

1. A method for implementing a hardware simulation verification process based on an FPGA cloud platform, characterized in that, The method includes the following steps: S100: The client obtains the source code file designed by the user, compiles and synthesizes the source code file to generate an instance tree, and obtains the resource usage of each node in the instance tree; S200: Receive a global instance specification instruction and a partitioning instruction input by the user based on the instance tree and the resource usage of each node in the instance tree; specify a global instance according to the global instance specification instruction; and split the instance tree into multiple instance modules according to the partitioning instruction. S300: Generates a signal flow graph between different modules based on the global instance and multiple split instance modules; S400: Obtain the resource usage of different FPGAs, receive configuration instructions input by the user based on the signal flow graph between different modules, the resource usage of each node in the instance tree, the resource usage of different FPGAs, and preset signal transmission requirements, configure the multiple instance modules to different FPGAs according to the configuration instructions and specify the signal attributes between different FPGAs, configure the connection ports and insert probes according to the signal attributes between different FPGAs, and obtain intermediate files; S500: Generate an FPGA sub-project top file based on the intermediate file, compile the FPGA sub-project top file to generate a sub-project bit stream, encrypt the sub-project bit stream, and send it to the cloud platform server; S600: Receives the waveform data reading trigger condition configured by the user and sends it to the cloud platform server. The cloud platform server deploys and runs the simulation program. When the waveform data reading trigger condition is met, it debugs and views the waveform data and returns it to the client for display.

2. The method according to claim 1, characterized in that, The S300 includes: S310: Acquires signals from multiple instance modules and compiles them into a netlist using a preset compilation and synthesis tool; S320: Determine the connection relationships of all signals between instance modules based on the netlist, and generate a signal flow graph between different modules.

3. The method according to claim 2, characterized in that, Configuration instructions include FPGA configuration instructions and signal attribute configuration instructions. The S400 includes: S410: Obtain the resource usage of different FPGAs, receive FPGA configuration instructions input by the user based on the signal flow graph between the different modules, the resource usage of each node in the instance tree, and the resource usage of the different FPGAs, and configure the split multiple instance modules into different FPGAs according to the FPGA configuration instructions; S420: Receives a signal attribute configuration instruction input by the user according to preset signal transmission requirements, specifies the signal attributes between different FPGAs according to the signal attribute configuration instruction, configures the connection port and inserts probes according to the signal attributes between different FPGAs, and obtains an intermediate file.

4. The method according to claim 3, characterized in that, In the S410, the resource consumption of the FPGA is greater than the total resource consumption of all instance modules configured in the current FPGA.

5. The method according to claim 3, characterized in that, The attributes of signals in S420 include data signals, valid signals, and release signals.

6. The method according to claim 5, characterized in that, Following the S600 are: If the waveform data does not meet the expected requirements, the corresponding waveform data is analyzed, the source code is modified according to the analysis results, and S100 is returned until the waveform data meets the expected requirements.

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