A chip packaging method for resisting electromagnetic signal interference

Abstract

An embodiment of the present invention relates to a chip packaging method that is resistant to electromagnetic signal interference, comprising: loading a wafer having multiple wafers to be packaged with its front side facing downward into a packaging array board having multiple hollow card slot structures that match the wafer positions on the wafer; covering the packaging array board with a shielding plate corresponding to the dicing groove position of the wafer to shield the conduction area, and then spraying an insulating layer on the upper surface of the packaging array board so that the insulating layer covers the back of the wafer and the side exposed on the packaging array board; removing the shielding plate, spraying an anti-interference coating on the upper surface of the packaging array board so that the anti-interference coating is connected to the wires in the conductive structure; dicing the packaging array board between two adjacent conductive structures to obtain multiple semi-packaged chips; packaging the semi-packaged chips with an external packaging structure, and grounding the wires in the conductive structure located on the lower surface of the packaging array board through the external packaging structure.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a chip packaging method capable of resisting electromagnetic signal interference. Background Art

[0002] For chip packaging technology, electromagnetic interference (EMI) is a common problem that needs to be considered. Electromagnetic interference refers to the phenomenon that electromagnetic waves propagate through the air or other media and affect other electronic devices or systems. For chips, electromagnetic interference problems mainly come from other external signal sources, such as:

[0003] Abnormal currents and voltages of other electronic components on the circuit board, converter noise, such as switching power supplies, can also generate electromagnetic noise inside the package. High-speed signals on the circuit board may also generate higher electromagnetic radiation, such as clock signals, high-speed serial interfaces, etc. In addition, there is radio signal interference, which will affect the operation of the chip.

[0004] In order to solve these electromagnetic signal interference problems, a series of measures have been taken in the packaging design and manufacturing process, such as using shielding materials, isolating high-speed signals, optimizing packaging structures, and considering the reasonable layout of circuit boards and other electronic equipment to minimize the impact of electromagnetic interference.

[0005] However, in current chip packaging designs, most of them add additional metal shielding layers and plastic sealing layers to each die after chip dicing, and shield electromagnetic interference through layer-by-layer packaging. However, this approach increases the size of the chip, and the process is complicated and cumbersome. Summary of the invention

[0006] The purpose of the present invention is to provide a chip packaging method for resisting electromagnetic signal interference, forming a coating structure for resisting electromagnetic signal interference before wafer dicing, then obtaining a semi-packaged chip by dicing, and finally completing external packaging and realizing anti-interference grounding by external packaging. The method has simple steps, is easy to implement and mass industrialize.

[0007] To this end, an embodiment of the present invention provides a chip packaging method for resisting electromagnetic signal interference, comprising:

[0008] A wafer with multiple wafers to be packaged is loaded with its front side facing downward into a packaging array board with multiple hollow card slot structures matching the wafer positions on the wafer, the front side of the wafer is exposed from the card slots of the hollow card slot structures, and the back side of the wafer is exposed upward on the packaging array board; a conductive area is provided between two adjacent hollow card slot structures of the packaging array board, each conductive area has two conducting structures, and the conducting structures have wires connected to the upper surface and the lower surface of the packaging array board;

[0009] A shielding plate corresponding to the position of the wafer scribe groove is placed on the package array board to shield the conductive area, and then an insulating layer is sprayed on the upper surface of the package array board so that the insulating layer covers the back side of the wafer and the side exposed on the package array board;

[0010] Remove the shielding plate, and spray an anti-interference coating on the upper surface of the package array board so that the anti-interference coating is connected to the wires in the conductive structure;

[0011] Slicing the package array board along the space between two adjacent conductive structures to obtain a plurality of semi-packaged chips;

[0012] The semi-packaged chip is packaged with an external packaging structure, and the wires in the conductive structure located on the lower surface of the package array board are grounded through the external packaging structure.

[0013] Preferably, the anti-interference coating is a conductive material, and the anti-interference coating is grounded through the wire.

[0014] Preferably, the insulating layer is a polymer insulating material.

[0015] Preferably, the spraying is carried out by a sprayer.

[0016] Preferably, the distances from the two conducting structures in each transfer area to the adjacent hollow card slots are equal.

[0017] Preferably, the method further comprises: customizing the packaging array plate and the shielding plate according to the wafer.

[0018] The chip packaging method for resisting electromagnetic signal interference provided by the embodiment of the present invention forms a coating structure for resisting electromagnetic signal interference before wafer dicing, then obtains a semi-packaged chip by dicing, and finally completes external packaging and realizes anti-interference grounding by external packaging. The method has simple steps, is easy to implement and mass industrialize. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A flow chart of a chip packaging method for resisting electromagnetic signal interference provided by an embodiment of the present invention;

[0020] Figure 2 A schematic diagram of a chip packaging method for resisting electromagnetic signal interference provided by an embodiment of the present invention Figure 1 ;

[0021] Figure 3 A schematic diagram of a chip packaging method for resisting electromagnetic signal interference provided by an embodiment of the present invention Figure 2 ;

[0022] Figure 4 A schematic diagram of a chip packaging method for resisting electromagnetic signal interference provided by an embodiment of the present invention Figure 3 ;

[0023] Figure 5 A schematic diagram of a chip packaging method for resisting electromagnetic signal interference provided by an embodiment of the present invention Figure 4 ;

[0024] Figure 6 A schematic diagram of a chip packaging method for resisting electromagnetic signal interference provided by an embodiment of the present invention Figure 5 . DETAILED DESCRIPTION

[0025] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments.

[0026] The embodiment of the present invention provides a chip packaging method for resisting electromagnetic signal interference, such as Figure 1 As shown, the main steps include:

[0027] Step 110, loading a wafer with a plurality of wafers to be packaged with its front side facing downward into a packaging array board having a plurality of hollow card slot structures adapted to the positions of the wafers on the wafer, with the front side of the wafers exposed from the card slots of the hollow card slot structures, and the back side of the wafers exposed upward on the packaging array board;

[0028] Among them, the package array board is customized according to the wafer, and the package array board is different for different models of wafers. The hollow card slot structure of the customized package array board is consistent with the size and position of the wafer on the wafer. The lower surface of the hollow card slot structure is hollowed out, so that the front side of the wafer (i.e. the side of the lead) can be exposed from the hollow card slot structure.

[0029] Along a dicing direction, there is a conductive area between two adjacent hollow card slot structures, and each conductive area has two conductive structures, and the conductive structures have wires connected to the upper surface and the lower surface of the package array board. The distances between the two conductive structures in each conductive area and the adjacent hollow card slots are equal. Figure 2 As shown in the figure, the package array board is numbered 1, the hollow card slot structure is numbered 11, the wafer is numbered 2, and the conductive structure is numbered 12. The cross-sectional structure is shown in the figure. Figure 3 shown.

[0030] Step 120, covering the package array board with a shielding plate corresponding to the position of the wafer scribe groove to shield the conductive area, and then spraying an insulating layer on the upper surface of the package array board so that the insulating layer covers the back side of the wafer and the side exposed on the package array board;

[0031] The structure after occlusion is as follows Figure 4The shielding plate is numbered 3. After spraying, the structure after removing the shielding plate is as follows: Figure 5 As shown, the insulating layer is labeled 4.

[0032] The insulating layer is preferably made of a high molecular polymer insulating material, such as polyethylene, polyvinyl chloride, polypropylene, polyimide, polytetrafluoroethylene, etc. Preferably, a polyimide material is used.

[0033] The spraying can be carried out using an existing spraying machine. For different materials, suitable spray coatings and spraying techniques can be selected accordingly to ensure the spraying effect and material performance.

[0034] Step 130, removing the shielding plate, spraying an anti-interference coating on the upper surface of the package array board, so that the anti-interference coating is connected to the wires in the conductive structure;

[0035] The anti-interference coating is a conductive material, so the anti-interference coating is connected to the wire. After the package is completed, the wire is grounded to achieve shielding against electromagnetic signal interference. The structure after spraying the anti-interference coating is as follows: Figure 6 As shown, the insulating layer is labeled 5.

[0036] Step 140, dicing the package array board along the space between two adjacent conductive structures to obtain a plurality of semi-packaged chips;

[0037] Existing dicing equipment can be used for dicing, and the process of the present invention has good compatibility with existing equipment.

[0038] Step 150, encapsulating the semi-encapsulated chip with an external encapsulation structure, and grounding the wires in the conductive structure located on the lower surface of the encapsulation array board through the external encapsulation structure.

[0039] The packaging step of this invention has the same process and equipment as the existing chip packaging step, and only requires the wire to be grounded.

[0040] The chip packaging method for resisting electromagnetic signal interference provided by the embodiment of the present invention forms a coating structure for resisting electromagnetic signal interference before wafer dicing, then obtains a semi-packaged chip by dicing, and finally completes external packaging and realizes anti-interference grounding by external packaging. The method has simple steps, is easy to implement, and is suitable for large-scale industrial production.

[0041] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A chip packaging method for resisting electromagnetic signal interference, characterized in that: The chip packaging method comprises: A wafer with multiple wafers to be packaged is loaded with its front side facing downward into a packaging array board with multiple hollow card slot structures matching the wafer positions on the wafer, the front side of the wafer is exposed from the card slots of the hollow card slot structures, and the back side of the wafer is exposed upward on the packaging array board; a conductive area is provided between two adjacent hollow card slot structures of the packaging array board, each conductive area has two conducting structures, and the conducting structures have wires connected to the upper surface and the lower surface of the packaging array board; A shielding plate corresponding to the position of the wafer scribe groove is placed on the package array board to shield the conductive area, and then an insulating layer is sprayed on the upper surface of the package array board so that the insulating layer covers the back side of the wafer and the side exposed on the package array board; Remove the shielding plate, and spray an anti-interference coating on the upper surface of the package array board so that the anti-interference coating is connected to the wires in the conductive structure; Slicing the package array board along the space between two adjacent conductive structures to obtain a plurality of semi-packaged chips; The semi-packaged chip is packaged with an external packaging structure, and the wires in the conductive structure located on the lower surface of the package array board are grounded through the external packaging structure.

2. The chip packaging method according to claim 1, characterized in that: The anti-interference coating is a conductive material, and the anti-interference coating is grounded through the wire.

3. The chip packaging method according to claim 1, characterized in that: The insulating layer is made of polymer insulating material.

4. The chip packaging method according to claim 1, characterized in that: The spraying is carried out by a spraying machine.

5. The chip packaging method according to claim 1, characterized in that: The distances between the two conducting structures in each transmission area and the adjacent hollow card slots are equal.

6. The chip packaging method according to claim 1, characterized in that: The method further includes: customizing the package array plate and the shielding plate according to the wafer.

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