A power quality monitoring circuit for a control device

Abstract

The application discloses a power quality monitoring circuit of a control device, which comprises a voltage detection circuit, the voltage detection circuit monitors bus voltage and outputs corresponding control signals to a control system according to a monitoring result, and the control system receives the control signals to control the operation of the control device; the power quality monitoring circuit comprises a first determination circuit, a second determination circuit, a third determination circuit, a fourth determination circuit, a first signal processing circuit and a second signal processing circuit; the first determination circuit is connected with the first signal processing circuit and the second signal processing circuit, the first signal processing circuit is connected with the fourth determination circuit, and the second signal processing circuit is further connected with the second determination circuit and the third determination circuit. The power monitoring circuit of the control device has the advantages that the function is single, the power voltage abnormal condition cannot be identified, and the control device cannot be controlled according to different response strategies based on power fluctuation.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and in particular to a power quality monitoring circuit for a control device. Background Technology

[0002] Power supply is a crucial component of modern electrical control equipment, and its quality directly determines the safe and stable operation of the system. However, power supply fluctuations can occur due to various factors, including the inherent quality of the power supply itself, deterioration of electronic components, or external electromagnetic interference. When the power supply voltage fluctuates, excessively high voltage can cause electrical breakdown and damage to system equipment; conversely, excessively low voltage can lead to abnormal restarts of internal storage devices, data loss, errors, or damage to underlying firmware. Therefore, power supply quality is of paramount importance to control system equipment that performs data storage and processing.

[0003] However, the main drawbacks of existing power monitoring circuits in control equipment are as follows: they can only monitor high voltage or low voltage, each circuit can only perform one function, they are limited in function, after detecting an abnormal power voltage, they cannot identify the specific abnormal voltage situation, and they do not distinguish the degree of power fluctuation, thus failing to help the control system to reasonably control the operation of the equipment when the power voltage fluctuates. Summary of the Invention

[0004] This invention provides a power quality monitoring circuit for control equipment to overcome the problems of existing power monitoring circuits for control equipment having limited functions, failing to identify specific voltage abnormalities after detecting power voltage anomalies, and not distinguishing the degree of power fluctuations, thus failing to help the control system to reasonably control equipment operation when power voltage fluctuates.

[0005] To achieve the above objectives, the technical solution of the present invention is as follows:

[0006] A power quality monitoring circuit for a control device includes a voltage detection circuit. The voltage detection circuit monitors the fluctuation value of the bus voltage in the control system and outputs a corresponding control signal to the control system based on the fluctuation value of the bus voltage. The control system controls the operation of the device based on the control signal.

[0007] The voltage detection circuit includes a voltage determination circuit, a first signal processing circuit, and a second signal processing circuit; the voltage determination circuit is used to determine the control signals of the first signal processing circuit and the second signal processing circuit based on the bus voltage fluctuation, and the control signals include high-level signals and low-level signals.

[0008] Furthermore, the voltage determination circuit includes a first determination circuit, a second determination circuit, a third determination circuit, and a fourth determination circuit. The first signal processing circuit is electrically connected to the first determination circuit and the fourth determination circuit, and the second signal processing circuit is electrically connected to the second determination circuit and the third determination circuit.

[0009] The second signal processing circuit includes a first operational amplifier U1B, a second operational amplifier U2B, a fifth transistor Q5, a seventh transistor Q7, an eighth transistor Q8, a third Zener diode T3, and a second capacitor C2. The positive input terminal of the first operational amplifier U1B is connected to one end of the twenty-second resistor R22. The negative input terminal of the first operational amplifier U1B, the emitter of the eighth transistor Q8, and one end of the thirty-second resistor R32 are connected. The collector of the eighth transistor Q8 is connected to the emitter of the fifth transistor Q5. The output terminal of the first operational amplifier U1B is connected to one end of the twenty-fourth resistor R24. The other end of the twenty-fourth resistor R24, one end of the third Zener diode T3, one end of the second capacitor C2, and the positive input terminal of the second operational amplifier U2B are connected. One end of the third Zener diode T3, one end of the second capacitor C2, and the other end of the thirty-second resistor R32 are connected.

[0010] The negative input terminal of the second operational amplifier U2B is connected to one end of the forty-first resistor R41 and one end of the forty-second resistor R42. The other end of the forty-first resistor R41 is connected to the bus, and the other end of the forty-second resistor R42 is grounded. The output terminal of the second operational amplifier U2B is connected to one end of the forty-fifth resistor R45. The other end of the forty-fifth resistor R45 is connected to the base of the seventh transistor Q7. The collector of the seventh transistor Q7 is connected to the eighteenth resistor R18, and the emitter of the seventh transistor Q7 is grounded.

[0011] Furthermore, the first signal processing circuit includes a first resistor R1, a fifth resistor R5, a ninth resistor R9, a thirteenth resistor R13, a fifteenth resistor R15, a first transistor Q1, and a fourth transistor Q4. The base of the first transistor Q1 is connected to one end of the fifth resistor R5, the emitter of the first transistor Q1 is connected to one end of the first resistor R1, the base of the fourth transistor Q4 is connected to one end of the fifteenth resistor R15, the collector of the fourth transistor Q4 is connected to one end of the ninth resistor R9, the other end of the ninth resistor R9 is connected to the other end of the first resistor R1, and the emitters of the first transistor Q1, the fourth transistor Q4, and one end of the thirteenth resistor R13 are connected together.

[0012] Furthermore, the first determination circuit includes a fifth capacitor C5, a sixth Zener diode T6, a third operational amplifier U3B, a thirty-sixth resistor R36, a thirty-seventh resistor R37, a thirty-eighth resistor R38, a thirty-ninth resistor R39, a fortieth resistor R40, an eleventh transistor Q11, and a sixth diode D6; one end of the fifth capacitor C5 and one end of the sixth Zener diode T6 are grounded, and the other ends of the fifth capacitor C5, the other end of the sixth Zener diode T6, and one end of the fortieth resistor R40 are all connected to the negative input terminal of the third operational amplifier U3B; one end of the thirty-seventh resistor R37 is connected to the bus, one end of the thirty-eighth resistor R38 is grounded, and the thirty-seventh resistor R37... The other end, the other end of the thirty-eighth resistor R38, and the other end of the fortieth resistor R40 are all connected to the positive input terminal of the third operational amplifier U3B; the output terminal of the third operational amplifier U3B is connected to one end of the thirty-ninth resistor R39, the other end of the thirty-ninth resistor R39 is connected to the base of the eleventh transistor Q11, the collector of the eleventh transistor Q11, the cathode of the sixth diode D6, one end of the thirty-sixth resistor R36, and the other end of the fifteenth resistor R15 are connected, the other end of the thirty-sixth resistor R36 is connected to the other end of the eighteenth resistor R18, and the emitter of the eleventh transistor Q11 is connected to the anode of the sixth diode D6 and grounded.

[0013] Furthermore, the second determination circuit includes a fourth capacitor C4, a fifth Zener diode T5, a fourth operational amplifier U3A, a twenty-seventh resistor R27, a twenty-eighth resistor R28, a twenty-ninth resistor R29, a thirtieth resistor R30, a thirty-third resistor R33, a thirty-fourth resistor R34, a thirty-fifth resistor R35, a ninth transistor Q9, a thirteenth transistor Q10, a fourth diode D4, and a fifth diode D5; one end of the fourth capacitor C4 and one end of the fifth Zener diode T5 are grounded, and the other ends of the fourth capacitor C4, the fifth Zener diode T5, and one end of the thirty-fifth resistor R35 are all connected to the negative input terminal of the fourth operational amplifier U3A; one end of the thirtieth resistor R30 is connected to the bus, one end of the thirty-third resistor R33 is grounded, and the other ends of the thirtieth resistor R30, the thirty-third resistor R33, and the thirty-fifth resistor R35 are all connected to the positive input terminal of the third operational amplifier U3B; the third operational amplifier... The output pin 1 of the amplifier U3B is connected to one end of the 34th resistor R34. The other end of the 34th resistor R34 is connected to the base of the 13th transistor Q10. The collector of the 13th transistor Q10, the cathode of the 5th diode D5, one end of the 31st resistor R31, and one end of the 29th resistor R29 are connected. The other end of the 31st resistor R31 is connected to the base of the 9th transistor Q9. The collector of the 9th transistor Q9, one end of the 4th diode D4, one end of the 28th resistor R28, and one end of the 27th resistor R27 are connected. The other end of the 28th resistor R28 is connected to the base of the 8th transistor Q8. The emitter of the 13th transistor Q10, the anode of the 5th diode D5, the emitter of the 9th transistor Q9, the anode of the 4th diode D4, and the other end of the 32nd resistor are grounded. The other end of the 29th resistor R29 and the other end of the 27th resistor R27 are connected to the other end of the 18th resistor R18.

[0014] Furthermore, the third determination circuit includes a third capacitor C3, a fourth Zener diode T4, a fifth operational amplifier U2A, a fourteenth resistor R14, a seventeenth resistor R17, a twentieth resistor R20, a twenty-first resistor R21, a twenty-third resistor R23, a twenty-fifth resistor R25, a twenty-sixth resistor R26, a sixth transistor Q6, and a third diode D3; one end of the third capacitor C3 and one end of the fourth Zener diode T4 are grounded, and the other ends of the third capacitor C3, the fourth Zener diode T4, and one end of the twenty-sixth resistor R26 are all connected to the negative input terminal of the fifth operational amplifier U2A; one end of the twenty-first resistor R21 is connected to the bus, one end of the twenty-third resistor R23 is grounded, and the other ends of the twenty-first resistor R21, the twenty-third resistor R23, and the twenty-sixth resistor R26 are all connected to... The positive input terminal of the fifth operational amplifier U2A is connected to one end of the twenty-fifth resistor R25. The other end of the twenty-fifth resistor R25 is connected to the base of the sixth transistor Q6. The collector of the sixth transistor Q6, the cathode of the third diode D3, one end of the seventeenth resistor R17, and one end of the twentieth resistor R20 are connected. The other end of the twentieth resistor R20 is connected to the base of the fifth transistor Q5. The other end of the seventeenth resistor R17 and one end of the fourteenth resistor R14 are connected to the other end of the eighteenth resistor R18. The other end of the fourteenth resistor R14 is connected to the collector of the fifth transistor Q5. The other end of the thirty-sixth resistor R36 is connected to the other end of the eighteenth resistor R18. The emitter of the sixth transistor Q6 is connected to the anode of the third diode D3 and grounded.

[0015] Furthermore, the fourth determination circuit includes a first capacitor C1, a second Zener diode T2, a sixth operational amplifier U1A, a third resistor R3, a sixth resistor R6, an eighth resistor R8, a seventh resistor R7, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a forty-third resistor R43, a forty-fourth resistor R44, a second transistor Q2, a third transistor Q3, a first diode D1, and a second diode D2; one end of the first capacitor C1 and one end of the second Zener diode T2 are grounded, and the other ends of the first capacitor C1, the second Zener diode T2, and one end of the twelfth resistor R12 are all connected to the negative input terminal of the sixth operational amplifier U1A; one end of the seventh resistor R7 is connected to the bus, one end of the tenth resistor R10 is grounded, and the other ends of the seventh resistor R7, the tenth resistor R10, and the twelfth resistor R12 are all connected to the negative input terminal of the sixth operational amplifier U1A; one end of the seventh resistor R7 is connected to the busbar, one end of the tenth resistor R10 is grounded, and the other ends of the seventh resistor R7, the tenth resistor R10, and the twelfth resistor R12 are all connected to the busbar. All are connected to the positive input terminal of the sixth operational amplifier U1A; the output pin 1 of the sixth operational amplifier U1A is connected to one end of the eleventh resistor R11, the other end of the eleventh resistor R11 is connected to the base of the third transistor Q3, the collector of the third transistor Q3, the cathode of the second diode D2, one end of the sixth resistor R6 and one end of the eighth resistor R8 are connected, the other end of the eighth resistor R8 is connected to the base of the second transistor Q2, the collector of the second transistor Q2, one end of the first diode D1, one end of the third resistor R3 and one end of the fifth resistor R5 are connected, the other end of the third resistor R3, the other end of the first resistor R1 and the other end of the sixth resistor R6 are connected to the other end of the eighteenth resistor R18, and the other end of the twenty-ninth resistor R29 and the other end of the twenty-seventh resistor R27 are connected to the other end of the eighteenth resistor R18. The emitter of the third transistor Q3, the anode of the second diode D2, the emitter of the second transistor Q2, the anode of the first diode D1, and the other end of the thirteenth resistor R13 are grounded; the output pin 4 of the sixth operational amplifier U1A is connected to one end of the forty-third resistor R43, one end of the forty-fourth resistor R44, the output pin 4 of the fifth operational amplifier U2A, and the output pin 4 of the fourth operational amplifier U3A; the other end of the forty-third resistor R43 is connected to the busbar, and the other end of the forty-fourth resistor R44 is grounded.

[0016] Furthermore, the other end of the 22nd resistor R22 is connected to one end of the 16th resistor R16 and one end of the 19th resistor R19. The other end of the 16th resistor R16 is connected to the busbar, and the other end of the 19th resistor R19 is grounded.

[0017] Furthermore, the other end of the eighteenth resistor R18 is connected to one end of the first Zener diode T1, the other end of the first Zener diode T1 is connected to one end of the second resistor R2 and one end of the fourth resistor R4, the other end of the second resistor R2 is connected to the busbar, and the other end of the fourth resistor R4 is grounded.

[0018] Beneficial Effects: This invention provides a power quality monitoring circuit for control equipment. It employs a voltage detection circuit to monitor the bus voltage and outputs corresponding control signals to the control system based on the monitoring results. The control system receives these control signals and controls the equipment's operation. When abnormal fluctuations occur in the power system voltage within the control equipment, the power quality monitoring circuit can distinguish the detailed abnormal state of the voltage fluctuation and issue different types of signals to the entire system based on these different states. The control equipment can respond differently to these signals. The system can perform power-down protection, data backup, and alarm responses based on different types of signals, thereby ensuring that the system's hardware is not damaged by abnormal voltage, and also ensuring that stored data or programs are not damaged by abnormal voltage. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a circuit diagram of a power quality monitoring circuit for a control device according to the present invention.

[0021] Figure 2 This is a connection architecture diagram of a power quality monitoring circuit for a control device according to the present invention.

[0022] Figure 3 This is a schematic diagram of the monitoring area of ​​a power quality monitoring circuit for a control device according to the present invention.

[0023] In the diagram: 101, First determination circuit; 102, Second determination circuit; 103, Third determination circuit; 104, Fourth determination circuit; 105, First signal processing circuit; 106, Second signal processing circuit. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] This embodiment provides a power quality monitoring circuit for a control device, such as... Figure 1 As shown, the system includes a voltage detection circuit. This circuit monitors the fluctuations in the bus voltage within the control system and outputs corresponding control signals to the control system based on these fluctuations. The control system then controls the operation of the equipment according to these control signals. The voltage detection circuit includes a voltage determination circuit, a first signal processing circuit, and a second signal processing circuit. The voltage determination circuit determines the control signals for the first and second signal processing circuits based on the bus voltage fluctuations. These control signals include high-level and low-level signals. The voltage determination circuit includes a first determination circuit, a second determination circuit, a third determination circuit, and a fourth determination circuit. The first signal processing circuit is electrically connected to the first and fourth determination circuits, and the second signal processing circuit is electrically connected to the second and third determination circuits.

[0026] The power quality monitoring circuit of the present invention has the main function of monitoring the detailed voltage fluctuation status of the control equipment and helping the control equipment to complete hardware protection and data protection according to different models. The voltage detection circuit can distinguish voltage values. Taking the first preset voltage VT1 as an example, one end of the sixth Zener diode T6 is connected to the bus, and the other end of the sixth Zener diode T6 is connected to the negative input terminal of the third operational amplifier U3B. (Given the characteristic of a Zener diode, it conducts when the voltage is above a certain value and does not conduct when the voltage is below a certain value.) Here, the sixth Zener diode T6 is the selected result, and its breakdown voltage is the first preset voltage VT1. Therefore, when the bus voltage Vt0 < Vt1, the sixth Zener diode T6 does not conduct, meaning the negative input terminal of the third operational amplifier U3B is at a high voltage, and the third operational amplifier U3B does not operate. At this time, there is no voltage output at pin 7 of the third operational amplifier U3B. Conversely, when the bus voltage Vt0 is greater than the first preset voltage VT1, the sixth Zener diode T6 breaks down, and the third operational amplifier U3B is essentially directly connected to VIN-, forming a circuit. At this time, the third operational amplifier U3B operates, and its output pin 7 outputs a high level. Therefore, it can be seen that the sixth Zener diode T6, the fifth Zener diode T5, the fourth Zener diode T4, and the second Zener diode T2 can have their first preset voltage Vt1, second preset voltage Vt2, third preset voltage Vt3, and fourth preset voltage Vt4 directly set through component selection.

[0027] like Figure 3 As shown, this power quality monitoring circuit divides the entire voltage input range into five monitoring zones by comparing the bus voltage Vt0 with four preset voltages (first preset voltage Vt1, second preset voltage Vt2, third preset voltage Vt3, and fourth preset voltage Vt4). Specifically, 0 < Vt0 < Vt1 is considered the first monitoring zone, Vt1 < Vt0 < Vt2 is considered the second monitoring zone, Vt2 < Vt0 < Vt3 is considered the third monitoring zone, Vt3 < Vt0 < Vt4 is considered the fourth monitoring zone, and Vt4 < Vt0 is considered the fifth monitoring zone. Specifically, when Vt0 < Vt1, the first determination circuit outputs a high level; when Vt0 > Vt1, the first determination circuit outputs a low level. When Vt0 < Vt2, the second determination circuit outputs a low level; when Vt0 > Vt2, the second determination circuit outputs a high level. When Vt0 < Vt3, the third determination circuit outputs a high level; when Vt0 > Vt3, the third determination circuit outputs a low level. When Vt0 < Vt4, the fourth determination circuit outputs a low level; when Vt0 > Vt4, the fourth determination circuit outputs a high level. Figure 2As shown, this invention provides a power quality monitoring circuit for a control device that can identify five monitoring zones of the power supply system voltage Vin (bus voltage Vt0) and respond differently to each zone. When the power supply system voltage Vin is in the third monitoring zone of the bus voltage Vt0, i.e., between Vt2 and Vt3, the power quality monitoring circuit does not respond; the first signal processing circuit outputs Vout1 as low, and the second signal processing circuit outputs Vout2 as high. When the power supply system voltage Vin is in the second or fourth monitoring zone, i.e., between Vt1 and Vt2 or between Vt3 and Vt4, the first signal processing circuit outputs Vout1 as low, while the second signal processing circuit outputs Vout2, which flips to emit a slow-responding low-level signal. At this time, the control device... The device can perform data backup operations based on the level signals of the output terminals Vout2 and Vout1 of the second signal processing circuit, and can also issue warnings to the equipment operators. When the power supply system voltage Vin is in the first monitoring zone or the fifth monitoring zone, i.e. between 0 and Vt1 and between Vt4 and Vt5, the output level of Vout1 of the first signal processing circuit flips, sending an immediate high-level signal, while the output level of Vout2 of the second signal processing circuit remains low. At this time, the control device will immediately power down, thereby protecting the control device hardware from damage. In summary, the power quality monitoring circuit outputs three signal states: When the first signal processing circuit outputs Vout1 at a low level and the second signal processing circuit outputs Vout2 at a high level, it is set as a "no action" signal, and the control system receives the "no action" signal to control the equipment to operate normally; when the first signal processing circuit outputs Vout1 at a low level and the second signal processing circuit outputs Vout2 from high to low, it is set as a "slow action" signal, and the control system receives the "slow action" signal to control the equipment to perform data backup operations. The purpose of the "slow action" is to prevent the control system from frequently issuing control commands due to small fluctuations in the bus voltage, which would lead to frequent control of the equipment to perform data backups. The "slow action" can filter out small voltage fluctuations and save hardware and software resources such as memory and CPU computing power of the control equipment; when the first signal processing circuit outputs Vout1 from low to high and the second signal processing circuit outputs Vout2 at a low level, it is set as a "fast action" signal, and the control system receives the "fast action" signal to immediately power down the entire equipment, thereby protecting the equipment from damage. The purpose of the "fast action" is to immediately power down the equipment to prevent the equipment from being electrically damaged.

[0028] In a specific embodiment, the second signal processing circuit includes a first operational amplifier U1B, a second operational amplifier U2B, a fifth transistor Q5, a seventh transistor Q7, an eighth transistor Q8, a third Zener diode T3, and a second capacitor C2. The positive input terminal of the first operational amplifier U1B is connected to one end of the twenty-second resistor R22. The negative input terminal of the first operational amplifier U1B, the emitter of the eighth transistor Q8, and one end of the thirty-second resistor R32 are connected. The collector of the eighth transistor Q8 is connected to the emitter of the fifth transistor Q5. The output terminal of the first operational amplifier U1B is connected to one end of the twenty-fourth resistor R24. The other end of the twenty-fourth resistor R24, one end of the third Zener diode T3, and the second capacitor C2 are also connected. One end of capacitor C2 is connected to the positive input terminal of the second operational amplifier U2B. One end of the third Zener diode T3, one end of the second capacitor C2, and the other end of the thirty-second resistor R32 are connected. The negative input terminal of the second operational amplifier U2B, one end of the forty-first resistor R41, and one end of the forty-second resistor R42 are connected. The other end of the forty-first resistor R41 is connected to the bus, and the other end of the forty-second resistor R42 is grounded. The output terminal of the second operational amplifier U2B is connected to one end of the forty-fifth resistor R45. The other end of the forty-fifth resistor R45 is connected to the base of the seventh transistor Q7. The collector of the seventh transistor Q7 is connected to the eighteenth resistor R18, and the emitter of the seventh transistor Q7 is grounded. The second signal processing circuit is the response circuit for the second and fourth monitoring zones. When the bus voltage Vt0 is operating in the second and fourth monitoring zones, the second determination circuit outputs a low level, and the third determination circuit outputs a low level. If either the second or third determination circuit outputs a low level, the output terminal Vout2 of the second signal processing circuit will output a low level.

[0029] In a specific embodiment, the first signal processing circuit includes a first resistor R1, a fifth resistor R5, a ninth resistor R9, a thirteenth resistor R13, a fifteenth resistor R15, a first transistor Q1, and a fourth transistor Q4. The base of the first transistor Q1 is connected to one end of the fifth resistor R5, and the emitter of the first transistor Q1 is connected to one end of the first resistor R1. The base of the fourth transistor Q4 is connected to one end of the fifteenth resistor R15, and the collector of the fourth transistor Q4 is connected to one end of the ninth resistor R9. The other end of the ninth resistor R9 is connected to the other end of the first resistor R1. The emitters of the first transistor Q1, the emitters of the fourth transistor Q4, and one end of the thirteenth resistor R13 are connected. The first signal processing circuit is a response circuit for the first and fifth monitoring zones. When the bus voltage Vt0 operates in the first and fifth monitoring zones, the first determination circuit outputs a high level, and the fourth determination circuit outputs a high level. If either the first determination circuit or the fourth determination circuit outputs a high level, the output terminal Vout1 of the first signal processing circuit will output a high level.

[0030] In a specific embodiment, the first determination circuit includes a fifth capacitor C5, a sixth Zener diode T6, a third operational amplifier U3B, a thirty-sixth resistor R36, a thirty-seventh resistor R37, a thirty-eighth resistor R38, a thirty-ninth resistor R39, a fortieth resistor R40, an eleventh transistor Q11, and a sixth diode D6; one end of the fifth capacitor C5 and one end of the sixth Zener diode T6 are grounded, and the other ends of the fifth capacitor C5, the other end of the sixth Zener diode T6, and one end of the fortieth resistor R40 are all connected to the negative input terminal of the third operational amplifier U3B; one end of the thirty-seventh resistor R37 is connected to the bus, one end of the thirty-eighth resistor R38 is grounded, and the thirty-seventh resistor R39 is grounded. The other end of resistor 7, the other end of resistor 38, and the other end of resistor 40 are all connected to the positive input terminal of the third operational amplifier U3B; the output terminal of the third operational amplifier U3B is connected to one end of resistor 39, the other end of resistor 39 is connected to the base of transistor Q11, the collector of transistor Q11, the cathode of diode D6, one end of resistor 36, and the other end of resistor R15 are connected, the other end of resistor 36 is connected to the other end of resistor R18, and the emitter of transistor Q11 is connected to the anode of diode D6 and grounded.

[0031] In a specific embodiment, the second determination circuit includes a fourth capacitor C4, a fifth Zener diode T5, a fourth operational amplifier U3A, a twenty-seventh resistor R27, a twenty-eighth resistor R28, a twenty-ninth resistor R29, a thirtieth resistor R30, a thirty-third resistor R33, a thirty-fourth resistor R34, a thirty-fifth resistor R35, a ninth transistor Q9, a thirteenth transistor Q10, a fourth diode D4, and a fifth diode D5; one end of the fourth capacitor C4 and one end of the fifth Zener diode T5 are grounded, and the other ends of the fourth capacitor C4, the fifth Zener diode T5, and one end of the thirty-fifth resistor R35 are all connected to the negative input terminal of the fourth operational amplifier U3A; one end of the thirtieth resistor R30 is connected to the bus, one end of the thirty-third resistor R33 is grounded, and the other ends of the thirtieth resistor R30, the thirty-third resistor R33, and the thirty-fifth resistor R35 are all connected to the positive input terminal of the third operational amplifier U3B; the third operational amplifier... The output pin 1 of amplifier U3B is connected to one end of the 34th resistor R34. The other end of the 34th resistor R34 is connected to the base of the 13th transistor Q10. The collector of the 13th transistor Q10, the cathode of the 5th diode D5, one end of the 31st resistor R31, and one end of the 29th resistor R29 are connected. The other end of the 31st resistor R31 is connected to the base of the 9th transistor Q9. The collector of the 9th transistor Q9, one end of the 4th diode D4, one end of the 28th resistor R28, and one end of the 27th resistor R27 are connected. The other end of the 28th resistor R28 is connected to the base of the 8th transistor Q8. The emitter of the 13th transistor Q10, the anode of the 5th diode D5, the emitter of the 9th transistor Q9, the anode of the 4th diode D4, and the other end of the 32nd resistor are grounded. The other end of the 29th resistor R29 and the other end of the 27th resistor R27 are connected to the other end of the 18th resistor R18.

[0032] In a specific embodiment, the third determination circuit includes a third capacitor C3, a fourth Zener diode T4, a fifth operational amplifier U2A, a fourteenth resistor R14, a seventeenth resistor R17, a twentieth resistor R20, a twenty-first resistor R21, a twenty-third resistor R23, a twenty-fifth resistor R25, a twenty-sixth resistor R26, a sixth transistor Q6, and a third diode D3. One end of the third capacitor C3 and one end of the fourth Zener diode T4 are grounded, and the other ends of the third capacitor C3, the fourth Zener diode T4, and one end of the twenty-sixth resistor R26 are all connected to the negative input terminal of the fifth operational amplifier U2A. One end of the twenty-first resistor R21 is connected to the busbar, one end of the twenty-third resistor R23 is grounded, and the other ends of the twenty-first resistor R21, the twenty-third resistor R23, and the twenty-sixth resistor R26 are all connected to... The output pin 1 of the fifth operational amplifier U2A is connected to one end of the twenty-fifth resistor R25. The other end of the twenty-fifth resistor R25 is connected to the base of the sixth transistor Q6. The collector of the sixth transistor Q6, the cathode of the third diode D3, one end of the seventeenth resistor R17, and one end of the twentieth resistor R20 are connected. The other end of the twentieth resistor R20 is connected to the base of the fifth transistor Q5. The other end of the seventeenth resistor R17 and one end of the fourteenth resistor R14 are connected to the other end of the eighteenth resistor R18. The other end of the fourteenth resistor R14 is connected to the collector of the fifth transistor Q5. The other end of the thirty-sixth resistor R36 is connected to the other end of the eighteenth resistor R18. The emitter of the sixth transistor Q6 is connected to the anode of the third diode D3 and grounded.

[0033] In a specific embodiment, the fourth determination circuit includes a first capacitor C1, a second Zener diode T2, a sixth operational amplifier U1A, a third resistor R3, a sixth resistor R6, an eighth resistor R8, a seventh resistor R7, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a forty-third resistor R43, a forty-fourth resistor R44, a second transistor Q2, a third transistor Q3, a first diode D1, and a second diode D2; one end of the first capacitor C1 and one end of the second Zener diode T2 are grounded, and the other ends of the first capacitor C1, the other end of the second Zener diode T2, and one end of the twelfth resistor R12 are all connected to the negative input terminal of the sixth operational amplifier U1A; one end of the seventh resistor R7 is connected to the bus, one end of the tenth resistor R10 is grounded, and the other ends of the seventh resistor R7, the other end of the tenth resistor R10, and the other end of the twelfth resistor R12 are all grounded. One end is connected to the positive input terminal of the sixth operational amplifier U1A; the output pin 1 of the sixth operational amplifier U1A is connected to one end of the eleventh resistor R11, the other end of the eleventh resistor R11 is connected to the base of the third transistor Q3, the collector of the third transistor Q3, the cathode of the second diode D2, one end of the sixth resistor R6 and one end of the eighth resistor R8 are connected, the other end of the eighth resistor R8 is connected to the base of the second transistor Q2, the collector of the second transistor Q2, one end of the first diode D1, one end of the third resistor R3 and one end of the fifth resistor R5 are connected, the other end of the third resistor R3, the other end of the first resistor R1 and the other end of the sixth resistor R6 are connected to the other end of the eighteenth resistor R18, and the other end of the twenty-ninth resistor R29 and the other end of the twenty-seventh resistor R27 are connected to the other end of the eighteenth resistor R18. The emitter of the third transistor Q3, the anode of the second diode D2, the emitter of the second transistor Q2, the anode of the first diode D1, and the other end of the thirteenth resistor R13 are grounded; the output pin 4 of the sixth operational amplifier U1A is connected to one end of the forty-third resistor R43, one end of the forty-fourth resistor R44, the output pin 4 of the fifth operational amplifier U2A, and the output pin 4 of the fourth operational amplifier U3A; the other end of the forty-third resistor R43 is connected to the busbar, and the other end of the forty-fourth resistor R44 is grounded.

[0034] In a specific embodiment, the other end of the 22nd resistor R22 is connected to one end of the 16th resistor R16 and one end of the 19th resistor R19. The other end of the 16th resistor R16 is connected to the busbar, and the other end of the 19th resistor R19 is grounded.

[0035] In a specific embodiment, the other end of the eighteenth resistor R18 is connected to one end of the first Zener diode T1, the other end of the first Zener diode T1 is connected to one end of the second resistor R2 and one end of the fourth resistor R4, the other end of the second resistor R2 is connected to the busbar, and the other end of the fourth resistor R4 is grounded.

[0036] The working principle is as follows: The specific circuit design is as follows: Figure 1As shown, Vt0+ and Vt0- are the positive and negative terminals of the DC bus of the power supply system Vt0 within the control equipment, respectively. When Vt0 operates in the third monitoring zone, the monitoring circuit does not activate, the first signal processing circuit outputs a low level at Vout1, and the second signal processing circuit outputs a high level at Vout2. When Vt0 operates in the second or fourth monitoring zone, the monitoring circuit activates, the first signal processing circuit output Vout1 remains at a low level, and the second signal processing circuit output Vout2 flips and slowly outputs a low level. When Vt0 operates in the first or fifth monitoring zone, the monitoring circuit activates, the first signal processing circuit output Vout1 flips and immediately outputs a high level, and the second signal processing circuit output Vout2 remains at a low level. Specifically, when the bus voltage Vt0 is in the third monitoring zone, i.e., Vt1 < Vt2 < Vt0 < Vt3 < Vt4, the bus voltage is transmitted to the positive input terminal of the fourth operational amplifier U3A after being divided by the thirtieth resistor R30 and the thirty-first resistor R33. The bus voltage then flows into the negative terminal Vt0- of the bus through the thirty-fifth resistor R35, the fifth Zener diode T5, and the fourth capacitor C4. At this time, the voltage at the positive terminal of the fifth Zener diode T5 is extracted and connected to the negative input terminal of the fourth operational amplifier U3A. The 35th resistor R35 is a current-limiting protection resistor, and the 4th capacitor C4 acts as a filter to ensure that the voltage across the 5th Zener diode T5 is relatively stable. The selection of the 5th Zener diode T5 can be based on the specific parameter Vt2. The circuit is designed so that when the bus voltage Vt0 > the second preset voltage Vt2, the 5th Zener diode T5 stabilizes the voltage of the 4th operational amplifier U3A at Vt2. At this time, after setting the values ​​of the 30th resistor R30 and the 33rd resistor R33, it is ensured that the voltage at the positive terminal of the 4th operational amplifier U3A is greater than Vt2. The output pin 1 of the 4th operational amplifier U3A sends a high-level signal, which is then connected to the base of the 13th transistor Q10 after being current-limited by the 34th resistor R34. At this time, the 13th transistor Q10 is turned on. The collector of the thirteenth transistor Q10 is connected to the twenty-seventh resistor R27, the twenty-ninth resistor R29, the thirty-first resistor R31, and the fifth diode D5. Resistors R29 and R31 are used for current limiting protection, while diode D5 is used for freewheeling protection. Resistor R29 is connected to the positive and negative terminals of the system voltage Vin via the first Zener diode T1, the second resistor R2, and the fourth resistor R4. The second resistor R2 and the fourth resistor R4 divide the system voltage Vin and connect it to resistor R29 to power the thirteenth transistor Q10. The first Zener diode T1 is used to prevent malfunction of the downstream transistors. When the thirteenth transistor Q10 is turned on, the right end of the thirty-first resistor R31 is at a low level, and the ninth transistor Q9 is turned off.The collector of the ninth transistor Q9 is connected to the twenty-seventh resistor R27, the twenty-eighth resistor R28, and the fourth diode D4. At this time, the collector side of the ninth transistor Q9 is at a high level, that is, the left side of the twenty-eighth resistor R28 is at a high level, and the eighth transistor Q8 connected to it is turned on.

[0037] like Figure 1As shown, the voltage divided by resistors R21 (21st) and R23 (23rd) is transmitted to the positive input terminal of the fifth operational amplifier U2A. This voltage then flows through resistor R26 (26th), Zener diode T4 (4th), and capacitor C3 (3rd) into the negative input terminal Vin- of the bus. At this point, the positive input voltage of Zener diode T4 is connected to the negative input terminal of the fifth operational amplifier U2A. Resistor R26 (26th) is a current-limiting protection resistor, and capacitor C3 (3rd) filters to ensure that the voltage across Zener diode T4 is relatively stable. The specific parameter Vt3 can be set for the selection of Zener diode T4. The circuit is designed so that when the bus voltage Vt0 < the third preset voltage Vt3, Zener diode T4 stabilizes the voltage of the fifth operational amplifier U2A at the third preset voltage Vt3. At this time, after setting the values ​​of resistors R21 (21st) and R23 (23rd), it is ensured that the positive input voltage of the fifth operational amplifier U2A is greater than the third preset voltage Vt3. However, at this actual moment, the bus voltage Vt0 < the third preset voltage Vt3, and pin 1 of the fifth operational amplifier U2A is not conducting. At this time, the twenty-fifth resistor R25 limits the current and connects to the base of the sixth transistor Q6, causing Q6 to not conduct. The collector of the sixth transistor Q6 is connected to the seventeenth resistor R17, the twentieth resistor R20, and the third diode D3. The seventeenth resistor R17 and the twentieth resistor R20 are used for current limiting protection, and D3 is used for freewheeling protection. The seventeenth resistor R17 is connected to the positive and negative terminals of the system voltage Vin through the first Zener diode T1, the second resistor R2, and the fourth resistor R4. The second resistor R2 and the fourth resistor R4 divide the voltage to connect the bus voltage to the seventeenth resistor R17 to power the sixth transistor Q6. The first Zener diode T1 is to prevent malfunction of the downstream transistors. When the sixth transistor Q6 is not conducting, the left end of the twentieth resistor R20 is at a high level, and the fifth transistor Q5 is conducting. The collector of transistor Q5 is connected to resistor R14, and the emitter of transistor Q5 is connected to the collector of transistor Q8. As analyzed above, transistor Q8 is currently conducting. The emitter of transistor Q8 is connected to resistor R32 and the negative terminal of operational amplifier U1B. At this time, the voltage across R32 is high. Operational amplifier U1B is connected to resistor R22, and then through resistors R16 and R19 to the positive terminal of the system voltage Vin. The circuit design ensures that when transistors Q5 and Q8 are both conducting, the voltage across resistor R32 is lower than the voltage at the positive input terminal of operational amplifier U1B; therefore, operational amplifier U1B is not conducting at this time. The output pin 7 of the first operational amplifier U1B is connected to the third Zener diode T3, the second capacitor C2, and the positive terminal of the second operational amplifier U2B after passing through the twenty-fourth resistor R24. The purpose of this circuit design is to slowly output the control signal.If the first operational amplifier U1B is turned on at this time, and the left side of the twenty-fourth resistor R24 ​​is at a high level, then the duration of the high-level output of the second operational amplifier U2B can be controlled by adjusting the parameters of the twenty-fourth resistor R24 ​​and the second capacitor C2. When the bus voltage is in the third monitoring zone, the first operational amplifier U1B is turned off, so the second operational amplifier U2B also does not output a high level. The output terminal of the second operational amplifier U2B is connected to the base of the seventh transistor Q7, and the collector of the seventh transistor Q7 is connected to the first Zener diode T1 through the eighteenth resistor R18, powered by the system voltage Vin. Since the second operational amplifier U2B is not turned on, the seventh transistor Q7 is also not turned on, and the output terminal Vout2 of the second signal processor outputs a high level.

[0038] In the third monitoring zone, the bus voltage Vt0 < the fourth preset voltage Vt4. The seventh resistor R7 and the tenth resistor R10 divide the voltage and transmit it to the positive input terminal of the sixth operational amplifier U1A. This voltage then flows through the twelfth resistor R12, the second Zener diode T2, and the first capacitor C1 into the negative terminal of the bus. At this time, the voltage at the positive terminal of the second Zener diode T2 is extracted and connected to the negative input segment of the sixth operational amplifier U1A. The twelfth resistor R12 is a current-limiting protection resistor, and the first capacitor C1 filters and ensures the voltage at the positive terminal of the second Zener diode T2. 2. With relatively stable voltages across the terminals, the selection of the second Zener diode T2 can be based on setting the specific parameters of the fourth preset voltage Vt4. The circuit design is such that when the bus voltage Vt0 > the fourth preset voltage Vt4, the second Zener diode T2 stabilizes the negative terminal voltage of the sixth operational amplifier U1A at the fourth preset voltage Vt4. At this time, after setting the values ​​of the thirtieth resistor R30 and the thirty-third resistor R33, it is ensured that the positive terminal voltage of the fourth operational amplifier U3A is greater than the fourth preset voltage Vt4, and the output pin 1 of the sixth operational amplifier U1A outputs a high-level signal. However, in the third monitoring area, the bus voltage Vt0 < the fourth preset voltage Vt4, so the sixth operational amplifier U1A does not operate, and its output pin 1 has no high-level output. The output pin 1 of the sixth operational amplifier U1A is connected to the base of the third transistor Q3 after being current-limited by the eleventh resistor R11. At this time, the third transistor Q3 fails to conduct. The collector of the third transistor Q3 is connected to the sixth resistor R6, the eighth resistor R8, and the second diode D2. Resistors R6 and R8 are used for current limiting protection, while diode D2 is used for freewheeling protection. The sixth resistor R6 is connected to the positive and negative terminals of the system voltage Vin via the first Zener diode T1, the second resistor R2, and the fourth resistor R4. The second and fourth resistors R2 and R4 divide the voltage, connecting the bus voltage to the sixth resistor R6 to power the third transistor Q3. The first Zener diode T1 is used to prevent malfunctions of downstream transistors. When the third transistor Q3 is not conducting, the left end of the eighth resistor R8 is at a high level, and the second transistor Q2 is conducting. The collector of the second transistor Q2 is connected to the third resistor R3, the fifth resistor R5, and the first diode D1. At this time, the collector side of the second transistor Q2 is at a low level, meaning the right side of the fifth resistor R5 is at a low level. Therefore, the first transistor Q1 connected to it is not conducting.

[0039] In the third monitoring zone, if the bus voltage Vt0 > the first preset voltage Vt1, the bus voltage is divided by resistors R37 and R38 and transmitted to the positive input terminal of the sixth operational amplifier U1A. This voltage then flows into the negative terminal of the bus through resistor R40, the sixth Zener diode T6, and capacitor C5. At this time, the voltage at the positive terminal of the sixth Zener diode T6 is extracted and connected to the negative input segment of the third operational amplifier U3B. Resistor R40 is a current-limiting protection resistor, and capacitor C5 acts as a filter to ensure that the voltage across the sixth Zener diode T6 is relatively stable. The selection of the sixth Zener diode T6 can be set by the first preset voltage. The specific parameters of voltage Vt1 are designed such that when the bus voltage Vt0 > the first preset voltage Vt1, the sixth Zener diode T6 stabilizes the voltage at the negative input of the third operational amplifier U3B at the first preset voltage Vt1. At this time, after setting the values ​​of the thirty-seventh resistor R37 and the thirty-eighth resistor R38, it is ensured that the voltage at the positive terminal of the third operational amplifier U3B is greater than the first preset voltage Vt1. The output pin 7 of the third operational amplifier U3B sends a high-level signal. After the current is limited by the thirty-ninth resistor R39, the output pin 7 of the third operational amplifier U3B is connected to the base of the eleventh transistor Q11, at which time the eleventh transistor Q11 is turned on. The collector of the eleventh transistor Q11 is connected to the thirty-sixth resistor R36, the fifteenth resistor R15, and the sixth diode D6. The thirty-sixth resistor R36 is connected to the first Zener diode T1. The system voltage Vin supplies power to the eleventh transistor Q11 through the second resistor R2, the fourth resistor R4, and the first Zener diode T1. The sixth diode D6 is used for freewheeling protection. The fifteenth resistor R15 connects the voltage on the collector side of the eleventh transistor Q11 to the base of the fourth transistor Q4. At this time, since the eleventh transistor Q11 is conducting, its collector is at a low level, therefore the base of the fourth transistor Q4 is also at a low level, and the fourth transistor Q4 fails to conduct. From the above analysis, it can be seen that in the third monitoring area, neither the first transistor Q1 nor the fourth transistor Q4 is conducting. The output Vout1 of the first signal processing circuit is connected to the negative terminal of the bus through the thirteenth resistor R13. At this time, the output Vout1 of the first signal processing circuit is at a low level, and the output Vout2 of the second signal processing circuit is at a high level.

[0040] Explanation of the principle of the second monitoring zone: When the bus voltage Vt0 is in the second monitoring zone, i.e., Vt1 < Vt0 < Vt2 < Vt3 < Vt4, according to the principle analysis of the second monitoring zone, when the first preset voltage Vt1 < the bus voltage Vt0, the third operational amplifier U3B operates in the amplification region, and the output pin 7 of the third operational amplifier U3B outputs a high level, the eleventh transistor Q11 is in the conducting state, therefore the base of the fourth transistor Q4 becomes low level, and the fourth transistor Q4 fails to conduct; when the bus voltage Vt0 < the second preset voltage Vt2, the fourth operational amplifier U3A is cut off, the left end of the thirty-fourth resistor R34 is low level, the thirteenth transistor Q10 fails to conduct, the left side of the thirty-first resistor R31 is high level, the ninth transistor Q9 conducts, the left side of the twenty-eighth resistor R28 is low level, and the eighth... When transistor Q8 is not conducting, the negative input segment of the first operational amplifier U1B is at a low level. When the bus voltage Vt0 < the third preset voltage Vt3, the fifth operational amplifier U2A is cut off, the left end of the twenty-fifth resistor R25 is at a low level, the sixth transistor Q6 fails to conduct, the left side of the twentieth resistor R20 is at a high level, the fifth transistor Q5 conducts, but the eighth transistor Q8 is not conducting, and the negative terminal of the first operational amplifier U1B remains at a low level. At this time, the first operational amplifier U1B is operating in the amplification region, the left side of the twenty-fourth resistor R24 ​​is at a high level, the second capacitor C2 is charging, the voltage at the positive input terminal of the second operational amplifier U2B is greater than the voltage at the negative input segment, the output pin 7 of the second operational amplifier U2B outputs a high level, the seventh transistor Q7 conducts, therefore the output Vout2 of the second signal processing circuit is at a low level. By adjusting the parameters of the twenty-fourth resistor R24 ​​and the second resistor C2, the speed at which the second operational amplifier U2B outputs a high level can be adjusted, thereby adjusting the speed at which the second signal processing circuit outputs a low level Vout2. When the bus voltage Vt0 < the fourth preset voltage Vt4, the sixth operational amplifier U1A is cut off, the terminals of the eleventh resistor R11 are at a low level, the third transistor Q3 fails to conduct, the left side of the eighth resistor R8 is at a high level, the second transistor Q2 conducts, the left side of the fifth resistor R5 is at a low level, the first transistor Q1 does not conduct, and since the fourth transistor Q4 is also not conducting at this time, the output Vout1 of the first signal processing circuit is at a low level. In summary, in the second monitoring area, the output Vout1 of the first signal processing circuit remains at a low level; the output Vout2 of the second signal processing circuit flips, changing from a high level to a low level, slowly emitting a low-level signal.

[0041] Explanation of the fourth monitoring zone principle: When the bus voltage Vt0 is in the fourth monitoring zone, i.e., Vt1 < Vt2 < Vt3 < Vt0 < Vt4, according to the principle analysis of the third monitoring zone, when the first preset voltage Vt1 < the bus voltage Vt0, the third operational amplifier U3B operates in the amplification region, and the output pin 7 of the third operational amplifier U3B outputs a high level, the eleventh transistor Q11 is in the conducting state, therefore the base of the fourth transistor Q4 becomes low level, and the fourth transistor Q4 fails to conduct; when the second preset voltage Vt2 < the bus voltage Vt0, the fourth operational amplifier U3A outputs a high level, the left side of the thirty-fourth resistor R34 is high level, the thirteenth transistor Q10 conducts, the left side of the thirty-first resistor R31 is low level, the first transistor Q9 fails to conduct, and the twenty-eighth resistor... When the left side of resistor R28 is high, transistor Q8 is turned on. When the third preset voltage Vt3 < bus voltage Vt0, the fifth operational amplifier U2A outputs a high level, the left side of resistor R25 is high, transistor Q6 is turned on, and the left side of resistor R20 is low, transistor Q5 is not turned on. At this time, the negative input of the first operational amplifier U1B is still low. The first operational amplifier U1B is now operating in the amplification region. The left side of resistor R24 ​​is high, capacitor C2 is charging, and the voltage at the positive input of the second operational amplifier U2B is greater than the voltage at the negative input. Output pin 7 of the second operational amplifier U2B outputs a high level, transistor Q7 is turned on, and therefore the output Vout2 of the second signal processing circuit is low. By adjusting the parameters of resistor R24 ​​and capacitor C2, the speed at which the second operational amplifier U2B outputs a high level can be adjusted, thereby adjusting the speed at which the second signal processing circuit outputs a low level Vout2. When the bus voltage Vt0 < the fourth preset voltage Vt4, the sixth operational amplifier U1A is cut off, the terminals of the eleventh resistor R11 are at a low level, the third transistor Q3 fails to conduct, the left side of the eighth resistor R8 is at a high level, the second transistor Q2 conducts, the left side of the fifth resistor R5 is at a low level, the first transistor Q1 does not conduct, and since the fourth transistor Q4 is also not conducting at this time, the output Vout1 of the first signal processing circuit is at a low level. In summary, when the bus voltage Vt0 is in the fourth monitoring zone, the output Vout1 of the first signal processing circuit remains at a low level; the output Vout2 of the second signal processing circuit flips from high to low and slowly emits a low-level signal.

[0042] Explanation of the first monitoring zone principle: When the bus voltage Vt0 is in the first monitoring zone, i.e., Vt0 < Vt1 < Vt2 < Vt3 < Vt4, according to the principle analysis of the third monitoring zone, when the first preset voltage Vt1 < the bus voltage Vt0, the third operational amplifier U3B operates in the cutoff region, there is no high level on the left side of the thirty-ninth resistor R39, the eleventh transistor Q11 fails to conduct, therefore the base of the fourth transistor Q4 is at a high level, the fourth transistor Q4 conducts, and therefore the first signal processing circuit outputs Vout1 at a high level; when the bus voltage Vt0 < the second preset voltage Vt2, the fourth operational amplifier U3A is cut off, the three-fourth resistor R34 is at a low level, the thirteenth transistor Q10 fails to conduct, the left side of the thirty-first resistor R31 is at a high level, the ninth transistor Q9 conducts, and the left side of the twenty-eighth resistor R28... When the voltage is low, transistor Q8 is not conducting, and the negative terminal of the first operational amplifier U1B is low. When the bus voltage Vt0 < the third preset voltage Vt3, the fifth operational amplifier U2A is cut off, the twenty-fifth resistor R25 is low, transistor Q6 fails to conduct, the left side of the twentieth resistor R20 is high, transistor Q5 conducts, but transistor Q8 is not conducting, and the negative terminal of the first operational amplifier U1B remains low. At this time, the first operational amplifier U1B operates in the amplification region, the left side of the twenty-fourth resistor R24 ​​is high, the second capacitor C2 charges, the voltage at the positive input terminal of the second operational amplifier U2B is greater than the voltage at the negative input terminal, the output pin 7 of the second operational amplifier U2B outputs a high level, transistor Q7 conducts, therefore the output Vout2 of the second signal processing circuit is low. By adjusting the parameters of the twenty-fourth resistor R24 ​​and the second capacitor C2, the speed at which the second operational amplifier U2B outputs a high level can be adjusted, thereby adjusting the speed at which the output Vout2 of the second signal processing circuit outputs a low level. When the bus voltage Vt0 < the fourth preset voltage Vt4, the first operational amplifier U1A is cut off, the terminals of the eleventh resistor R11 are at a low level, the third transistor Q3 fails to conduct, the left side of the eighth resistor R8 is at a high level, the second transistor Q2 conducts, the left side of the fifth resistor R5 is at a low level, the first transistor Q1 fails to conduct, but at this time the fourth transistor Q4 conducts, therefore the output terminal Vout1 of the first signal processing circuit outputs a high level. In summary, when the bus voltage Vt0 is in the first monitoring zone, the output terminal Vout of the first signal processing circuit immediately outputs a high level, while the output terminal Vout2 of the second signal processing circuit remains at a low level.

[0043] Explanation of the principle of the fifth monitoring zone: When the bus voltage Vt0 is in the fifth monitoring zone, i.e., Vt1 < Vt2 < Vt3 < Vt4 < Vt0, according to the principle analysis of the third monitoring zone, when the first preset voltage Vt1 < the bus voltage Vt0, the third operational amplifier U3B operates in the amplification region, and the output pin 7 of the third operational amplifier U3B outputs a high level, the eleventh transistor Q11 is in the conducting state, therefore the base of the fourth transistor Q4 becomes low level, and the fourth transistor Q4 fails to conduct; when the second preset voltage Vt2 < the bus voltage Vt0, the fourth operational amplifier U3A outputs a high level, the left side of the thirty-fourth resistor R34 is high level, the thirteenth transistor Q10 conducts, the left side of the thirty-first resistor R31 is low level, the ninth transistor Q9 fails to conduct, and the twenty-eighth resistor... When the left side of resistor R28 is at a high level, transistor Q8 is turned on. When the third preset voltage Vt3 < bus voltage Vt0, the fifth operational amplifier U2A outputs a high level, the left side of the twenty-fifth resistor R25 is at a high level, transistor Q6 is turned on, and the left side of the twentieth resistor R20 is at a low level, transistor Q5 fails to turn on. At this time, the negative terminal of the first operational amplifier U1B is still at a low level. The first operational amplifier U1B is now operating in the amplification region. The left side of the twenty-fourth resistor R24 ​​is at a high level, capacitor C2 is charging, and the voltage at the positive input terminal of the second operational amplifier U2B is greater than the voltage at the negative input terminal. Output pin 7 of the second operational amplifier U2B outputs a high level, transistor Q7 is turned on, and therefore the output Vout2 of the second signal processing circuit is low. By adjusting the parameters of the twenty-fourth resistor R24 ​​and the second capacitor C2, the speed at which the second operational amplifier U2B outputs a high level can be adjusted, thereby adjusting the speed at which the output Vout2 of the second signal processing circuit outputs a low level. When the fourth preset voltage Vt4 < the bus voltage Vt0, the sixth operational amplifier U1A outputs a high level, the left side of the eleventh resistor R11 is at a high level, the third transistor Q3 is turned on, the left side of the eighth resistor R8 is at a low level, the second transistor Q2 fails to turn on, the left side of the fifth resistor R5 is at a high level, the first transistor Q1 is turned on, and at this time, the output terminal Vout1 of the first signal processing circuit outputs a high level. In summary, when the bus voltage Vt0 is in the fifth monitoring zone, the output terminal Vout1 of the first signal processing circuit immediately outputs a high level, and the output terminal Vout2 of the second signal processing circuit remains at a low level.

[0044] This invention provides a power quality monitoring circuit for control equipment. This circuit can identify the severity of voltage fluctuations in the power supply system and issue different types of signals to the equipment and operators based on the degree of fluctuation. According to the different types of signals, the equipment can immediately power down to protect the hardware, or perform software and data backup and storage operations, and alert external equipment operators, thereby protecting software and data security. Furthermore, control equipment using this monitoring circuit can better protect the integrity of equipment hardware and data in the face of various power anomalies caused by inherent power quality issues, deterioration of electronic component performance, or external electromagnetic interference. This is particularly significant for industries with high safety requirements, such as railways, as it can reduce the damage and impact of power quality changes on equipment, thereby extending equipment lifespan. In industries with high safety requirements, such as railways and civil aviation, even a single equipment malfunction leading to passenger removal can result in significant property and personnel losses. Moreover, safer and more reliable equipment operation also contributes to reduced costs throughout its entire life cycle.

[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A power quality monitoring circuit for a control device, characterized in that, The system includes a voltage detection circuit that monitors the fluctuation value of the bus voltage in the control system of the device to be monitored, and outputs a corresponding control signal based on the fluctuation value of the bus voltage, which is then sent to the control system so that the control system can control the operation of the device based on the control signal. The voltage detection circuit includes a voltage determination circuit, a first signal processing circuit, and a second signal processing circuit; the voltage determination circuit is used to determine the control signals of the first signal processing circuit and the second signal processing circuit based on the fluctuation value of the bus voltage, and the control signals include high-level signals and low-level signals; The voltage determination circuit includes a first determination circuit, a second determination circuit, a third determination circuit, and a fourth determination circuit. The first signal processing circuit is electrically connected to the first determination circuit and the fourth determination circuit, and the second signal processing circuit is electrically connected to the second determination circuit and the third determination circuit. The second signal processing circuit includes a first operational amplifier U1B, a second operational amplifier U2B, a fifth transistor Q5, a seventh transistor Q7, an eighth transistor Q8, a third Zener diode T3, and a second capacitor C2. The positive input terminal of the first operational amplifier U1B is connected to one end of the twenty-second resistor R22. The negative input terminal of the first operational amplifier U1B, the emitter of the eighth transistor Q8, and one end of the thirty-second resistor R32 are connected. The collector of the eighth transistor Q8 is connected to the emitter of the fifth transistor Q5. The output terminal of the first operational amplifier U1B is connected to one end of the twenty-fourth resistor R24. The other end of the twenty-fourth resistor R24, one end of the third Zener diode T3, one end of the second capacitor C2, and the positive input terminal of the second operational amplifier U2B are connected. One end of the third Zener diode T3, one end of the second capacitor C2, and the other end of the thirty-second resistor R32 are connected. The negative input terminal of the second operational amplifier U2B is connected to one end of the forty-first resistor R41 and one end of the forty-second resistor R42. The other end of the forty-first resistor R41 is connected to the bus, and the other end of the forty-second resistor R42 is grounded. The output terminal of the second operational amplifier U2B is connected to one end of the forty-fifth resistor R45. The other end of the forty-fifth resistor R45 is connected to the base of the seventh transistor Q7. The collector of the seventh transistor Q7 is connected to the eighteenth resistor R18, and the emitter of the seventh transistor Q7 is grounded.

2. The power quality monitoring circuit for a control device according to claim 1, characterized in that, The first signal processing circuit includes a first resistor R1, a fifth resistor R5, a ninth resistor R9, a thirteenth resistor R13, a fifteenth resistor R15, a first transistor Q1, and a fourth transistor Q4. The base of the first transistor Q1 is connected to one end of the fifth resistor R5, the emitter of the first transistor Q1 is connected to one end of the first resistor R1, the base of the fourth transistor Q4 is connected to one end of the fifteenth resistor R15, the collector of the fourth transistor Q4 is connected to one end of the ninth resistor R9, the other end of the ninth resistor R9 is connected to the other end of the first resistor R1, and the emitters of the first transistor Q1, the fourth transistor Q4, and one end of the thirteenth resistor R13 are connected together.

3. The power quality monitoring circuit for a control device according to claim 1, characterized in that, The first determination circuit includes a fifth capacitor C5, a sixth Zener diode T6, a third operational amplifier U3B, a thirty-sixth resistor R36, a thirty-seventh resistor R37, a thirty-eighth resistor R38, a thirty-ninth resistor R39, a fortieth resistor R40, an eleventh transistor Q11, and a sixth diode D6. One end of the fifth capacitor C5 and one end of the sixth Zener diode T6 are grounded, and the other ends of the fifth capacitor C5, the sixth Zener diode T6, and one end of the fortieth resistor R40 are all connected to the negative input terminal of the third operational amplifier U3B. One end of the thirty-seventh resistor R37 is connected to the busbar, one end of the thirty-eighth resistor R38 is grounded, and the other end of the thirty-seventh resistor R37... The other end of the 38th resistor R38 and the other end of the 40th resistor R40 are all connected to the positive input terminal of the third operational amplifier U3B; the output terminal of the third operational amplifier U3B is connected to one end of the 39th resistor R39, the other end of the 39th resistor R39 is connected to the base of the 11th transistor Q11, the collector of the 11th transistor Q11, the cathode of the 6th diode D6, one end of the 36th resistor R36 and the other end of the 15th resistor R15 are connected, the other end of the 36th resistor R36 is connected to the other end of the 18th resistor R18, and the emitter of the 11th transistor Q11 is connected to the anode of the 6th diode D6 and grounded.

4. The power quality monitoring circuit for a control device according to claim 1, characterized in that, The second determination circuit includes a fourth capacitor C4, a fifth Zener diode T5, a fourth operational amplifier U3A, a twenty-seventh resistor R27, a twenty-eighth resistor R28, a twenty-ninth resistor R29, a thirtieth resistor R30, a thirty-third resistor R33, a thirty-fourth resistor R34, a thirty-fifth resistor R35, a ninth transistor Q9, a thirteenth transistor Q10, a fourth diode D4, and a fifth diode D5; one end of the fourth capacitor C4 and one end of the fifth Zener diode T5 are grounded, and the other ends of the fourth capacitor C4, the fifth Zener diode T5, and one end of the thirty-fifth resistor R35 are all connected to the negative input terminal of the fourth operational amplifier U3A; one end of the thirtieth resistor R30 is connected to the bus, one end of the thirty-third resistor R33 is grounded, and the other ends of the thirtieth resistor R30, the thirty-third resistor R33, and the thirty-fifth resistor R35 are all connected to the positive input terminal of the third operational amplifier U3B; the third operational amplifier U3A... Output pin 1 of 3B is connected to one end of the 34th resistor R34. The other end of the 34th resistor R34 is connected to the base of the 13th transistor Q10. The collector of the 13th transistor Q10, the cathode of the 5th diode D5, one end of the 31st resistor R31, and one end of the 29th resistor R29 are connected. The other end of the 31st resistor R31 is connected to the base of the 9th transistor Q9. The collector of the 9th transistor Q9, one end of the 4th diode D4, one end of the 28th resistor R28, and one end of the 27th resistor R27 are connected. The other end of the 28th resistor R28 is connected to the base of the 8th transistor Q8. The emitter of the 13th transistor Q10, the anode of the 5th diode D5, the emitter of the 9th transistor Q9, the anode of the 4th diode D4, and the other end of the 32nd resistor are grounded. The other end of the 29th resistor R29 and the other end of the 27th resistor R27 are connected to the other end of the 18th resistor R18.

5. The power quality monitoring circuit for a control device according to claim 1, characterized in that, The third determination circuit includes a third capacitor C3, a fourth Zener diode T4, a fifth operational amplifier U2A, a fourteenth resistor R14, a seventeenth resistor R17, a twentieth resistor R20, a twenty-first resistor R21, a twenty-third resistor R23, a twenty-fifth resistor R25, a twenty-sixth resistor R26, a sixth transistor Q6, and a third diode D3. One end of the third capacitor C3 and one end of the fourth Zener diode T4 are grounded, and the other ends of the third capacitor C3, the fourth Zener diode T4, and one end of the twenty-sixth resistor R26 are all connected to the negative input terminal of the fifth operational amplifier U2A. One end of the twenty-first resistor R21 is connected to the busbar, one end of the twenty-third resistor R23 is grounded, and the other ends of the twenty-first resistor R21, the twenty-third resistor R23, and the twenty-sixth resistor R26 are all connected to the fifth operational amplifier U2A. The positive input terminal of operational amplifier U2A; the output pin 1 of the fifth operational amplifier U2A is connected to one end of the twenty-fifth resistor R25. The other end of the twenty-fifth resistor R25 is connected to the base of the sixth transistor Q6. The collector of the sixth transistor Q6, the cathode of the third diode D3, one end of the seventeenth resistor R17, and one end of the twentieth resistor R20 are connected. The other end of the twentieth resistor R20 is connected to the base of the fifth transistor Q5. The other end of the seventeenth resistor R17 and one end of the fourteenth resistor R14 are connected to the other end of the eighteenth resistor R18. The other end of the fourteenth resistor R14 is connected to the collector of the fifth transistor Q5. The other end of the thirty-sixth resistor R36 is connected to the other end of the eighteenth resistor R18. The emitter of the sixth transistor Q6 is connected to the anode of the third diode D3 and grounded.

6. The power quality monitoring circuit for a control device according to claim 1, characterized in that, The fourth determination circuit includes a first capacitor C1, a second Zener diode T2, a sixth operational amplifier U1A, a third resistor R3, a sixth resistor R6, an eighth resistor R8, a seventh resistor R7, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a forty-third resistor R43, a forty-fourth resistor R44, a second transistor Q2, a third transistor Q3, a first diode D1, and a second diode D2; one end of the first capacitor C1 and one end of the second Zener diode T2 are grounded, and the other end of the first capacitor C1, the other end of the second Zener diode T2, and the tenth... One end of each of the two resistors R12 is connected to the negative input terminal of the sixth operational amplifier U1A; one end of the seventh resistor R7 is connected to the bus, one end of the tenth resistor R10 is grounded, and the other ends of the seventh resistor R7, the tenth resistor R10, and the twelfth resistor R12 are all connected to the positive input terminal of the sixth operational amplifier U1A; the output pin 1 of the sixth operational amplifier U1A is connected to one end of the eleventh resistor R11, and the other end of the eleventh resistor R11 is connected to the base of the third transistor Q3. The collector of the third transistor Q3, the... The cathode of diode D2, one end of the sixth resistor R6, and one end of the eighth resistor R8 are connected together. The other end of the eighth resistor R8 is connected to the base of the second transistor Q2. The collector of the second transistor Q2, one end of the first diode D1, one end of the third resistor R3, and one end of the fifth resistor R5 are connected together. The other ends of the third resistor R3, the first resistor R1, and the sixth resistor R6 are connected to the other end of the eighteenth resistor R18. The other ends of the twenty-ninth resistor R29 and the twenty-seventh resistor R27 are connected to the eighteenth resistor R18. The other end of resistor R18; the emitter of the third transistor Q3, the anode of the second diode D2, the emitter of the second transistor Q2, the anode of the first diode D1, and the other end of the thirteenth resistor R13 are grounded; the output pin 4 of the sixth operational amplifier U1A is connected to one end of the forty-third resistor R43, one end of the forty-fourth resistor R44, the output pin 4 of the fifth operational amplifier U2A, and the output pin 4 of the fourth operational amplifier U3A; the other end of the forty-third resistor R43 is connected to the busbar, and the other end of the forty-fourth resistor R44 is grounded.

7. The power quality monitoring circuit for a control device according to claim 1, characterized in that, The other end of the 22nd resistor R22 is connected to one end of the 16th resistor R16 and one end of the 19th resistor R19. The other end of the 16th resistor R16 is connected to the busbar, and the other end of the 19th resistor R19 is grounded.

8. The power quality monitoring circuit for a control device according to claim 1, characterized in that, The other end of the eighteenth resistor R18 is connected to one end of the first Zener diode T1, the other end of the first Zener diode T1 is connected to one end of the second resistor R2 and one end of the fourth resistor R4, the other end of the second resistor R2 is connected to the busbar, and the other end of the fourth resistor R4 is grounded.

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