A single-capacitor three-phase three-level inverter topology

Abstract

This invention proposes a single-capacitor three-phase three-level inverter topology and its capacitor voltage balance modulation strategy. The topology includes twelve switching transistors and one flying capacitor, with three phases symmetrical and each phase consisting of four switching transistors. All three phases share one flying capacitor. When the power supply voltage is V... dc At that time, the capacitor voltage was stabilized at 0.5V through a modulation strategy. dc At this point, each phase can generate 0.5V. dc V dc Three voltage levels are proposed. A corresponding space vector modulation strategy is developed for this topology to control the switching on and off of the switching transistors. Compared with traditional three-phase three-level flying capacitor inverters, this invention eliminates two capacitors, reducing the size of the device, increasing power density, and saving hardware costs. Simultaneously, the reduction in capacitors means that balancing the voltage of one capacitor is now sufficient, reducing the complexity of the inverter system and improving stability.

Description

Technical Field

[0001] This invention belongs to the field of power electronic converter technology, and specifically relates to a single-capacitor three-phase three-level flying capacitor inverter topology and its corresponding capacitor voltage balance modulation strategy, which can be mainly applied to photovoltaic power generation and energy storage. Technical Background

[0002] Traditional three-phase three-level flying capacitor inverters suffer from high hardware costs, numerous balancing capacitors, and low system reliability due to their large number of flying capacitors. Therefore, despite their advantage of easily expandable voltage levels, the actual commercialization of research results is limited, and there is room for improvement in their topology.

[0003] This invention eliminates two capacitors and adjusts the position of the switching transistors in the traditional three-phase three-level flying capacitor inverter topology, proposing a single-capacitor three-phase three-level inverter topology. At the same time, it proposes a matching modulation strategy to balance the capacitor voltage, solving the pain points of high hardware cost, low power density, and low system reliability, and making it easier to meet practical needs. Summary of the Invention

[0004] The purpose of this invention is to solve the problems of large product size, high cost, and low reliability caused by excessive flying capacitors in traditional three-phase three-level flying capacitor inverters. This invention proposes a single-capacitor three-phase three-level inverter and its capacitor voltage balance modulation strategy. To achieve the above objective, the technical solution of this invention is as follows:

[0005] In this topology, the A, B, and C phases are identical and share a common flying capacitor C. The entire circuit is powered by a DC voltage source V. dc Flying capacitor C, twelve switching transistors (using N-channel MOSFETs as an example) S a1 ~S a4 S b1 ~S b4 S c1 ~S c4 Composition. Voltage source V dc The positive electrode and S a1 S b1 S c1 The drains are connected; V dc negative electrode and S a3 S b3 S c3 The source and cathode of capacitor C are connected; S a2 Following S a1 With S a3 Between, S a2 The drain and S a1 The source and S are connected. a2 The source pole and Sa4 The drains are connected; S b2 Following S b1 With S b3 Between, S b2 The drain and S b1 The source and S are connected. b2 The source pole and S b4 The drains are connected; S c2 Following S c1 With S c3 Between, S c2 The drain and S c1 The source and S are connected. c2 The source pole and S c4 The drains are connected; S a4 The source of S is connected to the anode of capacitor C. a4 The drain is connected to S a1 The source pole and S a2 Between the drain and the S electrode; b4 The source of S is connected to the anode of capacitor C. b4 The drain is connected to S b1 The source pole and S b2 Between the drain and the S electrode; c4 The source of S is connected to the anode of capacitor C. c4 The drain is connected to S c1 The source pole and S c2 Between the drains; A-phase output from S a2 With S a3 The output of phase B is drawn from phase S. b2 With S b3 The C-phase output is drawn from the S-phase. c2 With S c3 Intermittently derived. Phases A, B, and C can all generate V. dc 0.5V dc Three voltage levels (0, 1, 0, and 1) are used (with the cathode of capacitor C as the 0 voltage reference point). Taking phase A as an example, the generation principle of a single-phase three-level voltage is analyzed: when the DC voltage source is V... dc This keeps the voltage across the flying capacitor C at 0.5V. dc When the switching transistor S a1 and S a2 Shutdown, S a3 and S a4 When the circuit is turned on, the output voltage of phase A is 0; when the switching transistor S... a1 and S a3 Shutdown, S a2 and S a4 When the circuit is turned on, the output voltage of phase A is 0.5V. dc When the switching transistor S a3 and S a4 Shutdown, S a1 and Sa2 When the circuit is turned on, the voltage output of phase A is V. dc Phase A outputs 0 and V. dc At this time, the voltage value of capacitor C is unaffected, when phase A outputs 0.5V. dc When capacitor C discharges, its voltage drops, disrupting the capacitor's balance. The next challenge is to restore the voltage across capacitor C to a balanced 0.5V. dc The main change is to modify the modulation strategy.

[0006] First, let's use N, O, and P to represent single-phase generation of 0 and 0.5V respectively. dc V dc Based on permutations and combinations, this topology can generate 27 different switching states, corresponding to 27 voltage space vectors. These are classified according to their length: vectors with a length of 0 are defined as zero vectors; vectors with a length of 1 / 3V are defined as zero vectors. dc , defined as a small vector; length is V dc The vector is defined as the median vector; its length is 2 / 3V. dc The term "long vector" is defined as follows: There are three types of zero vectors: PPP, OOO, and NNN; twelve types of small vectors: PPO, OON, POO, ONN, POP, ONO, OOP, NNO, OPP, NOO, OPO, and NON; six types of medium vectors: PON, PNO, ONP, NOP, NPO, and OPN; and six types of long vectors: PPN, PNN, PNP, NNP, NPP, and NPN. The modulation strategy is the same as that of a traditional three-phase three-level inverter, with the main difference being the capacitor voltage balancing method. This invention utilizes the principle that the difference in direction between the load current and the capacitor current can have different effects on the capacitor voltage to achieve capacitor balance. When the two directions are the same, the capacitor voltage decreases; when the two directions are opposite, the capacitor voltage increases. Based on this principle, a capacitor reference voltage V is set. c 0.5V dc When the capacitor sampling voltage is lower than V c At this time, by appropriately selecting the voltage vector so that the direction of the load current is opposite to the direction of the capacitor current, the capacitor voltage can be increased and then restored to V. c Similarly, when the capacitor sampling voltage is higher than V c When the load current direction is the same as the capacitor current direction, the capacitor voltage can be reduced to V. c This achieves dynamic voltage balance in the capacitor. Specifically:

[0007] Based on 27 voltage space vectors, a space vector diagram is obtained, such as... Figure 6As shown, the system is divided into six large sectors, each further divided into four smaller regions. Taking the synthesized reference vector located in the first large sector as an example, based on the nearest three-vector method, a five-segment symmetrical waveform is employed. The capacitor balance principle is described below. Taking the reference vector located in the first smaller region of the first large sector as an example, the vector action sequence PPO-POO-OOO-POO-PPO causes the load current and capacitor current to move in opposite directions, resulting in an increase in capacitor voltage. The vector action sequence OON-OOO-ONN-OOO-OON causes the load current and capacitor current to move in the same direction, resulting in a decrease in capacitor voltage. The voltage synthesized from the two sets of vectors is the same. Within each switching cycle, the capacitor sampling voltage is compared with the capacitor reference voltage V. c The magnitude of the reference vector is used to select the appropriate vector action sequence to balance the capacitor voltage. The principle of capacitor voltage balancing remains the same when the reference vector is located in other regions. The calculation of the duty cycle of each vector is the same as the modulation strategy of the traditional topology, and will not be repeated here.

[0008] Compared with traditional three-phase three-level flying capacitor inverters, this invention has the following advantages: it has two fewer switching transistors in its topology, resulting in higher power density, lower hardware cost, fewer capacitors required for voltage balancing, and higher stability. Attached Figure Description

[0009] Figure 1 Traditional three-phase three-level flying capacitor inverter topology;

[0010] Figure 2 A single-capacitor three-phase three-level inverter topology;

[0011] Figure 3 Schematic diagram of a single-capacitor three-phase three-level inverter with a single-phase output of 0;

[0012] Figure 4 A single-capacitor three-phase three-level inverter has a single-phase output of 0.5V. dc Schematic diagram;

[0013] Figure 5 A single-capacitor three-phase three-level inverter has a single-phase output of V. dc Schematic diagram;

[0014] Figure 6 Space vector distribution diagram of a single-capacitor three-phase three-level inverter; Detailed Implementation

[0015] This section, in conjunction with the accompanying drawings, describes the implementation of a simplified three-phase flying capacitor type three-level inverter.

[0016] This invention proposes a single-capacitor three-phase three-level inverter topology, such as... Figure 2As shown, compared with the traditional three-phase three-level flying capacitor inverter ( Figure 1 Compared to the previous version, the advantages are mainly reflected in reducing the number of flying capacitors, shrinking the inverter size, lowering hardware costs, and improving equipment stability. The detailed structure of the proposed topology includes: DC voltage source V... dc Flying capacitor C, twelve switching transistors (using N-channel MOSFETs as an example) S a1 ~S a4 S b1 ~S b4 S c1 ~S c4 Voltage source V dc The positive electrode and S a1 S b1 S c1 The drains are connected; V dc negative electrode and S a3 S b3 S c3 The source and cathode of capacitor C are connected; S a2 Following S a1 With S a3 Between, S a2 The drain and S a1 The source and S are connected. a2 The source pole and S a4 The drains are connected; S b2 Following S b1 With S b3 Between, S b2 The drain and S b1 The source and S are connected. b2 The source pole and S b4 The drains are connected; S c2 Following S c1 With S c3 Between, S c2 The drain and S c1 The source and S are connected. c2 The source pole and S c4 The drains are connected; S a4 The source of S is connected to the anode of capacitor C. a4 The drain is connected to S a1 The source pole and S a2 Between the drain and the S electrode; b4 The source of S is connected to the anode of capacitor C. b4 The drain is connected to S b1 The source pole and S b2 Between the drain and the S electrode; c4 The source of S is connected to the anode of capacitor C. c4 The drain is connected to S c1 The source pole and S c2Between the drains; A-phase output from S a2 With S a3 The output of phase B is drawn from phase S. b2 With S b3 The C-phase output is drawn from the S-phase. c2 With S c3 This is introduced in the middle.

[0017] Based on the above topology, each phase circuit can generate 0V and 0.5V. dc V dc Three voltage levels (with the cathode of capacitor C as the 0 voltage reference point). Taking phase A as an example, the generation principle of a single-phase three-level voltage is analyzed: when the DC voltage source is V... dc The voltage across the flying capacitor C remains at 0.5V. dc When the switching transistor S a1 and S a2 Shutdown, S a3 and S a4 When the circuit is turned on, the output voltage of phase A is 0. The current path at this time is as follows: Figure 3 As shown; when the switching transistor S a1 and S a3 Shutdown, S a2 and S a4 When the circuit is turned on, the output voltage of phase A is 0.5V. dc The current path at this time is as follows Figure 4 As shown; when the switching transistor S a3 and S a4 Shutdown, S a1 and S a2 When the circuit is turned on, the output voltage of phase A is V. dc The current path at this time is as follows Figure 5 As shown, of course, this is only true if the voltage across capacitor C remains at 0.5V. dc Only under certain conditions can the above theories be satisfied.

[0018] The next step is to maintain the capacitor at 0.5V. dc Balance, as analysis shows, occurs when the single-phase output is 0 or V. dc At this time, the capacitor voltage will not be affected when the single-phase output is 0.5V. dc When the capacitor discharges, its voltage drops, therefore, when dealing with voltages around 0.5V... dc During output, a modulation strategy is used to balance the capacitor. This invention utilizes the principle that the difference in direction between the load current and the capacitor current will have different effects on the capacitor voltage to achieve capacitor balance. First, the capacitor voltage is sampled and compared with the capacitor reference voltage V. c =0.5V dc A comparison is made when the actual capacitor voltage is less than the reference voltage V. cWhen the load current direction is opposite to the capacitor current direction, the capacitor voltage increases. When the actual capacitor voltage is greater than the reference voltage V... c By directing the load current in the opposite direction to the capacitor current, the capacitor voltage decreases. This process is repeated once per switching cycle to select the vector action sequence, ensuring that the voltage across capacitor C remains constant at V throughout a single switching cycle. c Nearby, dynamic equilibrium of the capacitor is achieved. Therefore, the next step is to select the sequence of vector actions that raise or lower the capacitor voltage, and require that they result in the same voltage, so that they can be selected when determining the capacitor voltage.

[0019] First, let's use N, O, and P to represent single-phase generation of 0 and 0.5V respectively. dc V dc Based on permutations and combinations, this topology can generate 27 different switching states, corresponding to 27 voltage space vectors. These are classified according to their length: vectors with a length of 0 are defined as zero vectors; vectors with a length of 1 / 3V are defined as zero vectors. dc , defined as a small vector; length is V dc The vector is defined as the median vector; its length is 2 / 3V. dc The vector is defined as a long vector. There are three types of zero vectors: PPP, OOO, and NNN; twelve types of small vectors: PPO, OON, POO, ONN, POP, ONO, OOP, NNO, OPP, NOO, OPO, and NON; six types of medium vectors: PON, PNO, ONP, NOP, NPO, and OPN; and six types of long vectors: PPN, PNN, PNP, NNP, NPP, and NPN. Based on this spatial vector, a control vector diagram is drawn, such as... Figure 6 As shown, the system is divided into six large sectors, each of which is further divided into four smaller regions. Based on the spatial vector diagram, by appropriately selecting redundant vectors, the direction of the load current can be actively controlled to adjust the capacitor voltage change trend when the synthesized voltage is the same. Taking the reference vector of the first smaller region of the first large sector as an example, and assuming the reference vector is located in the first smaller region of the first large sector: the vector action sequence PPO-POO-OOO-POO-PPO causes the load current to flow from the anode of capacitor C, increasing the capacitor voltage; the vector action sequence OON-OOO-ONN-OOO-OON causes the load current to flow from the cathode of capacitor C, decreasing the capacitor voltage. The reference voltage effects of these two sets of vector synthesis are equivalent. The vector action sequences for other sectors and regions are shown in Table 1. Other specific modulation strategies are the same as the traditional three-level inverter SVPWM modulation strategy and will not be elaborated here.

[0020]

[0021] Table 1. Order of Vector Actions

[0022] Depending on the application, power-matching switching transistors and other electronic devices must be selected. Switching transistor types include, but are not limited to, insulated-gate bipolar transistors (IGBTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs).

Claims

1. A single-capacitor three-phase three-level inverter, characterized in that, The inverter is powered by a DC voltage source V. dc Flying capacitor C and twelve switching transistors S a1 ~S a4 S b1 ~S b4 S c1 ~S c4 Composition; the DC voltage source V dc The positive electrode and S a1 S b1 S c1 The drain of the DC voltage source V is connected to the DC voltage source V. dc negative electrode and S a3 S b3 S c3 The source of S is connected to the cathode of the flying capacitor C; a2 Following S a1 With S a3 Between, S a2 The drain and S a1 The source and S are connected. a2 The source pole and S a3 The drains are connected; S b2 Following S b1 With S b3 Between, S b2 The drain and S b1 The source and S are connected. b2 The source pole and S b3 The drains are connected; S c2 Following S c1 With S c3 Between, S c2 The drain and S c1 The source and S are connected. c2 The source pole and S c3 The drains are connected; S a4 The source of S is connected to the anode of the flying capacitor C. a4 The drain is connected to S a1 The source pole and S a2 Between the drain and the S electrode; b4 The source of S is connected to the anode of the flying capacitor C. b4 The drain is connected to S b1 The source pole and S b2 Between the drain and the S electrode; c4 The source of S is connected to the anode of the flying capacitor C. c4 The drain is connected to S c1 The source pole and S c2 Between the drains; A-phase output from S a2 With S a3 The output of phase B is drawn from phase S. b2 With S b3 The C-phase output is drawn from the S-phase. c2 With S c3 This is introduced in the middle.

2. The single-capacitor three-phase three-level inverter according to claim 1, characterized in that, The input power supply voltage of the inverter is V. dc At this time, the voltage across the flying capacitor C remains at 0.5V. dc Single-phase output 0, 0.5V dc V dc Three levels.

3. The single-capacitor three-phase three-level inverter according to claim 1, characterized in that, The switching transistor is an insulated gate bipolar transistor (IGBT) or a metal-oxide-semiconductor field-effect transistor (MOSFET); the DC voltage source Vdc is a rectified DC voltage, or a DC voltage provided by a battery or photovoltaic cell.

4. The single-capacitor three-phase three-level inverter according to claim 1, characterized in that, The inverter is used for grid connection of photovoltaic new energy power generation, or for loads with delta or star connections, wherein the load is a purely resistive, purely inductive, purely capacitive, resistive-inductive, or resistive-capacitive load.

5. The single-capacitor three-phase three-level inverter according to claim 1, characterized in that, The inverter structure is adapted for rectification applications, and three-phase AC power is connected from the output terminal of the inverter to convert AC power into DC power.

Images