Display substrate and display device

Abstract

A display substrate includes a substrate, a plurality of first pixel circuits, and at least one first data line. The substrate includes a display area and a peripheral area at least partially surrounding the display area, the display area including a light-transmissive display region. The plurality of first pixel circuits are located in the light-transmissive display region. The at least one first data line extends in a first direction and partially in the light-transmissive display region. The first data line is configured to provide data signals to the plurality of first pixel circuits from opposite sides of the light-transmissive display region in the first direction.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, cameras are often installed on display devices to meet shooting needs. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate and a display device.

[0005] In one aspect, embodiments of this disclosure provide a display substrate, including: a substrate, a plurality of first pixel circuits, and at least one first data line. The substrate includes a display area and a peripheral area at least partially surrounding the display area, the display area including a light-transmitting display area. The plurality of first pixel circuits are located in the light-transmitting display area. The at least one first data line extends along a first direction and is partially located in the light-transmitting display area. The first data line is configured to provide data signals to the plurality of first pixel circuits from opposite sides of the light-transmitting display area in the first direction.

[0006] In some exemplary embodiments, the first data line includes a first sub-data line and a second sub-data line. The first sub-data line is located in the light-transmitting display area and extends along the first direction, and its two ends along the first direction are electrically connected to the second sub-data line. The first sub-data line is made of a transparent conductive material and is electrically connected to a plurality of first pixel circuits arranged along the first direction within the light-transmitting display area. The second sub-data line is made of a metallic material.

[0007] In some exemplary embodiments, the second sub-data line includes a first trace, a second trace, and a third trace; the second trace is electrically connected between the first trace and the third trace. The first trace and the third trace are located on opposite sides of the first sub-data line along a first direction; the second trace is located on one side of the first sub-data line in a second direction. The first direction intersects the second direction.

[0008] In some exemplary embodiments, the first sub-data line has a first end and a second end along the first direction, the first end of the first sub-data line is electrically connected to the first trace, and the second end of the first sub-data line is electrically connected to the third trace.

[0009] In some exemplary embodiments, the first trace and the third trace are in the same layer, the second trace and the first trace are in different layers, and the first sub-data line is located on the side of the first trace away from the substrate.

[0010] In some exemplary embodiments, the second trace is located on the side of the first trace away from the substrate and on the side of the first sub-data line close to the substrate.

[0011] In some exemplary embodiments, a first organic insulating layer is disposed on the side of the second trace close to the substrate, and a second organic insulating layer is disposed on the side of the second trace away from the substrate.

[0012] In some exemplary embodiments, the first sub-data line extends to an area outside the light-transmitting display area and is electrically connected to the first and third traces of the second sub-data line in the area outside the light-transmitting display area.

[0013] In some exemplary embodiments, the first and third traces of the second sub-data line extend to the light-transmitting display area and are electrically connected to the first sub-data line in the light-transmitting display area.

[0014] In some exemplary embodiments, the light-transmitting display area is circular or elliptical, and the second trace is arc-shaped.

[0015] On the other hand, embodiments of this disclosure provide a display device including a display substrate as described above.

[0016] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0017] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of one or more components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0018] Figure 1 This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0019] Figure 2This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0020] Figure 3 for Figure 2 The provided timing diagram for the pixel circuit;

[0021] Figure 4 This is a partial schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0022] Figure 5 for Figure 4 A partial cross-sectional view along the Q-Q' direction;

[0023] Figure 6 This is another partial schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0024] Figure 7 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0025] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0026] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0027] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0028] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0029] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0030] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional elements.

[0031] In this specification, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0032] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0033] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0034] In this disclosure, "light transmittance" refers to the ability of light to pass through a medium, and is the percentage of light flux passing through a transparent or translucent body relative to the incident light flux.

[0035] In this disclosure, "approximately" and "roughly" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this disclosure, "roughly the same" means that the values ​​differ by no more than 10%.

[0036] This disclosure provides a display substrate, including: a substrate, a plurality of first pixel circuits, and at least one first data line. The substrate includes a display area and a peripheral area at least partially surrounding the display area, the display area including a light-transmitting display area. The plurality of first pixel circuits are located in the light-transmitting display area. The at least one first data line extends along a first direction and is partially located in the light-transmitting display area. The first data line is configured to provide data signals to the plurality of first pixel circuits from opposite sides of the light-transmitting display area in the first direction.

[0037] The display substrate provided in this embodiment enables data signals to be transmitted from opposite sides in the first direction to the light-transmitting display area through the arrangement of the first data lines, thereby improving the display effect of the light-transmitting display area caused by the excessive impedance of the first data lines, and thus improving the refresh rate and uniform display effect of the display substrate.

[0038] In some exemplary embodiments, the first data line may include a first sub-data line and a second sub-data line. The first sub-data line is located in the light-transmitting display area and extends along a first direction. Both ends of the first sub-data line along the first direction are electrically connected to the second sub-data line. The first sub-data line is made of a transparent conductive material and is electrically connected to a plurality of first pixel circuits arranged along the first direction within the light-transmitting display area. The second sub-data line is made of a metallic material. In some examples, the first sub-data line may be located in the light-transmitting display area and made of a transparent conductive material, while the second sub-data line may be located in an area outside the light-transmitting display area (e.g., a non-light-transmitting display area or a peripheral area) and made of a metallic material. By connecting portions of the first and second sub-data lines in parallel, the load on the first sub-data line can be reduced, thereby improving the display effect of the display substrate.

[0039] In some exemplary embodiments, the second sub-data line may include a first trace, a second trace, and a third trace. The second trace is electrically connected between the first trace and the third trace. The first trace and the third trace are located on opposite sides of the first sub-data line along a first direction. The second trace is located on one side of the first sub-data line in a second direction. The first direction intersects the second direction. For example, the first direction is perpendicular to the second direction. However, this embodiment is not limited in this respect.

[0040] In some exemplary embodiments, the first sub-data line has a first end and a second end along a first direction. The first end of the first sub-data line is electrically connected to a first trace, and the second end of the first sub-data line is electrically connected to a third trace. In some examples, the connection position of the first sub-data line and the first trace may not overlap with the connection position of the second trace and the first trace, and the connection position of the first sub-data line and the third trace may not overlap with the connection position of the second trace and the third trace. However, this embodiment is not limited in this respect. For example, the connection position of the first sub-data line and the first trace may coincide with the connection position of the second trace and the first trace, and the connection position of the first sub-data line and the third trace may coincide with the connection position of the second trace and the third trace.

[0041] In some exemplary embodiments, the first trace and the third trace can be on the same layer. The second trace and the first trace can be on different layers. The first sub-data line can be located on the side of the first trace away from the substrate. In some examples, the second trace is located on the side of the first trace away from the substrate and on the side of the first sub-data line close to the substrate. However, this embodiment is not limited to this. For example, the second trace can be located on the side of the first trace close to the substrate, or it can be located on the side of the first sub-data line away from the substrate.

[0042] In some exemplary embodiments, a first organic insulating layer is disposed on the side of the second trace closer to the substrate, and a second organic insulating layer is disposed on the side of the second trace farther from the substrate. In this example, the second trace may be sandwiched between the two organic insulating layers, thereby reducing the parasitic capacitance between the traces and increasing the spacing between adjacent second traces.

[0043] In some exemplary embodiments, the first sub-data line may extend to an area outside the light-transmitting display area (e.g., a non-light-transmitting display area or surrounding area), and be electrically connected to the first and third traces of the second sub-data line in the area outside the light-transmitting display area. In this example, the connection point of the first and second sub-data lines may be located in an area outside the light-transmitting display area. However, this embodiment is not limited to this.

[0044] In some exemplary embodiments, the first and third traces of the second sub-data line extend to the light-transmitting display area and are electrically connected to the first sub-data line in the light-transmitting display area. In this example, the connection point of the first and second sub-data lines can be located within the light-transmitting display area. However, this embodiment is not limited to this.

[0045] The following examples illustrate the solution of this embodiment.

[0046] Figure 1 This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as Figure 1 As shown, the display substrate includes a display area AA and a peripheral area BB surrounding the display area AA. The display area AA of the display substrate may include a first display area A1 and a second display area A2 located on at least one side of the first display area A1. In some examples, the first display area A1 is the aforementioned light-transmitting display area, and may also be referred to as the under-display camera (UDC) area; the second display area A2 is the aforementioned non-light-transmitting display area, and may also be referred to as the normal display area. For example, the orthographic projection of hardware such as a photosensor (e.g., a camera) onto the display substrate may be located within the first display area A1 of the display substrate. In some examples, such as... Figure 1 As shown, the first display area A1 can be circular, and the size of the orthographic projection of the photosensor onto the display substrate can be less than or equal to the size of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area can be rectangular, and the size of the orthographic projection of the photosensor onto the display substrate can be less than or equal to the size of the inscribed circle of the first display area.

[0047] In some exemplary implementations, such as Figure 1 As shown, the first display area A1 can be located at the top center of the display area AA. The second display area A2 can surround the first display area A1. However, this embodiment is not limited to this. For example, the first display area can be located at other positions such as the upper left or upper right corner of the display area.

[0048] In some exemplary implementations, such as Figure 1 As shown, the display area AA can be rectangular, such as a rounded rectangle. The first display area A1 can be circular or elliptical. However, this embodiment is not limited to this. For example, the first display area can be other shapes such as rectangles or pentagons.

[0049] In some exemplary embodiments, the display area is provided with a plurality of sub-pixels. At least one sub-pixel includes pixel circuitry and a light-emitting element. The pixel circuitry is configured to drive the connected light-emitting element. For example, the pixel circuitry is configured to provide a drive current to drive the light-emitting element to emit light. In some examples, the light-emitting element may be an organic light-emitting diode (OLED), which emits red, green, blue, or white light, etc., under the drive of its corresponding pixel circuitry. The color emitted by the light-emitting element can be determined as needed.

[0050] In some exemplary embodiments, a pixel unit of the display area may include three sub-pixels, which may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, which may be a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, respectively.

[0051] In some exemplary embodiments, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; when a pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0052] In some exemplary embodiments, a sub-pixel may include a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor; for example, the pixel circuit may be a 3T1C (3 transistors and 1 capacitor) structure, a 7T1C (7 transistors and 1 capacitor) structure, or a 5T1C (5 transistors and 1 capacitor) structure. In some examples, the light-emitting element may be an OLED device. The light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0053] Figure 2 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. Figure 3 for Figure 2 The provided timing diagram for the pixel circuit is shown.

[0054] In some exemplary implementations, such as Figure 2As shown, the pixel circuit of this exemplary embodiment may include: six switching transistors (T1, T2, T4 to T7), one driving transistor T3, and one storage capacitor Cst. The six switching transistors are a data writing transistor T4, a threshold compensation transistor T2, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first reset transistor T1, and a second reset transistor T7. The light-emitting element EL includes an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode.

[0055] In some exemplary embodiments, the driving transistor and the six switching transistors can be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the processing difficulty of the display substrate, and improve product yield. In some possible implementations, the driving transistor and the six switching transistors may include both P-type and N-type transistors.

[0056] In some exemplary embodiments, the driving transistor and the six switching transistors can be low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs), oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the OPT TFT is made of oxide semiconductor. LTPS TFTs offer advantages such as high mobility and fast charging, while OPT TFTs offer advantages such as low leakage current. Integrating LTPS and OPT TFTs onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0057] In some exemplary implementations, such as Figure 2As shown, the pixel circuit is electrically connected to the scan line GL, data line DL, first power line PL1, second power line PL2, light emission control line EML, initial signal line INIT, first reset control line RST1, and second reset control line RST2. In some examples, the first power line PL1 is configured to provide a constant first voltage signal VDD to the pixel circuit, and the second power line PL2 is configured to provide a constant second voltage signal VSS to the pixel circuit, wherein the first voltage signal VDD is greater than the second voltage signal VSS. The scan line GL is configured to provide the scan signal SCAN to the pixel circuit, the data line DL is configured to provide the data signal DATA to the pixel circuit, the light emission control line EML is configured to provide the light emission control signal EM to the pixel circuit, the first reset control line RST1 is configured to provide the first reset control signal RESET1 to the pixel circuit, and the second reset control line RST2 is configured to provide the second reset signal RESET2 to the pixel circuit. In some examples, in a row of pixel circuits, the second reset control line RST2 may be connected to the scan line GL to be input with the scan signal SCAN. That is, the second reset signal RESET2(n) received by the nth row pixel circuit is the scan signal SCAN(n) received by the nth row pixel circuit. However, this embodiment is not limited to this. For example, the second reset control signal line RST2 can be input with a second reset control signal RESET2 different from the scan signal SCAN. In some examples, in the nth row pixel circuit, the first reset control line RST1 can be connected to the scan line GL of the (n-1)th row pixel circuit to be input with the scan signal SCAN(n-1), that is, the first reset control signal RESET1(n) is the same as the scan signal SCAN(n-1). In this way, the signal lines of the display substrate can be reduced, and a narrow bezel of the display substrate can be achieved.

[0058] In some exemplary implementations, such as Figure 2As shown, the driving transistor T3 is electrically connected to the light-emitting element EL, and outputs a driving current to drive the light-emitting element EL to emit light under the control of signals such as the scan signal SCAN, data signal DATA, first voltage signal VDD, and second voltage signal VSS. The gate of the data writing transistor T4 is electrically connected to the scan line GL, the first terminal of the data writing transistor T4 is electrically connected to the data line DL, and the second terminal of the data writing transistor T4 is electrically connected to the first terminal of the driving transistor T3. The gate of the threshold compensation transistor T2 is electrically connected to the scan line GL, the first terminal of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, and the second terminal of the threshold compensation transistor T2 is electrically connected to the second terminal of the driving transistor T3. The gate of the first light-emitting control transistor T5 is electrically connected to the light-emitting control line EML, the first terminal of the first light-emitting control transistor T5 is electrically connected to the first power supply line PL1, and the second terminal of the first light-emitting control transistor T5 is electrically connected to the first terminal of the driving transistor T3. The gate of the second light-emitting control transistor T6 is electrically connected to the light-emitting control line EML. The first electrode of the second light-emitting control transistor T6 is electrically connected to the second electrode of the driving transistor T3. The second electrode of the second light-emitting control transistor T6 is electrically connected to the anode of the light-emitting element EL. The first reset transistor T1 is electrically connected to the gate of the driving transistor T3 and is configured to reset the gate of the driving transistor T3. The second reset transistor T7 is electrically connected to the anode of the light-emitting element EL and is configured to reset the anode of the light-emitting element EL. The gate of the first reset transistor T1 is electrically connected to the first reset control line RST1. The first electrode of the first reset transistor T1 is electrically connected to the initial signal line INIT. The second electrode of the first reset transistor T1 is electrically connected to the gate of the driving transistor T3. The gate of the second reset transistor T7 is electrically connected to the second reset control line RST2. The first electrode of the second reset transistor T7 is electrically connected to the initial signal line INIT. The second electrode of the second reset transistor T7 is electrically connected to the anode of the light-emitting element EL. The first electrode of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3. The second electrode of the storage capacitor Cst is electrically connected to the first power supply line PL1.

[0059] In this example, the first node N1 is the connection point of the storage capacitor Cst, the first reset transistor T1, the driving transistor T3 and the threshold compensation transistor T2; the second node N2 is the connection point of the first light-emitting control transistor T5, the data writing transistor T4 and the driving transistor T3; the third node N3 is the connection point of the driving transistor T3, the threshold compensation transistor T2 and the second light-emitting control transistor T6; and the fourth node N4 is the connection point of the second light-emitting control transistor T6, the second reset transistor T7 and the light-emitting element EL.

[0060] The following reference Figure 3 right Figure 2 The operation of the pixel circuit shown will be explained. Specifically, using... Figure 2 The pixel circuit shown is illustrated using P-type transistors as an example.

[0061] In some exemplary implementations, such as Figure 2 and Figure 3 As shown, during a single frame display period, the operation of the pixel circuit can include: a first stage S1, a second stage S2, and a third stage S3.

[0062] The first stage, S1, is called the reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, turning on the first reset transistor T1. The initial signal Vinit provided by the initial signal line INIT is provided to the first node N1 to initialize N1 and clear the original data voltage in the storage capacitor Cst. The scan signal SCAN provided by the scan line GL is a high-level signal, and the light emission control signal EM provided by the light emission control line EML is a high-level signal, turning off the data writing transistor T4, the threshold compensation transistor T2, the first light emission control transistor T5, the second light emission control transistor T6, and the second reset transistor T7. During this stage, the light-emitting element EL does not emit light.

[0063] The second stage, S2, is called the data writing stage or threshold compensation stage. The scan signal SCAN provided by the scan line GL is low, while the first reset control signal RESET1 provided by the first reset control line RST1 and the light emission control signal EM provided by the light emission control line EML are both high. The data line DL outputs the data signal DATA. During this stage, because the second electrode of the storage capacitor Cst is low, the driving transistor T3 is turned on. The low scan signal SCAN turns on the threshold compensation transistor T2, the data writing transistor T4, and the second reset transistor T7. Threshold compensation transistor T2 and data write transistor T4 are turned on, allowing the data voltage Vdata output from data line DL to be supplied to first node N2 via second node N2, the turned-on drive transistor T3, third node N3, and the turned-on threshold compensation transistor T2. The difference between the data voltage Vdata output from data line DL and the threshold voltage of drive transistor T3 is charged into storage capacitor Cst. The voltage at the second electrode of storage capacitor Cst (i.e., first node N1) is Vdata - |Vth|, where Vdata is the data voltage output from data line DL and Vth is the threshold voltage of drive transistor T3. Second reset transistor T7 is turned on, allowing the initial signal Vinit provided by initial signal line INIT to be supplied to the anode of light-emitting element EL, initializing (resetting) the anode of light-emitting element EL, clearing its internal pre-stored voltage, completing the initialization, and ensuring that light-emitting element EL does not emit light. The first reset control signal RESET1 provided by first reset control line RST1 is a high-level signal, causing the first reset transistor T1 to turn off. The light emission control signal EM provided by the light emission control signal line EML is a high-level signal, which disconnects the first light emission control transistor T5 and the second light emission control transistor T6.

[0064] The third stage, S3, is called the light-emitting stage. The light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal, while the scan signal SCAN provided by the scan line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals. When the light-emitting control signal EM provided by the light-emitting control signal line EML is low, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on. The first voltage signal VDD output from the first power supply line PL1 provides a driving voltage to the anode of the light-emitting element EL through the turned-on first light-emitting control transistor T5, driving transistor T3, and second light-emitting control transistor T6, driving the light-emitting element EL to emit light.

[0065] During the driving process of the pixel circuit, the driving current flowing through the driving transistor T3 is determined by the voltage difference between its gate and its first terminal. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the driving transistor T3 is:

[0066] I = K × (Vgs - Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[(VDD-Vdata)] 2 ;

[0067] Where I is the driving current flowing through the driving transistor T3, which is also the driving current driving the light-emitting element EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the driving transistor T3, Vth is the threshold voltage of the driving transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power line PL1.

[0068] As can be seen from the above formula, the current flowing through the light-emitting element EL is independent of the threshold voltage of the driving transistor T3. Therefore, the pixel circuit of this embodiment can effectively compensate for the threshold voltage of the driving transistor T3.

[0069] In some exemplary embodiments, a first display area A1 is provided with a plurality of first sub-pixels. A first sub-pixel may include a first pixel circuit and a first light-emitting element electrically connected to the first pixel circuit. For example, the plurality of first pixel circuits and the plurality of first light-emitting elements in the first display area A1 may have a one-to-one correspondence. However, this embodiment is not limited to this. For example, the first pixel circuits and the first light-emitting elements in the first display area may have a one-to-many relationship. That is, one first pixel circuit in the first display area may drive two or more first light-emitting elements to emit light.

[0070] In some exemplary embodiments, the second display area A2 is provided with a plurality of second sub-pixels. Each second sub-pixel may include a second pixel circuit and a second light-emitting element electrically connected to the second pixel circuit. For example, the plurality of second pixel circuits and the plurality of second light-emitting elements in the second display area A2 may have a one-to-one correspondence.

[0071] In some exemplary implementations, such as Figure 1As shown, display area AA is provided with multiple first data lines DL1 and multiple second data lines DL2. The multiple second data lines DL2 are located in the second display area A2, extending along the first direction Y and arranged sequentially along the second direction X. The second data lines DL2 can be electrically connected to multiple second pixel circuits arranged along the first direction Y within the second display area A2, configured to provide data signals to the multiple second pixel circuits. Multiple first data lines DL1 are located in display area AA, extending along the first direction Y from the second display area A2 into the first display area A1. The first data lines DL1 can be electrically connected to multiple first pixel circuits arranged along the first direction Y within the first display area A1, and also to multiple second pixel circuits arranged along the first direction Y within the second display area A2. The first data lines DL1 can be configured to provide data signals to multiple first pixel circuits and multiple second pixel circuits located in the same column.

[0072] Figure 4 This is a partial schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Figure 5 for Figure 4 A partial cross-sectional view along the Q-Q' direction. Figure 4 The illustration uses only the six first data lines DL1 as an example. Figure 5 The illustration uses a transistor and a capacitor from the first pixel circuit as an example. However, this embodiment is not limited to this. The following description uses a first data line DL1 as an example.

[0073] In some exemplary implementations, such as Figure 4 As shown, the first data line DL1 may include a first sub-data line 21 located in the first display area A1 and a second sub-data line 22 located in the second display area A2. A portion of the second sub-data line 22 extends from the second display area A2 to the first display area A1 and is electrically connected to the first sub-data line 21, while the other portion of the second sub-data line 22 is arranged around the edge of the first display area A1. The connection position of the first sub-data line 21 and the second sub-data line 22 may be within the first display area A1 and close to the second display area A2. However, this embodiment is not limited to this. For example, the first sub-data line 21 may extend to the second display area A2 and be electrically connected to the second sub-data line 22 in the second display area A2.

[0074] In some exemplary implementations, such as Figure 4As shown, multiple first sub-data lines 21 are located in the first display area A1 and extend along the first direction Y. These multiple first sub-data lines 21 are arranged sequentially along the second direction X within the first display area A1. The first sub-data lines 21 are electrically connected to multiple first pixel circuits 30 arranged along the first direction Y within the first display area A1, and are configured to provide data signals to the multiple first pixel circuits 30. The first sub-data lines 21 can be made of transparent conductive materials, such as indium tin oxide (ITO) or indium zinc oxide (IZO), thereby ensuring the light transmittance of the first display area A1. The first sub-data lines 21 may have a first end 211 and a second end 212 in the first direction Y. The orthographic projections of the first end 211 and the second end 212 onto the substrate may not overlap with the orthographic projections of the first pixel circuits 30 onto the substrate. However, this embodiment is not limited to this.

[0075] In some exemplary implementations, such as Figure 4 As shown, the second sub-data line 22 may include a first trace 221, a second trace 222, and a third trace 223. The second trace 222 is electrically connected between the first trace 221 and the third trace 223. The first trace 221 and the third trace 223 are located on opposite sides of the first sub-data line 21 along a first direction Y. The second trace 222 is located on one side of the first sub-data line 21 in a second direction X. The first trace 221 may be located in a second display area A2 below the first display area A1 and is electrically connected to a plurality of second pixel circuits in the second display area A2. The first trace 221 is electrically connected to the second trace 222 on the lower side of the first display area A1 and extends to the first end 211 of the first display area A1 and is electrically connected to the first end 211 of the first sub-data line 21. The third trace 223 may be located in a second display area A2 above the first display area A1 and is electrically connected to a plurality of second pixel circuits in the second display area A2. The third trace 223 is electrically connected to the second trace 222 on the upper side of the first display area A1, and extends to the second end 212 of the first sub-data line 21 in the first display area A1 for electrical connection. However, this embodiment is not limited in this respect. For example, the third trace 223 may be located in the peripheral area BB of the first display area A1 away from the second display area A2.

[0076] In some exemplary implementations, such as Figure 4 As shown, the second trace 222 is located within the second display area A2 adjacent to the first display area A1 in the second direction X, and the second trace 222 can be arranged around the edge of the first display area A1. When the first display area A1 is circular or elliptical, the second trace 222 can be arc-shaped; when the first display area A1 is rectangular, the second trace 222 can be polygonal. However, this embodiment is not limited in this respect.

[0077] In some exemplary implementations, such as Figure 1 and Figure 4As shown, n first data lines DL1 can be divided into two groups, winding from the bottom of the first display area A1 along both the left and right sides to the top of the first display area A1. When n is even, n / 2 first data lines DL1 can wind from the bottom of the first display area A1 along the left side to the top, and n / 2 first data lines DL1 can wind from the bottom of the first display area A1 along the right side to the top. For example, in Figure 4 In this embodiment, three first data lines DL1 wind from the bottom of the first display area A1 along the left side to the top, and another three first data lines DL1 wind from the bottom of the first display area A1 along the right side to the top. In some examples, when n is odd, (n+1) / 2 first data lines DL1 can wind from the bottom of the first display area A1 along the left side to the top, and (n-1) / 2 first data lines DL1 can wind from the bottom of the first display area A1 along the right side to the top; or, (n-1) / 2 first data lines DL1 can wind from the bottom of the first display area A1 along the left side to the top, and (n+1) / 2 first data lines DL1 can wind from the bottom of the first display area A1 along the right side to the top. However, this embodiment is not limited to this.

[0078] In this exemplary embodiment, data signals can be transmitted to the first sub-data line 21 via the first trace 221 and the third trace 223, thereby enabling data signal transmission from both the top and bottom sides to the first pixel circuit 30 of the first display area A1. The routing of the first data line DL1 allows data signals to be transmitted from the opposite sides (i.e., the top and bottom sides) of the first display area A1 in the first direction Y to the first pixel circuit 30 of the first display area A1. This mitigates the impact on display performance caused by excessive data line load in the first display area due to the high impedance of the transparent conductive material. For example, it avoids the situation where the brightness of the first sub-pixel in the upper half of the first display area is too high due to the load of the first data line, and it also mitigates the adverse effects of excessively long rise and fall times of the data signal caused by excessive load on the first data line, which hinders the achievement of a high refresh rate.

[0079] In some exemplary implementations, such as Figure 5As shown, in a direction perpendicular to the display substrate, the display substrate may include: a substrate 10, a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a first transparent conductive layer disposed on the substrate 10. A first insulating layer 11 (or a first gate insulating layer) is disposed between the semiconductor layer and the first conductive layer. A second insulating layer 12 (or a second gate insulating layer) is disposed between the first conductive layer and the second conductive layer. A third insulating layer 13 (or an interlayer insulating layer) is disposed between the second conductive layer and the third conductive layer. A fourth insulating layer 14 is disposed between the third conductive layer and the fourth conductive layer. A fifth insulating layer 15 is disposed between the fourth conductive layer and the first transparent conductive layer. In some examples, the first insulating layer 11 to the third insulating layer 13 may be inorganic insulating layers, the fourth insulating layer 14 may be the aforementioned first organic insulating layer, and the fifth insulating layer 15 may be the aforementioned second organic insulating layer. However, this embodiment is not limited to this. In some examples, the fourth insulating layer 14 and the fifth insulating layer 15 may be inorganic insulating layers, or they may be a stacked structure of inorganic and organic layers.

[0080] In some exemplary implementations, such as Figure 5 As shown, the semiconductor layer includes at least: the active layer of the first transistor 23 of the first pixel circuit 30. The first conductive layer includes at least: the gate electrode of the first transistor 23 of the first pixel circuit 30 and the first capacitor electrode of the first storage capacitor 24. The second conductive layer includes at least: the second capacitor electrode of the first storage capacitor 24 of the first pixel circuit 30. The third conductive layer includes at least: the source electrode and drain electrode of the first transistor 23 of the first pixel circuit 30, the first trace 221 and the third trace 223 of the first data line DL1, and the second data line DL2. The fourth conductive layer includes at least: the second trace 222 of the first data line DL1. The first transparent conductive layer includes at least: the first sub-data line 21 of the first data line DL1. In some examples, the first display area A1 of the display substrate may also include: a planarization layer, an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode layer located on the side of the first transparent conductive layer away from the substrate 10. However, this embodiment is not limited in this respect.

[0081] In some exemplary implementations, such as Figure 4 and Figure 5As shown, the fourth insulating layer 14 has multiple first vias K1 and multiple second vias K2. The fourth insulating layer 14 within the first vias K1 and second vias K2 is removed, exposing the surface of the third conductive layer. The second trace 222 of the second sub-data line 22 of the first data line DL1 can be electrically connected to the first trace 221 through the first via K1, and can also be electrically connected to the third trace 223 through the second via K2. The second sub-data line 22 of the first data line DL1 can extend from the lower side of the first display area A1 around the edge of the first display area A1 to the upper side of the first display area A1.

[0082] In some exemplary implementations, such as Figure 4 and Figure 5 As shown, multiple third vias K3 and multiple fourth vias K4 are formed on the fifth insulating layer 15. The fourth insulating layer 14 and the fifth insulating layer 15 within the third vias K3 and the fourth vias K4 are removed, exposing the surface of the third conductive layer. The first end 211 of the first sub-data line 21 of the first data line DL1 can be electrically connected to the first trace 221 through the third via K3, and the second end 212 of the first sub-data line 21 can be electrically connected to the third trace 223 through the fourth via K4. In this example, the second trace 222 and the first sub-data line 21 can be connected in parallel between the first trace 221 and the third trace 223, thereby mitigating the adverse effect of excessive impedance of the first sub-data line 21 causing excessive load on the first data line. Moreover, since both the first trace 221 and the third trace 223 can provide data signals to the first sub-data line 21, the data signals can achieve a counteracting effect in the upper and lower parts of the first display area A1, thereby halving the load of the data signals in the first display area A1. The display in the upper half of the first display area A1 is not affected by excessive load, which is conducive to improving the refresh rate and the uniformity of the display effect.

[0083] In some exemplary embodiments, the first, second, third, and fourth conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first transparent conductive layer can be made of transparent conductive materials such as ITO or IZO. The first insulating layer 11, second insulating layer 12, and third insulating layer 13 can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The fourth insulating layer 14 and fifth insulating layer 15 can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. In this example, the second trace 222 is located between the fourth insulating layer 14 and the fifth insulating layer 15, which can reduce the parasitic capacitance between the traces. Furthermore, since the fourth conductive layer is free from interference from other traces, the spacing between adjacent second traces 222 can be increased. However, this embodiment is not limited in this respect.

[0084] The structure and fabrication process of the display substrate in this embodiment are merely illustrative. In some exemplary embodiments, the corresponding structure and patterning processes can be modified and increased or decreased according to actual needs. For example, the film layer containing the second trace can be located on the side of the second conductive layer away from the substrate and the side of the third conductive layer close to the substrate, or it can be located on the side of the first transparent conductive layer away from the substrate. However, this embodiment is not limited in this respect.

[0085] Figure 6 This is another partial schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 6 As shown, the first sub-data line 21 of the first data line DL1 can extend to the second display area A2 and be electrically connected to the second sub-data line 22 of the second display area A2. The first sub-data line 21 can be electrically connected to the second sub-data line 22 in the second display area A2 below the first display area A1, and can also be electrically connected to the second sub-data line 22 in the second display area A2 above the first display area A1, thereby enabling the provision of data signals to the first display area A1 from both the upper and lower sides in the first direction Y.

[0086] In some exemplary embodiments, the first sub-data line 21 can be electrically connected to both ends of the second trace 222 through vias formed in the fifth insulating layer 15, and the two ends of the second trace 222 can be electrically connected to the first trace 221 and the third trace 223 through vias formed in the fourth insulating layer 14. Alternatively, the two ends of the first sub-data line 21 can be electrically connected to the first trace 221 and the third trace 223 through vias formed in the fifth insulating layer 15, and the two ends of the second trace 222 can be electrically connected to the first trace 221 and the third trace 223 through vias formed in the fourth insulating layer 14. However, this embodiment is not limited to this.

[0087] The remaining structure of the display substrate in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0088] At least one embodiment of this disclosure also provides a display device, including the display substrate described above.

[0089] Figure 7 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Figure 7 As shown, this embodiment provides a display device, including: a display substrate 91 and a photosensor 92 located on the light-emitting side of a display structure layer away from the display substrate 91. The orthographic projection of the photosensor 92 on the display substrate 91 overlaps with the first display area A1.

[0090] In some examples, the display substrate 91 can be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device can be any product or component with display function, such as an OLED display, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and the embodiments disclosed herein are not limited thereto.

[0091] The accompanying drawings in this disclosure only illustrate the structures relevant to this disclosure; other structures can be referenced to common designs. Unless otherwise specified, embodiments of this disclosure, i.e., features within the embodiments, can be combined with each other to obtain new embodiments.

[0092] Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions disclosed herein without departing from the spirit and scope of the technical solutions disclosed herein, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.

Claims

1. A display substrate, characterized in that, include: A substrate includes a display area and at least a peripheral area surrounding the display area, the display area including a light-transmitting display area; Multiple first pixel circuits are located in the light-transmitting display area; At least one first data line extends along a first direction and is partially located in the light-transmitting display area; The at least one first data line is configured to provide data signals to a plurality of first pixel circuits from opposite sides of the light-transmitting display area in the first direction; The first data line includes: a first sub-data line and a second sub-data line; the first sub-data line is located in the light-transmitting display area and extends along the first direction, and the two ends of the first sub-data line along the first direction are electrically connected to the second sub-data line; The second sub-data line includes: a first trace, a second trace, and a third trace; the second trace is electrically connected between the first trace and the third trace; In a direction perpendicular to the display substrate, the display substrate includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a first transparent conductive layer disposed on a substrate; the first trace and the third trace are located on the third conductive layer, the second trace is located on the fourth conductive layer, and the first sub-data line is located on the first transparent conductive layer.

2. The display substrate according to claim 1, characterized in that, The first sub-data line is made of a transparent conductive material and is electrically connected to a plurality of first pixel circuits arranged along the first direction in the light-transmitting display area; the second sub-data line is made of a metallic material.

3. The display substrate according to claim 2, characterized in that, The first trace and the third trace are located on opposite sides of the first sub-data line along the first direction; the second trace is located on one side of the first sub-data line in the second direction. The first direction intersects with the second direction.

4. The display substrate according to claim 3, characterized in that, The first sub-data line has a first end and a second end along the first direction. The first end of the first sub-data line is electrically connected to the first trace, and the second end of the first sub-data line is electrically connected to the third trace.

5. The display substrate according to claim 3, characterized in that, The first trace and the third trace are in the same layer, the second trace and the first trace are in different layers, and the first sub-data line is located on the side of the first trace away from the substrate.

6. The display substrate according to claim 5, characterized in that, The second trace is located on the side of the first trace away from the substrate, and on the side of the first sub-data line close to the substrate.

7. The display substrate according to claim 5, characterized in that, A first organic insulating layer is disposed on the side of the second trace closer to the substrate, and a second organic insulating layer is disposed on the side of the second trace away from the substrate.

8. The display substrate according to any one of claims 3 to 7, characterized in that, The first sub-data line extends to an area outside the light-transmitting display area, and is electrically connected to the first and third traces of the second sub-data line in the area outside the light-transmitting display area.

9. The display substrate according to any one of claims 3 to 7, characterized in that, The first and third traces of the second sub-data line extend to the light-transmitting display area and are electrically connected to the first sub-data line in the light-transmitting display area.

10. The display substrate according to any one of claims 3 to 7, characterized in that, The light-transmitting display area is circular or elliptical, and the second trace is arc-shaped.

11. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 10.

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