Display panel, manufacturing method thereof and display device

Abstract

Embodiments of the present application disclose a display panel, a manufacturing method thereof and a display device. The display panel comprises a data wire, a voltage bus and a test connection line arranged at least between the data wire and the voltage bus. The line width of the test connection line is smaller than the line width of the data wire and the line width of the voltage bus. The test connection line comprises at least two connection sections and at least one blank section. The line width of the test connection line arranged at least between the data wire and the voltage bus is narrowed. After OST detection, the test connection line which does not need to be connected to the data wire and the voltage bus is etched off. The narrowed test connection line is beneficial to longitudinal etching and lateral etching of the etching liquid. Under the joint action of longitudinal etching and lateral etching, the narrowed test connection line is more likely to form a disconnected blank section, abnormal electrical connection is avoided, the process efficiency is improved, and the yield quality of the display panel is improved.

Description

Technical Field

[0001] This application relates to the field of displays, specifically to a display panel and its manufacturing method, and a display device. Background Technology

[0002] In recent years, the quality of display panels has received increasing attention from consumers. Connectivity inspection of the metal trace film layer is essential and crucial. Common defects in the metal trace film layer are generally two types of anomalies: open circuits due to broken lines or short circuits caused by metal residue. These anomalies will appear as dark lines, bright lines, and dotted lines during subsequent LED illumination, significantly reducing the quality of the display panel. Therefore, OST (open short circuit test) is included in the display panel manufacturing process to check for the above-mentioned anomalies. Thus, the detection rate of OST is particularly important. Generally, during OST testing, a portion of the circuitry is short-circuited for testing. After the test, the traces that do not need to be connected are etched off. The efficiency and quality of this trace etching affect the overall production efficiency and quality of the display panel.

[0003] Therefore, there is an urgent need for a display panel, its manufacturing method, and a display device to solve the above-mentioned technical problems. Summary of the Invention

[0004] This application provides a display panel and its manufacturing method, as well as a display device, which can improve the efficiency and quality of etching traces that do not need to be connected after OST testing.

[0005] This application provides a display panel, including:

[0006] A voltage bus extends along the first direction;

[0007] The data trace extends along the second direction;

[0008] The test connection line shall be installed at least between the data trace and the voltage bus;

[0009] Wherein, the first direction and the second direction are at an angle, the line width of the test connection line is smaller than the line width of the data trace, the line width of the test connection line is smaller than the line width of the voltage bus, and the test connection line includes at least two connection segments and at least one blank segment.

[0010] In some embodiments, the display panel includes: a substrate; a first metal layer located on the substrate, the first metal layer including each of the data traces and the test connection lines; and a first insulating layer located on the side of the first metal layer away from the substrate, the first insulating layer including a plurality of first openings, the first openings corresponding to the blank segments.

[0011] In some embodiments, the width of the first opening in the direction perpendicular to the extension of the corresponding connecting segment is greater than the width of the connecting segment in the direction perpendicular to the extension of the corresponding connecting segment.

[0012] In some embodiments, the first opening is disposed between two adjacent longitudinally extending connecting segments.

[0013] In some embodiments, the ratio of the width of the first opening in the direction perpendicular to the extension of the corresponding connecting segment to the width of the connecting segment in the direction perpendicular to the extension of the corresponding connecting segment is 2.5 to 7.

[0014] In some embodiments, the first metal layer further includes voltage traces and sensing lines extending along a second direction, wherein the voltage traces are electrically connected to the corresponding voltage bus; wherein, in the second direction, one voltage trace and one data trace form a group, two other data traces form a group, and one voltage trace and one sensing line form a group alternately arranged.

[0015] In some embodiments, the test connection line is further disposed between the sensing line and the voltage bus; wherein the line width of the test connection line is smaller than the line width of the sensing line.

[0016] This application also provides a method for manufacturing a display panel, including:

[0017] Provide a substrate;

[0018] A voltage bus extending in a first direction, a data trace extending in a second direction, and a test connection line connecting the data trace and the voltage bus are formed on the substrate to form a first metal layer. The line width of the test connection line is smaller than the line width of the data trace, and the line width of the test connection line is smaller than the line width of the voltage bus.

[0019] A first insulating layer is formed on the side of the first metal layer away from the substrate;

[0020] Perform open / short circuit tests on each wiring route;

[0021] A plurality of first openings are formed on the first insulating layer, the first openings exposing the test connection wires;

[0022] The test connection line is etched using the first opening, so that the test connection line exposed by the first opening forms a blank segment, and the test connection line not exposed by the first opening forms a connection segment.

[0023] In some embodiments, the step of forming a plurality of first openings on the first insulating layer, the first openings exposing the test connection wires, includes: forming a plurality of first openings on the first insulating layer, the first openings exposing the test connection wires, wherein the width of the first openings in the direction perpendicular to the extension of the corresponding connection segment is greater than the width of the connection segment in the direction perpendicular to the extension of the corresponding connection segment.

[0024] This application also provides a display device, including a display panel as described in any of the above and a device body, wherein the device body and the display panel are integrated into one unit.

[0025] The beneficial effects of this application are as follows: By narrowing the line width of the test connection lines at least between the data traces and the voltage bus, the line width of the test connection lines is smaller than that of the data traces and the voltage bus. After OST detection, it is beneficial to etch and break the test connection lines that do not need to be connected to the data traces and the voltage bus. The narrowed test connection lines are not only beneficial for the vertical etching of the etching solution, but also for the lateral etching of the etching solution. Under the combined effect of vertical and lateral etching, the narrowed test connection lines are more likely to form broken blank segments, avoiding abnormal electrical connections, improving process efficiency, and improving the yield and quality of the display panel. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a top view of the display panel provided in an embodiment of this application;

[0028] Figure 2 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application;

[0029] Figure 3 This is a flowchart of the steps in the method for manufacturing a display panel provided in an embodiment of this application;

[0030] Figures 4A to 4E This is a flowchart illustrating the method for manufacturing a display panel according to an embodiment of this application;

[0031] Figure 5 This is a schematic diagram of the structure of the display device provided in the embodiments of this application. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0033] In recent years, the quality of display panels has received increasing attention from consumers. Connectivity inspection of the metal trace film layer is essential and crucial. Common defects in the metal trace film layer are generally two types of anomalies: open circuits due to broken lines or short circuits caused by metal residue. These anomalies will appear as dark lines, bright lines, and dotted lines during subsequent LED illumination, significantly reducing the quality of the display panel. Therefore, OST (open short circuit test) is included in the display panel manufacturing process to check for the above-mentioned anomalies. Thus, the detection rate of OST is particularly important. Generally, during OST testing, a portion of the circuitry is short-circuited for testing. After the test, the traces that do not need to be connected are etched off. The efficiency and quality of this trace etching affect the overall production efficiency and quality of the display panel.

[0034] Please see Figure 1 , Figure 2 This application provides a display panel 100, including:

[0035] Voltage bus 300 extends along the first direction;

[0036] Data trace 200, extending along the second direction;

[0037] Test connection line 400 shall be provided at least between the data trace 200 and the voltage bus 300;

[0038] Wherein, the first direction and the second direction are at an angle, the line width of the test connection line 400 is smaller than the line width of the data trace 200, the line width of the test connection line 400 is smaller than the line width of the voltage bus 300, and the test connection line 400 includes at least two connection segments 410 and at least one blank segment 420.

[0039] This application narrows the linewidth of the test connection lines, which are at least located between the data traces and the voltage bus, so that the linewidth of the test connection lines is smaller than that of the data traces and the voltage bus. After OST detection, this facilitates the etching of test connection lines that do not need to be connected to the data traces and the voltage bus. The narrowed test connection lines not only facilitate the vertical etching of the etching solution but also the lateral etching of the etching solution. Under the combined effect of vertical and lateral etching, the narrowed test connection lines are more likely to form broken blank segments, avoiding abnormal electrical connections, improving process efficiency, and improving the yield and quality of the display panel.

[0040] The technical solution of this application will now be described in conjunction with specific embodiments.

[0041] In this embodiment, please refer to Figure 1 , Figure 2 The display panel 100 includes a voltage bus 300 extending along a first direction, a data trace 200 extending along a second direction, and a test connection line 400 disposed between the data trace 200 and the voltage bus 300; wherein the first direction and the second direction form an angle, the line width of the test connection line 400 is smaller than the line width of the data trace 200, the line width of the test connection line 400 is smaller than the line width of the voltage bus 300, and the test connection line 400 includes at least two connection segments 410 and at least one blank segment 420.

[0042] For ease of description, as shown in the figure, the first direction is parallel to the Y-axis, and the second direction is parallel to the X-axis. Please refer to [reference needed]. Figure 4E The longitudinal etching of the test connection line 400 by the etching solution refers to etching in a direction perpendicular to the display panel 100, i.e., the dashed arrow parallel to the Z-axis direction. The lateral etching of the test connection line 400 by the etching solution corresponds to the etching rate of the sidewall of the test connection line 400, i.e., the dashed arrow parallel to the X-axis direction. Under the combined action of longitudinal and lateral etching, the narrowed test connection line 400 is more likely to form a broken blank segment 420, avoiding abnormal electrical connections, improving process efficiency, and improving the yield quality of the display panel 100.

[0043] In some embodiments, please refer to Figure 2 The display panel 100 includes: a substrate 110; a first metal layer 120 located on the substrate 110, the first metal layer 120 including each of the data traces 200 and the test connection line 400; and a first insulating layer 130 located on the side of the first metal layer 120 away from the substrate 110, the first insulating layer 130 including a plurality of first openings 140, the first openings 140 corresponding to the blank segment 420.

[0044] After OST testing, the test connection line 400 that does not need to be connected to the data line 200 and the voltage bus 300 is etched off. The first insulating layer 130 above the first metal layer 120 needs to be provided with a first opening 140 so that the test connection line 400 can be etched using the first opening 140. The test connection line 400 exposed by the first opening 140 forms a blank segment 420, and the test connection line 400 not exposed by the first opening 140 forms a connection segment 410.

[0045] In some embodiments, please refer to Figure 2 The display panel 100 further includes a second metal layer 106 located on the first insulating layer 130, the second metal layer 106 including source and drain layers.

[0046] In some embodiments, please refer to Figure 2 The display panel 100 also includes a planarization layer 107 located on the second metal layer 106. The planarization layer 107 fills the first opening 140 for reinforcement. Generally, the material of the planarization layer 107 is an organic material, which can fill the hole well and at the same time provide the opening for better bending resistance.

[0047] In some embodiments, the voltage bus 300 may be disposed on the same layer as the first metal layer 120, the voltage bus 300 may be directly connected to the voltage trace 500, or / and disposed on the same layer as the second metal layer 106, the voltage bus 300 and the voltage trace 500 may be connected through vias, and may be set according to specific process routes and test routes, without specific limitations here.

[0048] In some embodiments, please refer to Figure 1 The width of the first opening 140 in the direction perpendicular to the extension of the corresponding connecting segment 410 is greater than the width of the connecting segment 410 in the direction perpendicular to the extension of the corresponding connecting segment 410.

[0049] The width of the first opening 140 in the direction perpendicular to the extension of the corresponding connecting segment 410 is greater than the line width of the connecting segment 410. The first opening 140 is used to drop etchant to etch the test connecting line 400. The slightly wider first opening 140 can provide etchant to increase the lateral etching efficiency of the test connecting line 400. The narrowed test connecting line 400 is not only beneficial to the longitudinal etching of the etchant, but also to the lateral etching of the etchant. Under the combined effect of longitudinal etching and lateral etching, the narrowed test connecting line 400 is more likely to form a broken blank segment 420, avoiding abnormal electrical connection.

[0050] In some embodiments, please refer to Figure 1 The first opening 140 is disposed between two adjacent longitudinally extending connecting segments 410.

[0051] The first opening 140 corresponds to the blank segment 420, that is, the etching position is generated in the longitudinal extension of the test connection line 400. Since the lateral extension of the test connection line 400 is close to the data trace 200, it is easy to cause abnormal etching of the data trace 200. Therefore, this position is selected for etching to avoid abnormal etching of the data trace 200 and ensure the normal electrical connection of the line.

[0052] In some embodiments, the ratio of the width of the first opening 140 in the direction perpendicular to the extension of the corresponding connecting segment 410 to the width of the connecting segment 410 in the direction perpendicular to the extension of the corresponding connecting segment 410 is 2.5 to 7.

[0053] The size of the first opening 140 affects the lateral etching of the test connection line 400. If the size of the first opening 140 is too large, it is easy to cause the etching solution to flow excessively into the non-opening area, resulting in abnormal line etching. If the size of the first opening 140 is too small, it is easy to cause insufficient lateral etching rate of the metal line, and the improvement of the etching effect of the metal line is not obvious. Therefore, the ratio of the width of the first opening 140 in the direction perpendicular to the extension of the corresponding connection segment 410 to the width of the connection segment 410 in the direction perpendicular to the extension of the corresponding connection segment 410 is 2.5 to 7. This can improve the lateral etching of the etching solution. Under the combined effect of longitudinal etching and lateral etching, the narrowed test connection line 400 is more likely to form a broken blank segment 420, avoiding abnormal electrical connection. It can also avoid excessive etching solution, reduce the risk of over-etching, and ensure the stability of the line electrical connection.

[0054] In some embodiments, please refer to Figure 1 The first metal layer 120 further includes a voltage trace 500 and a sensing line 600 extending along a second direction. The voltage trace 500 is electrically connected to the corresponding voltage bus 300. In the second direction, one voltage trace 500 and one data trace 200 form a group, two other data traces 200 form a group, and one voltage trace 500 and one sensing line 600 form a group, which are arranged alternately.

[0055] The voltage bus 300 includes a first voltage bus and a second voltage bus 320. The first voltage bus can be a VDD bus, and the second voltage bus 320 can be a VSS bus. The voltage trace 500 includes a first voltage trace 510 and a second voltage trace 520. The first voltage trace 510 can be a VDD trace, and the second voltage trace 520 can be a VSS trace.

[0056] For example, please see Figure 1 The display panel 100 includes a plurality of sub-pixels 700 arranged in an array. The sub-pixels 700 are any one of red sub-pixels 700, green sub-pixels 700, and blue sub-pixels 700. The light emission color of each column of sub-pixels 700 is the same. The data traces 200 are any one of red data traces R, green data traces G, and blue data traces B. The column direction is the first direction. The first voltage trace 510 and the red data trace R form a first group, the green data trace G and the blue data trace B form a second group, and the second voltage trace 520 and a sensing line 600 form a third group. In the second direction, the first group, the second group, and the third group are arranged alternately. The first group, the second group, and the third group are all disposed between two adjacent columns of sub-pixels 700.

[0057] The first, second, and third groups can form a 2 / 2 / 2 routing arrangement. The higher the sub-pixel density of the resolution (700), the closer the two traces in each group are, making short circuits more likely.

[0058] In OST testing, for example, please refer to Figure 1 In the diagram, for ease of understanding, only partial connections are shown. The red data trace R, the blue data trace B, and the second voltage trace 520 are interconnected. The red data trace R is connected to the second voltage bus 320 via the test connection line 400, the blue data trace B is connected to the second voltage bus 320 via the test connection line 400, and the second voltage trace 520 is connected to the second voltage bus 320. The first voltage trace 510, the green data trace G, and the sensing line 600 are disconnected from each other.

[0059] Alternatively, in OST testing, for example, the first voltage trace 510, the green data trace G, and the sensing line 600 are interconnected, with the green data trace G connected to the first voltage bus via the test connection line 400, the sensing line 600 connected to the first voltage bus via the test connection line 400, and the first voltage trace 510 connected to the first voltage bus; the red data trace R, the blue data trace B, and the second voltage trace 520 are disconnected from each other.

[0060] The voltage drop across three interconnected traces is low, resulting in a low potential. Under normal circumstances, the voltage drop across three disconnected traces is high, resulting in a high potential. The three disconnected traces can be measured separately. If there is a residual short circuit between two closely spaced traces in a certain group, the electrical signal of the floating trace will be pulled low by the electrical signal of the short-circuited trace, thus detecting the defect.

[0061] In some embodiments, please refer to Figure 1 The test connection line 400 is also disposed between the sensing line 600 and the voltage bus 300; wherein the line width of the test connection line 400 is smaller than the line width of the sensing line 600.

[0062] In OST testing, for example, the first voltage trace 510, the green data trace G, and the sensing line 600 are interconnected. The green data trace G is connected to the first voltage bus via the test connection line 400, and the sensing line 600 is connected to the first voltage bus via the test connection line 400. The first voltage trace 510 is connected to the first voltage bus. When the red data trace R, the blue data trace B, and the second voltage trace 520 are disconnected, the test connection line 400 needs to be placed between the sensing line 600 and the voltage bus 300. Similarly, the line width of the test connection line 400 needs to be smaller than the line width of the sensing line 600. The lateral etching of the test connection line 400 by the etching solution corresponds to the etching rate of the sidewall of the test connection line 400. Under the combined effect of longitudinal etching and lateral etching, the narrowed test connection line 400 is more likely to form a broken blank segment 420, avoiding abnormal electrical connections, improving process efficiency, and improving the yield quality of the display panel 100.

[0063] In some embodiments, the slope angle of the connecting segment 410 near the sidewall corresponding to the blank segment 420 is greater than the slope angle of the connecting segment 410 away from the sidewall corresponding to the blank segment 420.

[0064] The closer the connecting segment 410 is to the blank segment 420, the closer it is to the first opening 140 during the manufacturing process, and the closer it is to the etching solution, the larger the slope angle of the sidewall of the connecting segment 410, the more vertical the sidewall of the trace, the higher the efficiency of lateral etching, and the easier it is to etch and break, thereby avoiding abnormal electrical connections, improving process efficiency, and improving the yield and quality of the display panel 100.

[0065] In some embodiments, the line width of the connecting segment 410 near the corresponding blank segment 420 is smaller than the line width of the connecting segment 410 away from the corresponding blank segment 420.

[0066] The closer the connecting segment 410 is to the blank segment 420, the closer it is to the first opening 140 during the manufacturing process, and the closer it is to the etching solution, the narrower the line width of the connecting segment 410, the higher the efficiency of lateral etching, and the easier it is to etch through, thereby avoiding abnormal electrical connections, improving process efficiency, and improving the yield and quality of the display panel 100.

[0067] In some embodiments, the linewidth of the test connection line 400 depends on the amount of etching of the metal layer. While ensuring that it is less than the amount of side etching, it must also meet the exposure value requirements of the equipment for manufacturing the test connection line 400.

[0068] This side-etching process design achieves broken line etching without the need to develop new etching solutions, new processes, increase over-etching, or add compensation values. It simply sets the metal at the break location to a narrow line width, without affecting the in-plane metal trace design. During OST testing, although the width of this part of the metal is narrow, it can still conduct voltage and current. Moreover, OST testing mostly uses non-contact or contact detection, and the test voltage is usually not very high. Therefore, this design can perform OST testing very efficiently and meet the detection rate requirements.

[0069] In some embodiments, please refer to Figure 2 The display panel 100 further includes a first interlayer insulating layer 101 located on the surface of the first metal layer 120 away from the substrate 110, an active layer 102 located on the first interlayer insulating layer 101, a gate insulating layer 103 located on the active layer 102, a gate layer 104 located on the gate insulating layer 103, a second interlayer insulating layer 105 located on the gate layer 104, and a second metal layer 106 located on the gate insulating layer 103.

[0070] In some embodiments, the gate layer 104 includes a plurality of gates, and the first metal layer 120 further includes a light-shielding portion corresponding to the gate.

[0071] In some embodiments, the first insulating layer 130 may include a first interlayer insulating layer 101, the gate insulating layer 103, and a second interlayer insulating layer 105, and the first opening 140 penetrates the first interlayer insulating layer 101, the gate insulating layer 103, and the second interlayer insulating layer 105.

[0072] In some embodiments, the display panel 100 may be a liquid crystal display panel 100 or a self-emissive display panel 100.

[0073] In some embodiments, the display panel 100 may be a liquid crystal display panel 100, and the display panel 100 may further include a liquid crystal layer, a color filter layer, and upper and lower polarizing layers.

[0074] In some embodiments, the display panel 100 is a self-emissive display panel 100. The display panel 100 further includes a light-emitting device layer.

[0075] In some embodiments, the light-emitting device layer may include OLED (Organic Light-Emitting Diode) material, or Micro LED or Mini LED, without specific limitations.

[0076] In some embodiments, the light-emitting device layer may include OLED (Organic Light-Emitting Diode) material, the light-emitting device layer includes an anode layer on the planarization layer 107, a light-emitting material layer on the anode layer, and a cathode layer on the light-emitting material layer, the display panel 100 further includes a pixel definition layer disposed on the same layer as the light-emitting material layer, a polarizing layer on the light-emitting device layer, and a flexible cover plate on the polarizing layer, and the display panel 100 further includes a corresponding adhesive layer between the polarizing layer and the flexible cover plate.

[0077] This application narrows the linewidth of the test connection lines, which are at least located between the data traces and the voltage bus, so that the linewidth of the test connection lines is smaller than that of the data traces and the voltage bus. After OST detection, this facilitates the etching of test connection lines that do not need to be connected to the data traces and the voltage bus. The narrowed test connection lines not only facilitate the vertical etching of the etching solution but also the lateral etching of the etching solution. Under the combined effect of vertical and lateral etching, the narrowed test connection lines are more likely to form broken blank segments, avoiding abnormal electrical connections, improving process efficiency, and improving the yield and quality of the display panel.

[0078] Please see Figure 3 This application embodiment also provides a method for manufacturing a display panel 100, including:

[0079] S100, providing a substrate 110;

[0080] S200: A voltage bus 300 extending in a first direction, a data trace 200 extending in a second direction, and a test connection line 400 connecting the data trace 200 and the voltage bus 300 are formed on the substrate 110 to form a first metal layer 120. The line width of the test connection line 400 is smaller than the line width of the data trace 200 and the line width of the test connection line 400 is smaller than the line width of the voltage bus 300.

[0081] S300, A first insulating layer 130 is formed on the side of the first metal layer 120 away from the substrate 110;

[0082] S400, Perform open / short circuit tests on each wiring route;

[0083] S500, A plurality of first openings 140 are formed on the first insulating layer 130, the first openings 140 exposing the test connection wire 400.

[0084] S600, the test connection line 400 is etched using the first opening 140, so that the test connection line 400 exposed by the first opening 140 forms a blank segment 420, and the test connection line 400 not exposed by the first opening 140 forms a connection segment 410.

[0085] This application narrows the linewidth of the test connection lines, which are at least located between the data traces and the voltage bus, so that the linewidth of the test connection lines is smaller than that of the data traces and the voltage bus. After OST detection, this facilitates the etching of test connection lines that do not need to be connected to the data traces and the voltage bus. The narrowed test connection lines not only facilitate the vertical etching of the etching solution but also the lateral etching of the etching solution. Under the combined effect of vertical and lateral etching, the narrowed test connection lines are more likely to form broken blank segments, avoiding abnormal electrical connections, improving process efficiency, and improving the yield and quality of the display panel.

[0086] In this embodiment, the method for manufacturing the display panel 100 includes:

[0087] S100, a substrate 110 is provided, please refer to Figure 4B .

[0088] In some embodiments, the material of the substrate 110 may be a rigid material, such as glass, or a flexible material, such as polyimide, without specific limitation.

[0089] S200: A voltage bus 300 extending in a first direction, a data trace 200 extending in a second direction, and a test connection line 400 connecting the data trace 200 and the voltage bus 300 are formed on the substrate 110 to form a first metal layer 120. The linewidth of the test connection line 400 is smaller than the linewidth of the data trace 200, and the linewidth of the test connection line 400 is smaller than the linewidth of the voltage bus 300. Please refer to [link / reference]. Figure 4A .

[0090] In some embodiments, the voltage bus 300 may be disposed on the same layer as the first metal layer 120, the voltage bus 300 may be directly connected to the voltage trace 500, or / and disposed on the same layer as the second metal layer 106, the voltage bus 300 and the voltage trace 500 may be connected through vias, and may be set according to specific process routes and test routes, without specific limitations here.

[0091] In some embodiments, please refer to Figure 1The first metal layer 120 further includes a voltage trace 500 and a sensing line 600 extending along a second direction. The voltage trace 500 is electrically connected to the corresponding voltage bus 300. In the second direction, one voltage trace 500 and one data trace 200 form a group, two other data traces 200 form a group, and one voltage trace 500 and one sensing line 600 form a group, which are arranged alternately.

[0092] In some embodiments, please refer to Figure 1 The test connection line 400 is also disposed between the sensing line 600 and the voltage bus 300; wherein the line width of the test connection line 400 is smaller than the line width of the sensing line 600.

[0093] S300, A first insulating layer 130 is formed on the side of the first metal layer 120 away from the substrate 110. Please refer to [link / reference]. Figure 4B .

[0094] In some embodiments, please refer to Figure 2 The display panel 100 further includes a first interlayer insulating layer 101 located on the surface of the first metal layer 120 away from the substrate 110, an active layer 102 located on the first interlayer insulating layer 101, a gate insulating layer 103 located on the active layer 102, a gate layer 104 located on the gate insulating layer 103, a second interlayer insulating layer 105 located on the gate layer 104, and a second metal layer 106 located on the gate insulating layer 103.

[0095] In some embodiments, the gate layer 104 includes a plurality of gates, and the first metal layer 120 further includes a light-shielding portion corresponding to the gate.

[0096] In some embodiments, please refer to Figure 2 The first insulating layer 130 may include a first interlayer insulating layer 101, the gate insulating layer 103, and a second interlayer insulating layer 105, and the first opening 140 penetrates the first interlayer insulating layer 101, the gate insulating layer 103, and the second interlayer insulating layer 105.

[0097] S400, Perform open and short circuit tests on each wiring route.

[0098] In some embodiments, please refer to Figure 1The first metal layer 120 further includes a voltage trace 500 and a sensing line 600 extending along a second direction. The voltage trace 500 is electrically connected to the corresponding voltage bus 300. In the second direction, one voltage trace 500 and one data trace 200 form a group, two other data traces 200 form a group, and one voltage trace 500 and one sensing line 600 form a group, which are arranged alternately.

[0099] For example, please see Figure 1 The display panel 100 includes a plurality of sub-pixels 700 arranged in an array. The sub-pixels 700 are any one of red sub-pixels 700, green sub-pixels 700, and blue sub-pixels 700. The light emission color of each column of sub-pixels 700 is the same. The data traces 200 are any one of red data traces R, green data traces G, and blue data traces B. The column direction is the first direction. The first voltage trace 510 and the red data trace R form a first group, the green data trace G and the blue data trace B form a second group, and the second voltage trace 520 and a sensing line 600 form a third group. In the second direction, the first group, the second group, and the third group are arranged alternately. The first group, the second group, and the third group are all disposed between two adjacent columns of sub-pixels 700.

[0100] In some embodiments, please refer to Figure 1 The voltage bus 300 includes a first voltage bus and a second voltage bus 320. The first voltage bus can be a VDD bus, and the second voltage bus 320 can be a VSS bus. The voltage trace 500 includes a first voltage trace 510 and a second voltage trace 520. The first voltage trace 510 can be a VDD trace, and the second voltage trace 520 can be a VSS trace.

[0101] The first, second, and third groups can form a 2 / 2 / 2 wiring arrangement. The two wires in each group are close together, which can easily cause short circuits.

[0102] In OST testing, for example, please refer to Figure 1 Connect the red data trace R, the blue data trace B, and the second voltage trace 520 to each other. Connect the red data trace R to the second voltage bus 320 through the test connection line 400. Connect the blue data trace B to the second voltage bus 320 through the test connection line 400. Connect the second voltage trace 520 to the second voltage bus 320. Disconnect the first voltage trace 510, the green data trace G, and the sensing line 600 from each other.

[0103] Alternatively, in OST testing, for example, the first voltage trace 510, the green data trace G, and the sensing line 600 are interconnected, with the green data trace G connected to the first voltage bus via the test connection line 400, the sensing line 600 connected to the first voltage bus via the test connection line 400, and the first voltage trace 510 connected to the first voltage bus; the red data trace R, the blue data trace B, and the second voltage trace 520 are disconnected from each other.

[0104] The voltage drop across three interconnected traces is low, resulting in a low potential. Under normal circumstances, the voltage drop across three disconnected traces is high, resulting in a high potential. The three disconnected traces can be measured separately. If there is a residual short circuit between two closely spaced traces in a certain group, the electrical signal of the floating trace will be pulled low by the electrical signal of the short-circuited trace, thus detecting the defect.

[0105] S500, A plurality of first openings 140 are formed on the first insulating layer 130, the first openings 140 exposing the test connection wire 400. Please refer to [link / reference]. Figure 4B .

[0106] In some embodiments, please refer to Figure 2 The first insulating layer 130 may include the inter-insulating layer 101 and the gate insulating layer 103, and the first opening 140 penetrates the inter-insulating layer 101 and the gate insulating layer 103.

[0107] In some embodiments, please refer to Figure 1 The width of the first opening 140 in the direction perpendicular to the extension of the corresponding connecting segment 410 is greater than the width of the connecting segment 410 in the direction perpendicular to the extension of the corresponding connecting segment 410.

[0108] The width of the first opening 140 in the direction perpendicular to the extension of the corresponding connecting segment 410 is greater than the line width of the connecting segment 410. The first opening 140 is used to drop etchant to etch the test connecting line 400. The slightly wider first opening 140 can provide etchant to increase the lateral etching efficiency of the test connecting line 400. The narrowed test connecting line 400 is not only beneficial to the longitudinal etching of the etchant, but also to the lateral etching of the etchant. Under the combined effect of longitudinal etching and lateral etching, the narrowed test connecting line 400 is more likely to form a broken blank segment 420, avoiding abnormal electrical connection.

[0109] In some embodiments, the ratio of the width of the first opening 140 in the direction perpendicular to the extension of the corresponding connecting segment 410 to the width of the connecting segment 410 in the direction perpendicular to the extension of the corresponding connecting segment 410 is 2.5 to 7.

[0110] S600: The test connection line 400 is etched using the first opening 140, so that the test connection line 400 exposed by the first opening 140 forms a blank segment 420, and the test connection line 400 not exposed by the first opening 140 forms a connection segment 410. Please refer to [link / reference]. Figure 4C , Figure 4D , Figure 4E .

[0111] In some embodiments, please refer to Figure 1 The first opening 140 is disposed between two adjacent longitudinally extending connecting segments 410.

[0112] The first opening 140 corresponds to the blank segment 420, that is, the etching position is generated in the longitudinal extension of the test connection line 400. Since the lateral extension of the test connection line 400 is close to the data trace 200, it is easy to cause abnormal etching of the data trace 200. Therefore, this position is selected for etching to avoid abnormal etching of the data trace 200 and ensure the normal electrical connection of the line.

[0113] In some embodiments, please refer to Figure 4A The line width of the test connection line 400 exposed by the first opening 140 is smaller than the line width of the test connection line 400 not exposed by the first opening 140.

[0114] During the manufacturing process, the test connection line 400 exposed by the first opening 140 is the part that needs to be etched away. The smaller the line width of the test connection line 400 exposed by the first opening 140, the higher the efficiency of lateral etching and the easier it is to etch it off, thereby avoiding abnormal electrical connections, improving process efficiency, and improving the yield quality of the display panel 100.

[0115] In some embodiments, the line width of the connecting segment 410 near the corresponding blank segment 420 is smaller than the line width of the connecting segment 410 away from the corresponding blank segment 420.

[0116] The closer the connecting segment 410 is to the blank segment 420, the closer it is to the first opening 140 during the manufacturing process, and the closer it is to the etching solution, the narrower the line width of the connecting segment 410, the higher the efficiency of lateral etching, and the easier it is to etch through, thereby avoiding abnormal electrical connections, improving process efficiency, and improving the yield and quality of the display panel 100.

[0117] This application narrows the linewidth of the test connection lines, which are at least located between the data traces and the voltage bus, so that the linewidth of the test connection lines is smaller than that of the data traces and the voltage bus. After OST detection, this facilitates the etching of test connection lines that do not need to be connected to the data traces and the voltage bus. The narrowed test connection lines not only facilitate the vertical etching of the etching solution but also the lateral etching of the etching solution. Under the combined effect of vertical and lateral etching, the narrowed test connection lines are more likely to form broken blank segments, avoiding abnormal electrical connections, improving process efficiency, and improving the yield and quality of the display panel.

[0118] Please see Figure 5 The present invention also provides a display device 10, including a display panel 100 as described above and a device body 20, wherein the device body 20 and the display panel 100 are combined into one unit.

[0119] For the specific structure of the display panel 100, please refer to any of the above-described embodiments of the display panel 100 and the accompanying drawings, which will not be repeated here.

[0120] In this embodiment, the main body 20 of the device may include a middle frame, frame adhesive, etc., and the display device 10 may be a display terminal such as a mobile phone, tablet, or television, which is not limited here.

[0121] This application discloses a display panel and its manufacturing method and display device. The display panel includes data traces, a voltage bus, and at least one test connection line disposed between the data traces and the voltage bus. The line width of the test connection line is smaller than the line width of the data traces and smaller than the line width of the voltage bus. The test connection line includes at least two connection segments and at least one blank segment. By narrowing the line width of the test connection line disposed between the data traces and the voltage bus, this application facilitates the etching of test connection lines that do not need to be connected to the data traces and the voltage bus after OST detection. The narrowed test connection line is not only beneficial for the vertical etching of the etching solution, but also for the lateral etching of the etching solution. Under the combined effect of vertical etching and lateral etching, the narrowed test connection line is more likely to form a broken blank segment, avoiding abnormal electrical connections, improving process efficiency, and improving the yield and quality of the display panel.

[0122] The above provides a detailed description of a display panel, its manufacturing method, and the display device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, characterized in that, include: Substrate; A voltage bus extends along the first direction; The data trace extends along the second direction; Test connection lines are provided at least between the data traces and the voltage bus, and each of the data traces and the test connection lines is located in the first metal layer; A first insulating layer is located on the side of the first metal layer away from the substrate; Wherein, the first direction and the second direction form an angle, the line width of the test connection line is smaller than the line width of the data trace, the line width of the test connection line is smaller than the line width of the voltage bus, the test connection line includes at least two connection segments and at least one blank segment, the connection segment is broken at the blank segment, the first insulating layer includes a plurality of first openings, the first openings correspond to the blank segments, and the width of the first openings in the direction perpendicular to the extension of the corresponding connection segment is greater than the width of the connection segment in the direction perpendicular to the extension of the corresponding connection segment.

2. The display panel according to claim 1, characterized in that, The first opening is disposed between two adjacent longitudinally extending connecting segments.

3. The display panel according to claim 1, characterized in that, The ratio of the width of the first opening in the direction perpendicular to the extension of the corresponding connecting segment to the width of the connecting segment in the direction perpendicular to the extension of the corresponding connecting segment is 2.5 to 7.

4. The display panel according to claim 1, characterized in that, The first metal layer further includes voltage traces and sensing lines extending along the second direction, wherein the voltage traces are electrically connected to the corresponding voltage bus; In the second direction, a voltage trace and a data trace form a group, two data traces form a group, and a voltage trace and a sensing line form a group, which are arranged alternately.

5. The display panel according to claim 4, characterized in that, The test connection line is also disposed between the sensing line and the voltage bus; The line width of the test connection line is smaller than the line width of the sensing line.

6. A method for manufacturing a display panel, characterized in that, include: Provide a substrate; A voltage bus extending in a first direction, a data trace extending in a second direction, and a test connection line connecting the data trace and the voltage bus are formed on the substrate to form a first metal layer. The line width of the test connection line is smaller than the line width of the data trace, and the line width of the test connection line is smaller than the line width of the voltage bus. A first insulating layer is formed on the side of the first metal layer away from the substrate; Perform open / short circuit tests on each wiring route; A plurality of first openings are formed on the first insulating layer, the first openings exposing the test connection wires, and the width of the first openings in the direction perpendicular to the extension of the corresponding connection segment is greater than the width of the connection segment in the direction perpendicular to the extension of the corresponding connection segment. The test connection line is etched using the first opening, so that the test connection line exposed by the first opening forms a blank segment, and the test connection line not exposed by the first opening forms a connection segment, and the connection segment is broken at the blank segment.

7. A display device, characterized in that, The device includes a display panel and a device body as described in any one of claims 1 to 5, wherein the device body and the display panel are integrated as one unit.

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