Display substrate and display device

Abstract

A display substrate and a display device. The display substrate includes a base substrate, a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer stacked in sequence. The first insulating layer includes a first recessed structure, the first conductive layer includes a first conductive structure, and the first conductive structure includes a bottom surface proximal to the base substrate, a top surface distal to the base substrate, and a first side surface located between the bottom and top surfaces. The second insulating layer includes a first via, and the second conductive layer includes a second conductive structure. The orthographic projection of the first via on the base substrate at least partially overlaps with the orthographic projection of the first recessed structure on the base substrate. The first via exposes at least a portion of the first side surface of the first conductive structure, and the second conductive structure contacts at least a portion of the first side surface of the first conductive structure. This display substrate can effectively improve display performance.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) displays have many advantages, such as active light emission, high contrast, fast response time, and thinness, making them one of the main next-generation displays. With the rapid development of high-resolution products, higher requirements are being placed on the structural design of the display substrate, such as the arrangement of pixels and signal lines. Summary of the Invention

[0003] This disclosure provides at least one embodiment of a display substrate, including a substrate and a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer sequentially disposed on the substrate. The first insulating layer includes a first recessed structure, and the first conductive layer includes a first conductive structure, the first conductive structure including a bottom surface near the substrate, a top surface away from the substrate, and a first side surface located between the bottom surface and the top surface. The second insulating layer includes a first via, and the second conductive layer includes a second conductive structure. The second conductive structure contacts the first conductive structure through the first via, and the orthographic projection of the first via on the substrate at least partially overlaps with the orthographic projection of the first recessed structure on the substrate. The first via exposes at least a portion of the first side surface of the first conductive structure, and the second conductive structure contacts the at least a portion of the first side surface of the first conductive structure.

[0004] In some examples, the first insulating layer includes a first recessed structure; the second conductive structure includes a first protrusion, the orthographic projection of the first protrusion on the substrate being located within the orthographic projection of the first recessed structure on the substrate; the first protrusion is in contact with at least a portion of a first side surface of the first conductive structure.

[0005] In some examples, the first side surface of the first conductive structure includes a protruding curved surface, and the second conductive structure covers at least a portion of the protruding curved surface.

[0006] In some examples, the orthographic projection of the first recessed structure on the substrate at least partially overlaps with the orthographic projection of the first via on the substrate.

[0007] In some examples, the first conductive structure further includes a second side surface located between the bottom surface and the top surface, the first side surface being opposite to the second side surface, and the dimension of the first side surface in a direction perpendicular to the substrate being greater than the dimension of the second side surface in a direction perpendicular to the substrate.

[0008] In some examples, the first side surface includes a first side surface portion located on the side of the first insulating layer away from the substrate; the portion of the first side surface portion not covered by the second conductive structure has a dimension in a direction perpendicular to the substrate that is larger than the dimension of the second side surface in a direction perpendicular to the substrate.

[0009] In some examples, at least a portion of the top surface of the first conductive structure, which is directly connected to the first side surface, is separated from the second conductive layer.

[0010] In some examples, the display substrate has a first cross-section, the first recessed structure having a dimension of b within the first cross-section and along a reference direction, the reference direction being parallel to the surface of the substrate; within the first cross-section, the overlapping area of ​​the first via and the first recessed structure having a dimension of c along the reference direction, the portion of the first side surface of the first conductive structure covered by the second conductive structure having a dimension of d in a direction perpendicular to the substrate; the first conductive structure includes a contact portion located on the side of the first insulating layer away from the substrate and in contact with the second conductive structure having a dimension of e in a direction perpendicular to the substrate; c / b is greater than 0.1; d / e is greater than 0.3.

[0011] In some examples, c / b is greater than 0.15 and d / e is less than 0.8.

[0012] In some examples, c / b is less than 0.19 and d / e is less than 0.5.

[0013] In some examples, within the first cross section, the maximum depth of the first recessed structure is i, the angle between one side of the first recessed structure within the first cross section and the surface of the substrate is j, and the thickness of the portion of the second conductive structure in contact with the first conductive structure in the direction perpendicular to the substrate is k; d / e < 0.0273*i*sin(j) / k.

[0014] In some examples, c / b < 0.0102*i*sin(j) / k.

[0015] In some examples, the first side surface has a dimension of n in the direction perpendicular to the substrate, and the second side surface has a dimension of e in the direction perpendicular to the substrate, 0.1*(n / e) / sin(j)>(d / n).

[0016] In some examples, 0.08*(n / e) / sin(j)>d / n.

[0017] In some examples, the contact portion includes a second protrusion facing the first recessed structure, the orthographic projection of the second protrusion on the substrate being within the orthographic projection of the first recessed structure on the substrate; within the first cross-section, the dimension of the second protrusion in a direction perpendicular to the substrate is greater than the dimension of the portion of the first conductive layer located on the side surface of the first recessed structure in a direction perpendicular to the side surface of the first recessed structure.

[0018] In some examples, the first insulating layer further includes a second recessed structure spaced apart from the first recessed structure, and the first conductive structure further includes a second side surface located between the bottom surface and the top surface, the first side surface being opposite to the second side surface, the orthographic projection of the second side surface on the substrate at least partially overlapping the orthographic projection of the second recessed structure on the substrate; the first via also exposes at least a portion of the second side surface, and the second conductive structure covers at least a portion of the second side surface of the first conductive structure.

[0019] In some examples, in a direction perpendicular to the substrate, the size of the portion of the first side surface of the first conductive structure covered by the second conductive structure is different from the size of the portion of the second side surface covered by the second conductive structure.

[0020] In some examples, the overlap size between the orthographic projection of the first via on the substrate and the orthographic projection of the first recessed structure on the substrate is different from the overlap size between the orthographic projection of the first via on the substrate and the orthographic projection of the second recessed structure on the substrate.

[0021] At least one embodiment of this disclosure also provides a display substrate, comprising: a substrate, a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer sequentially disposed on the substrate, and a plurality of sub-pixels, the plurality of sub-pixels being located on the substrate and arranged in a plurality of pixel rows and a plurality of pixel columns along a first direction and a second direction, the first direction being different from the second direction. The first conductive layer includes a first conductive structure, a first signal line, and a second signal line spaced apart from each other, the first signal line and the second signal line extending along the second direction; the second conductive layer includes a second conductive structure; the first conductive structure includes a bottom surface near the substrate, a top surface away from the substrate, and a first side surface located between the bottom surface and the top surface; the second insulating layer includes a first via, the second conductive structure contacting the first conductive structure through the first via; the second conductive structure includes a first protrusion, the first via exposing at least a portion of the first side surface of the first conductive structure, the first protrusion contacting the at least a portion of the first side surface of the first conductive structure; the orthographic projection of the first protrusion on the substrate is located between the orthographic projection of the first signal line on the substrate and the orthographic projection of the second signal line on the substrate.

[0022] In some examples, the first conductive structure includes a second protrusion facing the first recessed structure, the orthographic projection of the second protrusion on the substrate being within the orthographic projection of the first recessed structure on the substrate.

[0023] In some examples, the distance between the orthographic projection of the first protrusion on the substrate and the orthographic projection of the first signal line on the substrate in the first direction is l, the distance between the orthographic projection of the second signal line on the substrate and the orthographic projection of the first signal line on the substrate in the first direction is m, the display substrate includes a first cross section perpendicular to the substrate, in the first cross section, the portion of the first conductive structure located on the side of the first insulating layer away from the substrate has a dimension e in the direction perpendicular to the substrate, the portion of the first side surface covered by the first protrusion has a dimension d in the direction perpendicular to the substrate, l / m>0.9(d / e).

[0024] In some examples, l / m > 1.2 * (d / e).

[0025] In some examples, the second insulating layer includes a plurality of vias arranged in a plurality of via rows and a plurality of via columns along the first and second directions, the plurality of vias including a plurality of first vias; the plurality of via rows including a first via row, in which every other via has three consecutive first vias.

[0026] In some examples, the plurality of via columns includes a first via column, in which each via is the first via, or there is a first via every other via.

[0027] In some examples, the plurality of pixel columns include a first pixel column and a second pixel column that are adjacent in the first direction, the first signal line is connected to a sub-pixel of the first pixel column to provide a first signal, the second signal line is connected to a sub-pixel of the second pixel column to provide a second signal, and the orthographic projection of the electrode of the light-emitting element of the first pixel column on the substrate side near the substrate overlaps at least partially with the orthographic projection of the first signal line on the substrate and the orthographic projection of the second signal line on the substrate.

[0028] In some examples, the second conductive structure is configured as the first electrode of the light-emitting element; the display substrate further includes a pixel defining layer located on the side of the second conductive layer away from the substrate, the pixel defining layer including a plurality of pixel opening regions, the plurality of pixel opening regions corresponding one-to-one with the plurality of sub-pixels, and the orthographic projection of the plurality of pixel opening regions on the substrate being separate from the orthographic projection of the first protrusion on the substrate.

[0029] In some examples, the pixel defining layer has a non-uniform thickness, and the orthographic projection of the first via on the substrate is separated from the orthographic projection of the portion of the pixel defining layer with the maximum thickness on the substrate.

[0030] In some examples, the pixel defining layer includes a plurality of protrusions located between the plurality of pixel opening regions; the plurality of protrusions include a first protrusion, a second protrusion, and a third protrusion disposed around the same pixel opening region, and the line connecting the centers of the orthographic projections of the first protrusion, the second protrusion, and the third protrusion on the substrate forms a triangle.

[0031] In some examples, the first protrusion is located between four adjacent pixel opening regions, and the second and third protrusions are located between two adjacent pixel opening regions respectively; the area of ​​the orthographic projection of the first protrusion on the substrate is greater than the area of ​​the orthographic projection of the second protrusion on the substrate and the area of ​​the orthographic projection of the third protrusion on the substrate.

[0032] In some examples, the display substrate further includes a third conductive layer located on the side of the first conductive layer near the substrate. The third conductive layer includes a shielding electrode and a first capacitor electrode. The shielding electrode is T-shaped and includes a first blocking portion extending along the first direction and a second blocking portion extending along the second direction. The first blocking portion and the second blocking portion are connected at the middle position of the second blocking portion in the second direction. The second blocking portion is connected to the first capacitor electrode.

[0033] In some examples, the first conductive layer includes a first reset voltage line extending along the second direction, and the third conductive layer includes a second reset voltage line extending along the first direction, the first reset voltage line being electrically connected to the second reset voltage line; the display substrate further includes a semiconductor layer located on the side of the third conductive layer closer to the substrate, the semiconductor layer including a connection portion; the connection portion electrically connects the first reset voltage line to the first electrode of a reset transistor in a sub-pixel; the orthographic projection of the connection portion on the substrate overlaps with the orthographic projection of the first reset voltage line on the substrate and the orthographic projection of the first electrode of the reset transistor on the substrate.

[0034] In some examples, the plurality of pixel columns includes a third pixel column, the third pixel column includes another first conductive structure, the first conductive layer further includes a third signal line and a fourth signal line extending along the second direction, the third signal line and the fourth signal line being electrically connected to each other; the display substrate further includes a semiconductor layer located on the side of the first conductive layer near the substrate, the other first conductive structure being electrically connected to the semiconductor layer, and the orthographic projection of the other first conductive structure on the substrate being separate from the orthographic projection of the second conductive layer on the substrate.

[0035] At least one embodiment of this disclosure also provides a display substrate, comprising: a substrate, a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer sequentially disposed on the substrate, and a pixel electrode located on the side of the second conductive layer away from the substrate, the pixel electrode being configured as a first electrode of a light-emitting element; the first insulating layer includes a first recessed structure, the first conductive layer includes a first conductive structure, the second conductive layer includes a second conductive structure, and the pixel electrode is electrically connected to the second conductive structure; the first conductive structure includes a bottom surface near the substrate, a top surface away from the substrate, and a first side surface located between the bottom surface and the top surface; the second insulating layer includes a first via, the second conductive structure contacts the first conductive structure through the first via, the orthographic projection of the first via on the substrate at least partially overlaps with the orthographic projection of the first recessed structure on the substrate; the second conductive structure includes a first protrusion, the first via exposing at least a portion of the first side surface of the first conductive structure, and the first protrusion contacting the at least a portion of the first side surface of the first conductive structure.

[0036] In some examples, the display substrate has a first cross-section, the first recessed structure having a dimension of b within the first cross-section and along the reference direction, the reference direction being parallel to the surface of the substrate; within the first cross-section, the overlapping area of ​​the first via and the first recessed structure having a dimension of c along the reference direction, the portion of the first side surface of the first conductive structure covered by the second conductive structure having a dimension of d in a direction perpendicular to the substrate, and the portion of the first conductive layer located on the side of the first insulating layer away from the substrate having a dimension of e in a direction perpendicular to the substrate; c / b is greater than 0.1; d / e is greater than 0.3.

[0037] In some examples, within the first cross section, the maximum depth of the first recessed structure is i, the angle between one side of the first recessed structure within the first cross section and the surface of the substrate is j, and the dimension of the portion of the second conductive structure located on the side of the first conductive structure away from the substrate and in contact with the first conductive structure in the direction perpendicular to the substrate is k; d / e>2.1*i*sin(j) / k.

[0038] In some examples, d / e > 2.5*i*sin(j) / k.

[0039] In some examples, c / b is greater than 0.28.

[0040] In some examples, the first side surface has a dimension n in the direction perpendicular to the substrate, and d / n is greater than 0.6.

[0041] In some examples, the average thickness of the first protrusion is less than the average thickness of the portion of the second conductive structure that contacts the top surface of the first conductive structure.

[0042] In some examples, the display substrate further includes a plurality of sub-pixels located on the substrate and arranged in a plurality of pixel rows and a plurality of pixel columns along a first direction and a second direction, wherein the first direction is different from the second direction; the first conductive layer further includes a plurality of connection electrodes, which are connected one-to-one with the plurality of sub-pixels to provide a power supply voltage; the plurality of sub-pixels includes a first sub-pixel, and the display substrate further includes a reset voltage line extending along the second direction, which is connected to the first sub-pixel to provide a reset voltage; the orthographic projection of the first protrusion on the substrate is located between the orthographic projection of the connection electrode corresponding to the first sub-pixel on the substrate and the orthographic projection of the reset voltage line on the substrate.

[0043] In some examples, along the first direction, the distance between the first protrusion and the reset voltage line is less than the distance between the first protrusion and the connecting electrode.

[0044] In some examples, the connecting electrode includes a main body and an extension extending along the first direction, the extension being smaller in the second direction than the main body in the second direction; in the second direction, the first conductive structure at least partially overlaps with the extension of the connecting electrode.

[0045] In some examples, the second conductive layer includes a plurality of power electrodes that are connected one-to-one with the plurality of connection electrodes to provide the power voltage. The power electrodes corresponding to each pixel column are connected to each other in a single structure, thereby forming a plurality of power lines extending along the second direction.

[0046] In some examples, the second conductive layer further includes multiple data lines extending along the second direction, each of which is connected to one of the multiple pixel columns to provide data signals; the multiple data lines are divided into multiple data line groups, each data line group including two data lines; a data line group is provided between every two adjacent pixel columns, and two power lines are spaced between adjacent data line groups.

[0047] In some examples, the display substrate further includes a plurality of reset voltage lines extending along the second direction, the plurality of reset voltage lines including a first reset voltage line and a second reset voltage line alternately arranged in the first direction, the first reset voltage line and the second reset voltage line being configured to provide a first reset voltage and a second reset voltage, respectively; two pixel columns are spaced between adjacent first reset voltage lines and second reset lines.

[0048] In some examples, the plurality of reset voltage lines are located in the first conductive layer, and a first reset voltage line or a second reset voltage line is provided between two power lines between adjacent data line groups; the orthographic projection of any one of the plurality of reset voltage lines on the substrate is separate from the orthographic projection of any one of the plurality of power lines on the substrate.

[0049] In some examples, the multiple reset voltage lines are located in the second conductive layer and are configured to correspond one-to-one with multiple data line groups, with each reset voltage line located between two data lines in the corresponding data line group.

[0050] In some examples, the two power lines between adjacent data line groups are connected to each other as a single structure, such that two adjacent power electrodes in the first direction of the two power lines are connected to each other as a single power electrode group; the display substrate includes a plurality of second conductive structures, which are arranged one-to-one with the plurality of power electrodes; the power electrode group includes a cutout area, which is provided with two second conductive structures.

[0051] In some examples, the second conductive layer further includes a connecting line extending along the second direction to separate the cutout area into two cutout sub-areas; the two second conductive structures are respectively disposed in the two cutout sub-areas and located on both sides of the connecting line.

[0052] In some examples, the display substrate further includes a third conductive layer located on the side of the first conductive layer near the substrate, a fourth conductive layer located between the third conductive layer and the first conductive layer, and a semiconductor layer located between the third conductive layer and the fourth conductive layer; the sub-pixel includes a reset transistor configured to reset a first electrode of the light-emitting element, the reset transistor including an active layer located in the semiconductor layer; the display substrate includes a first reset control line located on the third conductive layer and a second reset control line located on the fourth conductive layer, the first reset control line and the second reset control line respectively configured to perform gate voltage control on the reset transistor, and the orthogonal projections of the first reset control line and the second reset control line on the substrate at least partially overlap.

[0053] At least one embodiment of this disclosure also provides a touch display panel, including a display substrate provided in any of the above embodiments, and a touch structure stacked on the display substrate. The second conductive structure includes a first protrusion, which contacts at least a portion of a first side surface of the first conductive structure; the touch structure includes a touch electrode. In a direction perpendicular to the substrate, the orthographic projection of the touch electrode on the substrate is separate from the orthographic projection of the first protrusion on the substrate.

[0054] At least one embodiment of this disclosure also provides a display device, including the display substrate or touch display panel provided in any of the above embodiments. Attached Figure Description

[0055] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0056] Figure 1 This is a schematic diagram of a display substrate;

[0057] Figure 2 One of the schematic diagrams of a display substrate provided in at least one embodiment of this disclosure;

[0058] Figure 3 A second schematic diagram of a display substrate provided in at least one embodiment of this disclosure;

[0059] Figure 4 A third schematic diagram of a display substrate provided for at least one embodiment of this disclosure;

[0060] Figure 5A A schematic diagram of a pixel circuit provided in at least one embodiment of this disclosure;

[0061] Figure 5B for Figure 5A The circuit diagram shows a specific implementation example of the pixel circuit shown.

[0062] Figure 5C A timing signal diagram of a pixel circuit provided in at least one embodiment of this disclosure;

[0063] Figure 6A Fourth schematic diagram of a display substrate provided for at least one embodiment of this disclosure;

[0064] Figure 6B for Figure 6A A sectional view along section line A-A';

[0065] Figure 7 Fifth schematic diagram of a display substrate provided for at least one embodiment of this disclosure;

[0066] Figure 8A Sixth schematic diagram of a display substrate provided for at least one embodiment of this disclosure;

[0067] Figure 8B Seventh schematic diagram of a display substrate provided for at least one embodiment of this disclosure;

[0068] Figure 8C Eighth schematic diagram of a display substrate provided for at least one embodiment of this disclosure;

[0069] Figure 9A Schematic diagram nine of a display substrate provided for at least one embodiment of this disclosure;

[0070] Figure 9B This is diagram ten of a display substrate provided in at least one embodiment of the present disclosure;

[0071] Figure 9C 11. A schematic diagram of a display substrate provided for at least one embodiment of this disclosure;

[0072] Figure 9D 12 is a schematic diagram of a display substrate provided for at least one embodiment of this disclosure;

[0073] Figure 10A Schematic diagram thirteen of a display substrate provided for at least one embodiment of this disclosure;

[0074] Figure 10B Fourteenth schematic diagram of a display substrate provided for at least one embodiment of this disclosure;

[0075] Figure 10C Fifteenth schematic diagram of a display substrate provided for at least one embodiment of this disclosure;

[0076] Figure 11 Sixteenth schematic diagram of a display substrate provided for at least one embodiment of this disclosure;

[0077] Figure 12A Schematic diagram seventeen of a display substrate provided for at least one embodiment of the present disclosure;

[0078] Figure 12B Eighteen is a schematic diagram of a display substrate provided for at least one embodiment of this disclosure;

[0079] Figure 12C Schematic diagram nineteen of a display substrate provided for at least one embodiment of this disclosure;

[0080] Figure 13A This is 20th of a schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0081] Figure 13B for Figure 13AA sectional view along section line B-B';

[0082] Figure 14 Schematic diagram twenty-one of the display substrates provided in at least one embodiment of this disclosure;

[0083] Figure 15 Schematic diagram twenty-two of a display substrate provided for at least one embodiment of the present disclosure;

[0084] Figure 16A Schematic diagram twenty-three of a display substrate provided for at least one embodiment of the present disclosure;

[0085] Figure 16B Schematic diagram twenty-four of a display substrate provided for at least one embodiment of the present disclosure;

[0086] Figure 16C Schematic diagram twenty-five of a display substrate provided for at least one embodiment of the present disclosure;

[0087] Figure 17A Schematic diagram twenty-six of a display substrate provided for at least one embodiment of the present disclosure;

[0088] Figure 17B Schematic diagram twenty-seven of a display substrate provided for at least one embodiment of the present disclosure;

[0089] Figure 18A Schematic diagram twenty-eight for a display substrate provided in at least one embodiment of the present disclosure;

[0090] Figure 18B Schematic diagram twenty-nine of a display substrate provided for at least one embodiment of the present disclosure;

[0091] Figure 18C Thirty is a schematic diagram of a display substrate provided for at least one embodiment of this disclosure;

[0092] Figure 19A Schematic diagram thirty-one of the display substrates provided in at least one embodiment of this disclosure;

[0093] Figure 19B Schematic diagram thirty-two of a display substrate provided for at least one embodiment of the present disclosure;

[0094] Figure 19C Schematic diagram thirty-three of a display substrate provided for at least one embodiment of the present disclosure;

[0095] Figure 20 A schematic diagram of a display panel provided in at least one embodiment of this disclosure;

[0096] Figure 21 A schematic diagram of a touch display panel provided for at least one embodiment of this disclosure; and

[0097] Figure 22 This is a schematic diagram of a display device provided for at least one embodiment of the present disclosure. Detailed Implementation

[0098] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0099] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0100] Figure 1 This is a schematic diagram of the structure of a display substrate. (Example) Figure 1 As shown, the display substrate includes a first insulating layer 301', a first conductive layer 201', a second insulating layer 302', and a second conductive layer 202' sequentially disposed on a substrate (not shown). A through-hole V1' is formed in the second insulating layer 302', and the second conductive layer 202' is electrically connected to the first conductive layer 201' through the through-hole V1'.

[0101] like Figure 1 As shown, the second conductive layer 202' only overlaps with the upper surface of the first conductive layer 201', resulting in a limited overlap area, high contact resistance, and hindering the rapid transmission of electrical signals.

[0102] This disclosure provides at least one embodiment of a display substrate, including a substrate, a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer sequentially disposed on the substrate. The first insulating layer includes a first recessed structure, and the first conductive layer includes a first conductive structure, the first conductive structure including a bottom surface near the substrate, a top surface away from the substrate, and a first side surface located between the bottom surface and the top surface. The second insulating layer includes a first via, and the second conductive layer includes a second conductive structure. The second conductive structure contacts the first conductive structure through the first via, and the orthographic projection of the first via on the substrate at least partially overlaps with the orthographic projection of the first recessed structure on the substrate. The first via exposes at least a portion of the first side surface of the first conductive structure, and the second conductive structure contacts the at least a portion of the first side surface of the first conductive structure.

[0103] The display substrate provided in at least one embodiment of this disclosure exposes at least a portion of the first side surface of the first conductive structure by providing a first via, so that the second conductive structure contacts not only the upper surface of the first conductive structure but also the first side surface of the first conductive structure. This effectively increases the contact area between the first and second conductive structures, not only reducing contact resistance and improving the transmission efficiency of electrical signals, but also protecting the side surface of the first conductive structure, for example, protecting it from moisture erosion. In addition, this arrangement also increases the cross-sectional area of ​​the second conductive structure in the longitudinal direction (perpendicular to the substrate), which can not only effectively shield the interference of the first conductive structure to other conductive structures in the substrate, but also reduce the mutual interference between signal lines located on both sides of the second conductive structure.

[0104] At least one embodiment of this disclosure also provides a display substrate, including a substrate, a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer sequentially disposed on the substrate. The display substrate further includes a plurality of sub-pixels, which are located on the substrate and arranged in a plurality of pixel rows and a plurality of pixel columns along a first direction and a second direction, wherein the first direction is different from the second direction. The first conductive layer includes a first conductive structure, a first signal line, and a second signal line spaced apart from each other, the first signal line and the second signal line extending along the second direction; the second conductive layer includes a second conductive structure; the first conductive structure includes a bottom surface near the substrate, a top surface away from the substrate, and a first side surface located between the bottom surface and the top surface; the second insulating layer includes a first via, through which the second conductive structure contacts the first conductive structure; the second conductive structure includes a first protrusion, the first via exposing at least a portion of the first side surface of the first conductive structure, the first protrusion contacting the at least a portion of the first side surface of the first conductive structure; the orthographic projection of the first protrusion on the substrate is located between the orthographic projection of the first signal line on the substrate and the orthographic projection of the second signal line on the substrate.

[0105] The display substrate provided in at least one embodiment of this disclosure, by setting the first protrusion of the second conductive structure to contact the first side surface of the first conductive structure, not only increases the contact area between the first conductive structure and the second conductive structure and reduces their contact resistance, but also effectively increases the longitudinal cross-sectional area of ​​the second conductive structure. This can effectively shield the interference of the first conductive structure to other conductive structures in the substrate. At the same time, by setting the first protrusion between the first signal line and the second signal line, the mutual interference between the first signal line and the second signal line can also be reduced.

[0106] At least one embodiment of this disclosure also provides a display substrate, including a substrate, a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer sequentially disposed on the substrate, and a pixel electrode located on the side of the second conductive layer away from the substrate. The pixel electrode is configured as a first electrode of a light-emitting element and is electrically connected to the second conductive structure. The first insulating layer includes a first recessed structure, the first conductive layer includes a first conductive structure, and the second conductive layer includes a second conductive structure. The first conductive structure includes a bottom surface near the substrate, a top surface away from the substrate, and a first side surface located between the bottom surface and the top surface. The second insulating layer includes a first via, and the second conductive structure contacts the first conductive structure through the first via. The orthographic projection of the first via on the substrate at least partially overlaps with the orthographic projection of the first recessed structure on the substrate. The second conductive structure includes a first protrusion, and the first via exposes at least a portion of the first side surface of the first conductive structure. The first protrusion contacts the at least a portion of the first side surface of the first conductive structure.

[0107] The display substrate provided in at least one embodiment of this disclosure effectively increases the contact area between the first and second conductive structures, reduces the contact resistance, and improves the transmission efficiency of electrical signals by setting the first protrusion of the second conductive structure to contact the first side surface of the first conductive structure. In addition, since this setting also increases the cross-sectional area of ​​the second conductive structure in the longitudinal direction (perpendicular to the substrate), it can not only effectively shield the interference of the first conductive structure to other conductive structures in the substrate, but also reduce the mutual interference between signal lines located on both sides of the second conductive structure.

[0108] Figure 2 This is a schematic diagram of a display substrate provided in at least one embodiment of the present disclosure. Figure 2 As shown, the display substrate 20 includes a substrate 100, a first insulating layer 301, a first conductive layer 201, a second insulating layer 302, and a second conductive layer 202 sequentially disposed on the substrate 100. Although Figure 2 The diagram shows the first insulating layer 101 directly located on the substrate 100; however, this is not intended to limit the scope of this disclosure. In other examples, other films, such as other insulating or conductive layers, may be disposed between the first insulating layer 101 and the substrate 100.

[0109] like Figure 2 As shown, the first insulating layer 301 includes a recessed structure G1 (an example of a first recessed structure in this disclosure), which may or may not penetrate the first insulating layer 301. For example, as Figure 2As shown, the recessed structure G1 can be a through hole; in other examples, the recessed structure G1 can also be a groove. This disclosure does not limit the specific structure of the recessed structure G1.

[0110] The first conductive layer 201 includes a first conductive structure 21, which includes a recessed structure G2. For example, as... Figure 2 As shown, the recessed structure G2 is formed by the first conductive structure 21 covering the recessed structure G1, and the first conductive structure 21 fills into the recessed structure G1 to form the recessed structure G2. In the direction perpendicular to the substrate 100, the recessed structure G1 and the recessed structure G2 at least partially overlap.

[0111] The first conductive structure 21 includes a bottom surface 21a near the substrate 100, a top surface 21b away from the substrate 100, and a first side surface 21c located between the bottom surface 21a and the top surface 21b. The first side surface 21c is formed by the downward indentation of the first conductive structure 21. Figure 2 As shown, the first side surface 21c can be a sidewall of the recessed structure G2. The portion of the first side surface 21c that contacts the second conductive structure 22 is located on the side of the upper surface of the first insulating layer 301 away from the substrate. The first side surface 21c and the top surface 21b are located on the same side of the first conductive structure 21 and are directly connected. The first side surface 21c and the bottom surface 21a are located on opposite sides of the first conductive structure 21.

[0112] The second insulating layer 302 includes a via V1 (an example of a first via in this disclosure), and the second conductive layer 202 includes a second conductive structure 22, which contacts the first conductive structure 21 through the via V1. The orthographic projection of the via V1 on the substrate at least partially overlaps with the orthographic projection of the recessed structure G1 on the substrate. The via V1 exposes at least a portion of the first side surface 21c of the first conductive structure 21, and the second conductive structure 22 contacts at least a portion of the first side surface 21c of the first conductive structure 21.

[0113] By exposing at least a portion of the first side surface 21c of the first conductive structure 21 through the via V1, the second conductive structure 22 contacts not only the upper surface 21b of the first conductive structure 21 but also the first side surface 21c of the first conductive structure 21. This effectively increases the contact area between the first conductive structure 21 and the second conductive structure 22, reduces the contact resistance, and improves the transmission efficiency of electrical signals. Furthermore, this arrangement also increases the cross-sectional area of ​​the second conductive structure 22 in the longitudinal direction (perpendicular to the substrate), which can not only effectively shield the interference of the first conductive structure to other conductive structures in the substrate but also reduce the mutual interference between signal lines located on both sides of the second conductive structure.

[0114] For example, such as Figure 2 As shown, the orthographic projection of the recessed structure G1 on the substrate overlaps at least partially with the orthographic projection of the via V1 on the substrate, causing the portion of the second insulating layer 302 that overlaps with the recessed structure G1 to be recessed, exposing the first side surface 21c of the first conductive structure 21. Thus, the second conductive structure 22 not only contacts the top surface 21b of the first conductive structure 21, but also contacts its first side surface 21c.

[0115] like Figure 2 As shown, the second conductive structure 22 includes a protrusion 220 (an example of the first protrusion of this disclosure), which protrudes downward, i.e., toward the substrate 100. The orthographic projection of the protrusion 220 on the substrate 100 lies within the orthographic projection of the recessed structure G1 on the substrate. The protrusion 220 is in at least partial contact with the first side surface 21c of the first conductive structure 21. The protrusion 220 effectively increases the cross-sectional area of ​​the second conductive structure 22 in the longitudinal direction.

[0116] like Figure 2 As shown, the first side surface 21c of the first conductive structure 21 includes a protruding curved surface, and the protrusion 220 of the second conductive structure 22 covers at least a portion of the protruding curved surface.

[0117] By setting at least the portion of the first side surface 21c that contacts the second conductive structure 22 as a protruding curved surface, not only can the contact area be further increased, but the slope of the portion of the second conductive structure 22 that overlaps with the first side surface 21c can also be softened, so that the protrusion 220 is not too steep and will break.

[0118] For example, in Figure 2 In the cross section shown (an example of the first cross section of this disclosure), the angle between the tangent of the protruding surface and the top surface 21b of the first conductive structure 21 is greater than 70 degrees and gradually decreases from top to bottom.

[0119] like Figure 2As shown, the first conductive structure 21 includes a contact portion 211 located on the side of the first insulating layer 301 away from the substrate and in contact with the second conductive structure 22. The contact portion 211 can be regarded, for example, as a longitudinal segment of the first conductive structure 21 within the contact range with the second conductive structure 22.

[0120] like Figure 2 As shown, the contact portion 211 includes a protrusion 210 (an example of a second protrusion in this disclosure) facing the recessed structure G1, the orthographic projection of the protrusion 210 on the substrate being located within the orthographic projection of the recessed structure G1 on the substrate. For example, as Figure 2 As shown, the protrusion 210 is one end of the contact portion 211 near the recessed structure G1, and is the portion of the top surface of the contact portion 211 that protrudes toward the recessed structure G1 relative to the bottom surface. Figure 2 As shown, the surface of the protrusion 210 facing the recessed structure G1 is part of the first side surface 21c.

[0121] For example, such as Figure 2 As shown, along a reference direction F parallel to the substrate surface, the maximum size of the protrusion 210 is greater than the maximum thickness of the portion of the first conductive structure 21 covering the side surface (sidewall) of the recessed structure G1.

[0122] like Figure 2 As shown, the contact portion 211 near the recessed structure G1 is a part of the first side surface 21c, that is, the portion of the first side surface 21c located on the upper surface of the first insulating layer 301 away from the substrate. This portion is called the first side surface portion. The first conductive structure 21 also includes a second side surface 21d away from the recessed structure G1; the dimension of the first side surface portion in the direction perpendicular to the substrate is larger than the dimension of the second side surface 21d in the direction perpendicular to the substrate. Figure 2 As shown, the second side surface 21d is not in contact with the second conductive structure 22. For example, at least a portion of the top surface 21b of the first conductive structure 21 that is connected to the second side surface 21 is separated from the second conductive layer 202.

[0123] Since the first side surface portion is in contact with the second conductive structure 22 while the second side surface 21d is not in contact with the second conductive structure 22, setting the longitudinal dimension of the first side surface portion to be larger helps to improve the flatness of the portion where the second conductive structure 22 contacts the top surface 21b of the first conductive structure 21, thereby improving the yield of subsequent manufacturing processes.

[0124] exist Figure 2In the cross-section shown and along the reference direction F, the maximum dimension of the protrusion 210 is greater than the maximum thickness of the portion of the first conductive layer 21 covering the side surface of the recessed structure G1 (i.e., the sidewall of the recessed structure G2 located within the recessed structure G1), and the reference direction F is parallel to the surface of the substrate. This arrangement facilitates the overlap between the protrusion 220 and the protrusion 210.

[0125] For example, such as Figure 2 As shown, the display substrate 20 has a first cross-section, that is... Figure 2 The cross-section shown has a dimension of b within the first cross-section and along the reference direction F, and a dimension c within the first cross-section of the overlapping area between the through-hole V1 and the recessed structure G1 along the reference direction F. For example, as... Figure 2 As shown, when calculating the overlapping area between the recessed structure or through-hole structure and other structures, the distance between the lowest points of the recessed structure or through-hole structure within the first cross section is taken as the range of the recessed structure or through-hole structure; the following embodiments are the same and will not be described again.

[0126] The portion of the first side surface 21c of the first conductive structure 21 covered by the second conductive structure 22 has a dimension d in the direction perpendicular to the substrate 100, and the contact portion 211 of the first conductive structure 21 has a dimension e in the direction perpendicular to the substrate.

[0127] For example, the dimension (nd) of the portion of the first side surface 21c not covered by the second conductive structure 22 in the direction perpendicular to the substrate is greater than the dimension e of the second side surface 21d in the direction perpendicular to the substrate.

[0128] For example, c / b is greater than 0.1; d / e is greater than 0.3.

[0129] The ratio r1 of the size of the first side surface 21c of the first conductive structure 21 covered by the second conductive structure 22 to the size of the first side surface 21c is positively correlated with the ratio r2 of the overlap size of the via V1 and the recessed structure G1 to the size of the recessed structure G1. That is, the larger the overlap ratio r2 of the via V1 and the recessed structure G1, the larger the coverage size of the first side surface 21c of the first conductive structure 21 by the second conductive structure 22. Through the above arrangement, the second conductive structure 22 can effectively cover the side surface of the first conductive structure 21, thereby effectively reducing the contact resistance between the two.

[0130] For example, the second conductive layer 202 is made of a different material than the first conductive layer 201. For example, the second conductive layer 202 includes an ITO / AG / ITO stacked structure, while the first conductive layer 201 includes a TI / AL / TI stacked structure.

[0131] For example, c / b is greater than 0.15, and d / e is less than 0.8.

[0132] For example, c / b is less than 0.19, and d / e is less than 0.5.

[0133] For example, when the second conductive structure 22 is configured as a pixel electrode (e.g., an anode) of a light-emitting element, the performance of the light-emitting material formed on its surface is affected by the flatness of the surface of the second conductive structure 22. Insufficient flatness of the second conductive structure 22 reduces the luminous efficiency of the light-emitting element. Minimizing the overlap size between the via V1 and the recessed structure G1 within a certain range can help improve the flatness of the second conductive structure 22, thereby improving the display performance of the display substrate.

[0134] For example, such as Figure 2 As shown, within the first cross-section, the maximum depth of the recessed structure G1 is i, the angle between one side of the recessed structure G1 within the first cross-section and the surface of the substrate is j, and the dimension of the portion of the second conductive structure 22 that contacts the first conductive structure 21 in the direction perpendicular to the substrate is k. Figure 2 As shown, the recessed structure G1 has an inverted trapezoidal shape within the first cross-section. For example, the side is the side of the recessed structure G1 closest to the protrusion 210.

[0135] For example, d / e < 0.0273*i*sin(j) / k.

[0136] For example, c / b < 0.0102*i*sin(j) / k.

[0137] The size of the first side surface 21c covered is positively correlated with the depth of the recessed structure G1 and the bottom corner of the recessed structure G1, and negatively correlated with the thickness of the second conductive layer 202. Within a certain range, reducing d / e or c / b can reduce the overlap between the via V1 and the recessed structure G1, thereby reducing the size of the downward protrusion 220 of the second conductive structure 22 and improving the flatness of the second conductive layer 22.

[0138] For example, the first side surface 21c has a dimension of n in the direction perpendicular to the substrate, and the second side surface portion has a dimension of e in the direction perpendicular to the substrate 100. For example, 0.1*(n / e) / sin(j)>(d / n).

[0139] The larger the ratio (n / e) of the size of the first side surface 21c to the size of the second side surface 21d, the larger the area that needs to be covered; that is, n / e is directly proportional to d / n. The larger the bottom angle of the recessed structure G1, the greater the slope of the corresponding sidewall of the recessed structure G1, making it less likely for water vapor to remain on the surface, and thus requiring less covering; that is, sin(j) is inversely proportional to d / n. Based on the values ​​of n / e and sin(j), the value of d / n is adjusted to ensure that the exposed side surface of the first conductive structure is adequately protected, reducing water vapor corrosion and improving the service life of the first conductive structure.

[0140] For example, 0.08*(n / e) / sin(j)>d / n.

[0141] By adopting the above settings, the size of the first side surface 21c that is covered can be smaller, thereby improving the flatness of the second conductive structure 22.

[0142] In one example, b = 2.821um, c = 0.599um, c / b = 0.212, d = 0.3339um, e = 0.5872um, d / e = 0.569.

[0143] In another example, b = 2.816 μm, c = 0.6465, c / b = 0.2296, d = 0.5603 μm, e = 0.8477, d / e = 0.661 μm.

[0144] Figure 3 This is a schematic diagram of a display substrate provided for other embodiments of this disclosure. For example... Figure 3 As shown, the first insulating layer 301 also includes a recessed structure G3 (an example of a second recessed structure of this disclosure) spaced apart from the recessed structure G1, the recessed structure G2 which may or may not penetrate the first insulating layer 301. For example, as Figure 3 As shown, the recessed structure G2 can be a via; in other examples, the recessed structure G2 can also be a groove. This disclosure does not limit the specific structure of the recessed structure G2.

[0145] like Figure 3 As shown, for example, the first conductive structure 21 further includes a recessed structure G4. For example, the recessed structure G4 is formed because the first conductive structure 21 covers the recessed structure G3, and the first conductive structure 21 fills into the recessed structure G3 to form the recessed structure G4. In a direction perpendicular to the substrate 100, the recessed structure G3 and the recessed structure G4 at least partially overlap.

[0146] like Figure 3As shown, the first conductive structure 21 also includes a second side surface 21e located between its bottom surface 21a and top surface 21b, the second side surface 21e being opposite to the first side surface 21c. For example, the second side surface 21e and the first side surface 21c are connected by the top surface 21b.

[0147] For example, the orthographic projection of the second side surface 21e onto the substrate at least partially overlaps with the orthographic projection of the recessed structure G3 onto the substrate. The first via V1 also exposes at least a portion of the second side surface 21e, and the second conductive structure 22 also covers at least a portion of the second side surface 21e of the first conductive structure 21.

[0148] The recessed structures G1 and G3 are located on both sides of the via V1, and both overlap at least partially with the via V1 in a direction perpendicular to the substrate. This causes the second insulating layer 302 to be recessed, exposing a portion of the first side surface 21c and the second side surface 21e. In other words, the first conductive structure 21 has an upward convex shape in the via V1. The second conductive structure 23 is in contact with the top surface 21b, the first side surface 21c, and the second side surface 21e of the first conductive structure, thereby further increasing the contact area, reducing the contact resistance, and improving the shielding and protection capabilities.

[0149] Furthermore, the above arrangement makes the contact relationship between the second insulating layer 302 and the two sides of the first conductive structure 21 similar, maintaining the force balance on both sides of the first conductive structure and avoiding separation of the second insulating layer 302 and the first conductive structure 21; at the same time, making at least a part of the first conductive structure 21 located in the recessed structure G1 and the recessed structure G3 can improve the connection strength between the first conductive structure 21 and the first insulating layer 301 and avoid film separation.

[0150] For example, in Figure 3 In the cross section shown, the size of the portion of the first side surface 21c of the first conductive structure 21 covered by the second conductive structure 22 is different from the size of the portion of its second side surface 21e covered by the second conductive structure 22.

[0151] For example, such as Figure 3 As shown, the overlapping area of ​​the orthographic projection of the via V1 on the substrate and the orthographic projection of the recessed structure G1 on the substrate is different from the overlapping area of ​​the orthographic projection of the via V1 on the substrate and the orthographic projection of the recessed structure G2 on the substrate.

[0152] For example, such as Figure 3As shown, in the reference direction F parallel to the substrate surface, the overlap size c1 of the orthogonal projection of the via V1 on the substrate and the orthogonal projection of the recessed structure G1 on the substrate and the overlap size c2 of the orthogonal projection of the via V1 on the substrate and the orthogonal projection of the recessed structure G2 on the substrate are different.

[0153] Figure 4 This is a plan view of a display substrate provided in at least one embodiment of the present disclosure. Figure 2 and Figure 3 The cross-sectional structure shown can be, for example, Figure 4 The image shows a cross-sectional structure of the display substrate.

[0154] like Figure 4 As shown, the display substrate 20 includes a display area 110 and a non-display area 103 outside the display area 110. For example, the non-display area 103 is located in the peripheral region of the display area 110. The display substrate 20 includes a plurality of sub-pixels P located in the display area 110. For example, the plurality of sub-pixels are arranged in an array, such as multiple pixel rows and multiple pixel columns arranged along a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 are different, for example, they are orthogonal. For example, the pixel rows and pixel columns do not necessarily extend strictly along a straight line, but may also extend along a curve (e.g., a broken line), which generally extends along the first direction D1 or the second direction D2 respectively.

[0155] Each sub-pixel includes a pixel circuit that drives a light-emitting element to emit light, and multiple pixel circuits are arranged in an array along a first direction D1 and a second direction D2. For example, sub-pixels can be configured into pixel units in a conventional RGB manner to achieve full-color display. This disclosure does not limit the arrangement of sub-pixels or the method of achieving full-color display.

[0156] For example, such as Figure 4 As shown, the display substrate 20 also includes a wire (e.g., gate line 11) extending along the first direction D1 and multiple wires (e.g., data line 12) extending along the second direction D2 in the display area 110. The multiple horizontal wires and multiple vertical wires intersect each other and define multiple pixel areas in the display area 110. A sub-pixel 100 is correspondingly provided in each pixel area. Figure 2 The diagram only shows the approximate positional relationship of the gate line 11, data line 12, and sub-image 100 in the display substrate; the specific design can be carried out according to actual needs.

[0157] The pixel circuit can be, for example, a 2T1C (two transistors and one capacitor) pixel circuit, a 4T2C, 5T1C, 7T1C, or an nTmC (n and m are positive integers) pixel circuit. In different embodiments, the pixel circuit may further include a compensation sub-circuit, which can be an internal or external compensation sub-circuit, and may include transistors, capacitors, etc. For example, depending on the needs, the pixel circuit may further include a reset circuit, a light emission control sub-circuit, a detection circuit, etc. For example, the display substrate may also include a gate driving circuit 13 and a data driving circuit 14 located in the non-display area. The gate driving circuit 13 is connected to the pixel circuit via gate lines 11 to provide various scan signals, and the data driving circuit 14 is connected to the pixel circuit via data lines 12 to provide data signals. Figure 4 The positional relationship of the gate driving circuit 13 and data driving circuit 14, the gate line 11 and the data line 12 in the display substrate shown is only an example. The actual arrangement can be designed as needed.

[0158] For example, the display substrate 20 may also include control circuitry (not shown). This control circuitry may be configured to control the data driving circuitry 14 to apply the data signal and to control the gate driving circuitry to apply the scan signal. An example of this control circuitry is a timing control circuit (T-con). The control circuitry can take various forms, such as including a processor and a memory, the memory containing executable code, which the processor runs to perform the detection method described above.

[0159] For example, the processor can be a central processing unit (CPU) or other forms of processing device with data processing and / or instruction execution capabilities, such as a microprocessor, a programmable logic controller (PLC), etc.

[0160] For example, a storage device may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and a processor may execute the functions expected by the program instructions. Various application programs and various data may also be stored in the computer-readable storage medium.

[0161] The pixel circuit may include a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, and a storage sub-circuit, and may also include a light emission control sub-circuit, a reset circuit, etc., as needed. Figure 5A A schematic diagram of a pixel circuit is shown.

[0162] like Figure 5A As shown, the pixel circuit includes a driving sub-circuit 122, a data writing sub-circuit 126, and a compensation sub-circuit 128.

[0163] For example, the driving sub-circuit 122 includes a control terminal (i.e., a control electrode) 122a, a first terminal 122b, and a second terminal 122c, and is configured to be connected to the light-emitting element 120 and to control the driving current for driving the light-emitting element 120 according to the voltage on the control electrode. The control terminal 122a of the driving sub-circuit 122 is connected to the first node N1, the first terminal 122b of the driving sub-circuit 122 is connected to the second node N2, and the second terminal 122c of the driving sub-circuit 122 is connected to the third node N3.

[0164] For example, the data writing sub-circuit 126 is connected to the driving sub-circuit 122 and configured to write a data signal to the first terminal 122b of the driving sub-circuit 122 in response to a first scan signal. For example, as Figure 5A As shown, the data circuit 126 includes a control terminal 126a, a first terminal 126b, and a second terminal 126c. The control terminal 126a is configured to receive a first scan signal Ga1, the first terminal 126b is configured to receive a data signal Vd, and the second terminal 126c is connected to the first terminal 122b (i.e., the second node N2) of the drive sub-circuit 122. The data writing sub-circuit 126 is configured to write the data signal Vd to the first terminal 122b of the drive sub-circuit 122 in response to the first scan signal Ga1. For example, the first terminal 126b of the data writing sub-circuit 126 is connected to the data line 12 to receive the data signal Vd, and the control terminal 126a is connected to the gate line 11, which serves as the scan line, to receive the first scan signal Ga1. For example, during the data writing and compensation phase, the data writing sub-circuit 126 can be turned on in response to the first scan signal Ga1, thereby writing the data signal to the first terminal 122b (second node N2) of the driving sub-circuit 122 and storing the data signal so that, for example, during the light emission phase, a driving current for driving the light-emitting element 120 to emit light can be generated based on the data signal.

[0165] For example, the compensation sub-circuit 128 is connected to the drive sub-circuit 122 and configured to compensate the drive sub-circuit 122 in response to a second scan signal, which may be the same as or different from the first scan signal. For example, as Figure 5AAs shown, the compensation sub-circuit 128 includes a control terminal 128a, a first terminal 128b, and a second terminal 128c. The control terminal 128a of the compensation sub-circuit 128 is configured to receive a second scan signal Ga2. The first terminal 128b and the second terminal 128c of the compensation sub-circuit 128 are electrically connected to the second terminal 122c and the control terminal 122a of the driving sub-circuit 122, respectively. The compensation sub-circuit 128 is configured to perform threshold compensation on the driving sub-circuit 122 in response to the second scan signal Ga2.

[0166] For example, the pixel circuit also includes a storage sub-circuit 127, a first light emission control sub-circuit 123, a second light emission control sub-circuit 124, a first reset sub-circuit 125, and a second reset sub-circuit 129.

[0167] For example, the first scan signal Ga1 can be the same as the second scan signal Ga2. Alternatively, the first scan signal Ga1 and the second scan signal Ga2 can be connected to the same signal output terminal. Or, the first scan signal Ga1 and the second scan signal Ga2 can be transmitted through the same scan line.

[0168] In other examples, the first scan signal Ga1 may also be different from the second scan signal Ga2. For example, the first scan signal Ga1 and the second scan signal Ga2 may be connected to different signal output terminals. For example, the first scan signal Ga1 and the second scan signal Ga2 may be transmitted through different scan lines.

[0169] The storage sub-circuit 127 includes a first terminal (also called a first storage electrode) 127a and a second terminal (also called a second storage electrode) 127b. The first terminal 127a of the storage sub-circuit is configured to receive a first power supply voltage VDD, and the second terminal 127b of the storage sub-circuit is electrically connected to the control terminal 122a of the driving sub-circuit. For example, during the data writing and compensation stage, the compensation sub-circuit 128 can be turned on in response to the second scan signal Ga2, thereby storing the data signal written by the data writing sub-circuit 126 in the storage sub-circuit 127. At the same time, the compensation sub-circuit 128 can electrically connect the control terminal 122a and the second terminal 122c of the driving sub-circuit 122, thereby storing the relevant information of the threshold voltage of the driving sub-circuit 122 in the storage sub-circuit. Thus, for example, during the light emission stage, the stored data signal and the threshold voltage can be used to control the driving sub-circuit 122, thereby compensating the output of the driving sub-circuit 122.

[0170] For example, the storage sub-circuit 127 is electrically connected to the control terminal 122a and the first voltage terminal VDD of the driving sub-circuit 122, and is configured to store the data signal written by the data writing sub-circuit 126. For example, during the data writing and compensation phase, the compensation sub-circuit 128 can be turned on in response to the second scan signal Ga2, thereby storing the data signal written by the data writing sub-circuit 126 in the storage sub-circuit 127. For example, simultaneously during the data writing and compensation phase, the compensation sub-circuit 128 can electrically connect the control terminal 122a and the second terminal 122c of the driving sub-circuit 122, thereby storing the relevant information of the threshold voltage of the driving sub-circuit 122 in the storage sub-circuit accordingly. Thus, for example, during the light emission phase, the stored data signal and the threshold voltage can be used to control the driving sub-circuit 122, thereby compensating the output of the driving sub-circuit 122.

[0171] For example, the first light-emitting control sub-circuit 123 is connected to the first terminal 122b (second node N2) and the first voltage terminal VDD of the driving sub-circuit 122, and is configured to apply a first power supply voltage of the first voltage terminal VDD to the first terminal 122b of the driving sub-circuit 122 in response to the first light-emitting control signal EM1. For example, as Figure 5A As shown, the first light-emitting control sub-circuit 123 is connected to the first light-emitting control terminal EM1, the first voltage terminal VDD, and the second node N2.

[0172] For example, the second light-emitting control sub-circuit 124 is connected to the second light-emitting control terminal EM2, the first terminal 134 of the light-emitting element 120 and the second terminal 122c of the driving sub-circuit 122, and is configured to allow a driving current to be applied to the light-emitting element 122 in response to the second light-emitting control signal.

[0173] For example, during the light-emitting phase, the second light-emitting control sub-circuit 123 is turned on in response to the second light-emitting control signal EM2 provided by the second light-emitting control terminal EM2, so that the driving sub-circuit 122 can be electrically connected to the light-emitting element 120 through the second light-emitting control sub-circuit 123, thereby driving the light-emitting element 120 to emit light under the control of the driving current; while during the non-light-emitting phase, the second light-emitting control sub-circuit 123 is turned off in response to the second light-emitting control signal EM2, thereby preventing current from flowing through the light-emitting element 120 and causing it to emit light, which can improve the contrast of the corresponding display device.

[0174] For example, during the initialization phase, the second light-emitting control sub-circuit 124 can also be turned on in response to the second light-emitting control signal, thereby enabling the reset circuit to perform a reset operation on the drive sub-circuit 122 and the light-emitting element 120.

[0175] For example, the second light-emitting control signal EM2 can be the same as the first light-emitting control signal EM1. For example, the second light-emitting control signal EM2 can be connected to the same signal output terminal as the first light-emitting control signal EM. For example, the second light-emitting control signal EM2 can be transmitted through the same light-emitting control line as the first light-emitting control signal EM.

[0176] In other examples, the second light-emitting control signal EM2 may be different from the first light-emitting control signal EM1. For example, the second light-emitting control signal EM2 and the first light-emitting control signal EM1 may be connected to different signal output terminals. For example, the second light-emitting control signal EM2 and the first light-emitting control signal EM1 may be transmitted through different light-emitting control lines.

[0177] For example, the first reset sub-circuit 125 is connected to the first reset voltage terminal Vinit1 and the control terminal 122a (first node N1) of the drive sub-circuit 122, and is configured to apply the first reset voltage Vinit1 to the control terminal 122a of the drive sub-circuit 122 in response to the first reset control signal Rst1.

[0178] For example, the second reset sub-circuit 129 is connected to the second reset voltage terminal Vinit2 and the first terminal 122b (fourth node N4) of the light-emitting element 122, and is configured to apply the second reset voltage Vinit2 to the first terminal 134 of the light-emitting element 120 in response to the second reset control signal Rst2. For example, the first reset voltage Vinit1 and the second reset voltage Vinit2 can be the same voltage signal or different voltage signals. For example, the first reset voltage terminal Vinit1 and the second reset voltage terminal Vinit2 are connected to the same reset voltage source terminal (e.g., located in the non-display area) to receive the same reset voltage.

[0179] For example, the first reset sub-circuit 125 and the second reset sub-circuit 129 can be turned on in response to the first reset control signal Rst1 and the second reset control signal Rst2, respectively. This allows the second reset voltage Vinit2 to be applied to the first node N1 and the first reset voltage Vinit1 to be applied to the first terminal 134 of the light-emitting element 120, thereby resetting the driving sub-circuit 122, the compensation sub-circuit 128 and the light-emitting element 120, eliminating the influence of the previous light-emitting stage.

[0180] For example, the second reset control signal Rst2 for each row of sub-pixels can be the same signal as the first scan signal Ga1 for that row of sub-pixels, and both can be transmitted through the same gate line 11. Similarly, the first reset control signal Rst1 for each row of sub-pixels can be the same signal as the first scan signal Ga1 for the previous row of sub-pixels, and both can be transmitted through the same gate line 11.

[0181] For example, the light-emitting element 120 includes a first end (also referred to as a first electrode or pixel electrode) 134 and a second end (also referred to as a second electrode) 135. The first end 134 of the light-emitting element 120 is connected to a fourth node, and the second end 135 of the light-emitting element 120 is configured to be connected to a second voltage terminal VSS. For example, in one example, such as Figure 5A As shown, the second terminal 122c of the driving sub-circuit 122 can be connected to the fourth node N4 through the second light-emitting control sub-circuit 124. Embodiments of this disclosure include, but are not limited to, this scenario.

[0182] It should be noted that in the description of the embodiments of this disclosure, the first node N1, the second node N2, the third node N3 and the fourth node N4 do not necessarily represent actual existing components, but rather represent the junction points of related circuit connections in the circuit diagram.

[0183] It should be noted that, in the description of the embodiments of this disclosure, the symbol Vd can represent both a data signal terminal and the level of a data signal. Similarly, the symbols Ga1 and Ga2 can represent both the first scan signal and the second scan signal, or both the first scan signal terminal and the second scan signal terminal. Rst1 and Rst2 can represent both a reset control terminal and a reset control signal. The symbols Vinit1 and Vinit2 can represent both the first reset voltage terminal and the second reset voltage terminal, or both the first reset voltage and the second reset voltage. The symbol VDD can represent both the first voltage terminal and the first power supply voltage, and the symbol VSS can represent both the second voltage terminal and the second power supply voltage. The following embodiments are the same and will not be described again.

[0184] Figure 5B for Figure 5A The circuit diagram shown is a specific implementation example of the pixel circuit. For example... Figure 5B As shown, the pixel circuit includes: first to seventh transistors T1, T2, T3, T4, T5, T6, T7, and a storage capacitor Cst.

[0185] For example, such as Figure 5B As shown, the driving sub-circuit 122 can be implemented as a first transistor T1 (i.e., a driving transistor). The gate of the first transistor T1 serves as the control terminal 122a of the driving sub-circuit 122 and is connected to the first node N1; the first terminal of the first transistor T1 serves as the first terminal 122b of the driving sub-circuit 122 and is connected to the second node N2; the second terminal of the first transistor T1 serves as the second terminal 122c of the driving sub-circuit 122 and is connected to the third node N3.

[0186] For example, such as Figure 5BAs shown, the data writing sub-circuit 126 can be implemented as a second transistor T2. The gate of the second transistor T2 is connected to the first scan line (first scan signal terminal Ga1) to receive the first scan signal, the first terminal of the second transistor T2 is connected to the data line (data signal terminal Vd) to receive the data signal, and the second terminal of the second transistor T2 is connected to the first terminal 122b (second node N2) of the driving sub-circuit 122.

[0187] For example, such as Figure 5B As shown, the compensation sub-circuit 128 can be implemented as a third transistor T3 (i.e., a compensation transistor). The gate, first terminal, and second terminal of the third transistor T3 serve as the control terminal 128a, the first terminal 128b, and the second terminal 128c of the compensation sub-circuit, respectively. The gate of the third transistor T3 is configured to be connected to the second scan line (the second scan signal terminal Ga2) to receive the second scan signal. The first terminal of the third transistor T3 is connected to the second terminal 122c (third node N3) of the driving sub-circuit 122, and the second terminal of the third transistor T3 is connected to the control terminal 122a (first node N1) of the driving sub-circuit 122.

[0188] For example, such as Figure 5B As shown, the storage sub-circuit 127 can be implemented as a storage capacitor Cst, which includes a first capacitor electrode Ca and a second capacitor electrode Cb. The first capacitor electrode Ca is connected to the first voltage terminal VDD, and the second capacitor electrode Cb is connected to the control terminal 122a of the driving sub-circuit 122.

[0189] For example, such as Figure 5B As shown, the first light-emitting control sub-circuit 123 can be implemented as a fourth transistor T4. The gate of the fourth transistor T4 is connected to the first light-emitting control line (first light-emitting control terminal EM1) to receive the first light-emitting control signal, the first terminal of the fourth transistor T4 is connected to the first voltage terminal VDD to receive the first power supply voltage, and the second terminal of the fourth transistor T4 is connected to the first terminal 122b (second node N2) of the driving sub-circuit 122.

[0190] For example, the light-emitting element 120 is specifically implemented as a light-emitting diode (LED), such as an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or an inorganic light-emitting diode, such as a micro LED or a micro OLED. For example, the light-emitting element 120 can be a top-emitting structure, a bottom-emitting structure, or a double-sided emitting junction. The light-emitting element 120 can emit red, green, blue, or white light, etc. The embodiments of this disclosure do not limit the specific structure of the light-emitting element.

[0191] For example, the light-emitting element 120 includes a first electrode 134, a second electrode 135, and an organic functional layer sandwiched between the first electrode 134 and the second electrode 135. The organic functional layer includes a light-emitting layer. As needed, the organic functional layer may also include a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer, etc.

[0192] For example, the first electrode 134 (also called the pixel electrode, e.g., the anode) and the fourth node N4 of the light-emitting element 120 are connected to the second terminal 122c of the driving sub-circuit 122 via the second light-emitting control sub-circuit 124. The second electrode 135 (e.g., the cathode) of the light-emitting element 120 is connected to the second voltage terminal VSS to receive the second power supply voltage VSS. The circuit flowing from the second terminal 122c of the driving sub-circuit 122 into the light-emitting element 120 determines the brightness of the light-emitting element. For example, the second voltage terminal can be grounded, i.e., VSS can be 0V. For example, the second power supply voltage VSS can be a negative voltage.

[0193] For example, the second light-emitting control sub-circuit 124 can be implemented as a fifth transistor T5. The gate of the fifth transistor T5 is connected to the second light-emitting control line (second light-emitting control terminal EM2) to receive the second light-emitting control signal. The first terminal of the fifth transistor T5 is connected to the second terminal 122c (third node N3) of the driving sub-circuit 122, and the second terminal of the fifth transistor T5 is connected to the first terminal 134 (fourth node N4) of the light-emitting element 120.

[0194] For example, the first reset sub-circuit 125 can be implemented as a sixth transistor T6, and the second reset sub-circuit can be implemented as a seventh transistor T7. The gate of the sixth transistor T6 is configured to be connected to the first reset control terminal Rst1 to receive the first reset control signal Rst1. The first terminal of the sixth transistor T6 is connected to the first reset voltage terminal Vinit1 to receive the first reset voltage Vinit1. The second terminal of the sixth transistor T6 is configured to be connected to the first node N1. The gate of the seventh transistor T7 is configured to be connected to the second reset control terminal Rst2 to receive the second reset control signal Rst2. The first terminal of the seventh transistor T7 is connected to the second reset voltage terminal Vinit2 to receive the second reset voltage Vinit2. The second terminal of the seventh transistor T7 is configured to be connected to the fourth node N4.

[0195] It should be noted that the transistors used in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. The embodiments of this disclosure all use thin-film transistors as an example for illustration. The source and drain of the transistors used here can be structurally symmetrical, so their source and drain can be structurally indistinguishable. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is directly described as the first terminal, and the other as the second terminal.

[0196] Furthermore, transistors can be classified into N-type and P-type transistors based on their characteristics. When a transistor is P-type, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is N-type, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage). For example, as... Figure 5B As shown, the first to seventh transistors T1-T7 are all P-type transistors, such as low-temperature polycrystalline silicon thin-film transistors. However, this embodiment does not limit the type of transistors; when the type of transistor changes, the connection relationship in the circuit can be adjusted accordingly.

[0197] The following combination Figure 5C The signal timing diagram shown is for Figure 5B The working principle of the pixel circuit shown is explained. For example... Figure 5C As shown, the display process of each frame of the image includes three stages: initialization stage 1, data writing and compensation stage 2, and illumination stage 3.

[0198] like Figure 5C As shown, in this embodiment, the first scan signal Ga1 and the second scan signal Ga2 use the same signal, and the first light emission control signal EM1 and the second light emission control signal EM2 use the same signal; and the waveforms of the second reset control signal Rst2 and the first scan signal Ga1 / second scan signal Ga2 are the same, that is, the second reset control signal Rst2 and the first scan signal Ga1 / second scan signal Ga2 can use the same signal; the waveforms of the first reset signal Rst1 of the current row sub-pixel are the same as those of the first scan signal Ga1 / second scan signal Ga2 of the previous row sub-pixel, that is, the same signal is used. However, this is not intended to limit this disclosure. In other embodiments, different signals can be used as the first scan signal Ga1, the second scan signal Ga2, the first reset control signal Rst1, and the second reset control signal Rst2, and different signals can be used as the first light emission control signal EM1 and the second light emission control signal EM2.

[0199] In initialization phase 1, the first reset control signal Rst1 is input to turn on the sixth transistor T6, and the first reset voltage Vinit1 is applied to the gate of the first transistor T1, thereby resetting the first node N1.

[0200] In the data writing and compensation stage 2, the first scan signal Ga1, the second scan signal Ga2, and the data signal Vd are input. The second transistor T2 and the third transistor T3 are turned on. The data signal Vd is written to the second node N2 by the second transistor T2 and then charges the first node N1 through the first transistor T1 and the third transistor T3 until the potential of the first node N1 changes to Vd + Vth, at which point the first transistor T1 is turned off, where Vth is the threshold voltage of the first transistor T1. This potential of the first node N1 is stored in the storage capacitor Cst and thus maintained. In other words, the voltage information containing the data signal and the threshold voltage Vth is stored in the storage capacitor Cst for use in the subsequent light-emitting stage to provide grayscale display data and compensate for the threshold voltage of the first transistor T1 itself.

[0201] In the data writing and compensation stage 2, a second reset control signal Rst2 can also be input to turn on the seventh transistor T7, applying the second reset voltage Vinit2 to the fourth node N4, thereby resetting the fourth node N4. For example, the reset of the fourth node N4 can also be performed in the initialization stage 1, for example, the first reset control signal Rst1 and the second reset control signal Rst2 can be the same. This disclosure does not limit this aspect.

[0202] In the light-emitting stage 3, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are input to turn on the fourth transistor T4, the fifth transistor T5, and the first transistor T1. The fifth transistor T5 applies a driving current to the OLED to make it emit light. The value of the driving current I flowing through the OLED can be obtained according to the following formula:

[0203] I = K(VGS - Vth) 2 =K[(Vdata+Vth-VDD)-Vth] 2 =K(Vdata-VDD) 2 , where K is the conductivity coefficient of the first transistor.

[0204] In the above formula, Vth represents the threshold voltage of the first transistor T1, VGS represents the voltage between the gate and source (here, the first electrode) of the first transistor T1, and K is a constant value related to the first transistor T1 itself. As can be seen from the above formula for calculating I, the driving current I flowing through the OLED is no longer related to the threshold voltage Vth of the first transistor T1. This allows for compensation of the pixel circuit, solving the problem of threshold voltage drift caused by the driving transistor (the first transistor T1 in this embodiment) due to process technology and long-term operation, eliminating its influence on the driving current I, and thus improving the display effect of the display device using it.

[0205] The following Figure 5BTaking the pixel circuit shown as an example, and combining it with Figures 6A-6B , Figure 7 , Figures 8A-8C , Figures 9A-9C and Figure 10A The structure of a display substrate provided in at least one embodiment of the present disclosure will be described by way of example.

[0206] Figure 6A This is a schematic diagram of a display substrate 20 provided in at least one embodiment of the present disclosure. Figure 6B for Figure 6A A sectional view along section line A-A'. It should be noted that, for clarity, Figure 6B Some structures that do not have direct electrical connections at the cross-sectional lines have been omitted; this is for ease of comparison. Figure 8B and 9B The location of section line A-A' is also shown in the diagram.

[0207] like Figure 6A As shown, the display substrate 20 includes a substrate 100, on which a plurality of sub-pixels P are located. The pixel circuits of the plurality of sub-pixels P are arranged in a pixel circuit array, for example, the row direction of the pixel circuit array is a first direction D1, and the column direction is a second direction D2. In some embodiments, the pixel circuits of each sub-pixel may have the same structure, that is, the pixel circuits are repeatedly arranged in the row and column directions.

[0208] For ease of explanation, Figure 6A The example shows two rows and five columns of sub-pixels. For example, as shown... Figure 6A As shown, the arrangement rule of the pixel circuit of a sub-pixel can be the same as or different from the arrangement rule of the pixel electrode (i.e., the first electrode of the light-emitting element) above it. For ease of explanation, the description of the sub-pixel arrangement here refers to the arrangement rule of the pixel circuit, and the description of the relative positional relationship of the sub-pixels refers to the relative position of the pixel circuit of that sub-pixel. For example, adjacent sub-pixels refer to sub-pixels whose pixel circuits are adjacent to each other. The following embodiments are the same and will not be described again.

[0209] Combination Figures 6A-6B It can be seen that the semiconductor layer 102, insulating layer 401, conductive layer 501, insulating layer 402, conductive layer 502, insulating layer 403, conductive layer 503, insulating layer 404, and conductive layer 504 are sequentially disposed on the substrate 100, thereby forming a structure as shown in the figure. Figure 6A The structure of the display substrate is shown.

[0210] Figure 7 Corresponding to Figure 6A The semiconductor layer 102 and the conductive layer 501 are illustrated. Figure 8A and Figure 8C The pattern of conductive layer 502 is shown. Figure 8B exist Figure 7 The conductive layer 502 is shown based on this; Figure 9A Conductive layer 503 is shown. Figure 9B exist Figure 8B The conductive layer 503 is shown based on this; Figure 10A The conductive layer 504 is shown.

[0211] For ease of explanation, in the following description, Tng, Tns, Tnd, and Tna represent the gate, first electrode, second electrode, and channel region of the nth transistor Tn, respectively, where n is 1-7.

[0212] It should be noted that the term "same-layer arrangement" in this disclosure refers to two (or more) structures formed through the same deposition process and patterned through the same patterning process, and they are not necessarily located on the same horizontal plane; their materials may be the same or different. The term "integrated structure" in this disclosure refers to a structure formed by two (or more) structures through the same deposition process and patterned through the same patterning process, and their materials may be the same or different.

[0213] For example, such as Figure 7 As shown, the conductive layer 501 includes the gate of each transistor as well as some scan lines and control lines. The semiconductor layer 102 includes the active layers T1a-T7a of the first to seventh transistors T1-T7. Figure 7 As shown, the active layers T1a-T7a of the first to seventh transistors T1-T7 are interconnected as a single unit. For example, the semiconductor layers 102 in each column of sub-pixels are interconnected as a single unit, and the semiconductor layers in adjacent columns of sub-pixels are spaced apart from each other.

[0214] For example, such as Figure 7 As shown, the conductive layer 501 includes the gates T1g-T7g of the first to seventh transistors T1-T7. For example, the display substrate 20 employs a self-aligned process, using the first conductive layer 201 as a mask to perform a conductor-enhancing treatment (e.g., doping) on ​​the semiconductor layer 102, so that the portion of the semiconductor layer 102 not covered by the first conductive layer 201 is conductor-enhanced, thereby conductor-enhancing the portions of the active layer of each transistor located on both sides of the channel region to form the first and second electrodes of the transistor, respectively.

[0215] For example, such as Figure 7As shown, the third transistor T3 and the sixth transistor T6 each employ a dual-gate structure, including a first gate and a second gate. This improves the gate control capability of the transistors and reduces leakage current. Since both the third transistor T3 and the sixth transistor T6 are directly connected to the gate (i.e., the first node N1) of the first transistor T1 (i.e., the driving transistor), the stability of the third transistor T3 and the sixth transistor T6 directly affects the stability of the gate voltage (N1 node) of the first transistor T1. Employing a dual-gate structure to improve the gate control capability of the third transistor T3 and the sixth transistor T6 helps reduce the leakage current of the transistors, thereby helping to maintain the voltage at the N1 node. This ensures that the threshold voltage of the first transistor T1 is adequately compensated during the compensation phase, thus improving the display uniformity of the display substrate during the light-emitting stage.

[0216] like Figure 7 As shown, the third transistor T3 includes a first gate T3g1 and a second gate T3g2, as well as a first channel region and a second channel region corresponding to the first gate T3g1 and the second gate T3g2, respectively. The first channel region and the second channel region are shielded by the first gate T3g1 and the second gate T3g2 and are not shown in the figure. For example, the first gate T3g1 is located on the main body of the scan line 220 that controls the third transistor T3, and the second gate T3g2 is a protrusion that protrudes from the main body of the scan line 220 along the second direction D2. The third transistor T3 also includes a conductive region T3c located between the first gate T3g1 and the second gate T3g2, which is formed by conductiveizing the semiconductor layer exposed between the first gate T3g1 and the second gate T3g2. The conductive region T3c is separated from the first terminal T3s of the third transistor T3 by the first channel region of the third transistor T3, and the conductive region T3c is separated from the second terminal T3d of the third transistor T3 by the second channel region of the third transistor T3. The conductive region T3c, the first channel region, and the second channel region of the third transistor T3 are integral structures, and for example, all of them are made of polycrystalline silicon material. Similarly, the sixth transistor T6 also includes a conductive region T6c located between the first gate T6g1 and the second gate T2g.

[0217] For example, the first conductive layer 201 also includes multiple scan lines 210, multiple reset control lines 220, and multiple light emission control lines 230 that are insulated from each other. These signal lines can all serve as... Figure 4 An example of gate line 11 is shown.

[0218] Scan line 210 is electrically connected (or integrated) to the gate T2g of the second transistor T2 in the corresponding row of sub-pixels to provide a first scan signal Ga1. Reset control line 220 is electrically connected to the gate T6g of the sixth transistor T6 in the corresponding row of sub-pixels to provide a first reset control signal Rst1. Light emission control line 230 is electrically connected to the gate T4g of the fourth transistor T4 in the corresponding row of sub-pixels to provide a first light emission control signal EM1.

[0219] For example, such as Figure 7 As shown, the scan line 210 is also electrically connected to the gate of the third transistor T3 to provide the second scan signal Ga2, that is, the first scan signal Ga1 and the second scan signal Ga2 can be the same signal; the light emission control line 230 is also electrically connected to the gate T5g of the fifth transistor T5 to provide the second light emission control signal EM2, that is, the first light emission control signal EM1 and the second light emission control signal EM2 are the same signal.

[0220] For example, the first gate T3g1 extends along the first direction D1 and is part of the scan line 210. The second gate T3g2 extends along the second direction D2 and is an extension of the scan line 210 extending along the second direction D2.

[0221] For example, such as Figure 7 As shown, the gate of the seventh transistor T7 of the current row pixel circuit is electrically connected to the reset control line 220 corresponding to the next row pixel circuit (i.e., the row of pixel circuits where the scan lines are turned on sequentially after the current row of scan lines according to the scanning order of the scan lines) to receive the second reset control signal Rst2.

[0222] For example, such as Figure 8A As shown, the conductive layer 502 includes a first capacitor electrode Ca. This first capacitor electrode Ca overlaps with the gate T1g of the first transistor T1 in a direction perpendicular to the substrate 100, thereby forming a storage capacitor Cst. That is, the gate T1g of the first transistor T1 acts as the second capacitor electrode Cb of the storage capacitor Cst. For example, the first capacitor electrode Ca includes an opening 222 that exposes at least a portion of the gate T1g of the first transistor T1, facilitating electrical connection of the gate T1g to other structures. For example, the first capacitor electrodes Ca of sub-pixels located in the same pixel row are connected to each other in a unified structure. Because the first capacitor electrode Ca is configured to be electrically connected to the power line, this unified structure can reduce resistance, thereby reducing voltage drop and helping to uniformly deliver the power supply voltage to each sub-pixel on the substrate.

[0223] For example, the conductive layer 502 may further include multiple reset voltage lines 240 extending along the first direction D1, which are connected one-to-one with multiple rows of sub-pixels. Each reset voltage line 240 is electrically connected to the first electrode of the sixth transistor T6 in the corresponding row of sub-pixels to provide a first reset voltage Vinit1.

[0224] For example, such as Figure 8B As shown, the first terminal of the seventh transistor T7 in this row of sub-pixels is electrically connected to the reset voltage line 240 corresponding to the sub-pixel in the next row to receive the second reset voltage Vinit2. This will be discussed later in conjunction with... Figure 9B This will be described in detail.

[0225] For example, such as Figures 8A-8B As shown, the conductive layer 502 may further include a shielding electrode 221. For example, the shielding electrode 221 overlaps with the first electrode T2s of the second transistor T2 in a direction perpendicular to the substrate 100, thereby protecting the signal in the first electrode T2s of the second transistor T2 from interference from other signals. Since the first electrode T2s of the second transistor T2 is configured to receive the data signal Vd, and the data signal Vd determines the display grayscale of the sub-pixel, the shielding electrode 221 improves the stability of the data signal, thereby improving display performance.

[0226] For example, in conjunction with reference Figure 8B and Figure 6B The shielding electrode 221 also overlaps at least partially with the second electrode T6d of the sixth transistor T6 in a direction perpendicular to the substrate 100, so as to improve the stability of the signal on the second electrode T6d, thereby improving the stability of the sixth transistor T6 and further stabilizing the gate voltage of the first transistor T1.

[0227] For example, such as Figure 8B As shown, the shielding electrode 221 also extends to the adjacent sub-pixel and at least partially overlaps with the conductive region T3c of the third transistor T3 in the adjacent sub-pixel in a direction perpendicular to the substrate 100, so as to improve the stability of the signal in the conductive region T3c, thereby improving the stability of the third transistor T3 and further stabilizing the gate voltage of the first transistor T1.

[0228] For example, the shielding electrode 221, together with the first terminal T2s of the second transistor T2 and the second terminal T6d of the sixth transistor T6, forms a stable capacitor. The shielding electrode 221 is configured to apply a fixed voltage. Since the voltage difference across the capacitor cannot change abruptly, this improves the stability of the voltage across the first terminal T2s of the second transistor T2, the conductive region T3c of the third transistor T3, and the second terminal T6d of the sixth transistor T6. For example, the shielding electrode 221 is electrically connected to the power line 250 in the conductive layer 503 to apply a first power supply voltage VDD.

[0229] For example, the shielding electrode 221 can be L-shaped, V-shaped, or T-shaped, such as... Figure 8A As shown, the shielding electrode 221 is L-shaped and includes a first shielding portion 221a and a second shielding portion 221b extending in different directions. The second shielding portion 221b at least partially overlaps with the second electrode T6d of the sixth transistor T6 in a direction perpendicular to the substrate 100; the first shielding portion 221a at least partially overlaps with the first electrode T2s of the second transistor T2 and the conductive region T3c of the third transistor T3 in the adjacent sub-pixel in a direction perpendicular to the substrate 100, thereby shielding the conductive region T3 to improve the stability of the transistor. For example, the second shielding portion 221b extends along the second direction D2, and the first shielding portion 221a extends along the first direction D1.

[0230] Figure 8C This is a planar schematic diagram of another example of conductive layer 502. Figure 8C The illustrated embodiments and Figure 8A The main difference in the illustrated embodiment is that its shielding electrode 221 is T-shaped, and the second shielding portion 221b extends downward to the first capacitor electrode Ca and is integrally connected to the first capacitor electrode Ca. The connection point between the first shielding portion and the second shielding portion is located at the middle position of the second shielding portion in the second direction.

[0231] Since the first capacitor electrode Ca is configured to be electrically connected to the power line 250, the above arrangement allows the shield electrode 221 to be connected to the power line 250 through the first capacitor electrode Ca in the same layer, thereby avoiding the need for via 341 and simplifying the design.

[0232] For example, such as Figures 9A-9BAs shown, the conductive layer 503 includes multiple power lines 250 extending along the second direction D2. These power lines 250 are connected to a first voltage terminal VDD to transmit a first power supply voltage VDD. For example, these power lines 250 are electrically connected one-to-one with multiple columns of sub-pixels to provide the first power supply voltage VDD. Each power line 250 is electrically connected to the first capacitor electrode Ca in its corresponding column of sub-pixels via via 342, and to the first electrode T4s of the fourth transistor T4 via via 343. For example, the power line 250 is also electrically connected to the shielding electrode 221 via via 341, thereby giving the shielding electrode 221 a fixed potential and improving its shielding capability. For example, both vias 342 and 341 penetrate the third insulating layer 303, and via 343 penetrates insulating layers 401, 402, and 403.

[0233] For example, the conductive layer 503 also includes multiple data lines 12 extending along the second direction D2. For example, these multiple data lines 12 are electrically connected one-to-one with multiple columns of sub-pixels to provide a data signal Vd. For example, the data lines 12 are electrically connected to the first terminal T2s of the second transistor T2 in the corresponding column of sub-pixels through a via 346 to provide the data signal. For example, the via 346 penetrates insulating layers 401, 402, and 403.

[0234] For example, combining Figures 6A-6B , Figures 9A-9B As shown, the conductive layer 503 also includes a connecting electrode 231. One end of the connecting electrode 231 is electrically connected to the gate T1g of the first transistor T1 (i.e., the second capacitor electrode Cb) through an opening 222 in the first capacitor electrode Ca and a via 344 in the insulating layer. The other end is electrically connected to the second electrode T3d of the third transistor T3 through a via 345, thereby electrically connecting the second capacitor electrode Cb to the second electrode T3d of the third transistor T3. For example, the via 344 penetrates the insulating layers 402 and 403. For example, the via 345 penetrates the insulating layers 401, 402, and 403.

[0235] For example, combining Figures 6A-6B , Figures 9A-9B As shown, the conductive layer 503 also includes a connection electrode 232, which is electrically connected to the second electrode T5d of the fifth transistor T5 through a via 349, and is used to electrically connect the second electrode T5d of the fifth transistor T5 to the pixel electrode 134 of the light-emitting element through a via 350. For example, the via 349 penetrates the insulating layers 401, 402 and 403.

[0236] For example, such as Figures 9A-9BAs shown, the conductive layer 503 also includes a connection electrode 233. One end of the connection electrode 233 is electrically connected to the reset voltage line 240 through a via 348, and the other end is electrically connected to the first terminal T6s of the sixth transistor T6 through a via 347, so that the first terminal T6s of the sixth transistor T6 can receive the first reset voltage Vinit1 from the reset voltage line 240. For example, the via 348 penetrates the insulating layer 403. For example, the via 347 penetrates the insulating layers 401, 402, and 403.

[0237] In other examples, such as Figure 9C As shown, the semiconductor layer 102 includes a connection portion 104, which is conductiveized to become a conductor. The connection portion electrically connects the reset voltage line 240 (an example of the first reset voltage line of this disclosure) to the first electrode T6s of the reset transistor (i.e., the sixth transistor T6) in the sub-pixel. This arrangement eliminates the need for connecting electrodes 232 and vias 347, thereby simplifying the design.

[0238] For example, the orthographic projection of the connection portion on the substrate overlaps with the orthographic projection of the reset voltage line 240 on the substrate and the orthographic projection of the first electrode T6s of the reset transistor on the substrate.

[0239] For example, such as Figures 9B-9C As shown, the first terminal of the seventh transistor T7 in the previous row of sub-pixels is electrically connected to the first terminal of the sixth transistor T6 in the current row of sub-pixels, and is also connected to the reset voltage line 240 corresponding to the current row of sub-pixels (i.e., Figure 9B The topmost reset voltage line 240 is electrically connected to receive the second reset voltage Vinit2. The first terminal of the seventh transistor T7 in this row of sub-pixels is electrically connected to the first terminal of the sixth transistor T6 in the next row of sub-pixels, and is also connected to the reset voltage line 240 corresponding to the next row of sub-pixels (i.e., Figure 9B The middle reset voltage line 240 is electrically connected to receive the second reset voltage Vinit2.

[0240] like Figures 9A-9B As shown, the conductive layer 503 also includes multiple reset voltage lines 260 extending along the second direction D2. For example... Figure 9B As shown, each reset voltage line 260 is electrically connected to the reset voltage line 240 in the conductive layer 502 through the via 351, thereby forming a cross-shaped conductive mesh structure. This conductive mesh structure can reduce resistance, thereby reducing voltage drop and helping to uniformly transmit the reset voltage to each sub-pixel on the substrate.

[0241] For example, such as Figure 9BAs shown, each pair of adjacent reset voltage lines 260 is spaced two columns of sub-pixels apart. That is, the reset voltage line 260 and the sub-pixel column are not arranged in a one-to-one correspondence, which can reduce the wiring density. For example, in a set of signal lines between two adjacent columns of sub-pixels, the reset voltage line 260 and the power line 250 are directly adjacent to the data line 12 and are located on opposite sides of the data line 12. The reset voltage line 260 is located on the side of the data line 12 away from the sub-pixel column electrically connected to the data line 12.

[0242] For example, refer to Figure 8C and 9B -9C, the structure in which the first capacitor electrodes Ca of two adjacent sub-pixels in the first direction D1 are connected to each other as one unit, can also be regarded as the two first capacitor electrodes Ca being connected through the middle connecting part, and multiple data lines overlapping with multiple connecting parts in a direction perpendicular to the substrate.

[0243] The connection portion includes a first portion that overlaps with the corresponding data line 12 and a second portion that does not overlap with the corresponding data line; for example, the size of the first portion in the second direction D2 is larger than the size of the second portion in the second direction D2.

[0244] Since the first power supply voltage VDD is applied to the first capacitor electrode Ca, this setting can increase the capacitance between the first capacitor electrode Ca and the data line, thereby increasing the voltage holding capability of the first capacitor electrode.

[0245] For example, the smaller longitudinal portion overlaps with the reset voltage line 260 in a direction perpendicular to the substrate, thereby minimizing the interference of the first power supply voltage on the signal on the reset voltage line 260.

[0246] Combination Figures 6A-6B and Figure 10A As shown, the conductive layer 504 includes a first electrode (i.e., pixel electrode) 134 for the light-emitting element. The first electrode 134 of the light-emitting element of each sub-pixel is electrically connected to the connection electrode 232 in that sub-pixel through a via 350, and is thereby electrically connected to the second electrode T5d of the fifth transistor T5 through the connection electrode 233. The via 350, for example, penetrates the insulating layer 504. Figure 10A The contact area of ​​the first electrode 134 that contacts the via 350 is schematically shown in circles.

[0247] For example, refer to Figures 6A-6BThe display substrate 20 may further include a pixel defining layer 405 located on the first electrode of the light-emitting element. An opening is formed in the pixel defining layer 405 to expose at least a portion of the pixel electrode 134, thereby defining the pixel opening region (i.e., the effective light-emitting region) 600 of each sub-pixel of the display substrate. An organic functional layer 136 of the light-emitting element 120 is formed at least within this opening, and a second electrode 135 is formed on the organic functional layer 136 to form the light-emitting element 120. For example, the second electrode 135 may be a common electrode, arranged across the entire surface of the display substrate 20. For example, the first electrode 134 may be the anode of the light-emitting element, and the second electrode 135 may be the cathode of the light-emitting element. Figure 10A The pixel opening area 600 of each sub-pixel is schematically shown in rectangles, however, this is not intended to limit the present disclosure.

[0248] like Figure 10A As shown, the conductive layer 504 may also include a plurality of reset voltage lines 270 extending along the first direction D1. The reset voltage lines 270 are, for example, a zigzag structure, such as a Z-shape extending along the first direction D1, in order to match the shape of the first electrode 134 so as to facilitate wiring.

[0249] For example, the reset voltage line 270 is connected in parallel with the reset voltage line 260 and / or the reset voltage line 240 to further reduce the resistance of the reset voltage line and thus reduce the voltage drop on the reset voltage line. For example, the reset voltage line 270 is electrically connected with the reset voltage line 260 and / or the reset voltage line 240 in a non-display area. The reset voltage line 270 is not required.

[0250] It should be noted that the distribution of the first electrode of the light-emitting element of the display substrate provided in this embodiment is not limited to... Figure 10A The situation shown applies to the distribution of other pixel electrodes as well. Figure 10B This is a distribution diagram of the first electrode 134 of the light-emitting element provided in other embodiments of this disclosure. Figure 10C The connection between the first electrode and the pixel circuit below is shown.

[0251] like Figure 10B As shown, every four first electrodes 134 constitute an electrode group. The four first electrodes 134 in this electrode group correspond to one blue pixel, one red pixel, and two green pixels, respectively. The two green pixels are arranged opposite each other in a first direction, and the blue and red pixels are arranged opposite each other in a second direction. For example, as... Figure 10B As shown, the via 350 of the red pixel and the corresponding via 349 do not overlap in the direction perpendicular to the substrate.

[0252] The two green pixels have the same shape and area, while the blue, green, and red pixels each have different areas. For example, the least efficient blue sub-pixel has the largest area, and the most efficient red sub-pixel has the smallest area, to achieve better color intensity and image sharpness.

[0253] For example, the materials of each conductive layer may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloys composed of the above metals; or conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), etc.; or multilayer metal stacked structures; or metal and conductive metal oxide stacked structures.

[0254] For example, conductive layer 504 includes a TI / AL / TI stacked structure.

[0255] For example, the conductive layer 505 is made of a transparent conductive material, such as a metal oxide material, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), etc. For example, the conductive layer 505 includes an ITO / AG / ITO stacked structure.

[0256] For example, the light-emitting element 120 is a top-emitting structure, with the first electrode (i.e., pixel electrode) 134 being reflective and the second electrode 135 being transmissive or semi-transmissive. For example, the first electrode 134 is the anode, and the second electrode 135 is the cathode. For example, the first electrode 134 is an ITO / Ag / ITO stacked structure; the transparent conductive material ITO is a high work function material, and direct contact with the light-emitting material can improve the hole injection rate; the metallic material Ag helps to improve the reflectivity of the first electrode. For example, the second electrode 135 is a low work function material to act as the cathode, such as a semi-transmissive metal or metal alloy material, such as an Ag / Mg alloy material.

[0257] For example, the materials of each insulating layer are inorganic insulating layers, such as silicon oxide, silicon nitride, silicon oxynitride, etc., silicon oxides, silicon nitrides, or silicon oxynitrides, or insulating materials including metal oxynitrides such as aluminum oxide and titanium nitride.

[0258] For example, the pixel defining layer 405 is made of organic materials, such as polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA), and other organic insulating materials.

[0259] For example, the substrate 100 can be a rigid substrate, such as a glass substrate or a silicon substrate, or it can be formed of a flexible material with excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyaryl compounds, polyetherimide, polyethersulfone, polyethylene glycol terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), cellulose triacetate (TAC), cyclic olefin polymer (COP), and cyclic olefin copolymer (COC).

[0260] For example, the materials of the semiconductor layer 102 include, but are not limited to, silicon-based materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.) and organic materials (hexathiophene, polythiophene, etc.).

[0261] For example, the display substrate 20 includes Figure 2 The structure shown in this embodiment is used to... Figure 2 The connection structure shown is provided as an example at the connection between the first electrode 134 and the connecting electrode 232, but this is not intended to limit the scope of this disclosure.

[0262] Reference Figures 6A-6B The connecting electrode 232 (an example of the first conductive structure of this disclosure) includes a bottom surface 232a near the substrate, a top surface 232b away from the substrate, and a first side surface 232c located between the bottom surface 232a and the top surface 232b. The connecting electrode 232 is electrically connected to the first electrode 314 of the light-emitting element (an example of the second conductive structure of this disclosure) through a via 350 (an example of the first via of this disclosure). Via 350 and via 349 (an example of the first recessed structure of this disclosure) at least partially overlap in a direction perpendicular to the substrate, such that insulating layer 404 (an example of the second insulating layer of this disclosure) is recessed downwards, via 350 exposes at least a portion of the first side surface 232c of the connecting electrode 232, and causes the first electrode 314 of the light-emitting element to be recessed downwards and includes a protrusion 314a (an example of the first protrusion of this disclosure), the protrusion 314a contacting at least a portion of the first side surface 232c and covering the portion of the first side surface 232c exposed by the via 350.

[0263] like Figures 6A-6B As shown, the portion of the connecting electrode 232 and the portion of the first electrode 134 that directly contacts the connecting electrode 232 are both located between the signal lines on both sides.

[0264] like Figures 6A-6BAs shown, the protrusion 314a is located between the signal lines on both sides of the pixel column (an example of the first pixel column of this disclosure) where the sub-pixel is located, that is, between the first signal line on the left and the second signal line on the right. The first signal line is, for example, a data line 12 or a power line 250 connected to the sub-pixel. The second signal line is, for example, a reset voltage line 260, a data line 12 or a power line 250 on the right. The data line 12 and the power line 250 on the right are connected to the pixel column adjacent to the pixel column (an example of the second pixel column of this disclosure). That is, the orthographic projection of the protrusion 314a on the substrate 100 is located between the first signal line and its orthographic projection on the substrate and the orthographic projection of the second signal line on the substrate.

[0265] like Figure 6A As shown, the orthographic projection of the first electrode 134 of the light-emitting element of the first pixel column on the substrate at least partially overlaps with the orthographic projection of the power line 250 on the substrate to its left and the orthographic projection of the data line 12 on the substrate to its right.

[0266] like Figure 6B As shown, the orthographic projection of the electrode of the light-emitting element of the first pixel column on the substrate near the substrate is at least partially overlapped with the orthographic projection of the first signal line on the substrate and the orthographic projection of the second signal line on the substrate.

[0267] By positioning the protrusion 134a of the first electrode 134 in contact with the first side surface 232c of the connecting electrode 232, not only is the contact area between the first electrode 134 and the connecting electrode 232 increased, reducing their contact resistance, but the longitudinal cross-sectional area of ​​the first electrode 134 is also effectively increased. Furthermore, positioning the protrusion 134a between the first signal line and the second signal line can reduce mutual interference between them. For example, since high-frequency signals are transmitted in the data lines, they can easily interfere with signals in other signal lines. For instance, the protrusion 134a can reduce interference from one side's data line 12 to signals in other side's signal lines (such as data lines, power lines, reset voltage lines, etc.).

[0268] Reference Figure 2 and Figures 6A-6B , Figure 2 The structure shown can be viewed as part of the cross-sectional structure of the display substrate 20 along the section line A-A', that is... Figure 6B The structure outlined by the dashed circle in the middle, Figure 6B The connecting electrode 232, the first electrode 134, the protrusion 134a, the through hole 350, and the through hole 349 can be respectively regarded as Figure 2The first conductive structure 21, the second conductive structure 22, the protrusion 220, the through hole V1, and the recessed structure G1 are included. For Figure 2 The description also applies to Figure 6B This will not be elaborated upon here.

[0269] For example, such as Figures 6A-6B As shown, the connecting electrode 232 includes a protrusion 232t facing the via 349, and the orthographic projection of the protrusion 232t on the substrate is located within the orthographic projection of the via 349 on the substrate.

[0270] like Figure 6A As shown, the distance between the orthographic projection of the protrusion 134a on the substrate and the orthographic projection of the power line 250 (an example of a first signal line of this disclosure) on the substrate on the left, in the reference direction F (e.g., the first direction D1), is l. This reference direction F is parallel to the surface of the substrate, for example, parallel to the first direction D1. For example, the lowest point of the protrusion 134a can be measured during measurement. The distance between the orthographic projection of the data line 12 (an example of a second signal line of this disclosure) on the substrate and the orthographic projection of the power line 250 on the substrate on the right, in the first reference direction F, is m.

[0271] exist Figure 6B In the cross-section shown, the portion of the connecting electrode 232 located on the side of the insulating layer 403 away from the substrate has a dimension e in the direction perpendicular to the substrate, and the portion of the first side surface 232c covered by the protrusion 134a has a dimension d in the direction perpendicular to the substrate. For example, l / m > 0.9 (d / e). For example, l / m > 1.2 (d / e).

[0272] The farther the protrusion 134a is from the power line 250, the worse the shielding effect of the right-side data line 12 on the left-side power line 250 becomes, thus requiring more coverage of the first side surface 232c. Through this arrangement, it can be ensured that the protrusion 134a can effectively shield the data line 12 from interference with the signal on the power line 250.

[0273] For example, such as Figures 6A-6B As shown, the orthographic projection of the multiple pixel opening areas 600 on the substrate is separate from the orthographic projection of the protrusion 134a on the substrate, that is, they do not overlap. This avoids display defects such as color shift caused by the unevenness of the light-emitting material in the effective light-emitting area (i.e., pixel opening area) due to the setting of the protrusion 134a.

[0274] Figure 11This is a schematic diagram of a display substrate provided in some other embodiments of the present disclosure. The diagram shows the orthographic projection of the conductive layer 504 and vias 349 and 350 on the substrate. The vias 350 are schematically represented by hollow circles and the vias 349 by solid circles.

[0275] like Figure 11 As shown, insulating layer 403 includes a plurality of vias 349, each via 349 corresponding to a plurality of sub-pixels. The plurality of vias 349 are arranged along a first direction D1 and a second direction D2 to form a plurality of via rows and a plurality of via columns. Insulating layer 404 includes a plurality of vias 350, each via 350 corresponding to a plurality of sub-pixels and configured to correspond one-to-one with the plurality of vias 349. The plurality of vias 349 are arranged along the first direction D1 and the second direction D2 to form a plurality of via rows and a plurality of via columns.

[0276] For example, the overlap between via 349 and via 350 differs in each sub-pixel. Figure 11 As shown, in the pixel column where sub-pixel P1 is located, the orthographic projections of vias 349 and 350 on the substrate do not overlap, therefore they cannot form a [pixel structure]. Figure 2 or Figure 6B The structure shown.

[0277] For example, for each row of sub-pixels, every other sub-pixel has 3 consecutive adjacent sub-pixels with the following characteristics: Figure 2 or Figure 6B The structure shown indicates that for each row of vias 350, there are three consecutive vias 350 every other via 350. Each of these three vias 350 overlaps with its corresponding via 349 in a direction perpendicular to the substrate, forming a structure as shown. Figure 2 or Figure 6B The structure shown; the via 350 and the corresponding via 349 do not overlap in the direction perpendicular to the substrate. For example, the via corresponds to a red pixel.

[0278] For example, a multi-column subpixel includes a pixel column, where each subpixel in the pixel column has the following characteristics: Figure 2 or Figure 6B The structure shown (e.g.) Figure 11 (as shown in columns 1, 3, 4, and 5), or every other sub-pixel there exists a sub-pixel with the following characteristics: Figure 2 or Figure 6B The structure shown indicates that there is a row of vias 350, with each via 350 overlapping with its corresponding via 349 in a direction perpendicular to the substrate, forming a structure as shown. Figure 2 or Figure 6B The structure shown; or every other via 350, there exists a via 350 that overlaps with the corresponding via 349 in a direction perpendicular to the substrate, forming a structure as shown. Figure 2or Figure 6B The structure shown.

[0279] Figures 12A-12C This is a schematic diagram of a display substrate provided in some other embodiments of the present disclosure. The diagram shows the orthographic projection of the conductive layer 504, the pixel defining layer 405, and the vias 349 and 350 on the substrate. The vias 350 are schematically represented by hollow circles and the vias 349 by solid circles.

[0280] The pixel defining layer 405 includes multiple pixel opening regions 600 and non-opening regions. For example, the pixel defining layer 405 further forms multiple spaced protrusions 405a in the non-opening regions, meaning the pixel defining layer 405 has a non-uniform thickness. The protrusions 405a can support the mask during vapor deposition. In some examples, these protrusions are also referred to as spacers.

[0281] like Figures 12A-12C As shown, for example, the protrusion is cone-shaped. Figures 12A-12C The bottom and top of the protrusion 405a are schematically shown on the substrate using hollow and solid ellipses, respectively.

[0282] For example, the orthographic projection of the via 350 on the substrate is separate from the orthographic projection of the portion with the maximum thickness of the pixel defining layer on the substrate (i.e., the orthographic projection of the top of the protrusion 405a), meaning they do not overlap. This arrangement avoids the adverse effects of unevenness at the top of the protrusion 405a caused by the via 350 on its support function. For example, unevenness of the protrusion 405a may cause the mask to tilt, thereby affecting the unevenness of the organic functional layers (including the light-emitting layer) formed by vapor deposition.

[0283] like Figures 12A-12C As shown, the protrusion 405a can have different densities. For example, one protrusion can be set around the perimeter of a pixel opening area 600 (e.g., Figure 12A As shown), 2 (as shown) Figure 12B (as shown) or 3 (such as) Figure 12C (As shown) Protrusion 405a. The density of the protrusions can be determined based on the gap between the first electrodes 134. A higher density can improve the support stability of the mask plate.

[0284] like Figure 12C As shown, the pixel opening area 600 is surrounded by three protrusions 405a, namely a first protrusion 405a1, a second protrusion 405a2 and a third protrusion 405a3. The first protrusion 405a1, the second protrusion 405a2 and the third protrusion 405a3 are arranged around the pixel opening area 600, and the line connecting the center of their orthogonal projection on the substrate forms a triangle.

[0285] For example, such as Figure 12C As shown, the first protrusion 405a1 is located between four adjacent pixel opening areas 600, and the second protrusion 405a2 and the third protrusion 405a3 are located between two adjacent pixel opening areas, respectively. For example, the area of ​​the orthographic projection of the first protrusion 405a1 on the substrate is larger than the area of ​​the orthographic projection of the second protrusion 405a2 on the substrate and the area of ​​the orthographic projection of the third protrusion 405a3 on the substrate, respectively.

[0286] For example, such as Figure 9D As shown, the display substrate also includes a dummy area, such as... Figure 9D The first column of sub-pixels from the left in the middle has a pixel structure that is basically the same as that of the display area. The main difference is that there are no light-emitting elements or a first electrode 134 (i.e., the second conductive structure) in the virtual area. In other words, in this column of sub-pixels, the orthographic projection of the first conductive structure on the substrate is separate from the orthographic projection of the second conductive layer on the substrate. The purpose of this virtual area is to improve the uniformity of the process.

[0287] like Figure 9D As shown, the arrangement of the connecting electrode 232 (i.e., the first conductive structure) in the virtual area is the same as that in the effective display area, and the connection method of the connecting electrode 232 is also the same as that in the effective display area, which will not be described again here.

[0288] For example, in this case, the sub-pixel column in the virtual area (an example of the third pixel column in this disclosure, Figure 9D The data lines (an example of the third signal line of this disclosure) and power lines (an example of the fourth signal line of this disclosure) corresponding to the first column of sub-pixels from the left in the middle are electrically connected to each other. That is, the two signal lines provide the same signal, such as a power supply voltage signal, and are located on the same side of the pixel column. Since there is no problem of signal interference between virtual areas, there is no need to provide a protrusion of the first electrode 134 for shielding.

[0289] The following Figure 5B Taking the pixel circuit shown as an example, and combining it with Figures 13A-13B , Figure 14 , Figure 15 , Figures 16A-16C , Figures 17A-17B , Figures 18A-18C and Figures 19A-19C The structure of the display substrate provided in other embodiments of this disclosure will be described by way of example.

[0290] Figure 13A This is a schematic diagram of a display substrate 20 provided in other embodiments of this disclosure. Figure 13B for Figure 13A A sectional view along section line B-B'. It should be noted that, for clarity, Figure 13B Some structures that do not have direct electrical connections at the cross-section line have been omitted.

[0291] like Figure 13A As shown, the display substrate 20 includes a substrate 100, on which a plurality of sub-pixels are located. The pixel circuits of the plurality of sub-pixels P are arranged in a pixel circuit array, for example, the row direction of the pixel circuit array is a first direction D1, and the column direction is a second direction D2. In some embodiments, the pixel circuits of each sub-pixel may have the exact same structure, that is, the pixel circuits are repeatedly arranged in the row and column directions.

[0292] For ease of explanation, Figure 13A The example shows four columns of sub-pixels. For example, as shown... Figure 13A As shown, the arrangement rule of the pixel circuit of a sub-pixel can be the same as or different from the arrangement rule of the pixel electrode (i.e., the first electrode of the light-emitting element) above it. For ease of explanation, the description of the sub-pixel arrangement here refers to the arrangement rule of the pixel circuit, and the description of the relative positional relationship of the sub-pixels refers to the relative position of the pixel circuit of that sub-pixel. For example, adjacent sub-pixels refer to sub-pixels whose pixel circuits are adjacent to each other. The following embodiments are the same and will not be described again.

[0293] For example, such as Figures 13A-13B The display substrate 20 includes a semiconductor layer 105, an insulating layer 601, a conductive layer 711, an insulating layer 602, a conductive layer 712, an insulating layer 603, a semiconductor layer 106, an insulating layer 604, a conductive layer 713, an insulating layer 605, a conductive layer 714, an insulating layer 606, a conductive layer 715, an insulating layer 607, and a conductive layer 716, which are sequentially stacked on the substrate 100.

[0294] Figure 14 Corresponding to Figure 13A The diagram illustrates the semiconductor layer 105 and the conductive layer 711 (an example of the first metal layer of this disclosure). Figure 15 exist Figure 14 The pattern of conductive layer 712 is shown based on this. Figure 16A exist Figure 15 The pattern of semiconductor layer 106 and conductive layer 713 is shown on the basis; Figure 17A Conductive layer 714 is shown. Figure 17B exist Figure 16A The conductive layer 714 is shown based on this; Figure 18A Conductive layer 715 is shown. Figure 18B exist Figure 17B The conductive layer 715 is shown based on this.

[0295] For ease of explanation, in the following description, Tng, Tns, Tnd, and Tna represent the gate, first electrode, second electrode, and channel region of the nth transistor Tn, respectively, where n is 1-7.

[0296] It should be noted that the term "same-layer arrangement" in this disclosure refers to two (or more) structures formed through the same deposition process and patterned through the same patterning process, and they are not necessarily located on the same horizontal plane; their materials may be the same or different. The term "integrated structure" in this disclosure refers to a structure formed by two (or more) structures through the same deposition process and patterned through the same patterning process, and their materials may be the same or different.

[0297] For example, such as Figure 14 As shown, the semiconductor layer 105 includes channel regions (T1a, T2a, T4a, T5a, T7a) of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7, as well as first electrodes (T1s, T2s, T4s, T5s, T7s) and second electrodes (T1d, T2d, T4d, T5d, T7d).

[0298] For example, the display substrate 20 employs a self-aligned process, using the conductive layer 711 as a mask to perform a conductor-enhancing treatment (e.g., doping) on ​​the semiconductor layer 105, so that the portion of the semiconductor layer 105 not covered by the conductive layer 711 is conductor-enhanced. This conductor-enhanced portion of the semiconductor layer located on both sides of the channel region of each transistor forms the first and second electrodes of the transistor, respectively. For example, the material of the semiconductor layer 105 is low-temperature polycrystalline silicon.

[0299] For example, such as Figure 14 As shown, the conductive layer 711 also includes scan lines 710, reset control lines 720, and light emission control lines 730 that are insulated from each other. These signal lines can all serve as... Figure 4 An example of gate line 11 is shown.

[0300] Scan line 710 is electrically connected (or integrated) to the gate T2g of the second transistor T2 in the corresponding row of sub-pixels to provide a first scan signal Ga1. Reset control line 720 is electrically connected to the gate T6g of the sixth transistor T6 in the corresponding row of sub-pixels to provide a first reset control signal Rst1. Light emission control line 730 is electrically connected to the gate T4g of the fourth transistor T4 in the corresponding row of sub-pixels to provide a first light emission control signal EM1. For example, scan line 710 of the current row of sub-pixels can serve as reset control line 720 of the next row of sub-pixels.

[0301] For example, such as Figure 14As shown, the light-emitting control line 730 is also electrically connected to the gate T5g of the fifth transistor T5 to provide a second light-emitting control signal EM2, that is, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are the same signal.

[0302] For example, such as Figure 15 As shown, the conductive layer 712 (an example of the second metal layer of this disclosure) includes a first capacitor electrode Ca. This first capacitor electrode Ca overlaps with the gate T1g of the first transistor T1 in a direction perpendicular to the substrate 100 to form a storage capacitor Cst; that is, the gate T1g of the first transistor T1 acts as the second capacitor electrode Cb of the storage capacitor Cst. For example, the first capacitor electrode Ca includes an opening 722 that exposes at least a portion of the gate T1g of the first transistor T1 to facilitate electrical connection between the gate T1g and other structures. For example, the first capacitor electrodes Ca of sub-pixels located in the same pixel row are connected to each other as a single unit.

[0303] like Figure 15 As shown, the sizes of the openings 722 in adjacent sub-pixels in the first direction D1 are not consistent. For example, the sub-pixel with a larger opening 722 is a green pixel, and the sub-pixel with a smaller opening 722 is a red pixel or a blue pixel.

[0304] The green pixel's activation voltage and data signal differ from those of the red and blue pixels. Therefore, the green pixel's driving circuit needs adjustment to increase its charging speed, thereby improving display uniformity. By setting a larger opening 722, the area of ​​the first capacitor electrode Ca can be reduced, resulting in a smaller storage capacity Cst for the green pixel, thus increasing the charging speed. In other embodiments, the storage capacitance of the green pixel can be reduced in other ways, such as reducing the area of ​​the second capacitor electrode Cb or adjusting the aspect ratio of the driving transistor.

[0305] For example, the conductive layer 712 may also include a first auxiliary control line 721, a second auxiliary control line 725, and reset voltage lines 723 and 724 extending along the first direction D1, which will be discussed later in conjunction with... Figure 16A and Figures 17A-17B This will be explained in detail.

[0306] like Figure 16A As shown, semiconductor layer 106 includes channel regions (T3a, T6a) of third transistor T3 and sixth transistor T6, first electrodes (T3s, T6s) of third transistor T3 and sixth transistor T6, and second electrodes (T3d, T6d) of third transistor T3 and sixth transistor T6. Conductive layer 713 includes scan lines 740 and reset control lines 750 extending along a first direction D1.

[0307] For example, the material of semiconductor layer 106 is an oxide semiconductor, such as IGZO, ZnO, AZO, IZTO, etc.

[0308] Metal-oxide-slim transistors (MTBTs) have the advantage of low leakage current. Since both the third transistor T3 and the sixth transistor T6 are directly connected to the gate of the first transistor T1 (i.e., the driving transistor), their stability directly affects the stability of the gate voltage (N1 node) of the first transistor T1. Using N-type MTBTs for the third and sixth transistors helps reduce leakage current, thus helping to maintain the voltage at the N1 node. This allows for sufficient compensation of the threshold voltage of the first transistor T1 during the compensation phase, thereby improving the display uniformity of the display substrate during the light-emitting stage.

[0309] For example, the display substrate 20 uses a self-aligned process, using the conductive layer 713 as a mask to perform a conductor treatment (e.g., doping) on ​​the semiconductor layer 106, so that the portion of the semiconductor layer 106 not covered by the conductive layer 713 is conductor-conductive, thereby the portion of the semiconductor layer 106 located on both sides of the channel region of the third transistor T3 and the sixth transistor T6 is conductor-conductive to form the first electrode and the second electrode of the third transistor T3 and the sixth transistor T6, respectively.

[0310] For example, in conjunction with reference Figures 13A-13B and Figure 16A In a direction perpendicular to the substrate, the scan line 740 at least partially overlaps with the first auxiliary control line 721; for example, the orthogonal projection of the channel region T3a of the third transistor T3 located below the scan line 740 on the substrate lies within the orthogonal projection of the first auxiliary control line 721 on the substrate.

[0311] Thus, the first auxiliary control line 721 can act as a light-shielding layer, preventing light from entering the channel region of the third transistor T3 from the back and thus adversely affecting its characteristics. For example, oxide semiconductor materials are relatively sensitive to light. When the third transistor T3 uses oxide semiconductor material as its channel region, light entering the channel region can easily cause threshold voltage drift in the third transistor T3. By setting the first auxiliary control line 721, the stability of the third transistor T3 can be improved, further stabilizing the gate voltage of the first transistor T1.

[0312] For example, the scan line 740 and the first auxiliary control line 721 are configured to receive the same scan signal, thereby forming a double-sided gate structure for the third transistor T3, which improves the gate control capability of the third transistor T3 and further stabilizes the gate voltage of the first transistor T1.

[0313] For example, in conjunction with reference Figures 13A-13B and Figure 16A In a direction perpendicular to the substrate, the reset control line 750 at least partially overlaps with the substrate; for example, the orthogonal projection of the channel region T6a of the sixth transistor T6 located below the reset control line 750 on the substrate lies within the orthogonal projection of the second auxiliary control line 725 on the substrate.

[0314] Thus, the second auxiliary control line 725 can act as a light-shielding layer, preventing light from entering the channel region of the sixth transistor T6 from the back and thus adversely affecting its characteristics. For example, oxide semiconductor materials are relatively sensitive to light. When the sixth transistor T6 uses oxide semiconductor material as its channel region, light entering the channel region can easily cause threshold voltage drift in the sixth transistor T6. By setting the second auxiliary control line 725, the stability of the sixth transistor T6 can be improved, further stabilizing the gate voltage of the first transistor T1.

[0315] For example, the reset control line 750 and the second auxiliary control line 725 are configured to receive the same scan signal, thereby forming a double-sided gate structure for the sixth transistor T6, which improves the gate control capability of the sixth transistor T6 and further stabilizes the gate voltage of the first transistor T1.

[0316] In other examples, the active layer of the seventh transistor T7 can also be disposed in the semiconductor layer 106, for example, using an oxide semiconductor material. Since the first transistor T7 is directly electrically connected to the first electrode 134 of the light-emitting element 120, this arrangement can reduce the leakage current of the seventh transistor T7, improve the stability of the potential of the first electrode 134, and thus improve the stability of light emission.

[0317] like Figure 16B As shown, in this configuration, the conductive layer 712 further includes an auxiliary control line 810 (an example of a first reset control line of this disclosure), and the conductive layer 713 further includes a reset control line 820 (an example of a second reset control line of this disclosure). The reset control line 820 and the auxiliary control line 810 are configured to provide gate voltage control for the seventh transistor T7. For example, the reset control line 820 and the auxiliary control line 810 are configured to receive the same scan signal, thereby enabling the seventh transistor T7 to form a double-sided gate structure, which improves the gate control capability of the seventh transistor T7 and further stabilizes the voltage of the first electrode 134.

[0318] In a direction perpendicular to the substrate, the reset control line 820 and the auxiliary control line 810 at least partially overlap; for example, the orthogonal projection of the channel region of the seventh transistor T7 located below the reset control line 820 onto the substrate lies within the orthogonal projection of the auxiliary control line 810 onto the substrate.

[0319] In this case, the connection method of the seventh transistor T7 needs to be adjusted accordingly. For example, the second terminal T7d of the seventh transistor T7 and the second terminal T5d of the fifth transistor T5 are no longer directly electrically connected in the semiconductor layer 105, but need to be electrically connected through a via, which will not be elaborated here.

[0320] Figure 16C Schematic diagrams of display substrates provided in some examples of this disclosure are shown, such as... Figure 16C As shown, the display substrate also includes a light-shielding layer LS located on the semiconductor layer 105 near the substrate 100. The light-shielding layer LS is used to shield the channel region of the transistor, thereby preventing threshold drift of the transistor caused by light (e.g., from the back or side) incident on the channel region. For example, the light-shielding layer LS includes a first light-shielding pattern LS1, which is correspondingly disposed to the channel region T1a of the first transistor. The orthographic projection of the channel region T1a on the substrate falls within the first light-shielding pattern LS1, thereby shielding the channel region of the first transistor and improving the stability of the first node N1.

[0321] For example, the light-shielding layer LS may also include a second light-shielding pattern LS2, which is disposed corresponding to the channel regions of the third transistor T3 and the sixth transistor T6. The orthogonal projection of the channel regions of the third transistor T3 and the sixth transistor T6 onto the substrate falls within the second light-shielding pattern LS2, thereby shielding the channel regions of the third transistor T3 and the sixth transistor T6, effectively reducing the leakage current of the third transistor T3 and the sixth transistor T6, and further improving the stability of the first node N1.

[0322] For example, the material of the light-shielding layer LS can be a metallic material, or an organic or inorganic insulating light-shielding material.

[0323] For example, in conjunction with reference Figures 13A-13B as well as Figures 17A-17B The conductive layer 714 includes a connection electrode 701. One end of the connection electrode 701 is electrically connected to the gate T1g of the first transistor T1, i.e. the second capacitor electrode Cb, through an opening 722 in the first capacitor electrode Ca and a via 901 in the insulating layer. The other end is electrically connected to the second electrode T3d of the third transistor T3 through a via 902, thereby electrically connecting the second capacitor electrode Cb to the second electrode T3d of the third transistor T3.

[0324] For example, in conjunction with reference Figures 13A-13B as well as Figures 17A-17BThe conductive layer 714 also includes a connecting electrode 703, which is electrically connected to the first electrode T3s of the third transistor T3 and the first electrode T5s of the fifth transistor T5 through vias 904 and 914 respectively, thereby electrically connecting the first electrode T3s of the third transistor T3 to the first electrode T5s of the fifth transistor T5.

[0325] For example, the conductive layer 714 also includes a connection electrode 704, which is electrically connected to the second electrode T5d of the fifth transistor T5 and the second electrode T7d of the seventh transistor T7 through a via 905, so as to electrically connect the second electrode T5d of the fifth transistor T5 and the second electrode T7d of the seventh transistor T7 to the first electrode 134 of the light-emitting element 120.

[0326] For example, the conductive layer 714 also includes a connection electrode 708 configured to apply a first power supply voltage VDD. The connection electrode 708 is electrically connected to the first electrode T4s of the fourth transistor T4 and the first capacitor electrode Ca through vias 909 and 915, respectively.

[0327] For example, the conductive layer 714 also includes a connection electrode 709, which is electrically connected to the first electrode T2s of the second transistor T2 through a via 908.

[0328] For example, such as Figures 17A-17B As shown, the conductive layer 714 also includes a connection electrode 702. For example, the connection electrode 702 is electrically connected to the first terminal T6s of the sixth transistor T6 (an example of the gate reset transistor of the present disclosure) and the reset voltage line 724 (an example of the first gate reset voltage line of the present disclosure) through vias 903 (an example of the fifth via of the present disclosure) and 913, respectively, thereby electrically connecting the first terminal T6s of the sixth transistor T6 to the reset voltage line 724, so that the first terminal T6s of the sixth transistor T6 can receive the first reset voltage Vinit1 from the reset voltage line 724.

[0329] For example, such as Figures 17A-17B As shown, the conductive layer 714 also includes a connection electrode 707, which is electrically connected to the first terminal T7s of the seventh transistor T7 (an example of the pixel electrode reset transistor of the present disclosure) and the reset voltage line 723 (an example of the first pixel electrode reset voltage line of the present disclosure) through the via 906 (an example of the fourth via of the present disclosure) and the via 907, respectively, thereby electrically connecting the first terminal T7s of the seventh transistor T7 to the reset voltage line 723, so that the first terminal T7s of the seventh transistor T7 can receive the second reset voltage Vinit2 from the reset voltage line 723.

[0330] For example, such as Figures 17A-17BAs shown, the conductive layer 714 also includes reset voltage lines 760 and 780 extending along the second direction D2. In the first direction D1, reset voltage lines 760 and 780 are alternately arranged, with two columns of sub-pixels spaced between adjacent reset voltage lines 760 and 780. The connecting electrodes 708 in these two columns of sub-pixels are, for example, an integral structure. Each pair of adjacent columns of sub-pixels shares one reset voltage line 760 or one reset voltage line 780. The reset voltage line 760 is configured to provide a second reset voltage Vinit2, and the reset voltage line 780 is configured to provide a first reset voltage Vinit1.

[0331] like Figures 17A-17B As shown, the reset voltage line 760 (an example of the second pixel electrode reset voltage line of this disclosure) is electrically connected to the connection electrode 707 in the adjacent sub-pixel, for example, in a structure that is integrated together, thereby being electrically connected to the lateral reset voltage line 723, thereby forming a cross-shaped mesh conductive structure. This mesh conductive structure can reduce resistance, thereby reducing voltage drop, which helps to uniformly transmit the second reset voltage Vinit2 to each sub-pixel on the substrate.

[0332] like Figures 17A-17B As shown, the reset voltage line 780 (an example of the second gate reset voltage line of this disclosure) is electrically connected to the connection electrode 702 in the adjacent sub-pixel, for example, in a structure that is integrated together, thereby being electrically connected to the lateral reset voltage line 724, thereby forming a cross-shaped mesh conductive structure. This mesh conductive structure can reduce resistance, thereby reducing voltage drop, which helps to uniformly transmit the first reset voltage Vinit1 to each sub-pixel on the substrate.

[0333] For example, the conductive layer 715 includes data lines 12 extending along the second direction D2. For example, the plurality of data lines 12 are electrically connected one-to-one with a plurality of columns of sub-pixels to provide a data signal Vd, and each data line 12 is electrically connected to the first terminal T2s of the second transistor T2 in the corresponding column of sub-pixels to provide the data signal Vd.

[0334] Reference Figures 18A-18B The data line 12 is electrically connected to the connection electrode 709 through the via 913, thereby connecting to the first electrode T2s of the second transistor T2.

[0335] For example, the conductive layer 715 also includes a plurality of power electrodes 920, which are disposed one-to-one with a plurality of sub-pixels to provide a first power supply voltage VDD. Each power electrode 920 includes a recessed structure for providing other conductive structures (such as the connecting electrodes 910 mentioned later). The power electrodes 920 corresponding to a row of sub-pixels are connected to each other to form a single structure, thereby forming a power line 770 extending along the second direction D2.

[0336] Reference Figures 18A-18B Each power line 770 is electrically connected to the connection electrode 708 in the corresponding column of sub-pixels through a via 914, thereby delivering the first power supply voltage VDD to the first electrode T4s of the fourth transistor T4 and the first capacitor electrode Ca through the connection electrode 708.

[0337] For example, such as Figure 18B As shown, a data line group is provided between every two adjacent columns of sub-pixels. This data line group includes two data lines 12, which provide data signals to the two columns of sub-pixels respectively. There are two columns of sub-pixels between two adjacent data line groups.

[0338] The orthographic projections of the two data lines 12 on the substrate 100 do not overlap with the orthographic projections of the reset voltage lines 760 and 780 on the substrate, thereby avoiding the generation of parasitic capacitance.

[0339] Adjacent power lines 770 are spaced apart from each other. For example, as Figures 18A-18B As shown, a data line group is provided between every two adjacent power lines 770, and two power lines 770 are spaced apart between adjacent data line groups. The two power lines between two adjacent data line groups are spaced apart to avoid overlapping with the reset voltage line 780 or reset voltage line 760 below, which would generate parasitic capacitance. In other words, the reset voltage line 780 and reset voltage line 760 are respectively positioned to correspond to the gap between two adjacent power lines 770.

[0340] Reference Figures 13A-13B as well as Figures 18A-18B The conductive layer 715 also includes a connection electrode 910, which is electrically connected to the connection electrode 704 through a via 911, so as to electrically connect the connection electrode 704 to the first electrode 134 of the light-emitting element 120. Figures 13A-13B As shown, the connecting electrode 910 is electrically connected to the first electrode 134 of the light-emitting element 120 through the via 912.

[0341] The aforementioned connecting electrodes 910 and 704 serve as transition electrodes, leading out the first electrode of the lower transistor to electrically connect it to the upper light-emitting element. This arrangement avoids the direct penetration of vias in the direction perpendicular to the substrate, which would cause the conductive material to fill too deeply, resulting in poor connection, broken lines, or unevenness. By setting transition electrodes, the depth of vias is reduced, and the contact yield is improved.

[0342] Figure 18C This is a schematic diagram of a display substrate provided for other embodiments of this disclosure. For example... Figure 18CAs shown, in this embodiment, the reset voltage line 780 can be vertically moved upward into the conductive layer 715, located between two adjacent power lines 770. Figure 19A and Figure 19B This is a schematic diagram of a display substrate provided for some embodiments of the present disclosure. Figures 18A-18B The main difference in the illustrated embodiment is that the location of the reset voltage lines 760 and 780 has changed. The reset voltage lines 760 and 780 are not located in the conductive layer 714, but in the conductive layer 715, and are located between the two data lines 12 in the data line group.

[0343] like Figure 19B As shown, reset voltage line 780 is electrically connected to reset voltage line 724 through via 918 (an example of a second via in this disclosure), thereby forming a cross-hatched mesh structure of reset voltage lines. Reset voltage line 760 is electrically connected to reset voltage line 723 through via 919 (an example of a third via in this disclosure), thereby forming a cross-hatched mesh structure of reset voltage lines.

[0344] like Figure 19A As shown, in the first direction, reset voltage lines 760 and 780 are alternately arranged and alternately located between two data lines 12 in the data line group. The two power lines 770 between adjacent data line groups are connected as a single unit. Since the gap between these two power lines 770 no longer corresponds to a reset voltage line 760 or reset voltage line 780, connecting these two power lines 770 as a single unit does not cause parasitic capacitance.

[0345] For example, such as Figure 19A As shown, in the first direction D1, each pair of adjacent power electrodes 920 are connected to form a power electrode group 777. This power electrode group 777 includes a cutout area 771 for locating the connection electrode 910 in the sub-pixel corresponding to the two power electrodes 920. For example, the conductive layer 715 also includes a connecting line 772 extending along the second direction D2 and located in the middle of each cutout area 771, dividing one cutout area into two cutout sub-areas (an example of a closed cutout area in this disclosure). The two connection electrodes 910 in the cutout area 771 are located within the two cutout sub-areas and on opposite sides of the connecting line 772. The connection line 772 helps to further reduce the resistance of the power line 770.

[0346] refer to Figures 13A-13BThe conductive layer 206 includes a first electrode 134 of the light-emitting element 120. The display substrate 20 may also include a pixel defining layer 608 located on the first electrode 134 of the light-emitting element. An opening is formed in the pixel defining layer 608 to expose at least a portion of the pixel electrode 134, thereby defining the opening region (i.e., the effective light-emitting region) 800 of each sub-pixel of the display substrate. A light-emitting layer 136 of the light-emitting element 120 is formed at least within this opening (the light-emitting layer 136 may also cover a portion of the surface of the pixel defining layer away from the first electrode of the light-emitting element), and a second electrode 135 is formed on the light-emitting layer 136 to form the light-emitting element 120. For example, the second electrode 135 may be a common electrode, arranged across the entire surface of the display substrate 20. For example, the pixel electrode 134 may be the anode of the light-emitting element, and the second electrode 135 may be the cathode of the light-emitting element.

[0347] It should be noted that the distribution of the first electrode of the light-emitting element of the display substrate provided in this embodiment is not limited to... Figure 13A The situation illustrated also applies to other pixel electrode distributions. For example... Figure 19C As shown, Figure 10B The distribution diagram of the first electrode 134 of the light-emitting element shown is also applicable to the display substrate provided in this embodiment.

[0348] For example, the materials of each conductive layer may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloys composed of the above metals; or conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), etc.; or multilayer metal stacked structures; or metal and conductive metal oxide stacked structures.

[0349] For example, the light-emitting element 120 is a top-emitting structure, with the first electrode (i.e., pixel electrode) 134 being reflective and the second electrode 135 being transmissive or semi-transmissive. For example, the first electrode 134 is the anode, and the second electrode 135 is the cathode. For example, the first electrode 134 is an ITO / Ag / ITO stacked structure; the transparent conductive material ITO is a high work function material, and direct contact with the light-emitting material can improve the hole injection rate; the metallic material Ag helps to improve the reflectivity of the first electrode. For example, the second electrode 135 is a low work function material to act as the cathode, such as a semi-transmissive metal or metal alloy material, such as an Ag / Mg alloy material.

[0350] For example, the materials of each insulating layer are inorganic insulating layers, such as silicon oxide, silicon nitride, silicon oxynitride, etc., silicon oxides, silicon nitrides, or silicon oxynitrides, or insulating materials including metal oxynitrides such as aluminum oxide and titanium nitride.

[0351] For example, the pixel defining layer 608 is made of organic materials, such as polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA), and other organic insulating materials.

[0352] For example, the substrate 100 can be a rigid substrate, such as a glass substrate or a silicon substrate, or it can be formed of a flexible material with excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyaryl compounds, polyetherimide, polyethersulfone, polyethylene glycol terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), cellulose triacetate (TAC), cyclic olefin polymer (COP), and cyclic olefin copolymer (COC).

[0353] For example, the materials of the semiconductor layers 105 and 106 include, but are not limited to, silicon-based materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), oxide semiconductor materials such as metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.), and organic materials (hexathiophene, polythiophene, etc.).

[0354] For example, the display substrate 20 includes Figure 2 The structure shown in this embodiment is used to... Figure 2 The connection structure shown is illustrated at the connection between the connecting electrode 704 and the connecting electrode 910, but this is not intended to limit the scope of this disclosure.

[0355] Reference Figures 13A-13B The connection electrode 704 (an example of the first conductive structure of this disclosure) includes a bottom surface 704a close to the substrate, a top surface 704b away from the substrate, and a first side surface 704c located between the bottom surface 704a and the top surface 704b.

[0356] The connecting electrode 704 is electrically connected to the connecting electrode 910 (an example of a second conductive structure of the present disclosure) through a via 911 (an example of a first via of the present disclosure). The via 911 and the via 905 (an example of a first recessed structure of the present disclosure) at least partially overlap in a direction perpendicular to the substrate, such that the insulating layer 606 (an example of a second insulating layer of the present disclosure) is recessed downwards. The via 911 exposes at least a portion of the first side surface 704c of the connecting electrode 704, and the connecting electrode 910 is recessed downwards and includes a protrusion 910a (another example of a first protrusion of the present disclosure) that contacts at least a portion of the first side surface 704c and covers the portion of the first side surface 704c exposed by the via 911.

[0357] Reference Figure 2 and Figures 13A-13B , Figure 2 The structure shown can be viewed as part of the cross-sectional structure of the display substrate 20 along the section line B-B', that is... Figure 13B The structure outlined by the dashed circle in the middle, Figure 13B The connecting electrode 704, connecting electrode 910, protrusion 910a, through hole 911, and through hole 905 can be respectively regarded as Figure 2 The first conductive structure 21, the second conductive structure 22, the protrusion 220, the through hole V1, and the recessed structure G1 are included. For Figure 2 The description also applies to Figure 13B This will not be elaborated upon here.

[0358] For example, such as Figures 13A-13B As shown, the connecting electrode 704 includes a protrusion 704t facing the via 905, and the orthographic projection of the protrusion 704t on the substrate is located within the orthographic projection of the via 905 on the substrate.

[0359] For example, in Figure 13B In the cross section shown, the via 905 has a dimension of b along the reference direction F, which is parallel to the surface of the substrate, for example, the second direction D2; the overlapping area of ​​the via 911 and the via 905 has a dimension of c along the reference direction F; and the portion of the first side surface 704c of the connecting electrode 704 covered by the connecting electrode 910 has a dimension of d in the direction perpendicular to the substrate.

[0360] like Figure 13B As shown, the connection electrode 704 includes a contact portion 724 located on the side of the insulating layer 605 away from the substrate and in contact with the connection electrode 910. The contact portion 724 can be considered, for example, as a longitudinal segment of the connection electrode 704 within the contact range with the connection electrode 910; the dimension of the contact portion 724 in the direction perpendicular to the substrate is e. The dimension of the first side surface 704c in the direction perpendicular to the substrate is n.

[0361] For example, in Figure 13B Within the cross-section shown, the maximum depth of the via 905 is i, the angle between one side of the via 905 and the surface of the substrate is j, and the dimension of the portion of the connecting electrode 910 that contacts the connecting electrode 704 in the direction perpendicular to the substrate is k. For example, d / e > 2.1*i*sin(j) / k.

[0362] For example, c / b is greater than 0.1; d / e is greater than 0.3. For example, c / b is greater than 0.28.

[0363] For example, d / n is greater than 0.6.

[0364] The size of the first side surface 704c covered is positively correlated with the depth of the via 905 and the bottom corner of the via 905, and negatively correlated with the thickness of the connecting electrode 910. Within a certain range, reducing d / e or c / b can reduce the overlap between the via 911 and the via 905, thereby reducing the size of the downward protrusion 910a of the connecting electrode 910, improving the flatness of the connecting electrode 910, and further improving the flatness of the upper pixel electrode, thus improving the display quality.

[0365] For example, d / e > 2.5*i*sin(j) / k.

[0366] The above arrangement can increase the overlap area of ​​the vertical connecting electrode 910 and the connecting electrode 704, thereby helping to reduce the planar area of ​​the via 911 and the via 905. Since the pixel aperture area 800 needs to avoid overlapping with the via 911 or the via 905 as much as possible to improve flatness, this arrangement can effectively improve the aperture ratio of the display substrate.

[0367] In one example, b = 56.8 μm, c = 8.1 μm, c / b = 0.143, d = 2.9 μm, e = 14.1 μm, d / e = 0.206.

[0368] In another example, b = 33.2 μm, c = 5.1 μm, c / b = 0.154, d = 3.1 μm, e = 9.1 μm, d / e = 0.341.

[0369] In yet another example, b = 99.1 μm, c = 26.0 μm, c / b = 0.262, d = 12.8 μm, e = 22.5 μm, d / e = 0.569.

[0370] For example, the average thickness of the protrusion 910a is less than the average thickness of the portion of the connecting electrode 910 that contacts the top surface 704b of the connecting electrode 704.

[0371] For example, for each sub-pixel, the protrusion 910a is located between the reset voltage line 760 / 780 connected to that sub-pixel and the connection electrode 708; that is, the orthographic projection of the protrusion 910a on the substrate 100 is located between the orthographic projection of the reset voltage line 760 / 780 on the substrate and the orthographic projection of the connection electrode 708 on the substrate. Since the first power supply voltage VDD is applied to the connection electrode 708, this arrangement helps to reduce signal interference between the reset voltage line 760 / 780 and the connection electrode 708.

[0372] Reference Figures 13A-13B As shown, for the first sub-pixel from the left in the figure, the protrusion 910a is located between the reset voltage line 760 connected to that column of sub-pixels and the connecting electrode 708. Figure 13AAs shown, the distance between the orthographic projection of the protrusion 910a on the substrate and the orthographic projection of the reset voltage line 760 on the substrate in the reference direction F (such as the first direction D1) is s1, and the distance between the orthographic projection of the protrusion 910a on the substrate and the orthographic projection of the connecting electrode 708 on the substrate in the reference direction F is s2. For example, s1 is less than s2. This arrangement can provide better shielding for the reset voltage line 70.

[0373] For example, such as Figure 17B As shown, the connecting electrode 708 includes an extension 708a extending from the main body in a first direction D1, the extension 708a protruding toward the reset voltage line 706, and the dimension of the extension 708a in a second direction D2 being smaller than the dimension of the main body in the second direction D2. In the second direction D2, the connecting electrode 704 at least partially overlaps with the extension 708a of the connecting electrode 708. This arrangement helps to further improve the effect of shielding the power supply voltage signal in the connecting electrode 708 from interference with the reset voltage line 706.

[0374] At least one embodiment of this disclosure also provides a display panel including any of the above-described display substrates 20. For example, the display panel is an OLED display panel, and correspondingly, the display substrate 20 it includes is an OLED display substrate. The display substrate 20 may or may not include light-emitting elements; that is, the light-emitting elements may be formed in a panel factory after the display substrate 20 is completed. In the case where the display substrate 20 itself does not include light-emitting elements, the display panel provided in the embodiments of this disclosure further includes light-emitting elements in addition to the display substrate 20.

[0375] like Figure 20 As shown, for example, the display panel 30 also includes an encapsulation layer 801 and a cover plate 802 disposed on the display substrate 20. The encapsulation layer 801 is configured to seal the light-emitting elements on the display substrate 20 to prevent external moisture and oxygen from penetrating into the light-emitting elements and driving sub-circuits and causing damage to the devices. For example, the encapsulation layer 801 includes an organic thin film or a structure including alternating layers of inorganic thin films, organic thin films, and inorganic thin films. For example, a water-absorbing layer (not shown) may also be disposed between the encapsulation layer 801 and the display substrate 20, configured to absorb residual moisture or sol from the light-emitting elements in the early manufacturing process. The cover plate 802 is, for example, a glass cover plate or a flexible cover plate. For example, the cover plate 802 and the encapsulation layer 801 can be an integral structure.

[0376] At least one embodiment of this disclosure also provides a touch display panel, which includes any of the above-described display substrates 20. The following will be combined with... Figure 21 and the touch display panel includes Figures 6A-6BThe touch display panel provided in at least one embodiment of this disclosure is illustrated using the display substrate shown as an example.

[0377] like Figure 21 As shown, the touch display panel 50 includes a display substrate 20 and a touch structure 520 stacked together, and also includes an insulating layer 406 located between the display substrate 20 and the touch structure 520. For example, the insulating layer 406 includes an encapsulation layer 406 configured to seal the light-emitting element 120 to prevent external moisture and oxygen from penetrating into the light-emitting element and driving circuit, thereby causing damage to devices such as the light-emitting element 120. For example, the encapsulation layer 406 can be a single-layer structure or a multi-layer structure, such as including organic thin films, inorganic thin films, or a multi-layer structure including alternating layers of organic and inorganic thin films. For example, the touch display panel also includes a buffer layer (not shown) located between the encapsulation layer 406 and the touch structure 520. This buffer layer is used to improve the adhesion between the touch structure 520 and the display substrate 20.

[0378] like Figure 21 As shown, the touch structure 520 includes a touch electrode 521, which is, for example, a block electrode or a metal mesh electrode.

[0379] In a direction perpendicular to the substrate, the protrusions of the second conductive structure in the display substrate do not overlap with the touch electrodes; that is, the protrusions of the second conductive structure (e.g. Figure 21 The projection of the protrusion 314a) on the substrate is separated from the projection of the touch electrode on the substrate. This arrangement helps to avoid defects caused by the protrusion affecting the flatness of the touch electrode.

[0380] For example, in the orientation of the substrate, a first conductive structure (e.g.) is displayed in the substrate. Figure 21 The connecting electrode 232 in the middle does not overlap with the touch electrode; that is, the orthogonal projection of the first conductive structure on the substrate is separate from the orthogonal projection of the touch electrode on the substrate.

[0381] At least one embodiment of this disclosure also provides a display device 40, such as Figure 22 As shown, the display device 40 includes any of the above-mentioned display substrate 20, display panel, or touch display panel. In this embodiment, the display device can be any product or component with display function, such as a monitor, OLED panel, OLED TV, electronic paper, mobile phone, tablet computer, laptop computer, digital photo frame, or navigator.

[0382] The above description is merely an exemplary embodiment of the present invention and is not intended to limit the scope of protection of the present invention, which is determined by the appended claims.

Claims

1. A display substrate, comprising: Substrate; A first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer are sequentially disposed on the substrate. Wherein, the first insulating layer includes a first recessed structure, the first conductive layer includes a first conductive structure, the first conductive structure includes a bottom surface close to the substrate, a top surface away from the substrate, and a first side surface located between the bottom surface and the top surface; The second insulating layer includes a first via, and the second conductive layer includes a second conductive structure; The orthogonal projection of the first via on the substrate at least partially overlaps with the orthogonal projection of the first recessed structure on the substrate. The first via exposes at least a portion of a first side surface of the first conductive structure, and the second conductive structure contacts the at least portion of the first side surface of the first conductive structure; The first side surface of the first conductive structure includes a protruding curved surface, and the second conductive structure covers at least a portion of the protruding curved surface; The first conductive structure includes a connecting portion located in the first recessed structure and connected to the protruding curved surface; along a direction parallel to the surface of the substrate, the protruding curved surface protrudes relative to the connecting portion toward the center of the first recessed structure; The first conductive structure further includes a second side surface located between the bottom surface and the top surface, with the first side surface opposite to the second side surface; The first side surface includes a first side surface portion located on the side of the first insulating layer away from the substrate; the dimension of the first side surface portion in the direction perpendicular to the substrate is greater than the dimension of the second side surface in the direction perpendicular to the substrate.

2. The display substrate as claimed in claim 1, wherein, The second conductive structure includes a first protrusion, the orthographic projection of the first protrusion on the substrate being located within the orthographic projection of the first recessed structure on the substrate; The first protrusion is in contact with at least a portion of the first side surface of the first conductive structure.

3. The display substrate as described in claim 1, wherein, The orthographic projection of the first recessed structure on the substrate at least partially overlaps with the orthographic projection of the first via on the substrate.

4. The display substrate as claimed in claim 1, wherein, The portion of the first side surface not covered by the second conductive structure has a dimension in a direction perpendicular to the substrate that is larger than the dimension of the second side surface in the same direction.

5. The display substrate as claimed in claim 1, wherein, At least a portion of the top surface of the first conductive structure that is directly connected to the first side surface is separated from the second conductive layer.

6. The display substrate as claimed in claim 1, wherein, The display substrate has a first cross-section, and the first recessed structure has a dimension b within the first cross-section and along a reference direction, the reference direction being parallel to the surface of the substrate. Within the first cross section, the overlapping area of ​​the first via and the first recessed structure has a dimension of c along the reference direction, and the portion of the first side surface of the first conductive structure covered by the second conductive structure has a dimension of d in the direction perpendicular to the substrate; the first conductive structure includes a contact portion located on the side of the first insulating layer away from the substrate and in contact with the second conductive structure, with a dimension of e in the direction perpendicular to the substrate. c / b is greater than 0.1; d / e is greater than 0.

3.

7. The display substrate as claimed in claim 6, wherein, c / b is greater than 0.15, and d / e is less than 0.

8.

8. The display substrate as claimed in claim 6, wherein, c / b is less than 0.19, and d / e is less than 0.

5.

9. The display substrate as claimed in claim 6, wherein, Within the first cross section, the maximum depth of the first recessed structure is i, the angle between one side of the first recessed structure within the first cross section and the surface of the substrate is j, and the thickness of the portion of the second conductive structure that contacts the first conductive structure in the direction perpendicular to the substrate is k. d / e<0.0273*i*sin(j) / k.

10. The display substrate as claimed in claim 9, wherein, c / b<0.0102*i*sin(j) / k.

11. The display substrate as claimed in claim 9, wherein, The dimension of the first side surface in the direction perpendicular to the substrate is n, and the dimension of the second side surface in the direction perpendicular to the substrate is e; 0.1*(n / e) / sin(j)>(d / n).

12. The display substrate as claimed in claim 10, wherein, 0.08*(n / e) / sin(j)>d / n.

13. The display substrate according to any one of claims 6-12, wherein, The contact portion includes a second protrusion facing the first recessed structure, and the orthographic projection of the second protrusion on the substrate is located within the orthographic projection of the first recessed structure on the substrate. Within the first cross-section, the dimension of the second protrusion in the direction perpendicular to the substrate is greater than the dimension of the portion of the first conductive layer located on the side surface of the first recessed structure in the direction perpendicular to the side surface of the first recessed structure.

14. The display substrate as claimed in claim 2, wherein, The first insulating layer also includes a second recessed structure spaced apart from the first recessed structure. The first conductive structure further includes a third side surface located between the bottom surface and the top surface, with the first side surface opposite to the third side surface. The orthographic projection of the third side surface on the substrate at least partially overlaps with the orthographic projection of the second recessed structure on the substrate. The first via also exposes at least a portion of the third side surface, and the second conductive structure covers at least a portion of the third side surface of the first conductive structure.

15. The display substrate as claimed in claim 14, wherein, In a direction perpendicular to the substrate, the size of the portion of the first side surface of the first conductive structure covered by the second conductive structure is different from the size of the portion of the third side surface covered by the second conductive structure.

16. The display substrate as claimed in claim 14, wherein, The overlap size between the orthographic projection of the first via on the substrate and the orthographic projection of the first recessed structure on the substrate is different from the overlap size between the orthographic projection of the first via on the substrate and the orthographic projection of the second recessed structure on the substrate.

17. The display substrate as claimed in claim 14, wherein, At least a portion of the first conductive structure is located in the first recessed structure and the second recessed structure, respectively.

18. The display substrate as claimed in claim 17, wherein, The first conductive structure includes a second protrusion facing the first recessed structure, the orthographic projection of the second protrusion on the substrate being located within the orthographic projection of the first recessed structure on the substrate.

19. The display substrate as claimed in claim 17, wherein, The display substrate further includes a plurality of sub-pixels located on the substrate, the plurality of sub-pixels being arranged as a plurality of pixel rows along a first direction and a plurality of pixel columns along a second direction, the first direction being different from the second direction; The first conductive layer further includes a first signal line and a second signal line spaced apart from the first conductive structure, the first signal line and the second signal line extending along the second direction; The distance between the orthographic projection of the first protrusion on the substrate and the orthographic projection of the first signal line on the substrate in the first direction is l, and the distance between the orthographic projection of the second signal line on the substrate and the orthographic projection of the first signal line on the substrate in the first direction is m. The display substrate includes a first cross-section perpendicular to the substrate. Within the first cross-section, the portion of the first conductive structure located on the side of the first insulating layer away from the substrate has a dimension e in a direction perpendicular to the substrate, and the portion of the first side surface covered by the first protrusion has a dimension d in a direction perpendicular to the substrate. l / m>0.9(d / e).

20. The display substrate as claimed in claim 19, wherein, l / m>1.2*(d / e).

21. The display substrate as claimed in claim 19, wherein, The display substrate further includes a plurality of sub-pixels located on the substrate, the plurality of sub-pixels being arranged as a plurality of pixel rows along a first direction and a plurality of pixel columns along a second direction, the first direction being different from the second direction; The second insulating layer includes a plurality of vias, which are arranged in a plurality of via rows and a plurality of via columns along the first direction and the second direction, and the plurality of vias include a plurality of the first vias; The plurality of via rows includes a first via row, in which three consecutive first vias exist at every other via.

22. The display substrate as claimed in claim 21, wherein, The plurality of via columns includes a first via column, in which each via is the first via, or there is a first via every other via.

23. The display substrate as claimed in claim 21, wherein, The plurality of pixel columns include a first pixel column and a second pixel column that are adjacent in the first direction. The first signal line is connected to the sub-pixels of the first pixel column to provide a first signal, and the second signal line is connected to the sub-pixels of the second pixel column to provide a second signal. The orthographic projection of the electrode of the light-emitting element of the first pixel column on the substrate near the substrate overlaps at least partially with the orthographic projection of the first signal line and the orthographic projection of the second signal line on the substrate.

24. The display substrate as claimed in claim 21, wherein, The display substrate further includes a pixel defining layer located on the side of the second conductive structure away from the substrate. The pixel defining layer includes a plurality of pixel opening regions, each corresponding to one of the plurality of sub-pixels. The orthographic projection of the plurality of pixel opening regions on the substrate is separate from the orthographic projection of the first protrusion on the substrate.

25. The display substrate as claimed in claim 24, wherein, The pixel defining layer includes a plurality of protrusions, which are located between the plurality of pixel opening regions; The plurality of protrusions include a first protrusion, a second protrusion, and a third protrusion disposed around the same pixel opening area, and the line connecting the centers of the orthographic projections of the first protrusion, the second protrusion, and the third protrusion on the substrate forms a triangle.

26. The display substrate as claimed in claim 25, wherein, The first protrusion is located between four adjacent pixel opening areas, and the second and third protrusions are respectively located between two adjacent pixel opening areas; The area of ​​the orthographic projection of the first protrusion on the substrate is greater than the area of ​​the orthographic projection of the second protrusion on the substrate and the area of ​​the orthographic projection of the third protrusion on the substrate.

27. The display substrate of claim 17, further comprising a third conductive layer located on the side of the first conductive layer near the substrate. in, The display substrate further includes a plurality of sub-pixels located on the substrate, the plurality of sub-pixels being arranged as a plurality of pixel rows along a first direction and a plurality of pixel columns along a second direction, the first direction being different from the second direction; The third conductive layer includes a shielding electrode and a first capacitor electrode. The shielding electrode includes a portion extending along the first direction and a portion extending toward the first capacitor electrode of the sub-pixel where the shielding electrode is located.

28. The display substrate of claim 27, further comprising a third conductive layer located on the side of the first conductive layer near the substrate, wherein, The display substrate further includes a plurality of sub-pixels located on the substrate, the plurality of sub-pixels being arranged as a plurality of pixel rows along a first direction and a plurality of pixel columns along a second direction, the first direction being different from the second direction; The first conductive layer includes a first reset voltage line extending along the second direction, and the third conductive layer includes a second reset voltage line extending along the first direction, wherein the first reset voltage line is electrically connected to the second reset voltage line. The display substrate further includes a semiconductor layer located on the side of the third conductive layer near the substrate, the semiconductor layer including a connection portion; the connection portion electrically connects the first reset voltage line to the first electrode of the reset transistor in the sub-pixel; The orthographic projection of the connection portion on the substrate overlaps with the orthographic projection of the first reset voltage line on the substrate and the orthographic projection of the first electrode of the reset transistor on the substrate.

29. The display substrate as claimed in claim 17, wherein, The display substrate further includes a plurality of sub-pixels located on the substrate, the plurality of sub-pixels being arranged as a plurality of pixel rows along a first direction and a plurality of pixel columns along a second direction, the first direction being different from the second direction; The display substrate further includes a first gate reset voltage line and a first pixel electrode reset voltage line extending along the first direction, and a second gate reset voltage line and a second pixel electrode reset voltage line extending along the second direction. The first gate reset voltage line and the second gate reset voltage line are electrically connected through a second via, and the first pixel electrode reset voltage line and the second pixel electrode reset voltage line are electrically connected through a third via; The first gate reset voltage line and the second gate reset voltage line are used to provide a reset voltage signal to the gate of the driving transistor, and the first pixel electrode reset voltage line and the second pixel electrode reset voltage line are used to provide a reset voltage signal to the pixel electrode.

30. The display substrate as claimed in claim 29, wherein, The second pixel electrode reset voltage line is electrically connected to the first electrode of the pixel electrode reset transistor through the fourth via. The fourth via and the third via are separated from each other on the substrate.

31. The display substrate as claimed in claim 29, wherein, The second gate reset voltage line is electrically connected to the first electrode of the gate reset transistor through the fifth via, and the fifth via and the second via are separated from each other on the substrate.

32. The display substrate as claimed in claim 17, wherein, The display substrate further includes a plurality of sub-pixels located on the substrate, the plurality of sub-pixels being arranged as a plurality of pixel rows along a first direction and a plurality of pixel columns along a second direction, the first direction being different from the second direction; Each sub-pixel includes a first capacitor electrode, and the display substrate also includes multiple data lines extending along the second direction; The first capacitor electrodes of two adjacent sub-pixels in the first direction are connected by a connecting part, and the multiple data lines overlap with multiple connecting parts in a direction perpendicular to the substrate. The connecting part includes a first part that overlaps with the corresponding data line and a second part that does not overlap with the corresponding data line; The dimension of the first portion in the second direction is larger than the dimension of the second portion in the second direction; The display substrate further includes a reset voltage line extending along the second direction, the second portion of which overlaps with the reset voltage line in a direction perpendicular to the substrate.

33. A display substrate, comprising: Substrate; as well as A first metal layer, a second metal layer, a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer are sequentially disposed on the substrate. The display substrate further includes a first sub-pixel and a second sub-pixel located adjacent to each other in a first direction on the substrate. The first sub-pixel has a first pixel circuit, and the second sub-pixel has a second pixel circuit. The first pixel circuit and the second pixel circuit each include a capacitor, which includes a first capacitor electrode located in the second metal layer and a second capacitor electrode located in the first metal layer. The first capacitor electrode of the first pixel circuit and the first capacitor electrode of the second pixel circuit are connected to each other to form a single capacitor electrode block. The capacitor electrode block has a first opening and a second opening. The orthographic projection of the first opening on the substrate overlaps with the orthographic projection of the second capacitor electrode of the first pixel circuit on the substrate. The orthographic projection of the second opening on the substrate overlaps with the orthographic projection of the second capacitor electrode of the second pixel circuit on the substrate. The orthographic projection area of ​​the first opening on the substrate is smaller than the orthographic projection area of ​​the second opening on the substrate. The first conductive layer includes a first conductive structure; the second conductive layer includes a second conductive structure; The first conductive structure includes a bottom surface close to the substrate, a top surface away from the substrate, and a first side surface located between the bottom surface and the top surface; The second insulating layer includes a first via, and the second conductive structure contacts the first conductive structure through the first via; The second conductive structure includes a first protrusion, the first via exposing at least a portion of a first side surface of the first conductive structure, and the first protrusion contacting the at least portion of the first side surface of the first conductive structure; The first conductive structure further includes a second side surface located between the bottom surface and the top surface, with the first side surface opposite to the second side surface; The first side surface includes a first side surface portion located on the side of the first insulating layer away from the substrate; the dimension of the first side surface portion in the direction perpendicular to the substrate is greater than the dimension of the second side surface in the direction perpendicular to the substrate.

34. The display substrate as claimed in claim 33, wherein, The second conductive layer includes a reset voltage line, a first data line, a second data line, a first power line, and a second power line extending along a second direction, wherein the first direction is different from the second direction; Each of the first pixel circuit and the second pixel circuit includes a driving transistor and a data writing transistor; The reset voltage line is configured to provide a reset voltage to the pixel electrodes or gates of the driving transistors of the first pixel circuit and the second pixel circuit, and the first data line and the second data line are respectively configured to provide data voltage to the data write transistors of the first pixel circuit and the second pixel circuit. The first power line and the second power line are respectively configured to provide power supply voltage to the driving transistors of the first pixel circuit and the second pixel circuit; The reset voltage line is located between the first data line and the second data line; Both the first data line and the second data line are located between the first power line and the second power line; Both the first power line and the second power line have enclosed hollow areas.

35. The display substrate as claimed in claim 34, wherein, The orthographic projection of the pixel electrode of the first sub-pixel onto the substrate overlaps with the orthographic projections of the reset voltage line, the first data line, the second data line, the first power line, and the second power line onto the substrate.

36. The display substrate of claim 33, further comprising a plurality of sub-pixels, the plurality of sub-pixels being located on the substrate and arranged along the first direction and the second direction as a plurality of pixel rows and a plurality of pixel columns, wherein the first direction is different from the second direction; The first conductive layer further includes a plurality of connection electrodes, which are connected one-to-one with the plurality of sub-pixels to provide power supply voltage; The plurality of sub-pixels includes a first sub-pixel, and the display substrate further includes a reset voltage line extending along the second direction, the reset voltage line being connected to the first sub-pixel to provide a reset voltage. The orthographic projection of the first protrusion on the substrate is located between the orthographic projection of the connection electrode corresponding to the first sub-pixel on the substrate and the orthographic projection of the reset voltage line on the substrate.

37. The display substrate as claimed in claim 36, wherein, Along the first direction, the distance between the first protrusion and the reset voltage line is less than the distance between the first protrusion and the connecting electrode.

38. The display substrate as claimed in claim 37, wherein, The connecting electrode includes a main body and an extension extending along the first direction, wherein the dimension of the extension in the second direction is smaller than the dimension of the main body in the second direction; In the second direction, the first conductive structure at least partially overlaps with the extension of the connecting electrode.

39. The display substrate as claimed in claim 36, wherein, The second conductive layer includes a plurality of power electrodes, which are connected one-to-one with the plurality of connection electrodes to provide the power supply voltage. The power electrodes corresponding to each pixel column are connected to each other in a structure that forms multiple power lines extending along the second direction.

40. The display substrate as claimed in claim 39, wherein, The second conductive layer further includes multiple data lines extending along the second direction, each of which is connected to one of the multiple pixel columns to provide data signals. The multiple data lines are divided into multiple data line groups, and each data line group includes two data lines; A data line group is set between each pair of adjacent pixel columns, and two power lines are spaced between adjacent data line groups.

41. The display substrate of claim 40, comprising a plurality of reset voltage lines extending along the second direction. in, The plurality of reset voltage lines include a first reset voltage line and a second reset voltage line alternately arranged in the first direction, wherein the first reset voltage line and the second reset voltage line are respectively configured to provide a first reset voltage and a second reset voltage. There are two pixel columns between adjacent first and second reset voltage lines.

42. The display substrate as claimed in claim 41, wherein, The multiple reset voltage lines are located in the first conductive layer. A first reset voltage line or a second reset voltage line is provided between the two power lines of adjacent data line groups; The orthographic projection of any one of the plurality of reset voltage lines on the substrate is separate from the orthographic projection of any one of the plurality of power lines on the substrate.

43. The display substrate as claimed in claim 41, wherein, The multiple reset voltage lines are located in the second conductive layer and are configured to correspond one-to-one with multiple data line groups. Each reset voltage line is located between two data lines in the corresponding data line group.

44. The display substrate as claimed in claim 43, wherein, The structure in which two power lines between adjacent data line groups are connected to each other as a whole, such that two adjacent power electrodes in the first direction of the two power lines are connected to each other as a power electrode group. The display substrate includes a plurality of second conductive structures, and the plurality of second conductive structures are arranged in a one-to-one correspondence with the plurality of power electrodes; The power electrode assembly includes a hollowed-out area, and the hollowed-out area is provided with two second conductive structures.

45. The display substrate as claimed in claim 44, wherein, The second conductive layer further includes connecting lines that extend along the second direction, separating the cutout area into two cutout sub-areas; The two second conductive structures are respectively disposed in the two hollowed-out sub-regions and are located on both sides of the connecting line.

46. ​​The display substrate of claim 36, further comprising a third conductive layer located on the side of the first conductive layer near the substrate and a semiconductor layer located between the third conductive layer and the second metal layer, wherein, The second metal layer is located on the side of the third conductive layer closest to the substrate. The first sub-pixel includes a reset transistor configured to reset a first electrode of a light-emitting element, the reset transistor including an active layer located in the semiconductor layer; The display substrate includes a first reset control line located in the second metal layer and a second reset control line located in the third conductive layer. The first reset control line and the second reset control line are respectively configured to perform gate voltage control on the reset transistor, and the orthogonal projections of the first reset control line and the second reset control line on the substrate at least partially overlap.

47. A display device comprising a display substrate as described in any one of claims 1-46.

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