A timestamp synchronization method, system, terminal and storage medium

Abstract

This application provides a timestamp synchronization method, system, terminal, and storage medium, relating to the field of communication technology. The method includes: acquiring NTP time information and local timekeeping information for the current period; calculating the time difference between the NTP time information and the local timekeeping information to obtain a first time difference value for the current period; acquiring n historical time difference values ​​for n consecutive historical periods, wherein the n consecutive historical periods include the period preceding the current period; comparing the first time difference value and the n historical time difference values, and determining step fine-tuning parameters based on the comparison results, wherein the step fine-tuning parameters include positive fine-tuning action parameters and negative fine-tuning action parameters; adjusting the local timekeeping accumulation logic according to the step fine-tuning parameters, and outputting the current timestamp information. This application can improve the accuracy of timestamp synchronization while avoiding timestamp rollback.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a timestamp synchronization method, system, terminal and storage medium. Background Technology

[0002] Using PCIe (Peripheral Component Interconnect Express) network cards based on FPGA (Field Programmable Gate Array) for traffic capture is typically for high-traffic scenarios. When big data analytics vendors analyze the massive amounts of captured traffic, they need to obtain the capture time of each data packet. This allows them to reconstruct the entire communication process of the current data stream based on the chronological order of the data. If the timestamp is inaccurate or incorrect, causing time rollback, it will affect the current analysis process, leading to anomalies in traffic reconstruction. In some cases, it may even require additional computing resources to correct these time errors, increasing the CPU's computational burden. Therefore, the function of the network card to append a high-precision timestamp to the traffic captured on all lines is particularly important.

[0003] Currently, among the mainstream time synchronization solutions, one approach is to obtain the Ethernet time server's time based on NTP (Network Time Protocol) and then maintain local timekeeping without further synchronization. This results in the absolute time error of the local timekeeping accumulating and increasing over time. Another approach is to periodically obtain the Ethernet time from NTP (e.g., every second or every day) and then maintain local timekeeping. However, because the NTP synchronization time issued by the CPU fluctuates around the precise time, the error can be within ±1ms. When the error is negative, a timestamp callback will inevitably occur, causing the network card to revert to obtaining a backward timestamp.

[0004] Therefore, based on the NTP synchronization protocol, how to improve the accuracy of timestamp synchronization while avoiding timestamp rollback is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a timestamp synchronization method based on the NTP synchronization protocol, which improves the accuracy of timestamp synchronization while preventing timestamp rollback. This application also provides a timestamp synchronization system, terminal, and storage medium, achieving the same technical effects.

[0006] The first objective of this application is to provide a timestamp synchronization method.

[0007] The aforementioned objective of this application is achieved through the following technical solution:

[0008] A timestamp synchronization method, applied to a Field Programmable Gate Array (FPGA) high-speed serial computer expansion bus standard PCIe network card, the method comprising:

[0009] Obtain the Network Time Protocol (NTP) time information and local time information for the current period;

[0010] Calculate the time difference between the NTP time information and the local timekeeping information to obtain the first time difference value for the current period;

[0011] Obtain n historical time differences for n consecutive historical periods, wherein each historical time difference is obtained by pre-calculating the time difference between the NTP time information and the local timekeeping information of the historical period corresponding to each historical time difference, and the n consecutive historical periods include the previous period of the current period, where n is a positive integer greater than 1;

[0012] The first time difference and n historical time differences are compared, and the step fine-tuning parameters are determined according to the comparison results. The step fine-tuning parameters include positive fine-tuning action parameters and negative fine-tuning action parameters.

[0013] Based on the step fine-tuning parameters, the local timekeeping accumulation logic is adjusted, and the current timestamp information is output.

[0014] Preferably, in the timestamp synchronization method, after calculating the time difference between the NTP time information and the local timekeeping information to obtain the first time difference value for the current period, the method further includes:

[0015] Determine whether the first time difference is greater than or equal to a preset threshold.

[0016] If so, then based on the NTP time information, overwrite the current local time information and output the current timestamp information;

[0017] If not, then proceed with the step of obtaining n historical time differences for n consecutive historical periods.

[0018] Preferably, in the timestamp synchronization method, comparing the first time difference value and n historical time differences, and determining the step fine-tuning parameters based on the comparison results, includes:

[0019] The first time difference value is compared with the n historical time differences.

[0020] When the first time difference and the n historical time differences are all positive or all negative, the first time difference and the n historical time differences are arranged in periodic order to obtain a first sequence, wherein the first time difference is located at the end of the first sequence;

[0021] Calculate the first difference of the first sequence to obtain the second sequence;

[0022] Take the absolute value of all values ​​in the second sequence to obtain the third sequence;

[0023] Calculate the first difference of the third sequence to obtain the fourth sequence;

[0024] Determine whether all values ​​in the fourth sequence are greater than or equal to 0.

[0025] If so, when the first time difference and the n historical time differences are all positive, output positive fine-tuning action parameters; or, when the first time difference and the n historical time differences are all negative, output negative fine-tuning action parameters.

[0026] If not, then keep the current step fine-tuning parameters;

[0027] When the first time difference is positive and the historical time difference corresponding to the previous period of the current period is negative, the current step fine-tuning parameter is maintained.

[0028] When the first time difference is negative and the historical time difference corresponding to the previous cycle of the current cycle is positive, the current step fine-tuning parameter is maintained.

[0029] Preferably, in the timestamp synchronization method, adjusting the local timekeeping accumulation logic according to the step fine-tuning parameters and outputting the current timestamp information includes:

[0030] Based on the step fine-tuning parameters, modify the offset parameters of the timer and output the current timestamp information.

[0031] Preferably, in the timestamp synchronization method, the timer consists of an integer part and a decimal floating-point part, and modifying the offset parameter of the timer according to the step fine-tuning parameter includes:

[0032] The step fine-tuning parameters are accumulated in the decimal floating-point portion of the timer.

[0033] Preferably, in the timestamp synchronization method, the timer is a 96-bit counter.

[0034] Preferably, in the timestamp synchronization method, the step fine-tuning parameter uses 0.1 PPM of the current crystal oscillator as the fine-tuning step size, where PPM represents one part per million.

[0035] The second objective of this application is to provide a timestamp synchronization system.

[0036] The second objective of this application is achieved through the following technical solution:

[0037] A timestamp synchronization system is provided, the system being applied to a Field-Programmable Gate Array (FPGA) high-speed serial computer expansion bus standard PCIe network card, the system comprising:

[0038] The first acquisition module is used to acquire the Network Time Protocol (NTP) time information and local time information for the current period.

[0039] The difference calculation module is used to calculate the time difference between the NTP time information and the local timekeeping information to obtain the first time difference value of the current period;

[0040] The second acquisition module is used to acquire n historical time differences for n consecutive historical periods. Each historical time difference is obtained by pre-calculating the time difference between the NTP time information and the local timekeeping information of the historical period corresponding to each historical time difference. The n consecutive historical periods include the previous period of the current period, and n is a positive integer greater than 1.

[0041] The step fine-tuning module is used to compare the first time difference value and n historical time differences value, and to confirm the step fine-tuning parameters based on the comparison results. The step fine-tuning parameters include positive fine-tuning action parameters and negative fine-tuning action parameters.

[0042] The local timekeeping module is used to adjust the local timekeeping accumulation logic according to the step fine-tuning parameters and output the current timestamp information.

[0043] The third objective of this application is to provide a timestamp synchronization terminal.

[0044] The aforementioned objective three of this application is achieved through the following technical solution:

[0045] A timestamp synchronization terminal includes: a storage medium and a processor;

[0046] The storage medium stores computer-executed instructions.

[0047] The processor executes computer execution instructions stored in the storage medium to implement any of the above-described timestamp synchronization methods.

[0048] The fourth objective of this application is to provide a computer-readable storage medium.

[0049] The fourth objective of this application is achieved through the following technical solution:

[0050] A computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement any of the methods described above for timestamp synchronization.

[0051] The above technical solution is based on an FPGA PCIe network card platform, with all functions implemented in programmable logic. It employs periodic NTP time information transmission synchronization, acquiring the NTP time information and local timekeeping information for the current period; calculating the time difference between the NTP time information and the local timekeeping information to obtain the first time difference value for the current period; acquiring n historical time difference values ​​for n consecutive historical periods, where each historical time difference value is obtained by pre-calculating the time difference between the NTP time information and the local timekeeping information for the corresponding historical period, and the n consecutive historical periods include the period preceding the current period, where n is a positive integer greater than 1; comparing the first time difference value and the n historical time difference values, and determining the step fine-tuning parameters based on the comparison results; adjusting the local timekeeping accumulation logic according to the step fine-tuning parameters, and outputting the current timestamp information. The above technical solution generates step-by-step fine-tuning actions by comparing multiple time differences. Through multiple periodic time synchronization fine-tuning actions, it will inevitably converge to an adjustment value, unaffected by crystal oscillator temperature changes, achieving stable and accurate timekeeping. The step-by-step fine-tuning parameters include positive and negative fine-tuning action parameters, and the current fine-tuning judgment uses a local timekeeping accumulation logic, thus only adjusting for timekeeping acceleration and deceleration, avoiding timestamp rollback and overwriting issues. Furthermore, the above technical solution has low deployment costs, good portability, requires no additional hardware support, and is suitable for scenarios requiring precise relative time information.

[0052] In summary, the above technical solutions, based on the NTP synchronization protocol, can improve the accuracy of timestamp synchronization while avoiding timestamp rollback. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 This is a diagram showing the working data flow of a PCIe network card based on an FPGA.

[0055] Figure 2 This is a flowchart illustrating a timestamp synchronization method in an embodiment of this application;

[0056] Figure 3 This is a schematic diagram illustrating one scenario of comparing time differences.

[0057] Figure 4 This is a schematic diagram illustrating another scenario for comparing time differences.

[0058] Figure 5 This is another flowchart illustrating a timestamp synchronization method in an embodiment of this application;

[0059] Figure 6 A schematic diagram illustrating the parameter fine-tuning process of a 96-bit timer counter;

[0060] Figure 7 This is a schematic diagram of the structure of a timestamp synchronization system according to an embodiment of this application;

[0061] Figure 8 This is a schematic diagram of the structure of a timestamp synchronization terminal in an embodiment of this application. Detailed Implementation

[0062] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0063] In the embodiments provided in this application, it should be understood that the disclosed methods and systems can be implemented in other ways. The system embodiments described below are merely illustrative. For example, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple modules or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, and can be electrical, mechanical, or other forms.

[0064] It should be understood that the use of terms such as "system," "device," "unit," and / or "module" in this application is merely one method of distinguishing different components, elements, parts, sections, or assemblies at different levels. However, if other terms can achieve the same purpose, they may be replaced by other expressions.

[0065] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "a plurality of" or "several" means two or more, unless otherwise explicitly specified.

[0066] If a flowchart is used in this application, it is used to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, the steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0067] It should also be noted that, in this document, terms such as “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitation, an element defined by the phrase “comprising one…” does not exclude the presence of other identical elements in the article or device that includes the aforementioned element.

[0068] The embodiments in this application are written in a progressive manner.

[0069] The timestamp synchronization method provided in this application embodiment is mainly applied to FPGA PCIe network cards. FPGA stands for Field Programmable Gate Array. Its internal functional logic is developed using hardware description languages ​​such as Verilog or VHDL, and can be arbitrarily customized according to the developer's needs. With the explosive growth of network bandwidth, the network interface of the host's PCIe network card has gradually evolved from the initial 10 Mbps to 100 Mbps and 1 Gbps. As the demand for network traffic capture from big data analysis increases, existing network card interfaces even need to reach 40G and 100G. FPGA chips come with high-speed serial interfaces and built-in interface hard IP, which can easily realize 10G / 40G / 100G Ethernet traffic data access, and have high-speed PCIe interfaces. Therefore, many manufacturers currently use FPGA-based PCIe network card designs. The working data flow diagram of an FPGA-based PCIe network card is shown below. Figure 1 As shown. Due to current hardware limitations, no matter what platform the network card is made of, it is impossible to make the data timestamp accuracy within 1ns of the absolute time. Moreover, the timestamps required by big data analytics vendors usually do not need to have an extremely small difference between local time and absolute time. Instead, they only need the time difference between the timestamps of the entire captured data stream to be accurate.

[0070] like Figure 2 As shown in the figure, this application provides a timestamp synchronization method, which is applied to an FPGA PCIe network card. The method includes:

[0071] S101. Obtain the NTP time information and local clock information for the current period;

[0072] In S101, NTP stands for Network Time Protocol, a protocol used to synchronize computer time. It allows computers to synchronize with their servers or clock sources (such as quartz clocks, GPS, etc.), providing high-precision time correction and using encrypted authentication to prevent malicious protocol attacks. The purpose of NTP is to provide accurate and robust time services in the disordered environment of the Internet. For NTP to provide accurate time, it first needs an accurate time source, which should be Universal Time Coordinated (UTC). NTP can obtain UTC time from atomic clocks, observatories, satellites, or from the Internet. Specifically, the PCIe interface synchronizes by periodically sending (e.g., once per second) NTP time information; the current period's NTP time information can be obtained from the PCIe interface. To achieve a timed result, the FPGA needs to accumulate the time value using a timer; specifically, a timed timer can be used to obtain the local timed information for the current period.

[0073] S102. Calculate the time difference between the NTP time information and the local timekeeping information to obtain the first time difference value of the current period;

[0074] In S102, specifically, the time difference obtained by subtracting the time value in the local timekeeping information of the current period from the time value in the NTP time information of the current period is used as the first time difference value.

[0075] S103. Obtain n historical time differences for n consecutive historical periods, wherein each historical time difference is obtained by pre-calculating the time difference between the NTP time information and the local timekeeping information of the historical period corresponding to each historical time difference, and the n consecutive historical periods include the previous period of the current period, where n is a positive integer greater than 1.

[0076] In S103, the historical time difference can be pre-calculated with reference to the specific implementation details of S101 and S102; for example, it can be achieved through the following steps: obtaining the NTP time information and local time information of the current historical period; calculating the time difference between the NTP time information and the local time information of the current historical period to obtain the historical time difference value of the current historical period. The value of n can be determined according to the accuracy and efficiency requirements of timestamp synchronization. For example, considering the balance between the efficiency and accuracy of timestamp synchronization, n can be 2.

[0077] S104. Compare the first time difference and the n historical time differences, and confirm the step fine-tuning parameters according to the comparison results, wherein the step fine-tuning parameters include positive fine-tuning action parameters and negative fine-tuning action parameters;

[0078] In S104, the step fine-tuning parameters can be determined based on the comparison results of the first time difference and n historical time differences. Specifically, if the comparison results indicate that the difference between the local timekeeping and the standard time is widening and the current crystal oscillator frequency is too slow, then positive fine-tuning parameters are output; if the comparison results indicate that the difference between the local timekeeping and the standard time is widening and the current crystal oscillator frequency is too fast, then negative fine-tuning parameters are output. Based on the step fine-tuning parameters, ppm (Parts Per Million) compensation can be performed. For example, if the current crystal oscillator standard frequency is 100MHz, then an error of +0.1PPM would be 100.00001MHz. The step fine-tuning parameters are set to eliminate this 0.00001MHz error.

[0079] S105. Adjust the local timekeeping accumulation logic according to the step fine-tuning parameters, and output the current timestamp information.

[0080] In S105, to obtain a timekeeping result, the FPGA needs to accumulate the time value using a timer. The FPGA's internal local timekeeping accumulation logic operates under the system clock. For example, if the current clock speed of the timekeeping logic is 100MHz, it accumulates 10ns per clock cycle; if the clock speed is 200MHz, it accumulates 5ns per clock cycle. The reason FPGA timekeeping is more accurate than PC software timekeeping is that all FPGA logic is processed in parallel under clock control. Each logic function is unaffected by other functions, only by clock accuracy, achieving nanosecond-level accuracy. PC software timekeeping, due to CPU instruction execution arbitration and pipeline issues, only achieves millisecond-level accuracy. The stepping fine-tuning parameters include positive and negative fine-tuning parameters. The current fine-tuning judgment uses a progressive approach based on the local timekeeping accumulation logic, thus only adjusting for acceleration and deceleration, without timestamp rollback or overwriting. The timestamp information can be used for data timestamping logic. One implementation of this step includes: modifying the offset parameter of the timer according to the step fine-tuning parameter, and outputting the current timestamp information.

[0081] Currently, among the mainstream time synchronization solutions, one approach is to obtain the Ethernet time server's time based on NTP and then maintain local timekeeping without continuing synchronization. This results in the absolute time error of the local timekeeping accumulating and increasing over time. Another approach is to periodically obtain the Ethernet time from NTP (e.g., every second or every day) and then maintain local timekeeping. However, because the NTP synchronization time issued by the CPU fluctuates around the precise time, the error can be within ±1ms. When the error is negative, a timestamp callback will inevitably occur, causing the network card to revert to obtaining a backward timestamp.

[0082] The above embodiment uses an FPGA PCIe network card platform as its foundation, with all functions implemented in programmable logic. It employs periodic NTP time information transmission synchronization, acquiring the NTP time information and local timekeeping information for the current period; calculating the time difference between the NTP time information and the local timekeeping information to obtain the first time difference value for the current period; acquiring n historical time difference values ​​for n consecutive historical periods, where each historical time difference value is obtained by pre-calculating the time difference between the NTP time information and the local timekeeping information for the corresponding historical period, and the n consecutive historical periods include the period preceding the current period, where n is a positive integer greater than 1; comparing the first time difference value and the n historical time difference values, and determining the step fine-tuning parameters based on the comparison results; adjusting the local timekeeping accumulation logic according to the step fine-tuning parameters, and outputting the current timestamp information. The above embodiment uses multiple time difference comparisons to generate step fine-tuning actions, which, under multiple periodic time synchronization fine-tuning actions, will inevitably converge to an adjustment value, unaffected by crystal oscillator temperature changes, achieving stable and accurate timekeeping. The step-by-step fine-tuning parameters include positive and negative fine-tuning action parameters. The current fine-tuning judgment uses a local timekeeping accumulation logic, thus only adjusting for timekeeping acceleration and deceleration, avoiding timestamp rollback issues. Furthermore, the above embodiment has low deployment costs, good portability, requires no additional hardware support, and is suitable for scenarios requiring precise relative time information. In summary, the above embodiment, based on the NTP synchronization protocol, can improve the accuracy of timestamp synchronization while avoiding timestamp rollback.

[0083] In other embodiments of this application, one specific implementation of the step of comparing the first time difference and n historical time differences, and confirming the step fine-tuning parameters based on the comparison results, is as follows:

[0084] The first time difference value is compared with the n historical time differences.

[0085] When the first time difference and the n historical time differences are all positive or all negative, the first time difference and the n historical time differences are arranged in periodic order to obtain a first sequence, wherein the first time difference is located at the end of the first sequence;

[0086] Calculate the first difference of the first sequence to obtain the second sequence;

[0087] Take the absolute value of all values ​​in the second sequence to obtain the third sequence;

[0088] Calculate the first difference of the third sequence to obtain the fourth sequence;

[0089] Determine whether all values ​​in the fourth sequence are greater than or equal to 0.

[0090] If so, when the first time difference and the n historical time differences are all positive, output positive fine-tuning action parameters; or, when the first time difference and the n historical time differences are all negative, output negative fine-tuning action parameters.

[0091] If not, then keep the current step fine-tuning parameters;

[0092] When the first time difference is positive and the historical time difference corresponding to the previous period of the current period is negative, the current step fine-tuning parameter is maintained.

[0093] When the first time difference is negative and the historical time difference corresponding to the previous cycle of the current cycle is positive, the current step fine-tuning parameter is maintained.

[0094] Specifically, taking n=2 as an example, let the period preceding the current period be the first historical period, the period preceding the first historical period be the second historical period, the first time difference of the current period be ΔT3, the historical time difference of the first historical period be ΔT2, and the historical time difference of the second historical period be ΔT1.

[0095] Compare ΔT1, ΔT2, and ΔT3.

[0096] If ΔT1, ΔT2, and ΔT3 are all positive, and |ΔT3-ΔT2|≥|ΔT2-ΔT1|, then output the positive fine-tuning motion parameters; specifically, as follows... Figure 3 As shown, the first time difference of the current period corresponds to Figure 3 ΔT3, the historical time difference corresponding to the first historical period Figure 3 ΔT2, the historical time difference corresponding to the second historical period Figure 3In the figure, ΔT1, ΔT3, ΔT2 and ΔT1 are all positive, and |ΔT3-ΔT2|≥|ΔT2-ΔT1|. It can be seen from the figure that the gap between local timekeeping and standard time is widening under the current situation. The current crystal oscillator is operating at a relatively slow frequency and needs to be compensated by ppm. The positive fine-tuning action parameters are output.

[0097] If ΔT1, ΔT2, and ΔT3 are all positive, and |ΔT3-ΔT2| < |ΔT2-ΔT1|, then maintain the current step fine-tuning parameters; in the current case, the difference between local timekeeping and standard time is narrowing, which means that the current timekeeping time is converging to standard time, so the current step fine-tuning parameters can be maintained.

[0098] If ΔT3 is positive and ΔT2 is negative, then keep the current step fine-tuning parameters; in the current case, the difference between local timekeeping and standard time has converged, so keep the current step fine-tuning parameters.

[0099] If ΔT1, ΔT2, and ΔT3 are all negative, and |ΔT3-ΔT2|≥|ΔT2-ΔT1|, then output the negative fine-tuning action parameters; specifically, as follows... Figure 4 As shown, the first time difference of the current period corresponds to Figure 4 ΔT3, the historical time difference corresponding to the first historical period Figure 4 ΔT2, the historical time difference corresponding to the second historical period Figure 4 In the figure, ΔT1, ΔT3, ΔT2 and ΔT1 are all negative, and |ΔT3-ΔT2|≥|ΔT2-ΔT1|. It can be seen from the figure that the difference between local timekeeping and standard time is widening under the current situation. The current crystal oscillator is operating at a relatively fast frequency, so ppm compensation is required, and negative fine-tuning parameters are output.

[0100] If ΔT1, ΔT2, and ΔT3 are all negative, and |ΔT3-ΔT2|<|ΔT2-ΔT1|, then keep the current step fine-tuning parameters. In the current case, the difference between the local timekeeping and the standard time is narrowing, which means that the current timekeeping time is converging to the standard time, so keep the current step fine-tuning parameters.

[0101] If ΔT3 is negative and ΔT2 is positive, then keep the current step fine-tuning parameters. In the current case, the difference between local timekeeping and standard time has converged, so keep the current step fine-tuning parameters.

[0102] The above implementation steps determine whether to increase or decrease the current step adjustment parameter by comparing the time difference over n+1 consecutive cycles. Based on the difference between local time and standard time, it accurately identifies whether the current crystal oscillator frequency is too slow or too fast, and outputs the corresponding step adjustment parameter. This avoids large fluctuations in step adjustment and achieves stable convergence through multiple periodic time synchronization adjustments. Based on these implementation steps, the timestamp synchronization method achieves good timekeeping convergence and accuracy.

[0103] As can be seen from the above, calculating and using the first time difference to determine the error is a crucial step in the timestamp synchronization method. In other embodiments of this application, before comparing the first time difference with n historical time differences, the first time difference can also be compared with a preset threshold, such as... Figure 5 As shown, in other embodiments of this application, another timestamp synchronization method is also provided, the method being applied to an FPGA PCIe network card, the method comprising:

[0104] S201. Obtain the NTP time information and local clock information for the current period;

[0105] S202. Calculate the time difference between the NTP time information and the local timekeeping information to obtain the first time difference value of the current period;

[0106] For details on the implementation of S201 and S202, please refer to S101 and S102 above.

[0107] S203. Determine whether the first time difference is greater than or equal to a preset threshold. If yes, execute S204; otherwise, execute S205.

[0108] In S203, the preset threshold can be determined according to actual application requirements, for example, it can be 1 second; accordingly, if the time difference between the time value in the received NTP time information and the time value in the local timekeeping information is greater than or equal to 1 second, then S204 is executed; otherwise, S205 is executed.

[0109] S204. Based on the NTP time information, overwrite the current local time information and output the current timestamp information;

[0110] In S204, when the first time difference is greater than or equal to the preset threshold, the current local timekeeping information is overwritten according to the NTP time information of the current period, and the current timestamp information is output. This scenario usually occurs during the first synchronization.

[0111] S205. Obtain n historical time differences for n consecutive historical periods, wherein each historical time difference is obtained by pre-calculating the time difference between the NTP time information and the local timekeeping information of the historical period corresponding to each historical time difference, and the n consecutive historical periods include the previous period of the current period, where n is a positive integer greater than 1.

[0112] S206. Compare the first time difference and the n historical time differences, and confirm the step fine-tuning parameters according to the comparison results, wherein the step fine-tuning parameters include positive fine-tuning action parameters and negative fine-tuning action parameters;

[0113] S207. Adjust the local timekeeping accumulation logic according to the step fine-tuning parameters, and output the current timestamp information.

[0114] For details on the implementation of S205 to S207, please refer to S103 to S105 above.

[0115] In this embodiment, the first time difference is compared with a preset threshold. When the first time difference is greater than or equal to the preset threshold, the current local timekeeping information is overwritten according to the NTP time information of the current period, and the current timestamp information is output. This scenario generally occurs during the first synchronization. When the first difference is less than the preset threshold, the local timekeeping is adjusted by comparing the first time difference with n historical time differences.

[0116] To improve compensation accuracy, in other embodiments of this application, the timer consists of an integer part and a fractional floating-point part. One implementation of modifying the offset parameter of the timer according to the step fine-tuning parameter includes: adding the step fine-tuning parameter to the fractional floating-point part of the timer. Adjusting the integer carry through the fractional carry method results in high compensation accuracy.

[0117] Specifically, taking the timer as an example, which is a 96-bit counter, such as... Figure 6 As shown, the high 64 bits represent the integer time value in nanoseconds, and the low 32 bits represent the fractional part of nanoseconds. Taking a clock speed of 156.25m as an example, with a timing period of 6.4ns, the high 64 bits accumulate 6ns per clock cycle, while the fractional part of the low 32 bits needs to accumulate 0.4ns. This translates to a 32-bit floating-point number of 0x66666666. When the 32-bit floating-point number overflows, an additional 1 is added to the high 64 bits as the integer time.

[0118] To achieve fine-tuning of the crystal oscillator, in other embodiments of this application, the fine-tuning parameter uses 0.1 PPM of the current crystal oscillator as the fine-tuning step size, i.e., Feq*2^32*0.1ppm. For example, the fine-tuning value used for a 156.25MHz crystal oscillator is 2749 (decimal). The fine-tuning value is adjusted positively or negatively by adding or subtracting the lower 32 bits of the fractional part with each clock cycle. When a positive fine-tuning step of 128 steps is required, the fractional part is added by 128*2749 with each clock cycle. A fine-tuning step size of 0.1ppm means that the timekeeping accuracy can reach one ten-millionth of the crystal oscillator frequency, reducing the daily timekeeping error from the original 4.32s to 0.1us. Furthermore, the current fine-tuning judgment uses an incremental method, only adjusting for timekeeping acceleration and deceleration, without the problem of timestamp rollback and overwriting. Furthermore, although the NTP transmission time fluctuates within a 1ms precision range, through long-term synchronous fine-tuning, this timekeeping counter will converge to the average median of the NTP synchronization time. It will not cause drastic changes in the current timekeeping logic due to excessively large errors in a single NTP transmission. Moreover, this fine-tuning value will be adjusted in real-time based on the frequency shift caused by the current crystal oscillator's operating temperature. In this way, a stable, convergent, temperature-compensated, high-precision timekeeping logic can be obtained.

[0119] Based on the above settings for the timer and step fine-tuning parameters, a high-precision timekeeping scheme for local crystal oscillator PPM fine-tuning is realized. It can obtain time information with an accuracy of 1ms error through the NTP network, and obtain relative time information with an error of less than 0.1us through fine-tuning synchronization. It can also prevent timestamp callbacks, automatically adjust the error caused by crystal oscillator temperature drift, and further improve accuracy.

[0120] like Figure 7 As shown, in another embodiment of this application, a timestamp synchronization system is also provided. The system is applied to a Field-Programmable Gate Array (FPGA) high-speed serial computer expansion bus standard PCIe network card. The system includes:

[0121] The first acquisition module 10 is used to acquire the Network Time Protocol (NTP) time information and local time information for the current period.

[0122] The difference calculation module 11 is used to calculate the time difference between the NTP time information and the local timekeeping information to obtain the first time difference value of the current period;

[0123] The second acquisition module 12 is used to acquire n historical time differences for n consecutive historical periods, wherein each historical time difference is obtained by pre-calculating the time difference between the NTP time information and the local timekeeping information of the historical period corresponding to each historical time difference, and the n consecutive historical periods include the previous period of the current period, where n is a positive integer greater than 1.

[0124] The step fine-tuning module 13 is used to compare the first time difference value and n historical time differences value, and to confirm the step fine-tuning parameters according to the comparison result. The step fine-tuning parameters include positive fine-tuning action parameters and negative fine-tuning action parameters.

[0125] The local timekeeping module 14 is used to adjust the local timekeeping accumulation logic according to the step fine-tuning parameters and output the current timestamp information.

[0126] like Figure 8 As shown, in another embodiment of this application, a timestamp synchronization terminal is also provided, including: a storage medium 20 and a processor 21;

[0127] The storage medium 20 stores computer-executed instructions.

[0128] The processor 21 executes the computer execution instructions stored in the storage medium 20 to implement any of the above-described timestamp synchronization methods.

[0129] The processor 21 may include one or more processing cores. The processor 21 executes instructions, programs, code sets, or instruction sets stored in the storage medium 20, and calls data stored in the storage medium 20 to perform various functions and process data according to this application. The processor 21 may be at least one of a specific application-specific integrated circuit, digital signal processor, digital signal processing device, programmable logic device, field-programmable gate array, central processing unit, controller, microcontroller, and microprocessor. It is understood that, for different devices, the electronic devices used to implement the functions of the processor 21 may also be other types.

[0130] The storage medium 20 can be used to store instructions, programs, code, code sets, or instruction sets. The storage medium 20 may include a stored program area and a stored data area. The stored program area may store instructions for implementing an operating system, instructions for at least one function, and instructions for implementing any of the aforementioned timestamp synchronization methods; the stored data area may store data involved in any of the aforementioned timestamp synchronization methods.

[0131] In another embodiment of this application, a computer-readable storage medium is also provided, wherein computer-executable instructions are stored in the computer-readable storage medium, and the computer-executable instructions are executed by a processor to implement any of the above-described timestamp synchronization methods.

[0132] The computer-readable storage medium can be any medium capable of storing program code, such as a USB flash drive, portable hard drive, read-only memory, random access memory, or optical disc.

[0133] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A timestamp synchronization method, characterized in that, The method is applied to a standard PCIe network card (PCIE) for high-speed serial computer expansion bus in a Field-Programmable Gate Array (FPGA). The method includes: Obtain the Network Time Protocol (NTP) time information and local time information for the current period; Calculate the time difference between the NTP time information and the local timekeeping information to obtain the first time difference value for the current period; Obtain n historical time differences for n consecutive historical periods, wherein each historical time difference is obtained by pre-calculating the time difference between the NTP time information and the local timekeeping information of the historical period corresponding to each historical time difference, and the n consecutive historical periods include the previous period of the current period, where n is a positive integer greater than 1; The first time difference and n historical time differences are compared, and the step fine-tuning parameters are determined according to the comparison results. The step fine-tuning parameters include positive fine-tuning action parameters and negative fine-tuning action parameters. Based on the step fine-tuning parameters, the local timekeeping accumulation logic is adjusted, and the current timestamp information is output. The step of comparing the first time difference with the n historical time differences and determining the step fine-tuning parameters based on the comparison results includes: The first time difference value is compared with the n historical time differences. When the first time difference and the n historical time differences are all positive or all negative, the first time difference and the n historical time differences are arranged in periodic order to obtain a first sequence, wherein the first time difference is located at the end of the first sequence; Calculate the first difference of the first sequence to obtain the second sequence; Take the absolute value of all values ​​in the second sequence to obtain the third sequence; Calculate the first difference of the third sequence to obtain the fourth sequence; Determine whether all values ​​in the fourth sequence are greater than or equal to 0. If so, when the first time difference and the n historical time differences are all positive, output positive fine-tuning action parameters; or, when the first time difference and the n historical time differences are all negative, output negative fine-tuning action parameters. If not, then keep the current step fine-tuning parameters; When the first time difference is positive and the historical time difference corresponding to the previous period of the current period is negative, the current step fine-tuning parameter is maintained. When the first time difference is negative and the historical time difference corresponding to the previous cycle of the current cycle is positive, the current step fine-tuning parameter is maintained.

2. The method as described in claim 1, characterized in that, After calculating the time difference between the NTP time information and the local timekeeping information to obtain the first time difference value for the current period, the method further includes: Determine whether the first time difference is greater than or equal to a preset threshold. If so, then based on the NTP time information, overwrite the current local time information and output the current timestamp information; If not, then proceed with the step of obtaining n historical time differences for n consecutive historical periods.

3. The method as described in claim 1, characterized in that, The step of adjusting the local timekeeping accumulation logic according to the step fine-tuning parameters and outputting the current timestamp information includes: Based on the step fine-tuning parameters, modify the offset parameters of the timer and output the current timestamp information.

4. The method as described in claim 3, characterized in that, The timer consists of an integer part and a decimal floating-point part. Modifying the offset parameter of the timer according to the step fine-tuning parameters includes: The step fine-tuning parameters are accumulated in the decimal floating-point portion of the timer.

5. The method as described in claim 3 or 4, characterized in that, The timer is a 96-bit counter.

6. The method as described in claim 1, characterized in that, The step fine-tuning parameter uses 0.1 PPM of the current crystal oscillator as the fine-tuning step size, where PPM represents one part per million.

7. A timestamp synchronization system, characterized in that, Applied to the timestamp synchronization method of claim 1, the system is applied to a Field-Programmable Gate Array (FPGA) high-speed serial computer expansion bus standard PCIe network card, and the system includes: The first acquisition module is used to acquire the Network Time Protocol (NTP) time information and local time information for the current period. The difference calculation module is used to calculate the time difference between the NTP time information and the local timekeeping information to obtain the first time difference value of the current period; The second acquisition module is used to acquire n historical time differences for n consecutive historical periods. Each historical time difference is obtained by pre-calculating the time difference between the NTP time information and the local timekeeping information of the historical period corresponding to each historical time difference. The n consecutive historical periods include the previous period of the current period, and n is a positive integer greater than 1. The step fine-tuning module is used to compare the first time difference value and n historical time differences value, and to confirm the step fine-tuning parameters based on the comparison results. The step fine-tuning parameters include positive fine-tuning action parameters and negative fine-tuning action parameters. The local timekeeping module is used to adjust the local timekeeping accumulation logic according to the step fine-tuning parameters and output the current timestamp information.

8. A timestamp synchronization terminal, characterized in that, include: Storage media and processor; The storage medium stores computer-executed instructions. The processor executes computer execution instructions stored in the storage medium to implement the method as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1 to 6.

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