Synchronous signal generation method, device, chip and module equipment

Abstract

The application discloses a synchronization signal generation method and device, a chip and a module device. The method comprises the following steps: generating a second vertical synchronization (VSync) signal based on a first VSync signal, so that the generation time of the second VSync signal is infinitely close to the generation time of the first VSync signal; wherein the first VSync signal is used for triggering reading of video data corresponding to the first VSync signal from a first memory for first image quality processing, and storing the video data after the first image quality processing into a second memory; and the second VSync signal is used for triggering reading of video data corresponding to the second VSync signal from the second memory for second image quality processing. According to the method described in the application, the situation of frame dropping can be avoided without increasing the capacity of the second memory.

Description

Technical Field

[0001] The present invention relates to the field of communications, and in particular to a synchronization signal generation method, device, chip and module equipment. Background Art

[0002] Figure 1 FIG. 1 is a structural diagram of an existing video data processing device. Figure 1 As shown, a frame of video data is stored in the first memory, and the first image quality processing module generates a first vertical synchronization VSync signal. Based on the first VSync signal, the first image quality processing module reads the video data corresponding to the first VSync signal from the first memory to perform the first image quality processing, and then stores the processed video data in the second memory. The VSync signal can also be called a frame synchronization signal, which indicates the start of scanning a frame of video data. A frame of video data is also a display screen, and one VSync signal corresponds to one frame of video data. The timing control module generates a second VSync signal and sends the second VSync signal to the second image quality processing module. After receiving the second VSync signal, the second image quality processing module reads the video data corresponding to the second VSync signal from the second memory to perform the second image quality processing. In practice, it has been found that without increasing the capacity of the second memory, frame drops are prone to occur. Summary of the Invention

[0003] The present application provides a synchronization signal generation method, device, chip and module equipment, which are helpful in avoiding frame drops without increasing the capacity of the second memory.

[0004] In a first aspect, the present application provides a synchronization signal generation method, the method comprising:

[0005] A second VSync signal is generated based on the first vertical synchronization VSync signal, so that the generation time of the second VSync signal is infinitely close to the generation time of the first VSync signal. The first VSync signal is a VSync signal for first image quality processing, and the second VSync signal is a VSync signal for second image quality processing; wherein, the first VSync signal is used to trigger reading the video data corresponding to the first VSync signal from the first memory for first image quality processing, and storing the video data after the first image quality processing into the second memory; the second VSync signal is used to trigger reading the video data corresponding to the second VSync signal from the second memory for second image quality processing.

[0006] Based on the method described in the first aspect, it is helpful to avoid frame drops without increasing the capacity of the second memory.

[0007] In a possible implementation, the second VSync signal is generated based on the first VSync signal, including:

[0008] The second VSync signal is generated based on the first VSync signal, the first minimum interval threshold, and the first maximum interval threshold, the first minimum interval threshold being a minimum time interval between adjacent times of generating the second VSync signal, and the first maximum interval threshold being a maximum time interval between adjacent times of generating the second VSync signal.

[0009] Based on the possible implementation, the time interval between adjacent times of generating the second VSync signal is guaranteed to be between the first minimum interval threshold and the first maximum interval threshold, so that the time interval between adjacent times of generating the second VSync signal is prevented from suddenly becoming very small or very large, and picture jitter is avoided.

[0010] In a possible implementation, the second VSync signal is generated based on the first VSync signal, the first minimum interval threshold, and the first maximum interval threshold, including:

[0011] After the second VSync signal is generated, if the first VSync signal is detected between the first minimum interval threshold and the first maximum interval threshold, the second VSync signal is generated; if the first VSync signal is not detected between the first minimum interval threshold and the first maximum interval threshold, the second VSync signal is generated at the first maximum interval threshold, and it is continued to determine whether the first VSync signal is detected between the first minimum interval threshold and the first maximum interval threshold until the first VSync signal is detected between the first minimum interval threshold and the first maximum interval threshold.

[0012] Based on the optional manner, the generation time of the second VSync signal is step by step close to the generation time of the first VSync signal, and picture jitter is avoided.

[0013] In a possible implementation, the method further includes: performing MEMC processing on the video data corresponding to the second VSync signal after the motion estimation and motion compensation MEMC function is enabled; generating a third VSync signal, the third VSync signal being a VSync signal generated when the MEMC processing on the video data corresponding to the second VSync signal is completed; and generating the VSync signal for the target processing based on the third VSync signal, a second minimum interval threshold, and a second maximum interval threshold, so that a generation time of the VSync signal for the target processing is infinitely close to a generation time of the third VSync signal, the second minimum interval threshold being a minimum time interval between adjacent times of generating the VSync signal for the target processing, and the second maximum interval threshold being a maximum time interval between adjacent times of generating the VSync signal for the target processing, the target processing including an AISR (AI Super Resolution) processing based on a convolutional neural network and a video output processing, or the target processing including the video output processing.

[0014] In the possible implementation, the VSync signal for the target processing is generated based on the third VSync signal, the second minimum interval threshold, and the second maximum interval threshold, which helps to ensure that a time interval between adjacent times of generating the VSync signal for the target processing module is between the second minimum interval threshold and the second maximum interval threshold, and helps to avoid the time interval between the adjacent times of generating the VSync signal for the target processing module suddenly becoming very small or very large, thereby helping to avoid picture jitter.

[0015] In a possible implementation, the method further includes: performing, after the second image quality processing on the video data corresponding to the second VSync signal, the AISR processing based on the convolutional neural network and the video output processing on the video data corresponding to the second VSync signal in sequence.

[0016] In the possible implementation, before the AISR processing is performed, a time interval between adjacent two HSync signals for the second image quality processing is the same as a time interval between adjacent two HSync signals for the video output processing, and after the AISR processing is performed, the time interval between the adjacent two HSync signals for the second image quality processing is the same as a time interval between adjacent two HSync signals for the AISR processing, and a time interval between adjacent two HSync signals for the video output processing is less than the time interval between the adjacent two HSync signals for the AISR processing.

[0017] Since the amount of calculation of the AISR processing is large, 1 clock is calculated for 1 pixel or 4 clocks are calculated for 1 pixel, so by enlarging the time interval between the adjacent two HSync signals used for the AISR processing, it is beneficial to reduce the logic resources consumed by the AISR processing and reduce the power consumption of the device.

[0018] In a possible implementation, the method further includes: after performing the second image quality processing on the video data corresponding to the second VSync signal, sequentially performing the AISR processing and the MEMC processing on the video data corresponding to the second VSync signal, or sequentially performing the MEMC processing and the AISR processing on the video data corresponding to the second VSync signal, wherein the execution order of the AISR processing and the MEMC processing is determined based on the output resolution of the video data.

[0019] For example, if the output resolution of the video data is less than or equal to 4K, the AISR is placed before the MEMC, and if the output resolution is greater than 4K, the MEMC is placed before the AISR.

[0020] In this possible implementation, this can flexibly control the order of the AISR processing module and the MEMC processing module.

[0021] In a second aspect, the present application provides a communication apparatus, which comprises units for performing the method in the first aspect.

[0022] In a third aspect, the present application provides a chip, which comprises a processor and a communication interface, and the processor is configured to cause the chip to perform the method in the first aspect.

[0023] In a fourth aspect, the present application provides a module device, which comprises a communication module, a power supply module, a storage module, and a chip, wherein: the power supply module is configured to provide power for the module device; the storage module is configured to store data and instructions; the communication module is configured to perform internal communication of the module device, or to perform communication between the module device and an external device; and the chip is configured to perform the method in the first aspect.

[0024] In a fifth aspect, an embodiment of the present application discloses an electronic device, which comprises a memory and a processor, the memory is configured to store a computer program, the computer program comprises program instructions, and the processor is configured to invoke the program instructions to perform the method in the first aspect.

[0025] In a sixth aspect, the present application provides a computer readable storage medium, which stores computer readable instructions, when the computer readable instructions run on a communication apparatus, the communication apparatus performs the method in the first aspect.

[0026] In a seventh aspect, the present application provides a computer program or computer program product, comprising codes or instructions, which, when executed on a computer, cause the computer to perform the method according to the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0028] Figure 1 is a structural schematic diagram of a video data processing device;

[0029] Figure 2 is a structural schematic diagram of a synchronization signal generation device provided by the embodiments of the present application;

[0030] Figure 3 is a structural schematic diagram of another synchronization signal generation device provided by the embodiments of the present application;

[0031] Figure 4 is a schematic diagram of data processing delay provided by the embodiments of the present application;

[0032] Figure 5 is a structural schematic diagram of another synchronization signal generation device provided by the embodiments of the present application;

[0033] Figure 6 is a schematic diagram of another data processing delay provided by the embodiments of the present application;

[0034] Figure 7 is a structural schematic diagram of another synchronization signal generation device provided by the embodiments of the present application;

[0035] Figure 8 is a schematic diagram of another data processing delay provided by the embodiments of the present application;

[0036] Figure 9 is a structural schematic diagram of another synchronization signal generation device provided by the embodiments of the present application;

[0037] Figure 10 is a schematic diagram of another data processing delay provided by the embodiments of the present application;

[0038] Figure 11 is a schematic diagram of time interval of HSync signal provided by the embodiments of the present application;

[0039] Figure 12 is a flowchart of a method for generating a synchronization signal according to an embodiment of the present application;

[0040] Figure 13 is a structural diagram of an electronic device according to an embodiment of the present application;

[0041] Figure 14 is a structural diagram of a module device according to an embodiment of the present application. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of the present application.

[0043] The terms used in the embodiments of the present application are only for the purpose of describing the specific embodiments, and are not intended to be limiting of the present application. As used in the specification and the appended claims of the present application, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0044] In the embodiments of the present application, "and / or" describes the association relationship of the associated objects, which means that there can be three kinds of relationships. For example, A and / or B can represent the following three cases: A exists alone; A and B exist simultaneously; and B exists alone. Wherein, A and B can be singular or plural.

[0045] In the embodiments of the present application, the symbol " / " can represent that the associated objects before and after the symbol are in an "or" relationship. In addition, the symbol " / " can also represent the division symbol, that is, performing division operation. For example, A / B can represent A divided by B.

[0046] In the embodiments of the present application, "at least one" or similar expressions mean any combination of these items, including any combination of single item or multiple items, which means one or more, and multiple means two or more. For example, at least one of a, b or c can represent the following seven cases: a, b, c, a and b, a and c, b and c, a, b and c. Wherein, each of a, b and c can be an element or a set containing one or more elements.

[0047] In the embodiments of this application, "equal to" can be used in conjunction with "greater than" and is applicable to the technical solution adopted when "greater than" is used, and can also be used in conjunction with "less than" and is applicable to the technical solution adopted when "less than" is used. When "equal to" is used in conjunction with "greater than", it should not be used in conjunction with "less than"; when "equal to" is used in conjunction with "less than", it should not be used in conjunction with "greater than".

[0048] It should be noted that the terms "first", "second", "third", etc. in the specification and claims of the present application and in the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or server that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or devices.

[0049] The embodiments of the present application provide a synchronization signal generation method, device, chip, medium, and module device. The method can be performed by a synchronization signal generation device. Optionally, the synchronization signal generation device can be an electronic device or a chip within an electronic device, or the synchronization signal generation device can be a software module loaded into a terminal, or the synchronization signal generation device can be other types of products. Those skilled in the art can further expand upon the disclosure of this specification.

[0050] Among them, the electronic device may include a terminal, for example, the electronic device may be a mobile phone, a tablet computer, a computer with wireless transceiver function, a virtual reality (VR) user device, an augmented reality (AR) user device, a wireless terminal in industrial control, a vehicle-mounted user device, a wireless terminal in unmanned driving, a wireless terminal in telemedicine, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, a wearable user device, etc. The embodiments of the present application do not limit the application scenarios. The electronic device may sometimes also be referred to as a terminal, a user device, an access user device, a vehicle-mounted terminal, an industrial control terminal, a UE unit, a UE station, a mobile station, a mobile station, a remote station, a remote user device, a mobile device, a UE user device, a user device, a wireless communication device, a UE agent or a UE device, etc. The electronic device may also be any fixed or mobile device with a multi-mode communication function.

[0051] The following first introduces the synchronization signal generating device provided in the embodiment of the present application:

[0052] Figure 2 This is a schematic diagram of the structure of a synchronization signal generating device provided by an embodiment of the present application.Figure 2 As shown, the synchronization signal generation apparatus comprises a first memory 201, a first image quality processing module 202, a second memory 203, a time control module 204 and a second image quality processing module 205. Wherein:

[0053] The time control module 204 is configured to generate a second VSync signal based on a first vertical synchronization (VSync) signal, so that the generation time of the second VSync signal is infinitely close to the generation time of the first VSync signal, the first VSync signal is a VSync signal for first image quality processing, and the second VSync signal is a VSync signal for second image quality processing; wherein the first VSync signal is used to trigger the first image quality processing module 202 to read the video data corresponding to the first VSync signal from the first memory 201 for first image quality processing, and store the video data after the first image quality processing into the second memory 203; and the second VSync signal is used to trigger the second image quality processing module 205 to read the video data corresponding to the second VSync signal from the second memory 203 for second image quality processing.

[0054] In the embodiments of the present application, the first memory 201 is configured to store the input video data, and the second memory 203 is configured to store the video data processed by the first image quality processing module 202. The first image quality processing module 202 is configured to perform first image quality processing on the video data, such as reducing the video data and / or processing related to image quality, etc. The second image quality processing module 205 is configured to perform second image quality processing on the video data, such as enlarging the video data and / or filtering and / or processing related to image quality, etc. The time control module 204 is configured to control which frame and which line of video data is processed by the second image quality processing module 205.

[0055] The first image quality processing module 202 can generate a first VSync signal and a first horizonal synchronization (HSync) signal for the first image quality processing. The first VSync signal for the first image quality processing is used to trigger the first image quality processing on the video data of a frame corresponding to the first VSync signal read from the first memory, and to store the video data after the first image quality processing in the second memory. The first HSync signal for the first image quality processing is used to trigger the first image quality processing on the video data of a line corresponding to the first HSync signal read from the first memory, and to store the video data after the first image quality processing in the second memory. After generating one first VSync signal, the first image quality processing module 202 generates a plurality of first HSync signals. The VSync signal can also be referred to as a frame synchronization signal, indicating the start of scanning a frame of video data, and a frame of video data is also a display picture. One VSync signal corresponds to one frame of video data. The HSync signal can also be referred to as a line synchronization signal, indicating the start of scanning a line of video data. That is, the first image quality processing module 202 triggers the first image quality processing module 202 to obtain which frame and which line of video data for processing by generating the first VSync signal and the first HSync signal.

[0056] For example, assume that a frame of video data has 4320 lines of data. The first VSync signal 1 corresponds to the first frame of video data, the first HSync signal 1 corresponds to the first line of video data, the first HSync signal 2 corresponds to the second line of video data, and so on, and the first HSync signal 4320 corresponds to the 4320thline of video data. After the first image quality processing module 202 generates the first VSync signal 1, the first image quality processing module 202 generates the first HSync signal 1. After the first image quality processing module 202 generates the first HSync signal 1, the first image quality processing module 202 reads the first line of video data of the first frame of video data from the first memory 201 and performs first image quality processing on the first line of video data, and then stores the processed first line of video data in the second memory 203. Then the first image quality processing module 202 generates the first HSync signal 2. After the first image quality processing module 202 generates the first HSync signal 2, the first image quality processing module 202 reads the second line of video data of the first frame of video data from the first memory 201 and performs first image quality processing on the second line of video data, and then stores the processed second line of video data in the second memory 203. In this way, after the first image quality processing module 202 generates the first HSync signal 4320, the first image quality processing module 202 reads the 4320thline of video data of the first frame of video data from the first memory 201 and performs first image quality processing on the 4320thline of video data, and then stores the processed 4320thline of video data in the second memory 203. After the first frame of video data is processed, the first image quality processing module 202 generates the first VSync signal 2, which corresponds to the second frame of video data. After the first image quality processing module 202 generates the first VSync signal 2, the first image quality processing module 202 generates a plurality of first HSync signals corresponding to the first VSync signal 2, so that the first image quality processing module 202 reads a plurality of lines of video data of the second frame of video data from the first memory 201 and performs processing.

[0057] The time control module 204 can generate a second VSync signal for second image quality processing, and send the second VSync signal to the second image quality processing module 205. After the time control module 204 sends the second VSync signal to the second image quality processing module 205, the time control module 204 can generate a second HSync signal for second image quality processing. The second VSync signal for second image quality processing is used to trigger reading a frame of video data corresponding to the second VSync signal from the second memory for second image quality processing. The second HSync signal for second image quality processing is used to trigger reading a line of video data corresponding to the second HSync signal from the second memory for second image quality processing. That is, the time control module 204 triggers the second image quality processing module 205 to obtain which frame and which line of video data for processing by generating the second VSync signal and the second HSync signal.

[0058] In a possible implementation, the time control module 204 generates the second VSync signal based on the first VSync signal in the following manner: generating the second VSync signal based on the first VSync signal, a first minimum interval threshold, and a first maximum interval threshold, the first minimum interval threshold being a minimum time interval between adjacent times of generating the second VSync signal, and the first maximum interval threshold being a maximum time interval between adjacent times of generating the second VSync signal.

[0059] Based on the possible implementation, it is beneficial to ensure that the time interval between adjacent times of generating the second VSync signal is between the first minimum interval threshold and the first maximum interval threshold, avoiding the time interval between adjacent times of generating the second VSync signal suddenly becoming very small or very large, and thus avoiding screen flickering.

[0060] In a possible implementation, the time control module 204 generates the second VSync signal based on the first VSync signal, the first minimum interval threshold, and the first maximum interval threshold in the following manner:

[0061] After generating the second VSync signal, if the first VSync signal is detected within the first minimum interval threshold and the first maximum interval threshold, the second VSync signal is generated; if the first VSync signal is not detected within the first minimum interval threshold and the first maximum interval threshold, the second VSync signal is generated at the first maximum interval threshold, and the determination of whether the first VSync signal is detected within the first minimum interval threshold and the first maximum interval threshold is continued until the first VSync signal is detected within the first minimum interval threshold and the first maximum interval threshold.

[0062] For example, it is assumed that the first minimum interval threshold is 50 ms, and the first maximum interval threshold is 70 ms. After the time control module 204 generates the second VSync signal 1, when the first VSync signal is detected within the 50th ms and the 70th ms, the time control module 204 generates the second VSync signal 1, and at this time, the generation time of the second VSync signal is infinitely close to the generation time of the first VSync signal.

[0063] After the time control module 204 generates the second VSync signal 1, if the first VSync signal is not detected between the 50th ms and the 70th ms, the time control module 204 generates the second VSync signal 2 at the 70th ms, and starts the next round of locking of the first VSync signal. For example, after the time control module 204 generates the second VSync signal 2, if the first VSync signal is detected between the 50th ms and the 70th ms, the time control module 204 generates the second VSync signal 3. If the first VSync signal is not detected between the 50th ms and the 70th ms, the next round of locking of the first VSync signal is continuously started until the first VSync signal is detected between the 50th ms and the 70th ms after the generation of the second VSync signal.

[0064] Based on the possible implementation, it is beneficial to ensure that the time interval between the generation of the second VSync signal for two adjacent times is between the first minimum interval threshold and the first maximum interval threshold, to avoid the time interval between the generation of the second VSync signal for two adjacent times suddenly becoming very small or very large, to enable the generation time of the second VSync signal to gradually approach the generation time of the first VSync signal, and to be beneficial to avoid picture jitter.

[0065] In the described apparatus, Figure 2 By enabling the generation time of the second VSync signal to infinitely approach the generation time of the first VSync signal, it is possible to ensure that the speed of the first image quality processing module storing data into the second memory is equal to the speed of the second image quality processing module reading data from the second memory, thereby avoiding the occurrence of frame dropping. If the speed of the first image quality processing module storing data into the second memory is greater than the speed of the second image quality processing module reading data from the second memory, frame dropping may occur without increasing the capacity of the second memory. Therefore, by implementing Figure 2 The described apparatus is beneficial to avoid the occurrence of frame dropping without increasing the capacity of the second memory.

[0066] In one possible implementation, as shown in Figure 3 After the second image quality processing module 205, the synchronization signal generation apparatus can further include a video output module 206. The video output module 206 is configured to output video data corresponding to the second VSync signal.

[0067] The time control module 204 can generate a second VSync signal for the second image quality processing and for the video output, and send the second VSync signal to the second image quality processing module 205 and the video output module 206. After the time control module 204 sends the second VSync signal to the second image quality processing module 205 and the video output module 206, the time control module 204 can generate a second HSync signal for the second image quality processing and a second HSync signal for the video output. That is, the time control module 204 triggers the second image quality processing module 205 and the video output module 206 to acquire which frame and which line of video data to process by generating the second VSync signal and the second HSync signal.

[0068] Because of the processing delay, the first generation time of the second HSync signal for different processing can be different. For example, as shown in FIG. 2B, assuming that the processing delay of the second image quality processing module 205 is 4 lines of data, the second HSync signal for the second image quality processing is generated 4 times, and then the second HSync signal for the video output is generated for the first time. Figure 4

[0069] In a possible implementation, as shown in FIG. 2C, after the second image quality processing module 205, the synchronization signal generation apparatus can further include an AISR (super-resolution magnification based on a convolutional neural network) processing module 207 and a video output module 206. The AISR processing module 207 and the video output module 206 are used to sequentially perform AISR processing and video output processing on the video data corresponding to the second VSync signal. Figure 5

[0070] The time control module 204 can generate a second VSync signal for the second image quality processing, the AISR processing, and the video output, and send the second VSync signal to the second image quality processing module 205, the AISR processing module 207, and the video output module 206. After the time control module 204 sends the second VSync signal to the second image quality processing module 205, the AISR processing module 207, and the video output module 206, the time control module 204 can generate a second HSync signal for the second image quality processing, a second HSync signal for the AISR processing, and a second HSync signal for the video output. That is, the time control module 204 triggers the second image quality processing module 205, the AISR processing module 207, and the video output module 206 to acquire which frame and which line of video data to process by generating the second VSync signal and the second HSync signal.

[0071] Because of the processing delay, the first generation time of the second HSync signal for different processing can be different. For example, as shown in FIG. 2B, assuming that the processing delay of the second image quality processing module 205 is 4 lines of data, the second HSync signal for the second image quality processing is generated 4 times, and then the second HSync signal for the video output is generated for the first time.​​Figure 6 As shown, assuming that the processing time delay of the second image quality processing module 205 is 4 lines of data and the processing time delay of the AISR processing module 207 is 3 lines of data, the second HSync signal for the AISR processing is generated for the first time after the second HSync signal for the second image quality processing is generated for the fourth time. The second HSync signal for the video output is generated for the first time after the second HSync signal for the AISR processing is generated for the third time.

[0072] In a possible implementation, as shown in FIG. 2, the synchronization signal generation apparatus can further include a second image quality processing module 205. Figure 7 As shown, after the second image quality processing module 205, the synchronization signal generation apparatus can further include a MEMC (motion estimation and motion compensation) processing module 208 and a video output module 206. The MEMC processing module 208 and the video output processing module are configured to sequentially perform MEMC processing and video output processing on video data corresponding to the second VSync signal.

[0073] The time control module 204 can generate the second VSync signal for the second image quality processing and the MEMC processing, and send the second VSync signal to the second image quality processing module 205 and the MEMC processing module 208. After the time control module 204 sends the second VSync signal to the second image quality processing module 205 and the MEMC processing module 208, the time control module 204 can generate the second HSync signal for the second image quality processing and the second HSync signal for the MEMC processing. That is, the time control module 204 triggers the second image quality processing module 205 and the MEMC processing module 208 to acquire which frame and which line of video data to process by generating the second VSync signal and the second HSync signal.

[0074] The MEMC processing module 208 can generate a third VSync signal by itself and send the third VSync signal to the time control module 204 when the processing of a certain frame of video data is completed. The MEMC processing module 208 can generate a third HSync signal by itself and send the third HSync signal to the time control module 204 when the processing of a certain line of data is completed. The time control module 204 generates a VSync signal for video output after receiving the third VSync signal, and generates a HSync signal for video output after receiving the third HSync signal. That is, the timing of the video output module 206 (i.e., the VSync signal and the HSync signal) is based on the timing generated by the MEMC processing module 208.

[0075] Because of the processing delay, the first generation time of the second HSync signal for different processing can be different. For example, as shown in FIG. 2, the first generation time of the second HSync signal for the second image quality processing is different from the first generation time of the second HSync signal for the AISR processing. Figure 8As shown in FIG. 6, assuming that the processing time delay of the second image quality processing module 205 is 4 lines of data, the second HSync signal for the second image quality processing is generated 4 times, and the first second HSync signal for the MEMC processing is generated.

[0076] In a possible implementation, as shown in FIG. 7, the synchronization signal generation apparatus further includes an AISR processing module 207 and a MEMC processing module 208. Figure 9 As shown in FIG. 7, the synchronization signal generation apparatus further includes the AISR processing module 207, the MEMC processing module 208 and a video output module 206 after the second image quality processing module 205.

[0077] The time control module 204 triggers the second image quality processing module 205, the AISR processing module 207 and the MEMC processing module 208 to acquire which frame and which line of video data for processing by generating the second VSync signal and the second HSync signal. The timing of the video output module 206 (i.e., the VSync signal and the HSync signal) is based on the timing generated by the MEMC processing module 208 itself.

[0078] Because of the processing delay, the first generation time of the second HSync signal for different processing may be different. For example, as shown in FIG. 8, assuming that the processing time delay of the second image quality processing module 205 is 4 lines of data, and the processing time delay of the AISR processing module 207 is 3 lines of data, the second HSync signal for the second image quality processing is generated 4 times, and the first second HSync signal for the AISR processing is generated. The second HSync signal for the AISR processing is generated 3 times, and the first second HSync signal for the MEMC processing is generated. Figure 10 In a possible implementation, if

[0079] the MEMC processing module 208 is located before the AISR processing module 207 in FIG. 9, the time control module 204 triggers the second image quality processing module 205 and the MEMC processing module 208 to acquire which frame and which line of video data for processing by generating the second VSync signal and the second HSync signal. The timing of the AISR processing module 207 and the video output module 206 is based on the timing generated by the MEMC processing module 208 itself. Figure 9 In a possible implementation, the synchronization signal generation apparatus further includes the MEMC processing module 208 and a target processing module, the target processing module being located after the MEMC processing module 208; the target processing module includes the AISR processing module 207 and the video output module 206, or the target processing module includes the video output module 206.

[0080]

[0081] ​The MEMC processing module 208 is configured to perform MEMC processing on the video data corresponding to the second VSync signal after the MEMC function is enabled.

[0082] The MEMC processing module 208 is configured to generate a third VSync signal, which is a VSync signal generated when the MEMC processing on the video data corresponding to the second VSync signal is completed.

[0083] The time control module 204 is further configured to generate the VSync signal for the target processing based on the third VSync signal, a second minimum interval threshold and a second maximum interval threshold, so that the generation time of the VSync signal for the target processing is close to the generation time of the third VSync signal. The second minimum interval threshold is a minimum time interval between two adjacent times of generating the VSync signal for the target processing. The second maximum interval threshold is a maximum time interval between two adjacent times of generating the VSync signal for the target processing. The target processing includes the AISR processing and the video output processing, or the target processing includes the video output processing.

[0084] In this possible implementation, the synchronization signal generation apparatus further includes the MEMC processing module 208 and the target processing module in sequence after the second image quality processing module 205. The MEMC processing module 208 has an enabled state and a disabled state. In one case, the target processing module includes the AISR processing module 207 and the video output module 206. In another case, the target processing module includes the video output module 206. The synchronization signal generation apparatus can include the AISR processing module 207 before the MEMC processing module 208, or the AISR processing module 207 can not be included in the synchronization signal generation apparatus.

[0085] Before the MEMC processing module 208 is enabled, the VSync signal for the target processing is generated by the time control module 204 based on the first VSync signal for the first image quality processing module 202. After the MEMC processing module 208 is enabled, the VSync signal for the target processing is generated by the time control module 204 based on the third VSync signal generated by the MEMC processing module 208. If the time control module 204 immediately generates the VSync signal for the target processing after the MEMC processing module 208 generates the third VSync signal, the time interval between two adjacent times of generating the VSync signal for the target processing can suddenly become very small or very large, causing picture jitter.

[0086] In the possible implementation, the VSync signal for the target processing is generated based on the third VSync signal, the second minimum interval threshold and the second maximum interval threshold, so as to ensure that the time interval between two adjacent times of generating the VSync signal for the target processing is between the second minimum interval threshold and the second maximum interval threshold, and to avoid that the time interval between two adjacent times of generating the VSync signal for the target processing processing module is suddenly small or suddenly large, thereby avoiding picture jitter.

[0087] Optionally, the specific implementation of generating the VSync signal for the target processing based on the third VSync signal, the second minimum interval threshold and the second maximum interval threshold is as follows:

[0088] After the VSync signal for the target processing is generated, if the third VSync signal is detected between the second minimum interval threshold and the second maximum interval threshold, the VSync signal for the target processing is generated; if the third VSync signal is not detected between the second minimum interval threshold and the second maximum interval threshold, the VSync signal for the target processing is generated at the second maximum interval threshold, and the determination of whether the third VSync signal is detected between the second minimum interval threshold and the second maximum interval threshold is continued until the third VSync signal is detected between the second minimum interval threshold and the second maximum interval threshold.

[0089] Based on the optional manner, the generation time of the VSync signal for the target processing gradually approaches the generation time of the third VSync signal, thereby avoiding picture jitter.

[0090] In a possible implementation, after the second image quality processing module 205, the synchronization signal generation apparatus further includes an AISR processing module 207 and a video output module 206.

[0091] Before the AISR processing is performed, the time interval between two adjacent HSync signals for the second image quality processing is the same as the time interval between two adjacent HSync signals for the video output processing; after the AISR processing is performed, the time interval between two adjacent HSync signals for the second image quality processing is the same as the time interval between two adjacent HSync signals for the AISR processing, and the time interval between two adjacent HSync signals for the video output processing is smaller than the time interval between two adjacent HSync signals for the AISR processing. For example, as shown in FIG. 6. Figure 11

[0092] ​Since the amount of calculation of the AISR processing is large, 1 clock is calculated for 1 pixel or 4 clocks are calculated for one pixel, so by enlarging the time interval between the adjacent two HSync signals used for the AISR processing, the logical resources consumed by the AISR processing are reduced and the power consumption of the device is reduced.

[0093] In a possible implementation, the synchronization signal generation apparatus further includes an AISR processing module 207 and a MEMC processing module 208; the sequence of the AISR processing module and the MEMC processing module is determined based on the output resolution of the video data, that is, the sequence of the AISR processing module and the MEMC processing module is flexible and not fixed, so that the sequence of the AISR processing module and the MEMC processing module can be flexibly controlled.

[0094] For example, if the output resolution of the video data is less than or equal to 4K, the AISR is placed before the MEMC, and if the output resolution is greater than 4K, the MEMC is placed before the AISR.

[0095] The synchronization signal generation method provided by the embodiment of the application is further described below:

[0096] Please refer to Figure 12 , Figure 12 is a flowchart of a synchronization signal generation method provided by the embodiment of the application, and the synchronization signal generation method includes step 1201. Wherein:

[0097] 1201、The synchronization signal generation apparatus generates a second VSync signal based on a first VSync signal, so that the generation time of the second VSync signal is infinitely close to the generation time of the first VSync signal, the first VSync signal is a VSync signal used for first image quality processing, and the second VSync signal is a VSync signal used for second image quality processing.

[0098] Wherein, the first VSync signal is used to trigger reading of video data corresponding to the first VSync signal from a first memory for first image quality processing, and storing the video data after the first image quality processing in a second memory; the second VSync signal is used to trigger reading of video data corresponding to the second VSync signal from the second memory for second image quality processing. For related description of the first VSync signal and the second VSync signal, please refer to the description in the foregoing description which is not repeated here.

[0099] In a possible implementation, the specific implementation of the synchronization signal generation apparatus generating the second VSync signal based on the first VSync signal is: generating the second VSync signal based on the first VSync signal, a first minimum interval threshold, and a first maximum interval threshold, the first minimum interval threshold being a minimum time interval between adjacent times of generating the second VSync signal, and the first maximum interval threshold being a maximum time interval between adjacent times of generating the second VSync signal.

[0100] Based on the possible implementation, the time interval between adjacent times of generating the second VSync signal is guaranteed to be between the first minimum interval threshold and the first maximum interval threshold, which avoids the time interval between adjacent times of generating the second VSync signal suddenly becoming very small or very large, and helps to avoid picture jitter.

[0101] In a possible implementation, the specific implementation of the synchronization signal generation apparatus generating the second VSync signal based on the first VSync signal, the first minimum interval threshold, and the first maximum interval threshold is:

[0102] After generating the second VSync signal, if the first VSync signal is detected between the first minimum interval threshold and the first maximum interval threshold, the second VSync signal is generated; if the first VSync signal is not detected between the first minimum interval threshold and the first maximum interval threshold, the second VSync signal is generated at the first maximum interval threshold, and the determination of whether the first VSync signal is detected between the first minimum interval threshold and the first maximum interval threshold is continued until the first VSync signal is detected between the first minimum interval threshold and the first maximum interval threshold.

[0103] Based on the optional manner, the generation time of the second VSync signal can gradually approach the generation time of the first VSync signal, which helps to avoid picture jitter.

[0104] In the described method, Figure 12 In the described method, by making the generation time of the second VSync signal infinitely close to the generation time of the first VSync signal, it can be guaranteed that the speed of the first image quality processing module storing data into the second memory is equal to the speed of the second image quality processing module reading data from the second memory, thereby avoiding the occurrence of frame dropping. If the speed of the first image quality processing module storing data into the second memory is greater than the speed of the second image quality processing module reading data from the second memory, frame dropping may occur without increasing the capacity of the second memory. Therefore, by implementing the described method, frame dropping can be avoided without increasing the capacity of the second memory. Figure 12 In the described method, by making the generation time of the second VSync signal infinitely close to the generation time of the first VSync signal, it can be guaranteed that the speed of the first image quality processing module storing data into the second memory is equal to the speed of the second image quality processing module reading data from the second memory, thereby avoiding the occurrence of frame dropping. If the speed of the first image quality processing module storing data into the second memory is greater than the speed of the second image quality processing module reading data from the second memory, frame dropping may occur without increasing the capacity of the second memory. Therefore, by implementing the described method, frame dropping can be avoided without increasing the capacity of the second memory.

[0105] In a possible implementation, the synchronization signal generation apparatus can further perform the following operations:

[0106] (1) after detecting that the MEMC function is turned on, performing MEMC processing on video data corresponding to the second VSync signal;

[0107] (2) generating a third VSync signal, the third VSync signal being a VSync signal generated when the MEMC processing on the video data corresponding to the second VSync signal is completed;

[0108] (3) generating, based on the third VSync signal, a second minimum interval threshold, and a second maximum interval threshold, a VSync signal for target processing, so that a generation time of the VSync signal for target processing is infinitely close to a generation time of the third VSync signal, the second minimum interval threshold being a minimum time interval between adjacent times of generating the VSync signal for target processing, and the second maximum interval threshold being a maximum time interval between adjacent times of generating the VSync signal for target processing, the target processing including AISR processing and video output processing, or the target processing including video output processing.

[0109] In this possible implementation, the VSync signal for target processing is generated based on the third VSync signal, the second minimum interval threshold, and the second maximum interval threshold, which is conducive to ensuring that a time interval between adjacent times of generating the VSync signal for target processing is between the second minimum interval threshold and the second maximum interval threshold, avoiding the time interval between adjacent times of generating the VSync signal for target processing suddenly becoming very small or very large, and being conducive to avoiding picture jitter.

[0110] Optionally, a specific implementation of generating the VSync signal for target processing based on the third VSync signal, the second minimum interval threshold, and the second maximum interval threshold is as follows:

[0111] After the VSync signal for target processing is generated, if the third VSync signal is detected between the second minimum interval threshold and the second maximum interval threshold, the VSync signal for target processing is generated; if the third VSync signal is not detected between the second minimum interval threshold and the second maximum interval threshold, the VSync signal for target processing is generated at the second maximum interval threshold, and it is continued to determine whether the third VSync signal is detected between the second minimum interval threshold and the second maximum interval threshold until the third VSync signal is detected between the second minimum interval threshold and the second maximum interval threshold.

[0112] Based on the optional manner, the generation time of the VSync signal used for target processing can gradually approach the generation time of the third VSync signal, which is beneficial to avoid picture jitter.

[0113] In a possible implementation, after the second image quality processing is performed on the video data corresponding to the second VSync signal, the synchronization signal generation apparatus can further sequentially perform AISR processing and video output processing on the video data corresponding to the second VSync signal; wherein, before the AISR processing is performed, the time interval between adjacent two HSync signals used for the second image quality processing is the same as the time interval between adjacent two HSync signals used for the video output processing; after the AISR processing is performed, the time interval between adjacent two HSync signals used for the second image quality processing is the same as the time interval between adjacent two HSync signals used for the AISR processing, and the time interval between adjacent two HSync signals used for the video output processing is less than the time interval between adjacent two HSync signals used for the AISR processing.

[0114] Since the AISR processing has a large amount of calculation, one clock is used to calculate one pixel or four clocks are used to calculate one pixel, and therefore, by enlarging the time interval between adjacent two HSync signals used for the AISR processing, it is beneficial to reduce the logic resources consumed by the AISR processing and reduce the power consumption of the device.

[0115] In a possible implementation, after the second image quality processing is performed on the video data corresponding to the second VSync signal, the synchronization signal generation apparatus can further sequentially perform AISR processing and MEMC processing on the video data corresponding to the second VSync signal, or sequentially perform MEMC processing and AISR processing on the video data corresponding to the second VSync signal; wherein, the execution order of the AISR processing and the MEMC processing is determined based on the output resolution of the video data.

[0116] For example, if the output resolution of the video data is less than or equal to 4K, the AISR is placed before the MEMC, and if the output resolution is greater than 4K, the MEMC is placed before the AISR.

[0117] In this possible implementation, the order of the AISR processing module and the MEMC processing module can be flexibly controlled.

[0118] Embodiments of the present application further provide a chip, which can perform the related steps of the synchronization signal generation apparatus in the foregoing method embodiments. The chip comprises a processor and a communication interface, and the processor is configured to enable the chip to perform the following operations:

[0119] The second VSync signal is generated based on the first VSync signal, a first minimum interval threshold and a first maximum interval threshold, the first minimum interval threshold being a minimum time interval between adjacent two times of generating the second VSync signal, and the first maximum interval threshold being a maximum time interval between adjacent two times of generating the second VSync signal.

[0120] The first VSync signal is used to trigger reading of video data corresponding to the first VSync signal from the first memory for the first image quality processing, and the video data after the first image quality processing is stored into the second memory; and the second VSync signal is used to trigger reading of video data corresponding to the second VSync signal from the second memory for the second image quality processing.

[0121] In a possible implementation, the second VSync signal is generated based on the first VSync signal, including:

[0122] The second VSync signal is generated based on the first VSync signal, a first minimum interval threshold and a first maximum interval threshold, the first minimum interval threshold being a minimum time interval between adjacent two times of generating the second VSync signal, and the first maximum interval threshold being a maximum time interval between adjacent two times of generating the second VSync signal.

[0123] In a possible implementation, the second VSync signal is generated based on the first VSync signal, a first minimum interval threshold and a first maximum interval threshold, including:

[0124] After the second VSync signal is generated, if the first VSync signal is detected between the first minimum interval threshold and the first maximum interval threshold, the second VSync signal is generated;

[0125] If the first VSync signal is not detected between the first minimum interval threshold and the first maximum interval threshold, the second VSync signal is generated at the first maximum interval threshold, and it is continued to determine whether the first VSync signal is detected between the first minimum interval threshold and the first maximum interval threshold until the first VSync signal is detected between the first minimum interval threshold and the first maximum interval threshold.

[0126] In a possible implementation, the processor is further configured to cause the chip to perform the following operation: after the motion estimation and motion compensation MEMC function is started, the video data corresponding to the second VSync signal is processed by MEMC;

[0127] A third VSync signal is generated, the third VSync signal being a VSync signal generated when the MEMC processing of the video data corresponding to the second VSync signal is completed;

[0128] generate the VSync signal for the target processing based on the third VSync signal, a second minimum interval threshold and a second maximum interval threshold, so that a generation time of the VSync signal for the target processing is infinitely close to a generation time of the third VSync signal, the second minimum interval threshold is a minimum time interval between adjacent two times of generating the VSync signal for the target processing, and the second maximum interval threshold is a maximum time interval between adjacent two times of generating the VSync signal for the target processing, the target processing includes an AISR processing based on a convolutional neural network and a video output processing, or the target processing includes the video output processing.

[0129] In a possible implementation, the processor is further configured to cause the chip to perform the following operation: after performing the second image quality processing on the video data corresponding to the second VSync signal, sequentially performing an AISR processing based on a convolutional neural network and a video output processing on the video data corresponding to the second VSync signal.

[0130] In a possible implementation, the processor is further configured to cause the chip to perform the following operation: after performing the second image quality processing on the video data corresponding to the second VSync signal, sequentially performing an AISR processing based on a convolutional neural network and a video output processing on the video data corresponding to the second VSync signal.

[0131] In a possible implementation, the processor is further configured to cause the chip to perform the following operation: after performing the second image quality processing on the video data corresponding to the second VSync signal, sequentially performing an AISR processing based on a convolutional neural network and a video output processing on the video data corresponding to the second VSync signal.

[0132] Please refer to Figure 13 , Figure 13 is a structural schematic diagram of an electronic device provided by an embodiment of the present application. The electronic device 1300 can include a memory 1301, a processor 1302, and optionally a communication interface 1303. The memory 1301, the processor 1302 and the communication interface 1303 are connected through one or more communication buses. The communication interface 1303 is controlled by the processor 1302 for transmitting and receiving information.

[0133] The memory 1301 can include a read-only memory and a random access memory, and provide the processor 1302 with instructions and data. A portion of the memory 1301 can also include a non-volatile random access memory.

[0134] The communication interface 1303 is configured to receive or send data.

[0135] The processor 1302 can be a central processing unit (CPU), and can also be other general-purpose processors, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor, or the processor 1302 can also be any conventional processor, etc. Wherein:

[0136] The memory 1301 is configured to store program instructions.

[0137] The processor 1302 is configured to call the program instructions stored in the memory 1301.

[0138] The processor 1302 calls the program instructions stored in the memory 1301, so that the electronic device 1300 executes the method performed by the electronic device in the above method embodiment.

[0139] As shown in Figure 14 , Figure 14 is a structural schematic diagram of a module device provided by an embodiment of the application. The module device 1400 can execute the related steps of the electronic device in the foregoing method embodiments. The module device 1400 includes a communication module 1401, a power module 1402, a storage module 1403 and a chip 1404.

[0140] The power module 1402 is configured to provide power for the module device; the storage module 1403 is configured to store data and instructions; the communication module 1401 is configured to perform internal communication of the module device, or to perform communication between the module device and an external device; and the chip 1404 is configured to execute the method performed by the electronic device in the above method embodiments.

[0141] It should be noted that, Figure 13 and Figure 14The content not mentioned in the corresponding embodiments and the specific implementation of each step can refer to the content of the method embodiments, which will not be repeated here.

[0142] The embodiment of the present application further provides a computer readable storage medium, which stores instructions, when the instructions are run on a processor, the method flow of the method embodiment is realized.

[0143] The embodiment of the present application further provides a computer program product, when the computer program product is run on a processor, the method flow of the method embodiment is realized.

[0144] As to each means or unit described in the embodiments of the present application, they can be a software module / program, a hardware module, or a combination of software and hardware. For example, as to each means or unit applied in or integrated in a chip, they can be realized in a form of hardware, or at least in a part of them can be realized in a form of software program running in a processor integrated in the chip; as to each means or unit applied in or integrated in a chip module, they can be realized in a form of hardware, or at least in a part of them can be realized in a form of software program running in a processor integrated in the chip module; as to each means or unit applied in or integrated in a terminal, they can be realized in a form of hardware, or at least in a part of them can be realized in a form of software program running in a processor integrated in the terminal.

[0145] It should be noted that, for the foregoing method embodiments, in order to simply describe, they are all described as a series of action combinations, but those skilled in the art should know that the present application is not limited to the order of the actions described, because according to the present application, some operations can be performed in other order or at the same time. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0146] The descriptions of the various embodiments provided in the present application can be referred to each other, and the descriptions of the various embodiments are each focused on. The parts not described in detail in a certain embodiment can be referred to the related descriptions of other embodiments. For the convenience and brevity of description, for example, the functions of the various devices and the operations performed by the devices provided in the embodiments of the present application can be referred to the related descriptions of the method embodiments of the present application, and the various method embodiments can also be referred to, combined or cited each other.

[0147] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A synchronization signal generation method, characterized in that: The method comprises: After generating the second VSync signal, if the first VSync signal is detected between the first minimum interval threshold and the first maximum interval threshold, generating the second VSync signal again; If the first VSync signal is not detected between the first minimum interval threshold and the first maximum interval threshold, a second VSync signal is generated at the first maximum interval threshold, and whether the first VSync signal is detected between the first minimum interval threshold and the first maximum interval threshold is continuously determined until the first VSync signal is detected between the first minimum interval threshold and the first maximum interval threshold, so that the generation time of the second VSync signal is infinitely close to the generation time of the first VSync signal, the first VSync signal is a VSync signal used for first image quality processing, and the second VSync signal is a VSync signal used for second image quality processing; the first minimum interval threshold is the minimum time interval between two adjacent generation of the second VSync signal, and the first maximum interval threshold is the maximum time interval between two adjacent generation of the second VSync signal; Among them, the first VSync signal is used to trigger the reading of the video data corresponding to the first VSync signal from the first memory for first image quality processing, and the video data after the first image quality processing is stored in the second memory; the second VSync signal is used to trigger the reading of the video data corresponding to the second VSync signal from the second memory for second image quality processing.

2. The method according to claim 1, characterized in that The method further comprises: After the motion estimation and motion compensation MEMC function is turned on, performing MEMC processing on the video data corresponding to the second VSync signal; generating a third VSync signal, where the third VSync signal is a VSync signal generated when MEMC processing is completed on the video data corresponding to the second VSync signal; A VSync signal for target processing is generated based on the third VSync signal, the second minimum interval threshold and the second maximum interval threshold, so that the generation time of the VSync signal for target processing is infinitely close to the generation time of the third VSync signal, the second minimum interval threshold is the minimum time interval between two adjacent generation of VSync signals for target processing, and the second maximum interval threshold is the maximum time interval between two adjacent generation of VSync signals for target processing, the target processing includes super-resolution amplification AISR processing based on convolutional neural network and video output processing, or the target processing includes video output processing.

3. The method according to claim 1 or 2, characterized in that The method further comprises: After performing second image quality processing on the video data corresponding to the second VSync signal, the video data corresponding to the second VSync signal is sequentially subjected to super-resolution upscaling AISR processing based on a convolutional neural network and video output processing; Among them, before the AISR processing is executed, the time interval between two adjacent horizontal synchronization HSync signals used for the second image quality processing is the same as the time interval between two adjacent HSync signals used for video output processing; after the AISR processing is executed, the time interval between two adjacent HSync signals used for the second image quality processing is the same as the time interval between two adjacent HSync signals used for the AISR processing, and the time interval between two adjacent HSync signals used for video output processing is less than the time interval between two adjacent HSync signals used for the AISR processing.

4. The method according to claim 1 or 2, characterized in that The method further comprises: After performing the second image quality processing on the video data corresponding to the second VSync signal, super-resolution amplification AISR processing and motion estimation and motion compensation MEMC processing based on convolutional neural network are sequentially performed on the video data corresponding to the second VSync signal, or MEMC processing and AISR processing are sequentially performed on the video data corresponding to the second VSync signal; wherein, the execution order of the AISR processing and the MEMC processing is determined based on the output resolution of the video data.

5. A synchronization signal generating device, characterized in that: The device comprises: a timing control module, configured to, after generating the second VSync signal, generate the second VSync signal again if the first VSync signal is detected between the first minimum interval threshold and the first maximum interval threshold; The timing control module is further configured to, if the first VSync signal is not detected between the first minimum interval threshold and the first maximum interval threshold, generate a second VSync signal at the first maximum interval threshold, and continue to determine whether the first VSync signal is detected between the first minimum interval threshold and the first maximum interval threshold until the first VSync signal is detected between the first minimum interval threshold and the first maximum interval threshold, so that the generation time of the second VSync signal is infinitely close to the generation time of the first VSync signal, the first VSync signal is a VSync signal used for first image quality processing, and the second VSync signal is a VSync signal used for second image quality processing; the first minimum interval threshold is a minimum time interval between two adjacent generation of the second VSync signal, and the first maximum interval threshold is a maximum time interval between two adjacent generation of the second VSync signal; Among them, the first VSync signal is used to trigger the reading of the video data corresponding to the first VSync signal from the first memory for first image quality processing, and store the video data after the first image quality processing in the second memory; the second VSync signal is used to trigger the reading of the video data corresponding to the second VSync signal from the second memory for second image quality processing.

6. A chip, characterized in that: The method comprises a processor and a communication interface, wherein the processor is configured to execute the method according to any one of claims 1 to 4.

7. A module device, characterized in that: The module device includes a communication module, a power module, a storage module and a chip, wherein: The power supply module is used to provide electrical energy to the module device; The storage module is used to store data and instructions; The communication module is used for internal communication of the module device, or for communication between the module device and an external device; The chip is used to execute the method according to any one of claims 1 to 4.

8. An electronic device, characterized in that: The method comprises a memory and a processor, wherein the memory is used to store a computer program, the computer program comprises program instructions, and the processor is configured to call the program instructions to execute the method according to any one of claims 1 to 4.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-readable instructions, and when the computer-readable instructions are executed on a communication device, the communication device is caused to execute the method according to any one of claims 1 to 4.

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