Oxide semiconductor layer, thin film transistor and method for manufacturing the same, display panel, and display device

Abstract

A thin film transistor includes a substrate, a semiconductor layer disposed on the substrate, the semiconductor layer including a first surface proximate the substrate and a second surface distal from the substrate, the semiconductor layer having a material that is a metal oxide semiconductor material; the semiconductor layer having a channel region, the semiconductor layer having crystals of the metal oxide semiconductor formed at least in the channel region and proximate the first surface or the second surface.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to an oxide semiconductor layer, a thin-film transistor and its fabrication method, a display panel and a display device. Background Technology

[0002] Thin Film Transistor (TFT) is a semiconductor device commonly used in flat panel displays. As a pixel control and driving device in flat panel displays, it influences the development of flat panel displays. Summary of the Invention

[0003] On one hand, a thin-film transistor is provided, comprising: a substrate, and a semiconductor layer disposed on the substrate, the semiconductor layer including a first surface near the substrate and a second surface away from the substrate, the semiconductor layer being made of a metal oxide semiconductor material; the semiconductor layer having a channel region, and the semiconductor layer having a metal oxide semiconductor crystal formed at least in the channel region and near the first surface or the second surface.

[0004] In some embodiments, the thickness of the crystal in the semiconductor layer is greater than or equal to 1 / 4 of the thickness of the semiconductor layer and less than or equal to the thickness of the semiconductor layer.

[0005] In some embodiments, the size of the distribution range of the crystal along the length direction of the channel of the semiconductor layer is greater than or equal to 1 / 2 of the length of the channel of the semiconductor layer and less than or equal to the length of the channel of the semiconductor layer.

[0006] In some embodiments, the device further includes: a metal oxide layer that at least covers the middle portion of the channel region along the length of the channel, and the dimension of the metal oxide layer along the length of the channel is greater than or equal to 1 / 2 of the length of the channel, the metal oxide layer being in contact with the semiconductor layer.

[0007] In some embodiments, the semiconductor layer further includes a gate insulating layer, wherein the metal oxide layer is disposed between the gate insulating layer and the semiconductor layer.

[0008] In some embodiments, the crystal distribution density gradually increases in the semiconductor layer along the direction gradually approaching the metal oxide layer.

[0009] In some embodiments, the material of the semiconductor layer is selected from either indium zinc tin oxide or indium gallium zinc oxide; the indium zinc tin oxide and the indium gallium zinc oxide may or may not be doped with rare earth elements.

[0010] In some embodiments, when the indium zinc tin oxide and the indium gallium zinc oxide are doped with rare earth elements, the rare earth elements are Pr or Tb.

[0011] In some embodiments, when the material of the semiconductor layer is selected from indium zinc tin oxide, the ratio of the number of In atoms, Sn atoms, and Zn atoms in the indium zinc tin oxide is 4:2:4; or, the ratio of the number of In atoms, Sn atoms, and Zn atoms in the indium gallium zinc oxide is 2:4:4; when the material of the semiconductor layer is selected from indium gallium zinc oxide, the ratio of the number of In atoms, Ga atoms, and Zn atoms in the indium gallium zinc oxide is 1:1:1.

[0012] In some embodiments, the doping concentration of the rare earth element is 2 at%.

[0013] In some embodiments, the oxygen vacancy concentration in the semiconductor layer is less than or equal to 10%.

[0014] On the other hand, a display panel is provided, including: thin-film transistors as described above.

[0015] On the other hand, a display device is provided, comprising: a display panel as described above.

[0016] On the other hand, a method for fabricating a thin-film transistor is provided, wherein the thin-film transistor includes: a semiconductor layer having a channel region; the fabrication method includes: forming a first material layer and a second material layer stacked on a substrate, the first material layer and the second material layer being in contact, wherein the first material layer covers the entire layer, or the first material layer has the same pattern as the semiconductor layer, the orthographic projection of the second material layer on the substrate covers at least the middle portion of the first material layer corresponding to the channel region along the length direction of the channel, and the dimension of the orthographic projection of the second material layer on the substrate along the length direction of the channel is greater than or equal to 1 / 2 of the length of the channel, wherein the material of the first material layer is a metal oxide semiconductor material, and the material of the second material layer is a metal or a metal oxide.

[0017] The first material layer and the second material layer are heated so that the second material layer is induced to form a metal oxide semiconductor crystal at least on the surface of the first material layer near the second material layer at a preset temperature, wherein the preset temperature is greater than or equal to 200°C and less than or equal to 420°C.

[0018] With the first material layer covering the entire surface, after induction is complete, the first material layer is patterned to form a semiconductor layer.

[0019] In some embodiments, the preset temperature is less than or equal to 400°C.

[0020] In some embodiments, the heating time is 0.5h to 4h.

[0021] In some embodiments, the metal is selected from one or more alloys of aluminum, zinc, tin, tantalum, hafnium, zirconium, and titanium.

[0022] In some embodiments, the metal oxide includes at least one or more combinations of aluminum oxide, zinc oxide, tin oxide, tantalum oxide, hafnium oxide, zirconium oxide, and titanium oxide.

[0023] In some embodiments, the heating atmosphere is an oxygen-containing atmosphere, an inert atmosphere, or a vacuum atmosphere.

[0024] In some embodiments, forming a first material layer and a second material layer stacked on a substrate includes: sequentially forming the first material layer and the second material layer on the substrate, or sequentially forming the second material layer and the first material layer on the substrate.

[0025] In some embodiments, where the first material layer and the second material layer are sequentially formed on the substrate, the preparation method further includes removing the second material layer after induction is completed.

[0026] In another aspect, an oxide semiconductor layer is provided, which is obtained by contacting an oxide semiconductor with a metal induction layer and annealing at 200°C to 420°C to crystallize or partially crystallize the interface between the oxide semiconductor and the metal induction layer. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0028] Figure 1A This is a cross-sectional view of a thin-film transistor according to some embodiments;

[0029] Figure 1B A schematic diagram of a thin-film transistor transitioning from a depletion layer to an inversion layer according to some embodiments;

[0030] Figure 1CA schematic diagram of a thin-film transistor transitioning from a linear region to a saturation region according to some embodiments;

[0031] Figure 1D The output characteristic curves of the thin-film transistor at different gate voltages according to some embodiments are shown.

[0032] Figure 2A This is a cross-sectional view of a bottom-gate thin-film transistor according to some embodiments;

[0033] Figure 2B This is a cross-sectional view of another bottom-gate thin-film transistor according to some embodiments;

[0034] Figure 2C This is a cross-sectional view of a top-gate thin-film transistor according to some embodiments;

[0035] Figure 2D This is a cross-sectional view of another top-gate thin-film transistor according to some embodiments;

[0036] Figure 2E I for the transfer characteristic curves according to some embodiments ds 1 / 2 ~V gs A curve graph;

[0037] Figure 2F This is a cross-sectional view of another bottom-gate thin-film transistor according to some embodiments;

[0038] Figure 2G This is a cross-sectional view of another bottom-gate thin-film transistor according to some embodiments;

[0039] Figure 2H This is a cross-sectional view of another top-gate thin-film transistor according to some embodiments;

[0040] Figure 3A This is a flowchart of a method for fabricating a thin-film transistor according to some embodiments;

[0041] Figure 3B This is a cross-sectional view of another thin-film transistor according to some embodiments;

[0042] Figure 3C This is a cross-sectional view of another thin-film transistor according to some embodiments;

[0043] Figure 3D This is a cross-sectional view of another thin-film transistor according to some embodiments;

[0044] Figure 4A This is a flowchart of another method for fabricating a thin-film transistor according to some embodiments;

[0045] Figure 4B This is a cross-sectional view of another thin-film transistor according to some embodiments;

[0046] Figure 4C This is a cross-sectional view of another thin-film transistor according to some embodiments;

[0047] Figure 4D This is a cross-sectional view of another thin-film transistor according to some embodiments;

[0048] Figure 5A TEM images and electron diffraction patterns of Al / 244 thin films according to some embodiments;

[0049] Figure 5B Photoelectron spectra of 244 TFT and Al / 244-E TFT according to some embodiments;

[0050] Figure 5C Refractive index test diagrams of 244 TFT and Al / 244-E TFT according to some embodiments;

[0051] Figure 5D A comparison graph showing the transfer characteristic curves of a 244 TFT, an Al / 244 TFT, and an Al / 244-E TFT according to some embodiments;

[0052] Figure 5E This is a comparison graph showing the transfer characteristic curves of a 244 TFT under NBS conditions over time according to some embodiments;

[0053] Figure 5F This is a comparison chart of the transfer characteristic curves of Al / 244 TFT under NBS conditions as a function of time, according to some embodiments;

[0054] Figure 5G This is a comparison chart of the transfer characteristic curves of Al / 244-E TFT under NBS conditions as a function of time according to some embodiments;

[0055] Figure 6A TEM images and electron diffraction patterns of Zn / 244 thin films according to some embodiments;

[0056] Figure 6B A comparison graph showing the transfer characteristic curves of a 244 TFT and an Al / 244 TFT according to some embodiments;

[0057] Figure 6C This is a comparison graph showing the transfer characteristic curves of Zn / 244 TFT under NBS conditions as a function of time, according to some embodiments.

[0058] Figure 6D A comparison graph showing the transfer characteristic curves of 244 TFT, Hf / 244 TFT and Ta / 244 TFT according to some embodiments;

[0059] Figure 7 A comparison graph showing the transfer characteristic curves of a 244 TFT and a ZnO / 244 TFT according to some embodiments;

[0060] Figure 8 A comparison graph showing the transfer characteristic curves of a 244-N2 TFT and an Al / 244-N2 TFT according to some embodiments;

[0061] Figure 9A A comparison graph showing the transfer characteristic curves of a 424 TFT and an Al / 424 TFT according to some embodiments;

[0062] Figure 9B A comparison graph showing the transfer characteristic curves of Pr:424 TFT and Al / Pr:424 TFT according to some embodiments;

[0063] Figure 9C A comparison graph showing the transfer characteristic curves of Tb:424 TFT and Al / Tb:424 TFT according to some embodiments;

[0064] Figure 10 This is a comparison chart of the transfer characteristic curves of IGZO TFT and Al / IGZO TFT according to some embodiments. Detailed Implementation

[0065] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0066] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0067] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0068] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0069] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0070] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0071] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0072] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0073] Some embodiments of this disclosure provide a display device, including a display panel, and may also include other components, such as a circuit for providing electrical signals to the display panel to drive the display panel to display. This circuit may be called a control circuit and may include a circuit board and / or an integrated circuit (IC) electrically connected to the display panel.

[0074] Examples of display panels include LCD (Liquid Crystal Display), OLED (Organic Light-Emitting Diode), QLED (Quantum Dot Light-Emitting Diodes), MicroLED (Micro Light-Emitting Diodes), and miniLED (mini Light-Emitting Diodes) display panels.

[0075] The display device can specifically be a mobile phone, tablet computer, laptop, personal digital assistant (PDA), in-vehicle computer, laptop computer, digital camera, etc.

[0076] The display panel includes a substrate and driving circuits disposed on the substrate, such as pixel driving circuits and gate driving circuits. Examples of driving circuits may include thin-film transistors (TFTs). TFTs are important components constituting pixel driving circuits, gate driving circuits, etc. During power-on, by controlling the switching on and off of the TFTs, the pixel driving circuits and gate driving circuits can be controlled to drive the display panel to produce a display.

[0077] like Figure 1AAs shown, the thin-film transistor 1 includes a substrate 11, and a semiconductor layer 12, a gate 13, a gate insulating layer 14, a source 15, a drain 16, and an insulating protective layer 17 disposed on the substrate 11. The substrate 11 can be part of the aforementioned substrate material. Depending on the display panel, it can be a flexible display panel or a rigid display panel, and the substrate 11 can be either a flexible substrate or a rigid substrate. Examples of flexible substrates include plastic substrates, such as PI (Polyimide), or flexible substrates with a certain thickness made of glass or metal materials. Examples of rigid substrates include glass substrates or semiconductor substrates (such as silicon substrates, corundum substrates), etc. Of course, the substrate 11 can also be a substrate with other film layers formed thereon (such as metal layers, insulating layers, and / or buffer layers). The material of the gate 13 can be a metal material or a semiconductor material. The materials of the source 15 and drain 16 can be metal materials or metal oxide materials, and the material of the gate insulating layer 14 can be an insulating material, such as silicon oxide, silicon nitride, or a stacked material of silicon oxide and silicon nitride. The material of the insulating protective layer 17 can be an insulating material, such as silicon oxide, silicon nitride, etc.

[0078] In some embodiments, the semiconductor layer 12 is made of a metal oxide semiconductor material. For example, the semiconductor layer 12 may be made of a material containing elements such as In (indium), Ga (gallium), Zn (zinc), O (oxygen), and Sn (tin). Examples include indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), and indium tin zinc oxide (ITZO). These materials may also be doped with other elements to modify the semiconductor material, improving its mobility and / or bias stability. For example, these semiconductor materials may be doped with rare earth elements. That is, in the embodiments of this disclosure, the metal oxide semiconductor material may or may not be doped with rare earth elements.

[0079] Rare earth elements are a collective term for 17 special elements. They are named after the rare earth compounds that Swedish scientists used when extracting rare earth elements.

[0080] Rare earth elements include the lanthanides, as well as yttrium (Y) and scandium (Sc), which are closely related to the lanthanides. The lanthanides are: lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu), a total of 15 elements.

[0081] In some embodiments, the material of the semiconductor layer 12 is selected from either indium zinc tin oxide (ITZO) or indium gallium zinc oxide (IGZO); and the indium zinc tin oxide (ITZO) or indium gallium zinc oxide (IGZO) may or may not be doped with rare earth elements.

[0082] In some embodiments, when indium zinc tin oxide (ITZO) and indium gallium zinc oxide (IGZO) are doped with rare earth elements, the rare earth elements are Pr or Tb.

[0083] There is no specific limitation on the ratio of the number of atoms of each atom in the above-mentioned indium zinc tin oxide (ITZO) and indium gallium zinc oxide (IGZO).

[0084] In some embodiments, when the material of the semiconductor layer 12 is selected from indium zinc tin oxide (ITZO), the ratio of the number of In atoms, Sn atoms, and Zn atoms in ITZO is 4:2:4; or, the ratio of the number of In atoms, Sn atoms, and Zn atoms in ITZO is 2:4:4. When the material of the semiconductor layer 12 is selected from indium gallium zinc oxide (IGZO), the ratio of the number of In atoms, Ga atoms, and Zn atoms in IGZO is 1:1:1.

[0085] In some embodiments, the doping concentration of rare earth elements is 2 at%. That is, in Pr-doped indium zinc tin oxide (ITZO), the doping concentration of Pr is 2 at%, in Tb-doped indium zinc tin oxide (ITZO), the doping concentration of Tb is 2 at%, in Pr-doped indium gallium zinc oxide (IGZO), the doping concentration of Pr is 2 at%, and in Tb-doped indium gallium zinc oxide (IGZO), the doping concentration of Tb is 2 at%.

[0086] In other embodiments, the semiconductor layer 12 can be a single-layer structure or a double-layer structure. In the case of a double-layer semiconductor layer, the materials of each layer in the double-layer structure are different.

[0087] Taking n-type thin-film transistor 1 as an example, the working principle of thin-film transistor 1 is as follows:

[0088] like Figure 1BAs shown, when a positive voltage is applied to gate 13, the gate voltage generates an electric field in the gate insulating layer 14. Electric field lines extend from gate 13 towards the semiconductor surface, inducing charges at the surface. As the gate voltage increases, the semiconductor surface transforms from a depletion layer into an electron accumulation layer, forming an inversion layer. When strong inversion is achieved (requiring a gate 13 voltage V0), the inversion layer is further enhanced. gs The threshold voltage V of a thin-film transistor th When the turn-on voltage is reached, applying a voltage between the source 15 and drain 16 will allow charge carriers to flow through the channel. For example... Figure 1C and Figure 1D As shown, when the source-drain voltage V ds When the voltage is very low, the conductive channel is approximately a constant resistance, and the leakage current varies with the source-drain voltage V. ds The voltage increases linearly with increasing source-drain voltage, corresponding to the linear region of thin-film transistor 1. ds When the voltage is large, it affects the gate voltage, causing the electric field in the gate insulating layer 14 to gradually weaken from the source to the drain, and the electron density in the inversion layer on the semiconductor surface to gradually decrease from the source to the drain. The channel resistance increases with the source-drain voltage V. ds As it increases, the leakage current I increases. ds The increase becomes slower, corresponding to the transition from the linear region to the saturation region. When the source-drain voltage V ds When the voltage increases to a certain level, the thickness of the inversion layer at the drain end decreases to zero, and with the increase of the source-drain voltage V... ds If you continue to add more, the device will enter the saturation region.

[0089] Therefore, the operating region of the conducting thin-film transistor 1 is divided into the non-saturation region, the critical saturation point, and the saturation region. When V gs >V th V ds <V gs -V th When V is in the unsaturated region, the thin-film transistor 1 operates in the unsaturated region, and the corresponding unsaturated region current is shown in equation (1). ds >V gs -V th V gs >V th When the thin-film transistor 1 operates in the saturation region, the corresponding saturation current is shown in equation (2). Where μ is the electron mobility (also called carrier mobility), and C... ox W / L represents the capacitance per unit area of ​​a thin-film transistor (TFT) metal-insulator-semiconductor (MIS) structure, indicating the ratio of the TFT channel width to the channel length. Of course, when an inversion channel is not formed, the TFT is in the cutoff region.

[0090] (1)

[0091] (2)

[0092] In a liquid crystal display panel, thin-film transistor 1 operates in the non-saturation region for most of the time. As shown in equation (1), to increase the on-state current of thin-film transistor 1, μ and C can be increased. ox W / L, V gs and V ds The value of V, or a decrease in V th The value of .

[0093] For amorphous metal oxide semiconductor materials, the first material layer 10 contains a large number of micropores and defects, and the degree of atomic arrangement order is low. These factors greatly affect the electron mobility of the thin film transistor 1 that uses it as a channel, which is not conducive to improving the performance of the thin film transistor 1.

[0094] In some embodiments, such as Figure 2A , Figure 2B , Figure 2C and Figure 2D As shown, the semiconductor layer 12 includes a first surface 12a near the substrate 11 and a second surface 12b away from the substrate 11. The semiconductor layer 12 has a channel region 121, and a source region 122 and a drain region 123 disposed on opposite sides of the channel region 121. A metal-oxide-semiconductor crystal 30 is formed in the semiconductor layer 12 at least in the channel region 121 and near the first surface 12a or the second surface 12b. The source 15 of the thin-film transistor 1 is in contact with the source region 122, and the drain 16 of the thin-film transistor 1 is in contact with the drain region 123.

[0095] Taking thin-film transistor 1 as an example, such as Figure 2A and Figure 2B As shown, the first surface 12a is the surface of the semiconductor layer 12 near the gate insulating layer 14, and the second surface 12b is the surface of the semiconductor layer 12 near the insulating protective layer 17. Taking the thin-film transistor 1 as a top-gate type thin-film transistor as an example, as... Figure 2C and Figure 2D As shown, the first surface 12a is the surface of the semiconductor layer 12 near the buffer layer 18 on the substrate 11, and the second surface 12b is the surface of the semiconductor layer 12 near the gate insulating layer 14.

[0096] In these embodiments, by forming a metal-oxide-semiconductor crystal 30 at least in the channel region 121 of the semiconductor layer 12, and near the first surface 12a or the second surface 12b, the atomic order of the metal-oxide-semiconductor in the semiconductor layer 12 can be improved compared to using an amorphous oxide as the metal-oxide-semiconductor material. With increased atomic order, the overlap of electron clouds between atoms can be enhanced, reducing electron scattering during transport and improving electron mobility. Furthermore, increased atomic order can reduce various structural defects, which also contributes to improving the field-effect mobility and stability of the thin-film transistor 1.

[0097] Simultaneously, by testing the transfer characteristic curve of thin-film transistor 1, and based on the formula for the saturation region of the transfer characteristic, the transfer characteristic curve was subjected to I-testing. ds 1 / 2 ~V gs Curves, such as Figure 2E As shown in the formula (3), by fitting the straight line segment, the electron mobility μ and threshold voltage V can be extracted from the slope of the extrapolated curve. th The formula for calculating μ is shown in equation (4), which combines equation (3) and Figure 2E As shown, in I ds When =0, there exists V th =V gs At this time, V th The value is the x-coordinate corresponding to point A. Calculations show that, before the formation of the metal-oxide-semiconductor crystal 30, the electron mobility of the thin-film transistor 1 is 5 cm⁻¹. 2 / Vs~30 cm 2 Compared to / Vs, after the formation of the metal oxide semiconductor crystal 30 in the first material layer 10, the electron mobility of the thin film transistor 1 increases to 40 cm⁻¹. 2 Above / Vs, the threshold voltage remains near 0V. This further confirms that after forming the metal oxide semiconductor crystal 30, micropores and defects in the first material layer 10 can be reduced, thereby increasing the electron mobility μ and reducing the threshold voltage Vth of the thin film transistor 1.

[0098] (3)

[0099]

[0100] (4)

[0101] In some embodiments, such as Figure 2A , Figure 2B , Figure 2C and Figure 2DAs shown, the thickness d1 of crystal 30 in semiconductor layer 12 is greater than or equal to 1 / 4 of the thickness of semiconductor layer 12 and less than or equal to the thickness d of semiconductor layer 12.

[0102] Experiments have shown that by controlling the thickness d1 of the crystal 30 in the semiconductor layer 12 within the above-mentioned range, the carrier mobility of the thin-film transistor 1 can be increased by more than 200%.

[0103] In some embodiments, such as Figure 2A , Figure 2B , Figure 2C and Figure 2D As shown, the dimension L1 of the distribution range of crystal 30 along the length L of the channel is greater than or equal to 1 / 2 of the length L of the channel. Here, since crystal 30 is preferentially formed on the first surface 12a or the second surface 12b of semiconductor layer 12, the dimension L1 of the distribution range of crystal 30 along the length of the channel may be the largest near the first surface 12a or the second surface 12b of semiconductor layer 12. As it moves further away from the first surface 12a or the second surface 12b of semiconductor layer 12, the dimension L1 of the distribution range of crystal 30 along the length of the channel gradually decreases. Therefore, the dimension L1 of the distribution range of crystal 30 along the length of the channel is defined as the aforementioned maximum dimension, that is, the dimension of the distribution range of crystal 30 closest to the first surface 12a or the second surface 12b of semiconductor layer 12 along the length of the channel.

[0104] In these embodiments, by controlling the distribution range of the crystal 30 within the aforementioned range, the mobility of charge carriers throughout the channel region 121 can be improved, thereby significantly increasing the electron mobility of the thin-film transistor 1.

[0105] In some embodiments, such as Figure 2F , Figure 2G As shown, the thin-film transistor 1 further includes a metal oxide layer 19, which covers at least the middle part of the channel region 121 along the length L of the channel, and the dimension of the metal oxide layer 19 along the length L of the channel is greater than or equal to 1 / 2 of the length L of the channel. The metal oxide layer 19 is in contact with the semiconductor layer 12.

[0106] In these embodiments, the metal oxide layer 19 can be a material layer obtained after inducing the semiconductor layer 12 to form crystal 30. For example, before induction, the material of the metal oxide layer 19 can be a metal material. After induction, during the induction process, the metal material is turned into a metal oxide by introducing oxygen-containing gas to avoid introducing an additional conductive layer in the thin film transistor 1. Alternatively, the metal oxide layer 19 can be directly used as an induction layer to induce the semiconductor layer 22.

[0107] In some embodiments, the metal oxide layer 19 is disposed between the gate insulating layer 14 and the semiconductor layer 12. For example... Figure 2F As shown, when the thin-film transistor 1 is a bottom-gate thin-film transistor, the metal oxide layer 19 is disposed on one side of the first surface 12a, as... Figure 2H As shown, when the thin film transistor 1 is a top-gate thin film transistor, the metal oxide layer 19 is disposed on one side of the second surface 12b.

[0108] That is, the metal oxide layer 19 is disposed on the side of the semiconductor layer 12 near the gate insulating layer 14.

[0109] Of course, in other embodiments, the metal oxide layer 19 may also be disposed on the side of the semiconductor layer 12 away from the gate insulating layer 14. In this case, the metal oxide layer 19 may be disposed between the buffer layer 18 and the semiconductor layer 12 (top-gate thin-film transistor), or the thin-film transistor 1 may further include an interlayer insulating layer, with the metal oxide layer 19 disposed between the semiconductor layer 12 and the interlayer insulating layer.

[0110] In some embodiments, in the semiconductor layer 12, the distribution density of the crystal 30 gradually increases along the direction that gradually approaches the metal oxide layer 19.

[0111] Taking the metal oxide layer 19 disposed between the semiconductor layer 12 and the gate insulating layer 14 as an example, the crystal distribution is denser and more numerous along the direction that gradually approaches the metal oxide layer 19.

[0112] In some embodiments, crystal 30 is a ZnSO3 crystal. Electron diffraction pattern analysis shows that the electron diffraction pattern of the crystal conforms to that of ZnSO3 crystal. Transmission electron microscopy reveals that the crystal has a spherical morphology.

[0113] In some embodiments, the oxygen vacancy concentration in the semiconductor layer 12 is less than or equal to 10%. The oxygen vacancy concentration refers to the proportion of the number of oxygen vacancies to the total theoretical number of oxygen atoms in the entire semiconductor layer 12. For example, taking ITZO as the material of the semiconductor layer 12, and the ratio of the number of In atoms, Sn atoms, Zn atoms, and O atoms in ITZO as 4:2:4:14, the total theoretical number of oxygen atoms in the semiconductor layer 12 is the number of oxygen atoms in ITZO calculated based on the above ratio and the mass of sputtered ITZO.

[0114] In these embodiments, after crystal 30 is formed, the oxygen vacancy concentration is significantly reduced compared to the amorphous oxide in the metal oxide semiconductor material of semiconductor layer 12. This is because: with the formation of crystal 30 in semiconductor layer 12, structural defects in amorphous oxide can be effectively removed, thereby reducing the oxygen vacancy concentration. As the oxygen vacancy concentration decreases, the bias stability of thin film transistor 1 can be improved, thereby reducing the threshold voltage drift of thin film transistor 1 under NBS (negative gate bias stress).

[0115] In some embodiments, the threshold voltage drift of the thin-film transistor 1 under negative gate stress is less than or equal to 1V. The test conditions for negative gate stress are: gate bias voltage of -20V and time of 3600s.

[0116] It should be noted that, for n-type thin-film transistors, the threshold voltage will drift negatively under negative gate stress. Therefore, the threshold voltage drift of thin-film transistor 1 under negative gate stress is usually written as a negative number, representing the direction of drift. For example, if the threshold voltage drift of thin-film transistor 1 under negative gate stress is less than or equal to 1V, in the following embodiment, it is written as: the threshold voltage drift of thin-film transistor 1 under negative gate stress is ΔV. th Less than or equal to -1V refers to the threshold voltage drift ΔV of thin-film transistor 1 under negative gate compressive stress. th It can be any value between -1V and 0V.

[0117] In some embodiments, the subthreshold swing amplitude of the thin-film transistor 1 is less than or equal to 0.3 V / decade. The subthreshold swing amplitude can be obtained from the transfer characteristic curve. Tests have shown that when the crystal 30 is formed in the semiconductor layer 12, the subthreshold swing amplitude of the thin-film transistor 1 is significantly reduced.

[0118] In some embodiments, the I of the thin-film transistor 1 on / I off Greater than or equal to 1.0 × 10 7 A. Tests revealed that when crystal 30 is formed in semiconductor layer 12, the switching current of thin-film transistor 1 is higher than that of I. on / I off A larger value can improve the performance of thin-film transistor 1.

[0119] Some embodiments of this disclosure provide a method for fabricating a thin-film transistor. The thin-film transistor 1 includes a semiconductor layer 12, and the semiconductor layer 12 has a channel region 121, such as... Figure 3A As shown, the preparation method includes:

[0120] Step 1) Form gate 13 on substrate 11.

[0121] Taking substrate 11 as an example of a semiconductor substrate, substrate 11 can be a silicon substrate. In this case, the silicon can be heavily p-type doped, and the heavily p-type doped silicon can be used as both substrate 11 and gate 13. Gate 13 can be a single, continuous layer or it can have a specific pattern. Figure 3A The diagram shows the case where the gate 13 covers the entire surface, i.e., the gate 13 is formed after p-type heavy doping of the entire surface of the silicon substrate. The total thickness of the substrate 11 and the gate 13 can be 500 μm.

[0122] It should be noted that only the case of using p-type heavily doped silicon as substrate 11 and gate 13 is shown here. Those skilled in the art will understand that the material of gate 13 can also be a metallic material, such as a single layer or multilayer composite stack formed by one or more of the following materials: molybdenum (Mo), niobium (Nb), aluminum (Al), neodymium (Nd), titanium (Ti) and copper (Cu).

[0123] Step 2) Form a gate insulating layer 14 on the substrate 11 on which the gate 13 is formed.

[0124] The gate insulating layer 14 can be a thin film of silicon dioxide grown on a silicon substrate, such as... Figure 3A As shown, a silicon dioxide film can also be used for full-layer coverage, and the thickness of the silicon dioxide film can be 50nm~300nm.

[0125] Of course, the material of the gate insulating layer 14 can be silicon dioxide or other insulating materials, such as silicon nitride, or a stack of silicon nitride and silicon dioxide.

[0126] Step 3) Form source 15 and drain 16 on substrate 11 where gate insulating layer 14 is formed.

[0127] The source electrode 15 and the drain electrode 16 can be made of metallic materials, such as one or more of molybdenum (Mo), niobium (Nb), aluminum (Al), neodymium (Nd), titanium (Ti), copper (Cu), and gold, forming a single layer or multiple layers of composite material. Alternatively, the source electrode 15 and the drain electrode 16 can be made of metal oxide conductive materials, such as ITO (Indium Tin Oxides). No specific limitations are imposed here.

[0128] Here, taking ITO as the material for source 15 and drain 16, ITO thin films can be deposited by magnetron sputtering with a thickness of 50nm~300nm. After deposition, source 15 and drain 16 are formed by patterning process.

[0129] Among them, the radio frequency power of magnetron sputtering can be 30W~120W, the argon flow rate can be 20~50sccm (Standard Cubic Centimeter per Minute), the oxygen flow rate can be 1sccm~5sccm, and the working pressure can be 0.10 Pa~0.50 Pa.

[0130] Step 4) A first material layer 10 and a second material layer 20 are formed on the substrate 11 on which the active electrode 15 and the drain electrode 16 are formed. The first material layer 10 covers the entire surface, or the first material layer 10 has the same pattern as the semiconductor layer 12. The orthogonal projection of the second material layer 20 onto the substrate 11 at least covers the corresponding channel region 121 of the first material layer 10 along the length L of the channel (e.g., ...). Figure 3A The second material layer 20 is located in the middle of the direction indicated by the arrow a), and the dimension L2 of the orthogonal projection of the second material layer 20 onto the substrate 11 along the length L of the channel is greater than or equal to 1 / 2 of the length L of the channel. The material of the first material layer 10 is a metal oxide semiconductor material, and the material of the second material layer 20 is a metal or a metal oxide.

[0131] For example, metal oxide semiconductor materials can be materials containing elements such as In (indium), Ga (gallium), Zn (zinc), O (oxygen), and Sn (tin). Examples include indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), and indium tin zinc oxide (ITZO). These semiconductor materials can also be doped with other elements, such as rare earth elements.

[0132] When the material of the second material layer 20 is metal, from the perspective of reaction kinetics, the metal can provide additional electrons, causing the dangling bonds, HO bonds and weak M (metal)-O bonds near the interface of the first material layer 10 close to the second material layer 20 to break preferentially. From the perspective of Gibbs free energy, the metal is more inclined to capture weak oxygen bonds. These will all play an inductive role, causing the atoms of the material in the first material layer 10 to rearrange under the drive of lower thermal energy.

[0133] When the material of the second material layer 20 is a metal oxide, oxygen vacancies in the metal oxide will also migrate to the adjacent first material layer 10, and weakly bonded oxygen in the first material layer 10 will also migrate to the metal oxide, which can also play an inductive role.

[0134] In some embodiments, the metal is selected from one or more alloys of aluminum, zinc, tin, tantalum, hafnium, zirconium, and titanium.

[0135] Among them, aluminum has a face-centered cubic lattice structure, zinc has a hexagonal lattice structure, tin has a tetragonal lattice structure, tantalum has a body-centered cubic lattice structure, hafnium has a hexagonal lattice-derived structure below 1300℃, zirconium has a hexagonal lattice structure, and titanium has a hexagonal lattice structure.

[0136] In these embodiments, when the metal is selected from one or more of aluminum, tin, and tantalum, these metals are relatively difficult to crystallize compared to other metals, and the annealing (induction) temperature is relatively high. However, after some crystals 30 are formed in the first material layer 10, the device mobility and bias stability can be significantly improved. When the metal is selected from one or more of zinc, hafnium, zirconium, and titanium, these metals have good diffusion in the first material layer 10, high solid solubility, and can crystallize at a lower temperature. The field-effect mobility of the thin-film transistor 1 is significantly improved, but the bias stability is slightly worse.

[0137] In some embodiments, the metal oxide includes at least one or more combinations of aluminum oxide, zinc oxide, tin oxide, tantalum oxide, hafnium oxide, zirconium oxide, and titanium oxide.

[0138] These metal oxides can all play an inductive role similar to the corresponding metals (such as aluminum for aluminum oxide and zinc for zinc oxide), thereby forming a metal oxide semiconductor crystal 30 in the first material layer 10, which can also improve the field-effect mobility and bias stability of the thin film transistor 1.

[0139] In the case where the first material layer 10 covers the entire substrate 11, the orthogonal projection of the first material layer 10 onto the substrate 11 completely overlaps with the substrate 11. In this case, the first material layer 10 can be a metal oxide semiconductor thin film. In the case where the first material layer 10 has the same pattern as the semiconductor layer 12, the orthogonal projection of the first material layer 10 onto the substrate 11 partially overlaps with the substrate 11. In this case, a metal oxide semiconductor thin film can be formed first on the substrate 11 where the gate insulating layer 14 is formed (e.g., a metal oxide semiconductor thin film can be formed by magnetron sputtering), and then the first material layer 10 can be formed by a patterning process (i.e., a patterning process, which may include steps such as coating photoresist, exposure, development, and etching).

[0140] In these embodiments, since the orthogonal projection of the second material layer 20 on the substrate 11 at least covers the middle part of the channel region 121 corresponding to the first material layer 10 along the length L of the channel, and the size L2 of the orthogonal projection of the second material layer 20 on the substrate 11 along the length L of the channel is greater than or equal to 1 / 2 of the length L of the channel, during induction, the metal oxide semiconductor crystal 30 can be preferentially formed in the middle part of the channel region 121 corresponding to the first material layer 10 along the length L of the channel, and the size L1 of the distribution range of the crystal 30 along the length L of the channel can be guaranteed to be greater than or equal to 1 / 2 of the length L of the channel. This can improve the atomic ordering degree of the metal oxide semiconductor material in the length L of the channel, thereby improving the conductivity of the metal oxide semiconductor material in the length L of the channel and improving the electron mobility of the thin film transistor 1.

[0141] The specific positional relationship between the first material layer 10 and the second material layer 20 is not limited, and the second material layer 20 can be disposed above or below the first material layer 10.

[0142] Based on this, forming a first material layer 10 and a second material layer 20 stacked on the substrate 11 may include: such as Figure 3A As shown in step 4), a first material layer 10 and a second material layer 20 are sequentially formed on the substrate 11 to obtain... Figure 3A The structure shown in (I) can be obtained by sequentially forming a second material layer 20 and a first material layer 10 on the substrate 11, as shown in Figure (I). Figure 3A The structure shown in (II) is as follows.

[0143] In the case where a first material layer 10 and a second material layer 20 are sequentially formed on a substrate 11, the second material layer 20 is located above the first material layer 10. In the case where the second material layer 20 and the first material layer 10 are sequentially formed on a substrate 11, the second material layer 20 is located below the first material layer 10.

[0144] Step 5) Heating the first material layer 10 and the second material layer 20 induces the first material layer 10 to form a metal oxide semiconductor crystal 30 at least on the surface near the second material layer 20 at a preset temperature. The preset temperature is greater than or equal to 200°C and less than or equal to 420°C.

[0145] The heating atmosphere is not specifically limited, as long as the heating conditions enable the second material layer 20 to capture weakly bonded oxygen in the metal oxide semiconductor material, causing the atoms in the metal oxide semiconductor material to rearrange.

[0146] In some embodiments, the heating atmosphere is an oxygen-containing atmosphere, an inert atmosphere, or a vacuum atmosphere.

[0147] Examples of oxygen-containing atmospheres include air, while examples of inert atmospheres include nitrogen, helium, or neon.

[0148] In some embodiments, when the material of the second material layer 20 is metal, the second material layer 20 is formed on top of the first material layer, and after induction is completed, it further includes: Figure 3A As shown in step 6), the second material layer 20 is removed to obtain the following: Figure 3A The structure shown in (III) is as follows.

[0149] In other embodiments, when the material of the second material layer 20 is a metal oxide, the second material layer 20 may be formed above or below the first material layer 10.

[0150] It should be noted that when the second material layer 20 is formed below the first material layer 10, the dimension L2 of the orthogonal projection of the second material layer 20 onto the substrate 11 along the length L of the channel can be equal to the length L of the channel. That is, the second material layer 20 fills the space between the source 15 and the drain 16. In this case, the second material layer 20 can serve as the gate insulating layer 14 or a part of the gate insulating layer 14. Alternatively, the second material layer 20 may have the same pattern as the gate insulating layer 14 and be located between the gate insulating layer 14 and the semiconductor layer 12. In this case, the second material layer 20 is also the metal oxide layer described above. When the second material layer 20 is formed above the first material layer 10, it may or may not be removed after induction. If the second material layer 20 is not removed, it can serve as the insulating protective layer 17 or a part of the insulating protective layer 17. In this case, the second material layer 20 can also be the metal oxide layer described above.

[0151] In some embodiments, where the first material layer 10 covers the entire material layer, the preparation method further includes: patterning the first material layer 10 after induction to form a semiconductor layer 12.

[0152] Here, there are two possible implementation methods. In the first implementation method, such as... Figure 3AAs shown in step 4) (I), the second material layer 20 is formed above the first material layer 10. In this case, the second material layer 20 can cover the entire layer, or it can have a specific pattern. When the second material layer 20 covers the entire layer, after induction, the semiconductor layer 12 and the induced pattern can be formed in the same patterning process. The induced pattern can have the same pattern as the semiconductor layer 12. In this case, the material of the second material layer 20 can be an insulating material (such as a metal oxide) or a conductive material. If the material of the second material layer 20 is an insulating material, it can be removed or not. If the second material layer 20 is not removed, it can serve as an insulating protective layer 17 or as part of an insulating protective layer 17. Alternatively, the second material layer 20 can have the same pattern as the channel region 121 and be located between the insulating protective layer 17 and the first material layer 10. In this case, the second material layer 20 is also the metal oxide layer described above. If the material of the second material layer 20 is a conductive material, it can be removed. Of course, if the material of the second material layer 20 is a conductive material, it can be removed after induction, and then the semiconductor layer 12 can be formed by patterning. If the second material layer 20 has a certain pattern, there are two possible cases: First, the orthographic projection of the second material layer 20 onto the substrate 11 along the length L of the channel (size L2) is greater than the dimension L1 of the semiconductor layer 12 along the length L of the channel. In this case, patterning the first material layer 10 can be performed as described above, covering the entire second material layer 20. Second, the orthographic projection of the second material layer 20 onto the substrate 11 is less than or equal to the dimension L2 of the semiconductor layer 12 along the length L of the channel. After induction, the semiconductor layer 12 can be formed directly by patterning. Similarly, if the material of the second material layer 20 is an insulating material (such as a metal oxide), it can be removed or not after induction, as described above. If the material of the second material layer 20 is a conductive material, the second material layer 20 can be removed.

[0153] In the second implementation method, such as Figure 3AIn step 4), as shown in (II), the second material layer 20 is formed below the first material layer 10. At this time, the second material layer 20 has a specific pattern. For example, if the orthogonal projection of the second material layer 20 onto the substrate 11 covers the middle of the channel region 121 along the length L of the channel, and the dimension L2 of the orthogonal projection of the second material layer 20 onto the substrate 11 along the length L of the channel is greater than or equal to 1 / 2 of the channel length L and less than or equal to the channel length L, then after induction, the semiconductor layer 12 can be directly formed by patterning. The material of the second material layer 20 can be an insulating material, or a material that can be formed into an insulating material through an induction process. In this case, the second material layer 20 can serve as a gate insulating layer 14 or a part of a gate insulating layer 14, or, as... Figure 3A As shown in (II), the second material layer 20 has the same pattern as the channel region 121 and is located between the gate insulating layer 14 and the first material layer 10. In this case, the second material layer 20 can also be the metal oxide layer described above.

[0154] The above describes the case where the source 15 and drain 16 are disposed on the side of the semiconductor layer 12 close to the substrate 11. When the source 15 and drain 16 are disposed on the side of the semiconductor layer 12 away from the substrate 11, steps 4) and 5) occur before step 3). In this case, the second material layer 20 can also be formed below or above the first material layer 10. When the second material layer 20 is formed below the first material layer 10, the second material layer 20 can cover the entire layer or have a specific pattern. In this case, the second material layer 20 can directly serve as the gate insulating layer 14 or a part of the gate insulating layer 14, or, as... Figure 3B As shown, the second material layer 20 has the same pattern as the semiconductor layer 12 and is located between the gate insulating layer 14 and the first material layer 10. When the second material layer 20 is formed above the first material layer 10, the second material layer 20 may or may not be removed. If the second material layer 20 is removed, the following is obtained: Figure 3C In the structure shown, if the second material layer 20 is not removed, it can directly serve as an interlayer insulating layer or insulating protective layer 17. If the second material layer 20 covers the entire layer, vias can be provided on the second material layer 20 (as an interlayer insulating layer) at positions corresponding to the source region 122 and the drain region 123 to achieve contact between the source electrode 15 and the source region 122, and between the drain electrode 16 and the drain region 123. If the second material layer 20 has a specific pattern, it can cover only the channel region 121, or, as... Figure 3DAs shown, the second material layer 20 has the same pattern as the semiconductor layer 12. When the second material layer 20 only covers the channel region, the source 15 and drain 16 can be directly formed in the source and drain regions of the semiconductor layer 12. When the second material layer 20 has the same pattern as the semiconductor layer 12, as... Figure 3D As shown, the source 15 and drain 16 can contact the side of the semiconductor layer 12 to achieve electrical connection.

[0155] Of course, in some embodiments, the preparation method may also include the step of making an insulating protective layer 17.

[0156] The embodiments of this disclosure provide a method for fabricating a thin-film transistor. By setting a second material layer 20, the atoms in the metal oxide semiconductor material can be rearranged under lower thermal energy driven by the induction effect of the second material layer 20, thereby improving the electron mobility and bias stability of the thin-film transistor 1 and reducing the threshold voltage of the thin-film transistor 1, thereby improving the overall performance of the thin-film transistor.

[0157] In addition, in the embodiments of this disclosure, by setting the heating temperature to 200°C~420°C, the heat treatment temperature of the first material layer 10 and the second material layer 20 can be reduced to the greatest extent. This can improve the overall performance of the thin film transistor 1 while reducing the process temperature during the fabrication of the thin film transistor 1. This method can be applied to the fabrication of flexible display panels, thereby meeting application requirements.

[0158] In some embodiments, to further meet application requirements, the preset temperature is less than or equal to 400°C. The heating temperature can be further reduced.

[0159] In some embodiments, the heating time is 0.5 h to 4 h. Experiments have shown that by controlling the heating time within the above range, a crystal 30 of a certain thickness can be obtained, thereby achieving the purpose of improving electron mobility and bias stability.

[0160] In some other embodiments, in order to save manufacturing costs, the heating atmosphere can be an air atmosphere or a vacuum atmosphere.

[0161] The fabrication method of bottom-gate thin-film transistors has been introduced above. The fabrication method of top-gate thin-film transistors will be described below. Figure 4A As shown, it includes:

[0162] Step 1) Form source 15 and drain 16 on substrate 11.

[0163] The fabrication methods for source 15 and drain 16 can refer to the fabrication methods for source 15 and drain 16 in bottom-gate thin-film transistors. The substrate 11 can be a substrate with a buffer layer formed thereon.

[0164] Step 2) Form a first material layer 10 and a second material layer 20 stacked on the substrate 11 on which the active electrode 15 and the drain electrode 16 are formed.

[0165] The fabrication method of the first material layer 10 and the second material layer 20 can refer to step 4 in the fabrication method of the bottom gate thin film transistor.

[0166] Step 3) Heating the first material layer 10 and the second material layer 20 induces the first material layer 10 to form a metal oxide semiconductor crystal 30 at least on the surface near the second material layer 20 at a preset temperature. The preset temperature is greater than or equal to 200°C and less than or equal to 420°C.

[0167] This step can be referred to step 5 in the fabrication method of bottom-gate thin-film transistors.

[0168] The difference is that, when the second material layer 20 is formed above the first material layer 10 and is not removed, the second material layer 20 serves as the gate insulating layer 14 or is part of the gate insulating layer 14, or the second material layer 20 has the same pattern as the channel region 121 and is located between the gate insulating layer 14 and the first material layer 10.

[0169] Step 4) Form a gate insulating layer 14 on the substrate 11 on which the semiconductor layer 12 is formed.

[0170] Here, only the case where the second material layer 20 is removed in the structure shown in step 3) (IV) is shown. If the second material layer 20 is formed on top of the first material layer 10 in step 3) and the second material layer 20 is not removed, this step can be omitted.

[0171] Step 5) Form a gate 13 on the substrate 11 on which the gate insulating layer 14 is formed.

[0172] For example, the pattern of gate 13 can be the same as the pattern of channel region 121.

[0173] The above describes the case where the source 15 and drain 16 are disposed on the side of the semiconductor layer 12 close to the substrate 11. When the source 15 and drain 16 are disposed on the side of the semiconductor layer 12 away from the substrate 11, steps 2) and 3) occur before step 1). In this case, taking the example where the source 15 and drain 16 are formed on the side of the gate 13 away from the substrate 11, the second material layer 20 can also be formed above or below the first material layer 10. Furthermore, if the second material layer 20 is formed above the first material layer 10 and is not removed, such as... Figure 4BAs shown, the second material layer 20 can cover the entire area. In this case, the second material layer 20 can serve as the gate insulating layer 14, and vias can be provided at the positions corresponding to the source region 122 and the drain region 123 to achieve contact between the source electrode 15 and the source region 122, and contact between the drain electrode 16 and the drain region 123. Alternatively, as shown... Figure 4C As shown, the second material layer 20 has the same pattern as the channel region. In this case, vias can be formed only in the interlayer insulating layer to achieve contact between the source 15 and the source region 122, and between the drain 16 and the drain region 123. In other embodiments, such as... Figure 4D As shown, the second material layer 20 is formed below the first material layer 10. In this case, the second material layer 20 can have the same pattern as the semiconductor layer 12. Similarly, vias can be formed in the interlayer insulating layer to achieve contact between the source 15 and the source region 122, and contact between the drain 16 and the drain region 123.

[0174] Some embodiments of this disclosure provide an oxide semiconductor layer, which is obtained by contacting an oxide semiconductor with a metal induction layer and annealing at 200°C to 420°C to crystallize or partially crystallize the interface between the oxide semiconductor and the metal induction layer.

[0175] The metal-inducing layer is the first material layer mentioned above, and the oxide semiconductor is the second material layer mentioned above. Annealing at 200℃~420℃ to crystallize or partially crystallize the interface between the oxide semiconductor and the metal-inducing layer means that heating at 200℃~420℃ causes the oxide semiconductor to form metal oxide semiconductor crystals at least at the interface between it and the metal-inducing layer.

[0176] In the oxide semiconductor layer provided in this disclosure, by using a metal-induced layer to contact the oxide semiconductor, crystallization can be induced at the interface between the oxide semiconductor and the metal-induced layer at a relatively low temperature, thereby obtaining a crystalline interface. Compared with the amorphous oxide in the oxide semiconductor layer in related technologies, the structural defects of the crystalline interface can be reduced, the density with the oxide semiconductor layer can be increased, and the intrinsic defects can be reduced, thereby significantly improving the carrier mobility and bias stability of the crystalline interface.

[0177] Some embodiments of this disclosure provide a semiconductor device comprising an oxide semiconductor layer as described above.

[0178] The semiconductor devices provided in the embodiments of this disclosure have the same technical effects as the oxide semiconductor layers described above, and will not be repeated here.

[0179] In some embodiments, the semiconductor device may include integrated circuits, photodetectors, semiconductor light-emitting diodes, semiconductor lasers, and photovoltaic cells.

[0180] Based on the above specific embodiments, in order to objectively evaluate the technical effects of the technical solutions provided in this disclosure, the technical solutions provided in this disclosure will be described in detail and by way of comparative examples and experimental examples below.

[0181] Comparative Example 1

[0182] The fabrication method of the thin-film transistor in Comparative Example 1 is as follows:

[0183] (1) Select 300μm p-type heavily doped silicon as the bottom gate (i.e. gate 13) and substrate 11, and grow a 100nm thick SiO2 layer on it as the gate insulating layer 14.

[0184] (2) ITO thin film is deposited on the gate insulating layer 14 by magnetron sputtering as source 15 and drain 16 with a thickness of 50nm; magnetron sputtering deposition parameters: DC power is 60W, argon flow rate is 30sccm, oxygen flow rate is 1sccm, and working pressure is 0.18Pa.

[0185] (3) On ITO, an ITZO (In:Sn:Zn=2:4:4, that is, the ratio of the number of atoms of In, Sn and Zn is 2:4:4) thin film was deposited as semiconductor layer 12 with a thickness of 30nm. The magnetron sputtering deposition parameters were: RF power of 100W, argon flow rate of 10sccm, oxygen flow rate of 10sccm, and working pressure of 0.2Pa. The width and length of the channel were 800μm and 400μm, respectively, to obtain an Al-inducible 244TFT control sample.

[0186] (4) Annealing at 400°C for 1 hour in air atmosphere (i.e., heat treatment for 1 hour) to obtain 244 thin film transistors (i.e., 244 TFTs).

[0187] Experimental Example 1

[0188] The steps (1), (2) and (3) of the thin-film transistor fabrication method in Experimental Example 1 are basically the same as those in Comparative Example 1, and will not be repeated here.

[0189] The difference is that, before step (4), Experimental Example 1 also includes:

[0190] (5) At the center of the ITZO channel, a 15nm thick Al layer is deposited as the second material layer 20 using a mask. The Al layer has a width of 800μm and a length of 200μm.

[0191] And, by a step that is essentially the same as step (4) above, namely, annealing at 400°C for 1 hour in an air atmosphere, Al / 244 thin film transistors (i.e. Al / 244 TFTs) are obtained.

[0192] In addition, after obtaining the Al / 244 thin-film transistor, Experiment Example 1 also includes:

[0193] (6) The second material layer 20 (i.e., the Al layer) was etched away with 0.1M NaOH. The etching time was 3 minutes. Then the etched Al / 244 thin film transistor was cleaned with deionized water and the etched Al / 244 thin film transistor was designated as Al / 244-E thin film transistor (i.e., Al / 244-E TFT).

[0194] Transmission electron microscopy was used to observe the thin-film transistors obtained in Experimental Example 1 and the comparative example, and the results were as follows: Figure 5A The image shows a TEM (Transmission Electron Microscope) image and electron diffraction pattern of the semiconductor layer 12 of the Al / 244 TFT. It can be seen that spherical crystals are formed at the interface of ITZO near the Al layer. The thickness of crystal 30 is 5 nm to 15 nm, and the corresponding electron diffraction pattern shows the formation of ZnSnO3 crystals.

[0195] The relative content of oxygen vacancies at the interface of ITZO near the Al layer was measured using X-ray photoelectron spectroscopy, such as... Figure 5B As shown, the oxygen vacancy in Experimental Example 1 is also known as O II The area of ​​the integral region shown (approximately 9%) is relative to the O in the semiconductor layer 12 of the 244 TFT. II The area of ​​the integration region shown (approximately 15.2%) has decreased significantly. Additionally, O I This represents the integral region of oxygen in a metal-oxygen bond (i.e., the integral region of all oxygen atoms except for oxygen vacancies). Furthermore, as... Figure 5C As shown, ellipsometry measurements revealed that the refractive index of the ITZO interface near the Al layer in Experimental Example 1 was significantly higher than that of the ITZO surface in Comparative Example 1, indicating that the former had lower porosity and higher density. These findings demonstrate that the inductive effect of Al significantly enhances the microstructural order of ITZO and significantly reduces structural defects such as micropores and oxygen vacancies.

[0196] Meanwhile, the transfer characteristic curves of the Al / 244 TFT and Al / 244-E TFT in Example 1 and the 244 TFT in Comparative Example 1 were tested under a drain voltage of 10.1V, as shown in the figure. Figure 5DAs shown. Table 1 also lists the characteristic parameters of the 244 TFT in Comparative Example 1, the Al / 244 TFT and the Al / 244-E TFT in Example 1:

[0197] Table 1

[0198]

[0199] Combining Table 1 and Figure 5D It can be concluded that the field-effect mobility (μ) of the thin-film transistor in Experimental Example 1 before etching the aluminum layer (i.e., the second material layer 20) is... FE The height is relatively high, at 53.2cm. 2 / Vs, the subthreshold oscillation amplitude (SS) is low at 0.18V / decade, V th (Threshold voltage) is -0.21V, I on / I off The (switching current ratio) is relatively high at 2.49 × 10⁻⁶. 8 A. These parameters are all improved compared to the thin-film transistor in Comparative Example 1. The μ of the thin-film transistor in Experimental Example 1 after etching the aluminum layer... FE It is 51.3cm 2 / Vs, the subthreshold oscillation amplitude (SS) is low at 0.21V / decade, V th (Threshold voltage) is -0.19V, I on / I off The (switching current ratio) is relatively high at 1.89 × 10⁻⁶. 8 A. These parameters show very little change compared to before etching, indicating that the device performance is essentially maintained after etching. In the negative bias stability (NBS, -20V, 3600s) test, combined with Table 1, and... Figure 5E , Figure 5F and Figure 5G As shown, with 244TFT(ΔV) th Compared to (-2.08 V), the Al / 244 TFT exhibits very stable behavior (ΔV = -2.08 V). th =-0.24 V). The Al layer is etched away, ΔV th It can still maintain a low level, approximately -0.32V. Here, (NBS, -20V, 3600s) indicates that the test conditions for negative bias stability are a gate bias of -20V for 3600s. Figure 5E , Figure 5F and Figure 5GAs shown, the graph compares the transfer characteristic curves of the 244 TFT, Al / 244 TFT, and Al / 244-E TFT at 600s to 3600s under a gate bias of -20V. The arrows indicate the drift direction of the threshold voltage of the 244 TFT, Al / 244 TFT, and Al / 244-E TFT as the test time increases. Figure 5E , Figure 5F and Figure 5G It can be seen that as the test time increases from 600s to 3600s, the 244 TFT exhibits a significant negative threshold voltage drift, while the Al / 244 TFT and Al / 244-E TFT show no significant negative threshold voltage drift.

[0200] Experiment Example 2

[0201] The fabrication method of the thin-film transistor in Experiment 2 is basically the same as that in Experiment 1. The difference is that the second material layer 20 is replaced with metal Zn to fabricate a Zn / 244 thin-film transistor (i.e., Zn / 244 TFT).

[0202] Transmission electron microscopy was used to observe thin-film transistors, and the results were obtained as follows: Figure 6A The images shown are TEM images and electron diffraction patterns of the semiconductor layer 12 of the Zn / 244 TFT. It can be seen that after Zn-induced crystallization, the entire ITZO film is completely crystallized. The electron diffraction pattern shows the formation of ZnSnO3 crystals. These indicate that the microstructure ordering of ITZO is significantly improved through the induction effect of Zn.

[0203] The transfer characteristic curves of the Zn / 244 TFT in Example 1 were tested under a drain voltage of 10.1V, as shown below. Figure 6B As shown in the figure. Table 1 also lists the characteristic parameters of the Zn / 244 TFT.

[0204] Combining Tables 1 and 6B, the field-effect mobility (μ) of the Zn / 244 TFT is... FE The highest height is 52.8cm. 2 / Vs, the subthreshold swing amplitude (SS) is low at 0.19V / decade, V th (Threshold voltage) is -0.24V, I on / I off The (switching current ratio) is relatively high at 2.27 × 10⁻⁶. 8 A, these parameters are all improved compared to 244 TFT. Combined with... Figure 6C As shown in Table 1, in the negative bias stability test (NBS test conditions are gate bias voltage of -20V and time of 3600s), compared with 244 TFT (ΔV) thCompared to (ΔV = -2.08 V), the Zn / 244 TFT exhibits more stable behavior (ΔV = -2.08 V). th = -0.97V). Among them, Figure 6C The graph shows a comparison of the transfer characteristic curves of a Zn / 244 TFT at 600s intervals from 600s to 3600s under a gate bias of -20V. The arrows indicate the drift direction of the threshold voltage of the Zn / 244 TFT as the test time increases. Figure 6C It can be seen that as the test time increases from 600s to 3600s, the threshold voltage of the Zn / 244 TFT exhibits a certain degree of negative drift, but the drift is relatively small compared to that of the 244 TFT.

[0205] Example 3

[0206] The fabrication method of the thin-film transistor in Experiment 3 is basically the same as that in Experiment 1, except that the second material layer 20 in Experiment 3 is replaced with metal Ta. A Ta / 244 thin-film transistor (i.e., Ta / 244 TFT) is fabricated.

[0207] Experiment Example 4

[0208] The fabrication method of the thin-film transistor in Experiment 4 is basically the same as that in Experiment 1, except that the second material layer 20 in Experiment 4 is replaced with metal Hf. An Hf / 244 thin-film transistor (i.e., a Ta / 244 TFT) is fabricated.

[0209] The transfer characteristic curves of the thin-film transistors in Example 3 and Example 4 were tested under a drain voltage of 10.1V, as shown below. Figure 6D As shown, the threshold voltages of the transfer characteristic curves for both are close to 0V, and the leakage currents are both below 10V in the channel-off state. -12 Around A, it is at a relatively low level, and during the channel turn-on phase, the channel current increases rapidly and rises to a relatively high level. The field-effect mobility (μ) of the Ta / 244 TFT is... FE The length is 53.3cm. 2 / Vs, Hf / 244 TFT field-effect mobility (μ FE The length is 54.9 cm. 2 / Vs.

[0210] Experimental Example 5

[0211] The fabrication method of the thin-film transistor in Experiment 5 is basically the same as that in Experiment 1, except that the second material layer 20 in Experiment 5 is replaced with zinc oxide (ZnO). A ZnO / 244 thin-film transistor (i.e., ZnO / 244 TFT) is fabricated.

[0212] The transfer characteristic curves of the thin-film transistor in Example 5 were tested under a drain voltage of 10.1V, as shown below. Figure 7 As shown in the figure, the threshold voltage of the transfer characteristic curve is close to 0V, and the leakage current is around 10V in the channel-off state. -12 Around A, it is at a relatively low level, and during the channel turn-on phase, the channel current increases rapidly and rises to a relatively high level. ZnO / 244 TFT field-effect mobility (μ) FE It can reach 41.8 cm. 2 / Vs.

[0213] Comparative Example 2

[0214] The fabrication method of the thin-film transistor in Comparative Example 2 is basically the same as that in Comparative Example 1, except that step (4) is carried out under a nitrogen atmosphere. A 244-N2 thin-film transistor (i.e., a 244-N2 TFT) is fabricated.

[0215] Experimental Example 6

[0216] The fabrication method of the thin-film transistor in Experiment 6 is basically the same as that in Experiment 1, except that step (4) is carried out under a nitrogen atmosphere. A thin-film transistor of Al / 244-N2 (i.e., 244-N2 TFT) is fabricated.

[0217] The transfer characteristic curves of the Al / 244-N2 TFT in Example 6 and the 244-N2 TFT in Comparative Example 2 were tested under a drain voltage of 10.1V. Figure 8 As shown in the figure, the threshold voltages of the transfer characteristic curves are all close to 0V. In the channel-off state, the leakage current is around 10V. -12 The current is around A, at a relatively low level, and during the channel turn-on phase, the channel current increases rapidly and rises to a relatively high level. The field-effect mobility (μA) of the 244-N2 TFT is... FE The length is 17.6 cm. 2 / Vs, while the field-effect mobility of Al / 244-N2 TFT is as high as 49.4 cm⁻¹. 2 / Vs.

[0218] Comparative Example 3

[0219] The fabrication method of the thin-film transistor in Comparative Example 3 is basically the same as that in Comparative Example 1. The difference is that the first material layer in Comparative Example 3 is replaced with ITZO (In:Sn:Zn=4:2:4, that is, the ratio of the number of In, Sn and Zn atoms is 4:2:4), and a 424 thin-film transistor (i.e., 424 TFT) is obtained.

[0220] Experimental Example 7

[0221] The fabrication method of the thin-film transistor in Experiment 7 is basically the same as that in Experiment 1. The difference is that the first material layer in Experiment 7 is replaced with ITZO (In:Sn:Zn=4:2:4, that is, the ratio of the number of In, Sn and Zn atoms is 4:2:4), and an Al / 424 thin-film transistor (i.e. Al / 424 TFT) is obtained.

[0222] The transfer characteristic curves of the Al / 424 TFT in Example 7 and the 424 TFT in Comparative Example 2 were tested under a drain voltage of 10.1V, as shown below. Figure 9A As shown in the figure, the threshold voltage of the transfer characteristic curve is close to 0V, and the leakage current is around 10V in the channel-off state. -12 The current is around A, at a relatively low level, and during the channel turn-on phase, the channel current increases rapidly and rises to a relatively high level. The field-effect mobility (μ) of the Al / 424 TFT is... FE The tallest is 163.5cm. 2 / Vs, while the field-effect mobility of the 424 TFT (μ FE Only 31.5 cm 2 / Vs.

[0223] Comparative Example 4

[0224] The fabrication method of the thin-film transistor in Comparative Example 4 is basically the same as that in Comparative Example 3. The difference is that the first material layer 10 in Comparative Example 4 is replaced with Pr-doped ITZO (In:Sn:Zn=4:2:4, that is, the ratio of the number of In, Sn and Zn atoms is 4:2:4, and the doping concentration of Pr is 2 at.%), to obtain a Pr:424 thin-film transistor (that is, Pr:424 TFT).

[0225] Experimental Example 8

[0226] The fabrication method of the thin-film transistor in Experiment 8 is basically the same as that in Experiment 7. The difference is that the first material layer 10 in Experiment 8 is replaced with Pr-doped ITZO (In:Sn:Zn=4:2:4, that is, the ratio of the number of In, Sn and Zn atoms is 4:2:4, and the doping concentration of Pr is 2 at.%), to obtain an Al / Pr:424 thin-film transistor (i.e., Al / Pr:424 TFT).

[0227] The transfer characteristic curves of the Al / Pr:424 TFT in Example 8 and the Pr:424 TFT in Comparative Example 4 were tested under a drain voltage of 10.1V, as shown below. Figure 9B As shown in the figure, the threshold voltage of the transfer characteristic curve is close to 0V, and the leakage current is around 10V in the channel-off state. -12Around A, it is at a relatively low level, and during the channel turn-on phase, the channel current increases rapidly and rises to a relatively high level. Pr:424 TFT field-effect mobility (μ) FE The length is 38.4cm. 2 / Vs, while the field-effect mobility (μ) of Al / Pr:424 TFT FE Up to 81.0 cm tall 2 / Vs.

[0228] Comparative Example 5

[0229] The fabrication method of the thin-film transistor in Comparative Example 5 is basically the same as that in Comparative Example 4. The difference is that the first material layer 10 in Comparative Example 5 is replaced with Tb-doped ITZO (In:Sn:Zn=4:2:4, that is, the ratio of the number of In, Sn and Zn atoms is 4:2:4, and the doping concentration of Tb is 2 at.%), to obtain a Tb:424 thin-film transistor (that is, Tb:424 TFT).

[0230] Experimental Example 9

[0231] The fabrication method of the thin-film transistor in Experiment 9 is basically the same as that in Experiment 8. The difference is that the first material layer 10 in Experiment 9 is replaced with Tb-doped ITZO (In:Sn:Zn=4:2:4, that is, the ratio of the number of In, Sn and Zn atoms is 4:2:4, and the doping concentration of Tb is 2 at.%), to obtain an Al / Tb:424 thin-film transistor (i.e., Al / Tb:424 TFT).

[0232] The transfer characteristic curves of the Al / Tb:424 TFT in Example 9 and the Tb:424 TFT in Comparative Example 5 were tested under a drain voltage of 10.1V, as shown below. Figure 9C As shown in the figure, the threshold voltage of the transfer characteristic curve is close to 0V, and the leakage current is around 10V in the channel-off state. -12 Around A, it is at a relatively low level, and during the channel opening phase, the channel current increases rapidly and rises to a relatively high level. Tb: The field-effect mobility (μ) of the TFT is... FE The value is 31.3 cm. 2 / Vs, while the field-effect mobility (μ) of Al / Tb:424 TFT FE ) Up to 79.6 cm 2 / Vs.

[0233] Comparative Example 6

[0234] The fabrication method of the thin-film transistor in Comparative Example 6 is basically the same as that in Comparative Example 5. The difference is that the first material layer 10 in Comparative Example 6 is replaced with IGZO (In:Ga:Zn=1:1:1, that is, the ratio of the number of In, Ga and Zn atoms is 1:1:1) to obtain the IGZO thin-film transistor (i.e. IGZO TFT).

[0235] Experimental Example 10

[0236] The fabrication method of the thin-film transistor in Experiment 10 is basically the same as that in Experiment 9. The difference is that the first material layer 10 in Experiment 10 is replaced with IGZO (In:Ga:Zn=1:1:1, that is, the ratio of the number of In, Ga and Zn atoms is 1:1:1) to obtain the Al / IGZO thin-film transistor (that is, Al / IGZO TFT).

[0237] The transfer characteristic curves of the Al / IGZO TFT in Example 10 and the IGZO TFT in Comparative Example 6 were tested under a drain voltage of 10.1V, as shown below. Figure 10 As shown in the figure, the threshold voltage of the transfer characteristic curve is close to 0V, and the leakage current is around 10V in the channel-off state. -12 The current is around A, at a relatively low level, and during the channel turn-on phase, the channel current increases rapidly and rises to a relatively high level. The field-effect mobility (μA) of the IGZO TFT... FE The value is 10.7 cm. 2 / Vs, while the field-effect mobility (μ) of Al / IGZO TFT FE It can reach 30.3 cm. 2 / Vs.

[0238] In summary, by introducing a second material layer 20 and inducing it at a lower temperature, the second material layer 20 induces the first material layer 10 to form a metal-oxide-semiconductor crystal 30. On one hand, compared to the amorphous oxide in the semiconductor layer 12, this increases the density of the semiconductor layer 12, reducing structural defects such as voids and micropores, thereby improving the carrier mobility (i.e., electron mobility) of the semiconductor layer 12. On the other hand, the ordered microstructure (such as the atomic structure of the metal-oxide-semiconductor material) can also enhance the overlap of electron clouds between atoms, reduce electron scattering during transport, and improve electron mobility. Furthermore, improving the microstructure can reduce oxygen vacancies, thereby improving bias stability. Additionally, by controlling the heating temperature during induction at a lower temperature, fabrication can be performed on a flexible substrate, meeting the future application requirements of flexible panels.

[0239] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure is determined by the scope of the claims.

Claims

1. A thin-film transistor, comprising: Substrate; A semiconductor layer is disposed on the substrate, the semiconductor layer including a first surface close to the substrate and a second surface away from the substrate, the semiconductor layer being made of a metal oxide semiconductor material; The semiconductor layer has a channel region, and at least in the channel region, a metal oxide semiconductor crystal is formed in the semiconductor layer near the first surface or the second surface; the crystal is a spherical crystal. A metal oxide layer, which at least covers the middle portion of the channel region along the length of the channel, and the dimension of the metal oxide layer along the length of the channel is greater than or equal to 1 / 2 of the length of the channel, and the metal oxide layer is in contact with the semiconductor layer; the material of the metal oxide layer is aluminum oxide. A gate insulating layer, wherein the metal oxide layer is disposed between the gate insulating layer and the semiconductor layer.

2. The thin-film transistor according to claim 1, wherein, The thickness of the crystal in the semiconductor layer is greater than or equal to 1 / 4 of the thickness of the semiconductor layer and less than or equal to the thickness of the semiconductor layer.

3. The thin-film transistor according to claim 1 or 2, wherein, The distribution range of the crystal along the length of the channel of the semiconductor layer is greater than or equal to 1 / 2 of the length of the channel of the semiconductor layer and less than or equal to the length of the channel of the semiconductor layer.

4. The thin-film transistor according to claim 1, wherein, In the semiconductor layer, the crystal distribution density gradually increases along the direction that gradually approaches the metal oxide layer.

5. The thin-film transistor according to any one of claims 1 to 2, 4, wherein, The semiconductor layer is made of either indium zinc tin oxide or indium gallium zinc oxide; the indium zinc tin oxide and the indium gallium zinc oxide may or may not be doped with rare earth elements.

6. The thin-film transistor according to claim 5, wherein, In the case of indium zinc tin oxide and indium gallium zinc oxide doped with rare earth elements, the rare earth element is Pr or Tb.

7. The thin-film transistor according to claim 6, wherein, When the material of the semiconductor layer is selected from indium zinc tin oxide, the ratio of the number of In atoms, Sn atoms and Zn atoms in the indium zinc tin oxide is 4:2:4; or, the ratio of the number of In atoms, Sn atoms and Zn atoms in the indium gallium zinc oxide is 2:4:

4. When the material of the semiconductor layer is selected from indium gallium zinc oxide, the ratio of the number of In atoms, Ga atoms, and Zn atoms in the indium gallium zinc oxide is 1:1:

1.

8. The thin-film transistor according to claim 6 or 7, wherein, The doping concentration of the rare earth element is 2 at.

9. The thin-film transistor according to any one of claims 1 to 2, 4, 6, and 7, wherein, The oxygen vacancy concentration in the semiconductor layer is less than or equal to 10%.

10. A display panel, comprising: The thin-film transistor as described in any one of claims 1 to 9.

11. A display device, comprising: The display panel as described in claim 10.

12. A method for fabricating a thin-film transistor, wherein, The thin-film transistor includes: a semiconductor layer, the semiconductor layer including a channel region; The preparation method includes: A first material layer and a second material layer are stacked on a substrate, the first material layer and the second material layer are in contact, wherein the first material layer covers the entire layer, or the first material layer has the same pattern as the semiconductor layer, the orthographic projection of the second material layer on the substrate covers at least the middle part of the first material layer corresponding to the channel region along the length direction of the channel, and the dimension of the orthographic projection of the second material layer on the substrate along the length direction of the channel is greater than or equal to 1 / 2 of the length of the channel, the material of the first material layer is a metal oxide semiconductor material, and the material of the second material layer is aluminum or aluminum oxide; The first material layer and the second material layer are heated so that the second material layer is induced to form a spherical crystal of metal oxide semiconductor at least on the surface near the second material layer at a preset temperature, wherein the preset temperature is greater than or equal to 200°C and less than or equal to 420°C. With the first material layer covering the entire surface, after induction is complete, the first material layer is patterned to form the semiconductor layer; after induction is complete, the second material layer forms a metal oxide layer. The preparation method further includes: forming a gate insulating layer, wherein the metal oxide layer is disposed between the gate insulating layer and the semiconductor layer.

13. The method for fabricating a thin-film transistor according to claim 12, wherein, The preset temperature is less than or equal to 400℃.

14. The method for fabricating a thin-film transistor according to claim 12 or 13, wherein, The heating time is 0.5h to 4h.

15. The method for fabricating a thin-film transistor according to claim 12 or 13, wherein, The metal is selected from one or more alloys of aluminum, zinc, tin, tantalum, hafnium, zirconium and titanium.

16. The method for fabricating a thin-film transistor according to claim 12 or 13, wherein, The metal oxide includes at least one or more combinations of aluminum oxide, zinc oxide, tin oxide, tantalum oxide, hafnium oxide, zirconium oxide, and titanium oxide.

17. The method for fabricating a thin-film transistor according to claim 12 or 13, wherein, The heating atmosphere is an oxygen-containing atmosphere, an inert atmosphere, or a vacuum atmosphere.

18. The method for fabricating a thin-film transistor according to claim 12 or 13, wherein, The formation of a first material layer and a second material layer stacked on the substrate includes: The first material layer and the second material layer are formed sequentially on the gate insulating layer, or the second material layer and the first material layer are formed sequentially on the gate insulating layer.

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