A reusability verification platform and method based on VIP verification

Abstract

This application provides a reusable verification platform and method based on VIP verification, including: a verification environment and a DUT (Device Under Test) connected via an interface bus, and test cases for configuring the verification platform. The verification environment includes: a VIP verification module, a conversion module, and a UVC (Ultraviolet Control Center) module. The conversion module is connected to both the VIP verification module and the UVC module and performs data format conversion to adapt to the chip company's custom stimulus and the VIP verification module's stimulus, respectively. The VIP verification module is connected to the DUT via the interface bus. By adding a conversion module between the VIP verification module and the DUT for data format conversion, this application avoids the problem of rewriting all test cases when replacing VIP verification components, improving the reusability of the verification platform, shortening the product development cycle, accelerating the company's new product development progress, and enhancing market competitiveness. Furthermore, the converters are independent of each other, facilitating code development and maintenance, and enabling reuse between different projects.

Description

Technical Field

[0001] This application relates to the field of chip verification technology, and in particular to a reusability verification platform and method based on VIP verification. Background Technology

[0002] As chip design becomes increasingly complex, the verification components developed in-house by design companies are typically highly versatile, such as those compatible with various protocols like Ethernet, PCIe, and USB. However, developing these components in-house incurs significant time and manpower costs. Furthermore, design verification personnel within the same company may misinterpret the protocols, potentially leading to errors in the final functional design. Therefore, many design companies prioritize integrating VIP (Verification IP) into their verification environments to replace in-house verification components.

[0003] Existing methods for verification by integrating VIP components simply involve calling functions defined in the VIP components directly within the test cases. This makes test case construction entirely dependent on the VIP components. However, for some complex test scenarios, the functions provided by the VIP components cannot meet the requirements, resulting in insufficient flexibility in test case construction. Furthermore, when the VIP components need to be modified, the reusability of the corresponding verification environment is low, and the time and manpower costs are also high. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a reusable verification platform and verification method based on VIP verification, so as to solve any of the technical problems in the prior art, such as low reusability of the verification environment and low operating efficiency when different VIP verification components are replaced.

[0005] To achieve the above and other related objectives, a first aspect of this application provides a reusability verification platform and method based on VIP verification. The verification platform includes: a module under test (DUT), an interface bus, a verification environment, and test cases. The verification environment and the DUT are connected via the interface bus. The test cases are used to configure the verification platform and generate different test cases by specifying different sequences. The verification environment includes: a VIP verification module, a conversion module, and a UVC module. The conversion module is connected to the VIP verification module and the UVC module respectively, and performs data format conversion to adapt to the chip company's custom incentives and the incentives of the VIP verification module respectively. The VIP verification module is connected to the DUT via the interface bus.

[0006] In one embodiment of this application, the VIP verification module includes multiple VIP components; the conversion module integrates multiple converters; the UVC module includes a scoreboard component; and the various components in the verification environment interact with each other using TLM transaction-level communication.

[0007] In one embodiment of this application, the test cases are primarily responsible for configuring the verification platform. Different test cases can be generated by specifying different sequences. Specific test items can be implemented for each function within different test cases, thereby comprehensively verifying the DUT (Device Under Test) and identifying potential problems within it. The interface bus is used to implement data interaction between the verification environment and the DUT. After instantiating the DUT and the interface bus, data interaction can be performed through parameter calls. The verification environment encapsulates all components in the verification platform. When running different test cases, simply instantiating this verification environment in different test cases enables the instantiation of all fixed components. It is also responsible for the instantiation of components within the verification platform and the connections between components.

[0008] In one embodiment of this application, the plurality of converters are independent of each other and are connected to the plurality of VIP components one by one; and the plurality of converters receive different test cases for verification.

[0009] In one embodiment of this application, the VIP component includes: a first sequence generator, a driver, and a first monitor; the converter includes: a second sequence generator and a second monitor; wherein the first sequence generator and the first monitor are respectively connected to the module to be verified (DUT) via the interface bus.

[0010] In one embodiment of this application, the verification method includes: calling a chip company-defined stimulus in the test case and attaching it to a second sequence generator; the second sequence generator converts the chip company-defined stimulus format into a stimulus format corresponding to the VIP component, and sends the format-converted stimulus data sequentially to the first sequence generator and the driver; the driver sends the data it obtains to the DUT (Device Under Test) through the interface bus; the DUT performs calculations and sends the calculation results to the first monitor through the interface bus; the second monitor receives the data sent by the first monitor, performs format conversion to convert the data format corresponding to the VIP component into a chip company-defined data format, and sends it to the scoring board component for data comparison to obtain the verification result.

[0011] In one embodiment of this application, the verification method further includes: calling a chip company-defined stimulus in the test case, and attaching different test cases to corresponding different second sequence generators.

[0012] In summary, the reusable verification platform and method based on VIP verification provided in this application have the following beneficial effects: By adding a conversion module between the VIP verification module and the DUT (Data Under Test) module for data format conversion, this application avoids the problem of rewriting all test cases when replacing VIP verification components, improves the reusability of the verification platform, helps shorten the product development cycle, accelerates the development progress of new products, and further enhances market competitiveness; and by making each converter adapted to different VIP components independent, the coupling between multiple converters is reduced, which is beneficial for code development and maintenance, and also for reuse between different projects; by using macros to compile each converter independently, the random workload of simulation tools is reduced, and simulation efficiency is improved. Attached Figure Description

[0013] Figure 1 The diagram shows a framework of an existing VIP-based verification environment in one embodiment of this application.

[0014] Figure 2A and 2B The diagram shows a module schematic of a VIP-based reusability verification platform according to one embodiment of this application.

[0015] Figure 3 The diagram shown is a schematic representation of the reusability verification platform based on VIP verification in one embodiment of this application.

[0016] Figure 4 The diagram shown is a flowchart of a reusability verification method based on VIP verification according to an embodiment of this application. Detailed Implementation

[0017] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0018] It should be noted that in the following description, reference is made to the accompanying drawings, which illustrate several embodiments of this application. It should be understood that other embodiments may also be used, and changes in mechanical composition, structure, electrical system, and operation may be made without departing from the spirit and scope of this application. The following detailed description should not be considered limiting, and the scope of the embodiments of this application is defined only by the claims of the published patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. Spatially related terms, such as “upper,” “lower,” “left,” “right,” “below,” “below,” “lower part,” “above,” “upper part,” etc., may be used herein to illustrate the relationship between one element or feature shown in the figures and another element or feature.

[0019] Throughout this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," and "holding" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0020] Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context indicates otherwise. The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data used can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. It should be further understood that the terms “comprising,” “including,” indicate the presence of the stated features, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are to be interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” An exception to this definition will only occur if the combination of elements, functions, or operations is inherently mutually exclusive in some way.

[0021] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the invention.

[0022] To address the existing problems, this application proposes a reusability verification platform and method based on VIP verification, which solves any of the technical problems in the prior art, such as low reusability of the verification environment and low operating efficiency when different VIP verification components are replaced.

[0023] The following explanations are provided for the abbreviations used in this application: DUT stands for Design Under Test; Env stands for Test Environment; VIP0 and VIP1 represent different verification IPs provided by third-party vendors; UVC stands for UVM component developed by the chip company; interface stands for Interface Bus, used to connect DUT and Env; and testcases stands for Test Cases.

[0024] like Figure 1 The diagram shown illustrates the framework of an existing VIP-based verification environment in one embodiment of this application.

[0025] Based on the existing verification platform, the data flow includes:

[0026] 1. In testcases, call the functions or tasks defined by the VIP, and attach the sequence (stimulus source) to the sequencer (sequence generator) in the corresponding VIP verification component VIP0 or VIP1 respectively;

[0027] 2. After obtaining the sequence from the sequencer, the driver in the VIP verification component VIP0 or VIP1 sends it to the DUT through the interface.

[0028] 3. The monitor in the VIP verification component VIP0 or VIP1 continuously monitors the signals on the interface bus and sends them to the scoreboard in UVC for data comparison to obtain the verification results.

[0029] Existing verification platforms utilize built-in functions or tasks within third-party VIP verification components to write test cases, resulting in lower time and manpower costs and a simpler platform structure. However, these platforms rely entirely on third-party VIP verification components for test case construction. For more complex test scenarios, the functions or tasks provided by these components are insufficient, making them inflexible in test case building. Furthermore, existing verification platforms suffer from low reusability of the verification environment when modifications to the VIP verification components are needed. Figure 1 All components within the gray box (VIP0 and / or VIP1, UVC, testcase) need to be rewritten, which will drastically increase the time and manpower costs.

[0030] like Figure 2A The diagram shown illustrates a module schematic of a reusability verification platform based on VIP verification according to an embodiment of this application. The verification platform includes: a module under test (DUT), an interface bus, a verification environment, and test cases; the verification environment and the DUT are connected via the interface bus; the test cases are used to configure the verification platform, generating different test cases by specifying different sequences.

[0031] In one embodiment of this application, the test cases are mainly responsible for configuring the verification platform. Different test cases can be generated by specifying different sequences. Specific test items can be implemented for each function in different test cases, thereby comprehensively verifying the DUT (Device Under Test) and discovering possible problems in the DUT.

[0032] It should be noted that the test cases can generate different test cases by specifying different sequences, and these test cases can be attached to the conversion module for data format conversion.

[0033] The interface bus is used to realize data interaction between the verification environment (Env) and the module to be verified (DUT); after the module to be verified (DUT) and the interface bus are instantiated, data interaction can be performed by parameter calling.

[0034] The verification environment (Env) is used to encapsulate all components in the verification platform. When running different test cases, this verification environment only needs to be instantiated in different test cases to realize the instantiation of all fixed components. It is also responsible for the instantiation of components in the verification platform and the connection between components.

[0035] In one embodiment of this application, the verification environment (Env) includes: a VIP verification module, a conversion module, and a UVC module; the conversion module is connected to the VIP verification module and the UVC module respectively, and performs data format conversion to adapt to the chip company's customized stimulus and the VIP verification module's stimulus respectively; the VIP verification module is connected to the module to be verified (DUT) through the interface bus.

[0036] In one embodiment of this application, as Figure 2B As shown, the VIP verification module includes multiple VIP components; the conversion module integrates multiple converters; the UVC module includes a scoreboard component; and the various components in the verification environment (Env) interact with each other using TLM transaction-level communication.

[0037] It should be noted that multiple VIP verification components can be stable, commercially available VIPs from the same or different suppliers, such as VIP0, VIP1, VIP2, etc.

[0038] In one embodiment of this application, the plurality of converters are independent of each other and are connected to the plurality of VIP components one by one; and the plurality of converters receive different test cases for verification.

[0039] For example, each third-party VIP verification component has its own independent converter, such as VIP0_converter, VIP1_converter, VIP2_converter, etc. When the VIP verification component needs to be changed, only the corresponding converter needs to be replaced, which improves the reusability of the verification platform and makes the rewritten components simpler.

[0040] In one embodiment of this application, the VIP component includes: a first sequence generator, a driver, and a first monitor; the converter includes: a second sequence generator and a second monitor; wherein the first sequence generator and the first monitor are respectively connected to the module to be verified (DUT) via the interface bus.

[0041] Specifically, the sequencer is the medium for communication between the sequence and the driver. The driver sends a request to the sequencer, which then drives the sequence to obtain the transaction class and sends it to the driver. The sequence is the source of the stimulus. Different stimuli can be generated simply by setting different sequences as the default sequences of the sequencer in the test cases.

[0042] The driver sends a request to the sequencer to obtain the transaction class. The sequencer then drives the sequence to obtain the transaction class and sends it to the driver, which then transmits it to the DUT (Device Under Test) through the interface bus and drives the DUT.

[0043] The monitor is derived from the uvm_monitor class. The first monitor is used to detect the output of the DUT module to be verified. After the DUT module finishes its calculation, it transmits the valid data from the output end to the second monitor through the interface bus. After data format conversion, the data is transmitted to the UVC module to verify whether the DUT module to be verified outputs data correctly.

[0044] The interface bus serves as a bridge for data interaction between the verification environment (Env) and the device under test (DUT). Since the DUT's code is written in Verilog and is a static instance, while the verification environment is an abstract object based on SystemVerilog and is a dynamic instance, the two cannot be directly connected. Therefore, the verification platform introduces the interface bus. After instantiating the DUT and the interface bus at the top level of the verification platform, data interaction can be performed directly through parameter calls.

[0045] The verification platform provided in this application performs data format conversion by adding a conversion module between the VIP verification module and the DUT (Data Under Test) module. This avoids the problem of rewriting all test cases when replacing the VIP verification component, improves the reusability of the verification platform, helps shorten the product development cycle, accelerates the development progress of new products, and further enhances market competitiveness. Furthermore, by making each converter adapted to different VIP components independent, the coupling between multiple converters is reduced, which is beneficial for code development and maintenance, as well as for reuse between different projects. By using macros to compile each converter independently, the random workload of simulation tools is reduced, and simulation efficiency is improved.

[0046] like Figure 3 The diagram shown illustrates the specific structure and data flow of a VIP-based reusability verification platform according to one embodiment of this application. Figure 4 The diagram shown is a flowchart illustrating a reusability verification method based on VIP verification in one embodiment of this application.

[0047] In one embodiment of this application, the verification method specifically includes:

[0048] S1: In the test case, call the chip company's custom stimulus and attach it to the second sequence generator;

[0049] It should be noted that the test cases call the chip company's custom stimulus and attach different test cases to the corresponding second sequence generators.

[0050] S2: The second sequence generator converts the chip company's custom stimulus format into the stimulus format corresponding to the VIP component, and sends the converted stimulus data to the first sequence generator and the driver in sequence;

[0051] S3: The driver sends the data it receives to the DUT (Device Under Test) through the interface bus;

[0052] S4: The DUT (Device Under Test) performs calculations and sends the calculation results to the first monitor via the interface bus;

[0053] S5: The second monitor receives the data sent by the first monitor and performs format conversion to convert the data format corresponding to the VIP component into the data format customized by the chip company, and sends it to the scoring board component for data comparison to obtain the verification result.

[0054] It should be noted that when it is necessary to modify the VIP verification component provided by a third party, the verification platform provided in this application requires rewriting fewer components; only the corresponding VIP verification component and the corresponding converter need to be rewritten. Figure 3 The gray area (VIP0 and / or VIP1, VIP0_converter and / or VIP_converter).

[0055] In summary, this application provides a reusability verification platform and method based on VIP verification. The verification platform includes: a module under test (DUT), an interface bus, a verification environment, and test cases. The verification environment and the DUT are connected through the interface bus. The test cases are used to configure the verification platform and generate different test cases by specifying different sequences. The verification environment includes: a VIP verification module, a conversion module, and a UVC module. The conversion module is connected to the VIP verification module and the UVC module respectively, and performs data format conversion to adapt to the chip company's custom incentives and the incentives of the VIP verification module respectively. The VIP verification module is connected to the DUT through the interface bus.

[0056] This application adds a conversion module between the VIP verification module and the DUT (Data Under Test) module for data format conversion, avoiding the need to rewrite all test cases when replacing the VIP verification component. This improves the reusability of the verification platform, shortens the product development cycle, accelerates the development of new products, and further enhances market competitiveness. Furthermore, by making each converter adaptable to different VIP components independent, the coupling between multiple converters is reduced, which is beneficial for code development and maintenance, and also facilitates reuse across different projects. Using macros to compile each converter independently reduces the random workload of simulation tools and improves simulation efficiency.

[0057] This application effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0058] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A reusability verification platform and method based on VIP verification, characterized in that, The verification platform includes: a device under test (DUT), an interface bus, a verification environment, and test cases; the verification environment and the DUT are connected via the interface bus; the test cases are used to configure the verification platform, generating different test cases by specifying different sequences; wherein... The verification environment includes a VIP verification module, a conversion module, and a UVC module. The conversion module is connected to the VIP verification module and the UVC module respectively, and performs data format conversion to adapt to the chip company's custom incentives and the incentives of the VIP verification module respectively. The VIP verification module is connected to the DUT module to be verified through the interface bus. The VIP verification module includes multiple VIP components; the conversion module integrates multiple converters; the UVC module includes a scoreboard component; the various components in the verification environment interact with each other using TLM transaction-level communication. The plurality of converters are independent of each other and are connected to the plurality of VIP components one by one; and the plurality of converters receive different test cases for verification.

2. The reusability verification platform and method based on VIP verification according to claim 1, characterized in that, The test cases are mainly responsible for configuring the verification platform. Different test cases can be generated by specifying different sequences. Specific test items can be implemented for each function in different test cases, thereby comprehensively verifying the DUT (Device Under Test) and discovering possible problems in the DUT. The interface bus is used to realize data interaction between the verification environment and the DUT (Device Under Test); after the DUT and the interface bus are instantiated, data interaction can be performed by parameter calling. The verification environment is used to encapsulate all components in the verification platform. When running different test cases, this verification environment can be instantiated in different test cases to realize the instantiation of all fixed components. It is also responsible for the instantiation of components in the verification platform and the connection between components.

3. The reusability verification platform and method based on VIP verification according to claim 1, characterized in that, The VIP component includes: a first sequence generator, a driver, and a first monitor; the converter includes: a second sequence generator and a second monitor; wherein... The first sequence generator and the first monitor are respectively connected to the DUT (Device Under Test) through the interface bus.

4. The reusability verification platform and method based on VIP verification according to claim 3, characterized in that, The verification method includes: The test case calls the chip company's custom stimulus and attaches it to the second sequence generator; The second sequence generator converts the chip company's custom stimulus format into the stimulus format corresponding to the VIP component, and sends the converted stimulus data to the first sequence generator and the driver in sequence; The driver sends the data it receives to the DUT (Device Under Test) module via the interface bus. The module to be verified (DUT) performs calculations and sends the calculation results to the first monitor via the interface bus. The second monitor receives the data sent by the first monitor and performs format conversion to convert the data format corresponding to the VIP component into the chip company's custom data format, and sends it to the scoring board component for data comparison to obtain the verification result.

5. The reusability verification platform and method based on VIP verification according to claim 4, characterized in that, The verification method further includes: calling the chip company's custom stimulus in the test case, and attaching different test cases to corresponding different second sequence generators.

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