An implementation method of a self-defined DMA IP core based on an AXI bus

Abstract

This invention discloses a method for implementing a custom DMAIP core based on the AXI bus, applied to the Xilinx Zynq 7000 series. It includes the IP core establishment process for the PS-PL channel and the IP core establishment process for the PL-PS channel. The PS-PL channel establishment mainly includes steps such as creating an IP core, receiving and processing control data from the PS end via SOO_AXI, receiving and processing high-speed data from the PS end via MOO_AXI, and sending the high-speed data to the PL end via M_AXIS. The PL-PS channel establishment mainly includes steps such as creating an IP core, receiving and processing control data from the PS end via SOO_AXI, receiving and processing high-speed data from the PL end via the S_AXIS port, and sending the high-speed data to the PS end via M00_AXI. The custom DMAIP core based on the AXI bus implemented using this invention has the advantages of customizable interface and high flexibility.

Description

Technical Field

[0001] This invention relates to the Xilinx Zynq 7000 series, and more specifically to an implementation method of a custom DMA IP core based on the AXI bus for the Zynq 7000 series. Background Technology

[0002] The Zynq 7000 is a series of programmable system-on-a-chip (SoC) designed and manufactured by Xilinx. This series of products embeds programmable logic and a dual-core ARM Cortex A9 hard processor into a single chip. It mainly consists of two parts: the processor system (PS) and the programmable logic (PL). The two communicate with each other via a high-speed AXI bus. Through direct memory access (DMA), large amounts of data can be transferred directly to the system memory without going through the CPU. After the external device has prepared the data, it only needs to send a command to the DMA controller, which sends the address and size of the data. The DMA controller is responsible for storing the data directly from the external device to the system memory, which greatly improves the overall throughput of the system.

[0003] The Zynq 7000 series offers three types of DMA IP cores: DMA, CDMA, and VDMA. Among these, the DMA IP core is the most widely used, providing high-bandwidth direct memory access between memory and AXI4-Stream target peripherals. However, because Xilinx's DMA IP cores integrate the PS-to-PL and PL-to-PS channels, their flexibility is insufficient, preventing users from adding custom interfaces and making it difficult to address some specific requirements in real-world applications. Therefore, developing a custom DMA IP core based on the AXI bus suitable for the Zynq 7000 is of great significance. Summary of the Invention

[0004] The purpose of this invention is to address the problem that the existing DMA IP cores under Zynq 7000 lack flexibility and cannot meet the special needs of practical applications. This invention proposes a method for implementing a custom DMA IP core based on the AXI bus. This method implements two DMA IP cores, PS to PL and PL to PS, respectively. Users can add custom interfaces, which provides better flexibility and can meet the actual engineering needs.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] A method for implementing a custom DMA IP core based on the AXI bus, including the IP core establishment process from PS channel to PL channel and the IP core establishment process from PL channel to PS channel;

[0007] The process of establishing an IP core from the PS channel to the PL channel is as follows:

[0008] S1, create an IP core with an AXI4 interface, and add ports S00_AXI, M00_AXI, and M_AXIS;

[0009] S2 receives control data from the PS end through the SOO_AXI port. The write address channel signal in the SOO_AXI port serves as the starting address for receiving control data, and the write data channel signal serves as the received control data. After each data reception, the address is offset by a fixed number of bytes. The received control data is then parsed, and the parsed control data information is sent to the MOO_AXI port as the base address and total data length for the PL end to receive high-speed data from the PS end. The parsed control data information includes bit 0 as the data valid signal, bits 1-32 as the data length signal, and bits 33-64 as the data base address signal.

[0010] S3: Receive high-speed data from the PS terminal via the MOO_AXI port. At this time, the PL terminal is the master and the PS terminal is the slave. Use the data base address signal as the read address channel signal of the MOO_AXI port, and receive high-speed data from the read data channel signal. The total length of the received data is the data length signal. Calculate the valid flag signal, signal toggle signal, and end flag signal required for the M_AXIS port timing using the data valid signal. Convert the high-speed data, valid flag signal, signal toggle signal, and end flag signal into the M_AXIS timing, and send the converted data to the PL terminal through the M_AXIS port.

[0011] The process of establishing an IP core from the PL channel to the PS channel is as follows:

[0012] S4, create an IP core with an AXI4 interface, and add ports S00_AXI, M00_AXI, and S_AXIS;

[0013] S5 receives control data from the PS end through the SOO_AXI port. It uses the write address channel signal in the SOO_AXI port as the starting address for receiving control data and the write data channel signal as the received control data. After each reception of control data, it offsets the address of the received control data by a fixed number of bytes. It also parses the received control data and sends the parsed control data information to the MOO_AXI port. The parsed control data information contains the base address and total data length information required by the PL end to send high-speed data to the PS end.

[0014] S6 receives high-speed data from the PL end through the S_AXIS port, including high-speed data signals, valid flag signals, signal toggle signals, and end flag signals, and transmits them to the MOO_AXI port. At the MOO_AXI port, the high-speed data is sent to the PS end according to the parsed control data information.

[0015] The present invention has the following advantages:

[0016] 1. This invention implements two DMAIP cores, PS to PL and PL to PS, respectively. Users can add custom interfaces, such as controlling the data transmission and reception frequency by adding interrupt interval time, which can meet the engineering needs of different users.

[0017] 2. The FPGA resources required by this invention are relatively small. The custom DMAIP core based on the AXI bus implemented by this invention has the advantages of customizable interface and good flexibility. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the IP core for the PS to PL channel of this invention;

[0019] Figure 2 This is a schematic diagram of the IP core for the PL to PS channel of this invention;

[0020] Figure 3 This is a flowchart of the IP core creation process of this invention. Detailed Implementation

[0021] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0022] like Figure 1-3 As shown, a method for implementing a custom DMAIP core based on the AXI bus includes the IP core establishment process from PS to PL channel and the IP core establishment process from PL to PS channel.

[0023] The process of establishing an IP core from the PS channel to the PL channel is as follows:

[0024] S1, create an IP core with an AXI4 interface, and add ports S00_AXI, M00_AXI, and M_AXIS;

[0025] S2 receives control data from the PS end through the SOO_AXI port. The write address channel signal in the SOO_AXI port serves as the starting address for receiving control data, and the write data channel signal serves as the received control data. After each data reception, the address is offset by a fixed number of bytes. The received control data is then parsed, and the parsed control data information is sent to the MOO_AXI port as the base address and total data length for the PL end to receive high-speed data from the PS end. The parsed control data information includes bit 0 as the data valid signal, bits 1-32 as the data length signal, and bits 33-64 as the data base address signal.

[0026] S3: Receive high-speed data from the PS terminal via the MOO_AXI port. At this time, the PL terminal is the master and the PS terminal is the slave. Use the data base address signal as the read address channel signal of the MOO_AXI port, and receive high-speed data from the read data channel signal. The total length of the received data is the data length signal. Calculate the valid flag signal, signal toggle signal, and end flag signal required for the M_AXIS port timing using the data valid signal. Convert the high-speed data, valid flag signal, signal toggle signal, and end flag signal into the M_AXIS timing, and send the converted data to the PL terminal through the M_AXIS port.

[0027] The process of establishing an IP core from the PL channel to the PS channel is as follows:

[0028] S4, create an IP core with an AXI4 interface, and add ports S00_AXI, M00_AXI, and S_AXIS;

[0029] S5 receives control data from the PS end through the SOO_AXI port. It uses the write address channel signal in the SOO_AXI port as the starting address for receiving control data and the write data channel signal as the received control data. After each reception of control data, it offsets the address of the received control data by a fixed number of bytes. It also parses the received control data and sends the parsed control data information to the MOO_AXI port. The parsed control data information contains the base address and total data length information required by the PL end to send high-speed data to the PS end.

[0030] S6 receives high-speed data from the PL end through the S_AXIS port, including high-speed data signals, valid flag signals, signal toggle signals, and end flag signals, and transmits them to the MOO_AXI port. At the MOO_AXI port, the high-speed data is sent to the PS end according to the parsed control data information.

[0031] In summary, this method includes the IP core establishment process for the PS-PL channel and the IP core establishment process for the PL-PS channel. The establishment of the PS-PL channel mainly includes steps such as creating an IP core, receiving and processing PS control frames via SOO_AXI, receiving and processing high-speed data from the PS via MOO_AXI, and sending the high-speed data to the PL via MOO_AXI. The establishment of the PL-PS channel mainly includes steps such as creating an IP core, receiving and processing high-speed data from the PL via S_AXIS, receiving and processing PS control frames via SOO_AXI, and sending the high-speed data to the PS via MOO_AXI.

[0032] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0033] Specific embodiments have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this invention. Therefore, the content of this specification should not be construed as a limitation of this invention.

Claims

1. A method for implementing a custom DMAIP core based on the AXI bus, characterized in that, This includes the IP core establishment process from the PS channel to the PL channel and the IP core establishment process from the PL channel to the PS channel. The process of establishing an IP core from the PS channel to the PL channel is as follows: S1, create an IP core with an AXI4 interface, and add ports S00_AXI, M00_AXI, and M_AXIS; S2 receives control data from the PS end through the SOO_AXI port. The write address channel signal in the SOO_AXI port serves as the starting address for receiving control data, and the write data channel signal serves as the received control data. After each data reception, the address is offset by a fixed number of bytes. The received control data is then parsed, and the parsed control data information is sent to the MOO_AXI port as the base address and total data length for the PL end to receive high-speed data from the PS end. The parsed control data information includes bit 0 as the data valid signal, bits 1-32 as the data length signal, and bits 33-64 as the data base address signal. S3: Receive high-speed data from the PS terminal via the MOO_AXI port. At this time, the PL terminal is the master and the PS terminal is the slave. Use the data base address signal as the read address channel signal of the MOO_AXI port, and receive high-speed data from the read data channel signal. The total length of the received data is the data length signal. Calculate the valid flag signal, signal toggle signal, and end flag signal required for the M_AXIS port timing using the data valid signal. Convert the high-speed data, valid flag signal, signal toggle signal, and end flag signal into the M_AXIS timing, and send the converted data to the PL terminal through the M_AXIS port. The process of establishing an IP core from the PL channel to the PS channel is as follows: S4, create an IP core with an AXI4 interface, and add ports S00_AXI, M00_AXI, and S_AXIS; S5 receives control data from the PS end through the SOO_AXI port. It uses the write address channel signal in the SOO_AXI port as the starting address for receiving control data and the write data channel signal as the received control data. After each reception of control data, it offsets the address of the received control data by a fixed number of bytes. It also parses the received control data and sends the parsed control data information to the MOO_AXI port. The parsed control data information contains the base address and total data length information required by the PL end to send high-speed data to the PS end. S6 receives high-speed data from the PL end through the S_AXIS port, including high-speed data signals, valid flag signals, signal toggle signals, and end flag signals, and transmits them to the MOO_AXI port. At the MOO_AXI port, the high-speed data is sent to the PS end according to the parsed control data information.

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