A Non-Real-Time Sampling Synchronization Method for Distributed Multi-Machine Systems

Abstract

The present invention discloses a non-real-time sampling synchronization method for a distributed multi-machine system. After the integer times of the sampling point moments of each slave chassis are put into one-to-one correspondence with the integer times of the sampling point moments of the master chassis, the differences between the sampling point moments of each slave chassis and the fractional times corresponding to the sampling point moments of the master chassis are compared. If the difference is outside the threshold, the fractional time of the sampling point moment of the master chassis is used to replace the fractional time corresponding to the sampling point moment of the slave chassis. If the difference is within the threshold, the fractional time of the sampling point moment of the slave chassis remains unchanged, thus achieving the synchronization of sampling data. The non-real-time sampling synchronization method for a distributed multi-machine system provided by the present invention does not rely on a real-time operating system and a real-time sampling mechanism, has strong versatility, and can ensure the synchronization of sampling data.

Description

Technical Field

[0001] The present invention relates to a non-real-time sampling synchronization method for a distributed multi-machine system, belonging to the technical field of power automation. Background Art

[0002] With the continuous development of the power system, the functions of secondary power equipment are required to be more and more powerful, and at the same time, the sampling data is required to increase continuously. Therefore, sometimes multi-chassis collaborative work is needed. When multi-chassis collaborative work, data synchronization problems will be encountered.

[0003] At present, there are two main-sub machine synchronization methods. One is to expand a synchronization expansion module in the main machine chassis. This synchronization expansion module receives an external B-code time synchronization signal (Global Positioning System (GPS) / Beidou timing source) and forwards it to each sub-machine chassis; the other method is that each chassis receives an external B-code time synchronization signal sent by the same timing source.

[0004] For the first synchronization method, the main machine chassis needs to add an additional module type; for the second synchronization method, sufficient external B-code time synchronization signals are required. Generally, the number of external B-code time synchronization signal sources in the power plant is limited and cannot provide multiple B-code time synchronization signals for a set of devices.

[0005] In order to achieve better sampling synchronization of multi-chassis, those skilled in the art need to provide an economical and effective synchronization sampling method. Summary of the Invention

[0006] Objective: To overcome the deficiencies in the prior art, the present invention provides a non-real-time sampling synchronization method for a distributed multi-machine system, which does not rely on a real-time operating system and a real-time sampling mechanism, has strong versatility, and can ensure the synchronization of sampling data.

[0007] Technical Solution: To solve the above technical problems, the technical solution adopted by the present invention is as follows:

[0008] A non-real-time sampling synchronization method for a distributed multi-machine system includes the following steps:

[0009] Step 1: The CPU module of the main machine chassis generates n-1 synchronization messages at a moment Δt before the whole second. The CPU module of the main machine chassis sends the synchronization messages to the CPU modules of each sub-machine chassis respectively. The CPU module of each sub-machine chassis parses the synchronization messages to generate a corresponding synchronization signal for each sub-machine chassis. The CPU module of the sub-machine chassis sends the synchronization signals to the sampling modules of the sub-machine chassis through a synchronization bus respectively. The sampling module of the sub-machine chassis obtains the count value of the 32-bit second counter according to the synchronization signal, which is the starting moment of the synchronization pulse signal second.

[0010] Step 2: The integer time of the sampling point moment of the sampling module in the slave chassis is determined by the count value of the 32-bit second counter, and the fractional time of the sampling point moment is determined by the time offset from the start moment of the second of the synchronization pulse signal.

[0011] Step 3: The CPU module in the master chassis generates a synchronization signal at the whole second moment and sends the synchronization signal to each sampling module in the master chassis through the synchronization bus.

[0012] Step 4: Each sampling module in the master chassis obtains the count value of the 32-bit second counter according to the synchronization signal. At the start moment of the second of the synchronization pulse signal, the integer time of the sampling point moment of the sampling module in the master chassis is determined by the count value of the 32-bit second counter, and the fractional time of the sampling point moment is determined by the time offset from the start moment of the second of the synchronization pulse signal.

[0013] Step 5: The sampling module of each slave chassis forms a data message with the sampling point moment as the frame header and the corresponding sampling data frame and sends it to the CPU module of its own slave chassis.

[0014] Step 6: The CPU module of each slave chassis uploads the data message to the CPU module of the master chassis respectively.

[0015] Step 7: The CPU module of the master chassis obtains the sampling point moment of each slave chassis according to the frame header of the data message. After the integer time of the sampling point moment of each slave chassis is corresponded one by one with the integer time of the sampling point moment of the master chassis, the difference between the sampling point moment of each slave chassis and the fractional time corresponding to the sampling point moment of the master chassis is compared. If the difference is outside the threshold, the fractional time of the sampling point moment of the master chassis is used to replace the fractional time corresponding to the sampling point moment of the slave chassis. If the difference is within the threshold, the fractional time of the sampling point moment of the slave chassis remains unchanged, that is, the sampling data synchronization is realized.

[0016] As a preferred solution, it further includes Step 8: The CPU module of the master chassis receives the external B-code time synchronization signal, generates the absolute time scale of the distributed multi-machine system after real-time decoding processing, and the CPU module of the master chassis adds the absolute time scale to the sampling data of each chassis collected by the distributed multi-machine system as the time scale information for the distributed multi-machine system to communicate with the outside.

[0017] As a preferred solution, the calculation formula of the time offset from the start moment of the second of the synchronization pulse signal is as follows:

[0018] dt_offset_n = dt_tick * dt_n

[0019] Among them, dt_offset_n represents the time offset of the starting moment of the second of the synchronous pulse signal at the nth sampling point, dt_tick represents the time interval count value of each sampling point on average, and dt_n is the nth sampling point.

[0020] As a preferred solution, the calculation formula of dt_tick is as follows:

[0021] dt_tick = dT_tick / dT_N

[0022] Among them, dT_tick is the time interval between two synchronous pulse signals, and dT_N is the number of sampling points between two synchronous pulse signals.

[0023] As a preferred solution, Δt = t1 + t2

[0024] Among them, t1 is the transmission delay of the optical Ethernet link, and t2 is the transmission delay of the synchronous message data.

[0025] As a preferred solution, t1 = n * L / c

[0026] Among them, c is the speed of light, n is the group refractive index of the optical fiber, and L is the length of the optical fiber.

[0027] As a preferred solution, t2 = 8 * 1 / ν * N, where 8 means each byte is 8 bits, ν is the rate of the optical Ethernet, and N is the length of the synchronous message.

[0028] As a preferred solution, the CPU module of the host chassis and the CPU module of the slave chassis respectively transmit the upstream data and the downstream data through independent optical transceiver modules.

[0029] Beneficial effects: A non-real-time sampling synchronization method for a distributed multi-machine system provided by the present invention has the following advantages compared with the prior art:

[0030] (1) The implementation method of the present invention is simple and the cost is low.

[0031] (2) The master-slave communication adopts a group of optical transceiver modules, and the upstream data and the downstream data are separated, which not only makes full use of the transceiver function of the optical module, but also prevents data conflicts and ensures the stability of the data.

[0032] (3) Using the time offset of the sampling point as the data alignment moment ensures the synchronization of the data, updates the synchronous pulse once per second, and reduces the cumulative synchronization error. Description of the Drawings

[0033] Figure 1 It is a schematic structural diagram of the distributed multi-machine system of the present invention. Detailed Embodiments

[0034] The present invention will be further described in conjunction with specific embodiments as follows.

[0035] As Figure 1 shown, a distributed multi-computer system includes: n chassis, where 1 is the main chassis and n - 1 are sub-chassis. Each chassis has an independent custom synchronization signal, and n is greater than or equal to 2. A first synchronization bus is provided in the main chassis, and second to n - 1 synchronization buses are sequentially provided in each sub-chassis.

[0036] Both the main chassis and the sub-chassis include a CPU module and m sampling modules.

[0037] The CPU module and m sampling modules in the main chassis transfer data and signals through the first synchronization bus.

[0038] The CPU module and m sampling modules in each sub-chassis transfer data and signals sequentially through the second to n - 1 synchronization buses.

[0039] The CPU module in the main chassis is connected to the CPU modules in each sub-chassis through different optical ports. The transmit port of the optical port is used for the CPU in the main chassis to issue the custom synchronization signal, and the receive port is used for the CPU in the main chassis to collect the sampled data sent from the sub-chassis. The data transmission and reception are completely independent, which can avoid data conflicts and ensure the accuracy of the master-slave chassis synchronization.

[0040] The sampling module can collect analog signals such as digital signals, direct current, temperature, and alternating voltage and current.

[0041] The CPU module in the main chassis receives the external B-code time synchronization signal. After real-time decoding and processing, it generates the absolute time scale of the entire distributed multi-computer system. Through this absolute time scale, the time scale information of year, month, day, hour, minute, second, and nS can be obtained, and this absolute time scale has the function of maintaining time when out of synchronization. The CPU module in the main chassis adds the absolute time scale to the sampled data of each chassis collected by the entire distributed multi-computer system as the time scale information for communication between the distributed multi-computer system and the outside.

[0042] A non-real-time sampling synchronization method for a distributed multi-computer system includes the following steps:

[0043] Step 1, at a moment Δt before the whole second, the CPU module in the main chassis generates n - 1 synchronization messages each containing a 32-bit second counter, and issues the synchronization messages each containing a 32-bit second counter to the CPU modules in each sub-chassis through different optical Ethernet networks respectively. After parsing the synchronization messages, the CPU modules in each sub-chassis generate synchronization signals containing synchronization pulse signals and 32-bit second counters. The synchronization pulse signal is sent once per second, and the count value of the 32-bit second counter is incremented by 1 per second. The CPU modules in each sub-chassis respectively transmit the synchronization signals to each sampling module through the synchronization bus.

[0044] Step 2: The sampling module obtains the second start time of the synchronization pulse signal of the synchronization signal and the count value of the 32-bit second counter through the synchronization bus. The integer time of the sampling point of the sampling point is determined by the count value of the 32-bit second counter, and the fractional time of the sampling point is determined by the time offset of the second start time of the synchronization pulse signal.

[0045] The time offset of the second start time of the synchronization pulse of the sampling point of the sampling module is calculated by the following formula:

[0046] The count value of the time interval dt_tick for each sampling point on average is: dt_tick = dT_tick / dT_N;

[0047] The time offset of the nth sampling point from the second start time of the synchronization pulse signal: dt_offset_n = dt_tick * dt_n.

[0048] Where, dT_tick is the time interval between two synchronization pulse signals, dT_N is the number of sampling points between two synchronization pulse signals, and dt_n is the nth sampling point.

[0049] According to the above formula, the count value of the time interval dt_tick for each sampling point on average can be obtained, and thus the time offset dt_offset_n of the nth sampling point can be obtained. Clear dt_n at the whole second moment.

[0050] Step 3: The CPU module of the mainframe chassis generates 1 synchronization signal including the synchronization pulse signal and the 32-bit second calculator at the whole second moment, and the synchronization signal is transmitted to each sampling module of the mainframe chassis through the synchronization bus.

[0051] Step 4: The integer time of the sampling point of the sampling module of the mainframe chassis is determined by the count value of the 32-bit second counter, and the fractional time of the sampling point is determined by the time offset of the second start time of the synchronization pulse signal.

[0052] The calculation method of the time offset dt_offdet_n of the nth point of the sampling point of the sampling module of the mainframe chassis is the same as the method in Step 2.

[0053] Step 5: Each sampling module of each sub-chassis adds the 32-bit second count value and the time offset dt_offset_n of the sampling point to the frame header of each frame of the message, and after packetizing with the sampling module data frame, it is sent to the CPU module of its respective sub-chassis.

[0054] Step 6: The CPU module of each sub-chassis packetizes the data obtained by the sampling module of its own sub-chassis to obtain a sampling message, and uploads the sampling message to the CPU module of the mainframe chassis through the optical Ethernet.

[0055] Step 7, the CPU module of the mainframe chassis receives the sampling data of each sampling module in this chassis and the sampling messages sent from each sub-chassis, and by parsing the sampling messages, obtains the 32-bit second count value of each sub-chassis and the time offset dt_offset_n of the sampling point, and realizes the synchronization of sampling data by comparing the 32-bit second count value of each sampling data and the time offset dt_offset_n of the sampling point.

[0056] The steps of sampling data synchronization are as follows:

[0057] After the integer time of the sampling point moment of each sub-chassis is corresponded to the integer time of the sampling point moment of the mainframe chassis one by one, compare the difference between the decimal time of the sampling point moment of each sub-chassis and the decimal time corresponding to the sampling point moment of the mainframe chassis. If the difference is outside the threshold, replace the decimal time of the sampling point moment of the mainframe chassis with the decimal time corresponding to the sampling point moment of the sub-chassis. If the difference is within the threshold, the decimal time of the sampling point moment of the sub-chassis remains unchanged, that is, the synchronization of sampling data is realized.

[0058] Step 8, the CPU module of the mainframe chassis receives the external B-code time synchronization signal, generates the absolute time scale of the entire distributed multi-machine system after real-time decoding processing, and adds the absolute time scale to the sampling data of each chassis collected by the entire distributed multi-machine system, as the time scale for the distributed multi-machine system to communicate with the outside.

[0059] In this embodiment, the CPU module of the sub-chassis completes the parsing of the synchronization message sent by the CPU module of the mainframe chassis and generates a synchronization signal with a delay of Δt. This delay includes the optical Ethernet link transmission delay t1 and the synchronization message data transmission delay t2, that is, Δt = t1 + t2. Therefore, the CPU module of the mainframe chassis sends the synchronization message to the sub-chassis at Δt moment before the whole second, so that the second start moment of the synchronization signal of the sub-chassis is synchronized with the second start moment of the synchronization signal of the mainframe chassis, and the 32-bit second count value of the synchronization signal of the sub-chassis is the same as the 32-bit second count value of the synchronization signal of the mainframe chassis.

[0060] The above optical Ethernet link transmission delay t1 = n*L / c, where c is the speed of light, about 300,000 km / s, n is the refractive index of the fiber group, generally between 1.467 and 1.468 (multimode fiber with a wavelength of 1310 nm), and L is the fiber length. For the mainframe chassis and the sub-chassis, generally multi-mode fibers with a fiber length of 2m and a wavelength of 1310 nm are used for interconnection, then the optical fiber link transmission delay time is about 10 ns.

[0061] The above-mentioned synchronous message data transmission delay t2 = 8 * 1 / ν * N, where 8 represents that each byte is 8 bits, ν is the optical Ethernet rate, and N is the synchronous message length (in bytes). For a 100-Mbps fiber optic Ethernet, its rate is 100 Mbps, the synchronous message length is the minimum frame length of 100-Mbps Ethernet, which is 64 bytes, and the synchronous message transmission delay is 5.12 us.

[0062] The above-mentioned times t1 and t2 are fixed and measurable, so the time Δt is also fixed and measurable. Considering that t1 is much smaller than t2, Δt is approximately equal to t2.

[0063] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A non-real-time sampling synchronization method for a distributed multi-machine system, characterized in that: It includes the following steps: Step 1: The CPU module of the mainframe chassis generates n-1 synchronization messages at the moment Δt before the whole second. The CPU module of the mainframe chassis sends the synchronization messages to the CPU modules of each sub-chassis respectively. The CPU module of each sub-chassis parses the synchronization messages to generate the synchronization signals corresponding to each sub-chassis. The CPU module of the sub-chassis sends the synchronization signals to the sampling modules of the sub-chassis through the synchronization bus respectively. The sampling module of the sub-chassis obtains the count value of the 32-bit second counter according to the synchronization signal, which is the starting moment of the synchronization pulse signal second; Step 2: The integer time of the sampling point moment of the sampling module of the sub-chassis is determined by the count value of the 32-bit second counter, and the fractional time of the sampling point moment is determined by the time offset of the starting moment of the synchronization pulse signal second; Step 3: The CPU module of the mainframe chassis generates a synchronization signal at the whole second moment and sends the synchronization signal to each sampling module of the mainframe chassis through the synchronization bus; Step 4: Each sampling module of the mainframe chassis obtains the count value of the 32-bit second counter according to the synchronization signal, which is the starting moment of the synchronization pulse signal second. The integer time of the sampling point moment of the sampling module of the mainframe chassis is determined by the count value of the 32-bit second counter, and the fractional time of the sampling point moment is determined by the time offset of the starting moment of the synchronization pulse signal second; Step 5: The sampling module of each sub-chassis forms a data message with the sampling point moment as the frame header and the corresponding sampling data frame and sends it to the CPU module of its own sub-chassis; Step 6: The CPU module of each sub-chassis uploads the data message to the CPU module of the mainframe chassis respectively; Step 7: The CPU module of the mainframe chassis obtains the sampling point moment of each sub-chassis according to the frame header of the data message. After the integer time of the sampling point moment of each sub-chassis is corresponded one by one with the integer time of the sampling point moment of the mainframe chassis, the difference between the sampling point moment of each sub-chassis and the fractional time corresponding to the sampling point moment of the mainframe chassis is compared. If the difference is outside the threshold, the fractional time of the sampling point moment of the mainframe chassis is used to replace the fractional time corresponding to the sampling point moment of the sub-chassis. If the difference is within the threshold, the fractional time of the sampling point moment of the sub-chassis remains unchanged.

2. The non-real-time sampling synchronization method for a distributed multi-machine system according to claim 1, wherein: It also includes Step 8: The CPU module of the mainframe chassis receives the external B-code time synchronization signal, generates the absolute time scale of the distributed multi-machine system after real-time decoding processing, and the CPU module of the mainframe chassis adds the absolute time scale to the sampling data of each chassis collected by the distributed multi-machine system as the time scale information for the distributed multi-machine system to communicate with the outside.

3. A non-real-time sampling synchronization method for a distributed multi-machine system according to claim 1 or 2, characterized in that: The calculation formula of the time offset of the starting moment of the synchronization pulse signal second is as follows: dt_offset_n = dt_tick * dt_n Where, dt_offset_n represents the time offset of the starting moment of the synchronization pulse signal second of the nth sampling point, dt_tick represents the count value of the time interval per sampling point on average, and dt_n is the nth sampling point.

4. A non-real-time sampling synchronization method for a distributed multi-machine system according to claim 3, characterized in that: The calculation formula of dt_tick is as follows: dt_tick = dT_tick / dT_N Among them, dT_tick is the time interval between two synchronous pulse signals, and dT_N is the number of sampling points between two synchronous pulse signals.

5. A non-real-time sampling synchronization method for a distributed multi-machine system according to claim 1 or 2, characterized in that: Δt = t1 + t2 Among them, t1 is the transmission delay of the optical Ethernet link, and t2 is the transmission delay of the synchronous message data.

6. A non-real-time sampling synchronization method for a distributed multi-machine system according to claim 5, characterized in that: t1 = n * L / c Among them, c is the speed of light, n is the group refractive index of the optical fiber, and L is the length of the optical fiber.

7. A non-real-time sampling synchronization method for a distributed multi-machine system according to claim 5, characterized in that: t2 = 8 * 1 / ν * N Among them, 8 means that each byte is 8 bits, ν is the optical Ethernet rate, and N is the length of the synchronous message.

8. A non-real-time sampling synchronization method for a distributed multi-machine system according to claim 1 or 2, characterized in that: The CPU module of the host chassis and the CPU module of the slave chassis respectively transmit the uplink data and the downlink data through independent optical transceiver modules.

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