Design methods, devices, electronic devices, and storage media for digital circuits

Abstract

A digital circuit design method, apparatus, electronic device, and storage medium. The digital circuit design method includes: determining at least one target logic module in at least one sub-design that requires engineering modification; performing engineering modification processing on each target logic module; wherein the engineering modification processing includes: determining the difference between the target logic module before and after physical implementation; based on the difference, reconstructing the target logic module to obtain a reconstructed logic module, wherein the reconstructed logic module matches the state elements in the target logic module; and performing engineering modification on the reconstructed logic module to obtain a modified logic module. The digital circuit design method enables engineering modification at a module granularity, eliminating design restrictions on engineering modification, greatly improving the efficiency of engineering modification and accelerating project R&D progress.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a digital circuit design method, a digital circuit design device, an electronic device, and a non-transitory computer-readable storage medium. Background Art

[0002] The integrated circuit design process consists of front-end design and back-end design. Front-end design primarily encompasses algorithm or hardware architecture design and analysis, RTL (Register Transfer Level) implementation, functional verification, and logic synthesis. Back-end design encompasses layout and routing, timing closure, and physical verification. Each stage of the integrated circuit design process involves complex design processes, and each stage can require weeks or even months of development time. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a method for designing a digital circuit, wherein the digital circuit includes at least one sub-design, each sub-design includes at least one logic module, and each sub-design is individually laid out and routed. The design method includes: determining at least one target logic module in the at least one sub-design that requires engineering modification; performing engineering modification processing on each target logic module; wherein the engineering modification processing includes: determining a difference between the target logic module before and after physical implementation; based on the difference, reconstructing the target logic module to obtain a reconstructed logic module, wherein the reconstructed logic module matches a state element in the target logic module; and performing engineering modification on the reconstructed logic module to obtain a modified logic module.

[0004] For example, in at least one embodiment of the present disclosure, a method for designing a digital circuit is provided, in which the difference between the target logic module before and after physical implementation is determined, including: obtaining a front-end netlist and a first back-end netlist corresponding to the target sub-design where the target logic module is located; determining that the portion corresponding to the target logic module in the front-end netlist is the module front-end netlist, and determining that the portion corresponding to the target logic module in the first back-end netlist is the first module back-end netlist; comparing the module front-end netlist and the first module back-end netlist to determine the state elements added to the first module back-end netlist relative to the module front-end netlist, and using the added state elements as the difference.

[0005] For example, in at least one embodiment of the present disclosure, a design method for a digital circuit is provided, in which the target logic module is reconstructed based on the difference to obtain a reconstructed logic module, including: based on the difference, modifying the state elements in the back-end netlist of the first module to obtain the back-end netlist of the second module corresponding to the reconstructed logic module, wherein the back-end netlist of the second module has a one-to-one mapping relationship with the state elements in the front-end netlist of the module.

[0006] For example, in at least one embodiment of the present disclosure, a method for designing a digital circuit is provided, in which, based on the difference, the state elements in the back-end netlist of the first module are modified to obtain the back-end netlist of the second module corresponding to the reconstructed logic module, including: removing the added state elements in the back-end netlist of the first module; and modifying the connection relationship of the devices connected to the added state elements to obtain the back-end netlist of the second module.

[0007] For example, in at least one embodiment of the present disclosure, a method for designing a digital circuit is provided, wherein the state element includes an input port.

[0008] For example, in at least one embodiment of the present disclosure, a method for designing a digital circuit is provided, wherein the state element includes an input port, and removing the added state element in the back-end netlist of the first module includes: removing the input port newly added in the back-end netlist of the first module relative to the front-end netlist of the module.

[0009] For example, in at least one embodiment of the present disclosure, a method for designing a digital circuit is provided, in which the connection relationship of the devices connected to the added state element is modified to obtain the second module back-end netlist, including: determining at least one reserved input port in the first module back-end netlist that has the same interface definition as the newly added input port; connecting the devices connected to the added state element in the first module back-end netlist to the corresponding reserved input ports to obtain the second module back-end netlist; wherein, in the second module back-end netlist and the module front-end netlist, the number of input ports of the target logic module and the interface definition of the corresponding input ports are exactly the same.

[0010] For example, in at least one embodiment of the present disclosure, a design method for a digital circuit is provided, in which engineering modification is performed on the reconstructed logic module to obtain a modified logic module, including: using an engineering modification tool to perform engineering modification on the reconstructed logic module to obtain an intermediate logic module, wherein the register transfer level description file corresponding to the intermediate logic module, the second module back-end netlist, the register transfer level description file corresponding to the intermediate logic module, and the third module back-end netlist corresponding to the intermediate logic module are equivalent to each other; and the intermediate logic module is restored to obtain the modified logic module.

[0011] For example, in at least one embodiment of the present disclosure, a method for designing a digital circuit is provided, in which the intermediate logic module is restored to obtain the modified logic module, including: based on the difference, restoring the third module back-end netlist to obtain a fourth module back-end netlist corresponding to the modified logic module, wherein the fourth module back-end netlist matches all state elements in the first module back-end netlist.

[0012] For example, in at least one embodiment of the present disclosure, a design method for a digital circuit is provided, wherein the state element includes an input port, and based on the difference, the third module back-end netlist corresponding to the intermediate logic module is restored to obtain the fourth module back-end netlist corresponding to the modified logic module, including: based on the difference, determining the input port added to the first module back-end netlist relative to the module front-end netlist; adding the added input port to the third module back-end netlist; determining at least one device in the first module back-end netlist connected to the added input port; determining at least one device in the third module back-end netlist corresponding to the at least one device as a device to be restored; and restoring the connection relationship of the device to be restored in the third module back-end netlist to the state in the first module back-end netlist to obtain the fourth module back-end netlist.

[0013] For example, at least one embodiment of the present disclosure provides a digital circuit design method further comprising: performing formal equivalence verification on the target sub-design based on the modified logic module.

[0014] For example, in at least one embodiment of the present disclosure, a design method for a digital circuit is provided, in which formal equivalence verification is performed on the target sub-design based on the modified logic module, including: updating the first module back-end netlist in the first back-end netlist corresponding to the target sub-design to the fourth module back-end netlist corresponding to the modified logic module to obtain a second back-end netlist; obtaining a register transfer level description file corresponding to the target sub-design after the engineering modification, and performing formal equivalence verification based on the register transfer level description file and the second back-end netlist.

[0015] For example, at least one embodiment of the present disclosure provides a method for designing a digital circuit, in which the engineering modification process is performed on the at least one logic module in parallel.

[0016] At least one embodiment of the present disclosure provides a digital circuit design device, wherein the digital circuit includes at least one sub-design, each sub-design includes at least one logic module, and each sub-design is independently laid out and routed. The design device includes: a determination unit configured to determine at least one target logic module in the at least one sub-design that requires engineering modification; an execution unit configured to perform engineering modification processing on each target logic module; wherein the engineering modification processing includes: determining the difference between the target logic module before and after physical implementation; based on the difference, reconstructing the target logic module to obtain a reconstructed logic module, wherein the reconstructed logic module matches a state element in the target logic module; and performing engineering modification on the reconstructed logic module to obtain a modified logic module.

[0017] At least one embodiment of the present disclosure provides an electronic device, comprising: a memory, which non-transitorily stores computer-executable instructions; and a processor, configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the processor, implement the digital circuit design method according to at least one embodiment of the present disclosure.

[0018] At least one embodiment of the present disclosure provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the digital circuit design method according to at least one embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0020] Figure 1A-Figure 1C Schematic diagram of the front-end netlist and back-end netlist of the logic module;

[0021] Figure 2 A schematic flow chart of a digital circuit design method provided in at least one embodiment of the present disclosure;

[0022] Figure 3 A schematic flowchart of an engineering modification process provided for at least one embodiment of the present disclosure;

[0023] Figure 4A A schematic diagram of a back-end netlist of a second module provided in an embodiment of the present disclosure;

[0024] Figure 4B A schematic diagram of a back-end netlist of a third module provided in an embodiment of the present disclosure;

[0025] Figure 4C A schematic diagram of a back-end netlist of a fourth module provided in an embodiment of the present disclosure;

[0026] Figure 5A A schematic block diagram of a digital circuit design device provided in at least one embodiment of the present disclosure;

[0027] Figure 5B A schematic block diagram of an execution unit provided in at least one embodiment of the present disclosure;

[0028] Figure 6 A schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure;

[0029] Figure 7 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0031] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0032] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and components.

[0033] During the back-end design of integrated circuits, for example, after logic synthesis, place and route, or timing closure, design issues may arise and require modification. Directly modifying the RTL (Register Transfer Level) file requires re-running the entire design process, severely impacting project progress and wasting significant back-end design effort. In these cases, an Engineering Change Order (ECO) can be performed to implement the circuit modifications.

[0034] Typically, engineering modifications are divided into logic engineering modifications (Logic ECO) and physical engineering modifications (Physical ECO) based on the execution stage. Logic engineering modifications are usually performed before chip tape-out. For example, based on the final register transfer level description file, some logic is added or deleted in the form of a script to the register transfer level description file, or more subtle modifications are made, such as cleaning up some circuit paths for signal integrity, thereby achieving engineering modifications to the circuit function. Physical engineering modifications are usually performed during the chip production stage. For example, some required components (cells) are added to the design or spare components (spare cells) in the circuit are used to implement engineering modifications to meet the circuit constraint requirements.

[0035] Engineering modifications can be made manually by designers or automatically using engineering modification tools, such as ConformalECO Designer. Currently, the basic principle of commercial tools for automated circuit engineering modifications is logical equivalence. For example, the register transfer level description file and the corresponding post-layout netlist before engineering modification are called the old RTL and old netlist, forming the old design pair. The register transfer level description file and the corresponding post-layout netlist after engineering modification are called the new RTL and new netlist, forming the new design pair. Automated engineering modification tools must ensure logical equivalence between the old RTL, old netlist, new RTL, and new netlist, for example, by performing equivalence verification on the old RTL, old netlist, new RTL, and new netlist.

[0036] Logical equivalence uses formal, static methods to determine whether different versions of files are functionally equivalent. During equivalence verification, the old and new design pairs must have matching state elements across the entire state space. This means that all input ports and registers must match between the old RTL, old netlist, new RTL, and new netlist. Matching here means they have a one-to-one mapping relationship.

[0037] For example, integrated circuits are designed using a hierarchical design approach. For example, a large integrated circuit can be divided into multiple sub-designs, each of which is independently laid out and routed. There are no dependencies between the sub-designs, and the remaining portion of the integrated circuit, excluding the sub-designs, is considered the top-level design. For example, a sub-design may include multiple logic modules, and the portion of the sub-design excluding the logic modules is considered a sub-top-level design. Depending on the depth and complexity of the integrated circuit's hierarchy, sub-sub-top-level designs can even exist within the sub-design.

[0038] For example, for a sub-design of an integrated circuit, all input ports in the sub-top-level design in the old RTL corresponding to the sub-design are called first input ports, and all input ports in the sub-top-level design in the old netlist are called second input ports. The first input port needs to have a corresponding second input port. In this case, it is said that there is a one-to-one mapping relationship between the old design pairs.

[0039] Currently, automatic engineering modification tools can only be executed at the layout level. This is because at the layout level, that is, the top-level design, the state elements do not change during the physical synthesis process. However, the logic modules included in the layout may change during the physical implementation process due to clock tree synthesis, fan-out optimization, feedthrough, etc., which may cause the state elements of the logic modules to change during the physical synthesis process.

[0040] Figure 1A-Figure 1C Schematic diagram of the front-end netlist and back-end netlist of the logic module.

[0041] It should be noted that the front-end netlist (pre-layout netlist or pre-place and route netlist) in this disclosure refers to the gate-level netlist obtained after logic synthesis of the register transfer level description file, that is, the netlist before the wiring layout is performed. The front-end netlist represents the component connection relationship at the logic layer. The back-end netlist (post-layout netlist or post-place and route netlist) refers to the netlist generated after physical synthesis of the front-end netlist, that is, the netlist after optimization processes such as layout and routing, timing optimization, clock tree synthesis, and high fan-out synthesis. The back-end netlist adds clock tree, buffer and other information based on physical implementation. Typically, the logic modules in the back-end netlist will have additional input ports, physical cross-links, etc. compared to the front-end netlist.

[0042] like Figure 1AAs shown, the black rectangle in the front-end netlist (a) represents layout 1. For example, layout 1 is a design or sub-design of an integrated circuit. Layout 1 includes an input port 0, buffer 0, and logic module 1. For example, input port 0 is used to input a clock signal. The dashed rectangle represents logic module 1. For example, logic module 1 is any logic module in layout 1. Logic module 1 includes an input port 1, three sequential devices (such as register 0, register 1, and register 2), and buffer 1. For example, the clock signal input from input port 0 is processed by buffer 0, then input to logic module 1 via input port 1. After being processed by buffer 1, it is input to the clock signal input terminals of the three sequential devices.

[0043] For example, after performing clock tree synthesis (CTS) on the front-end netlist (a), the back-end netlist (b) is generated. Compared with the front-end netlist (a), the layout-level state elements (such as input ports) in the back-end netlist (b) have not changed. That is, layout 1 still includes input port 0.

[0044] However, at the level of logic module 1, the state elements (e.g., input ports) have changed, e.g. Figure 1A As shown, back-end netlist (b) adds two input ports compared to front-end netlist (a): input port 1_1 and input port 1_2. These two additional input ports receive the clock signal from input port 0 via two newly added buffers. Furthermore, two buffers 1_1 and 1_2 are added within logic module 1 to receive the clock signals from input port 1_1 and input port 1_2, respectively. For example, in back-end netlist (b), the clock input port of register 0 is connected to input port 1 via buffer 1, the clock input port of register 1 is connected to input port 1_1 via buffer 1_1, and the clock input port of register 2 is connected to input port 1_2 via buffer 1_2.

[0045] refer to Figure 1A It can be seen that in the back-end netlist generated by clock tree synthesis of the front-end netlist, logic module 1 has a new input port to optimize the circuit. In other words, the part corresponding to logic module 1 in the front-end netlist and the part of the state elements corresponding to logic module 1 in the back-end netlist do not match.

[0046] like Figure 1B As shown, the black rectangle in the front-end netlist (c) represents the board Figure 2 , for example Figure 2 It is the design or sub-design of integrated circuits, Figure 2 Includes an input port 2. The dotted rectangle represents the logic module 2. For example, the logic module 2 is the Figure 2In any logic module, logic module 2 includes 1 input port 3 and 3 combinational logics (for example, combinational logic 1, combinational logic 2 and combinational logic 3). Figure 1B Definitions of other circuit elements in Figure 1A The same as in the previous section, no further details will be given here.

[0047] For example, after performing high-fanout synthesis on the front-end netlist (c), the back-end netlist (d) is obtained. Compared with the front-end netlist (c), the state elements (such as input ports) at the layout level in the back-end netlist (d) have not changed, that is, the layout Figure 2 The backend netlist (d) still includes input port 2. However, at the logic module 2 level, the backend netlist (d) adds two input ports, input port 3_1 and input port 3_2, compared to the frontend netlist (c). These two additional input ports still receive the signal from input port 2 through the newly added buffer. For example, in the backend netlist (d), combinational logic 1 receives the signal from input port 3, combinational logic 2 receives the signal from input port 3_1, and combinational logic 3 receives the signal from input port 3_2.

[0048] refer to Figure 1B It can be seen that in the back-end netlist (d) generated by high fan-out synthesis of the front-end netlist (c), logic module 2 has a new input port to optimize the circuit. In other words, the part corresponding to logic module 2 in the front-end netlist (c) does not match the part of the state elements corresponding to logic module 2 in the back-end netlist (d).

[0049] like Figure 1C As shown, the black rectangle in the front-end netlist (e) represents the board Figure 3 , for example Figure 3 It is the design or sub-design of integrated circuits, Figure 3 Includes an input port 4. The dotted rectangle represents the logic module 3. For example, the logic module 3 is the Figure 3 Any logic module in .

[0050] For example, after physically implementing the front-end netlist (e), the back-end netlist (f) is obtained. For example, during the physical implementation process, due to the limited top-level wiring resources of the integrated circuit, if two modules are not adjacent and have a logical connection relationship, they need to be connected. In this case, the connection line between the two modules generally needs to pass through other modules. In this case, the connection line between the two modules is called a feedthrough. For example, due to the feedthrough, input port 5 is added to module 3.

[0051] refer to Figure 1CIt can be seen that in the back-end netlist (f) generated by physically implementing the front-end netlist (e), a new input port is added to the logic module 3 to optimize the circuit. In other words, the part corresponding to the logic module 3 in the front-end netlist (e) and the part of the state elements corresponding to the logic module 3 in the back-end netlist (f) do not match.

[0052] It should be noted that Figure 1A-Figure 1C The schematic diagram shown here illustrates circuit connections, providing a more intuitive representation of the connections between components in the netlist. It does not represent the register transfer level description file or the netlist itself. Furthermore, the layout may include more logic modules and components, and a logic module may include more components, combinational logic, or input ports, without limitation in this disclosure.

[0053] according to Figure 1A-Figure 1C As can be seen, because the state elements at the logic module level change after physical synthesis, the register transfer level description file and the back-end netlist do not match at the logic module level. Therefore, the automatic engineering modification tool will determine that the logic module level is not equivalent, making it impossible to use the automatic engineering modification tool to perform module-level engineering modifications on the digital circuit.

[0054] However, the increasing scale of integrated circuit designs, with layouts potentially containing millions of gate-level components, poses significant challenges to engineering modification tools. In practice, modifications often require modifying a single or several logic modules, but current engineering modification tools are unable to perform module-level engineering modifications.

[0055] At least one embodiment of the present disclosure provides a digital circuit design method, a digital circuit design apparatus, an electronic device, and a non-transitory computer-readable storage medium. The digital circuit design method includes: determining at least one target logic module in at least one sub-design that requires engineering modification; performing engineering modification processing on each target logic module; wherein the engineering modification processing includes: determining the difference between the target logic module before and after physical implementation; based on the difference, reconstructing the target logic module to obtain a reconstructed logic module, wherein the reconstructed logic module matches the state elements in the target logic module; and performing engineering modification on the reconstructed logic module to obtain a modified logic module.

[0056] The digital circuit design method provided by at least one embodiment of the present disclosure reconstructs a logic module so that the reconstructed logic module matches the state elements in the target logic module. Afterwards, any engineering modification tool can be used to perform engineering modification on the modified logic module to achieve module-level engineering modification. Engineering modification is no longer subject to design restrictions, greatly improving the efficiency of engineering modification and accelerating project development progress.

[0057] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0058] Figure 2 A schematic flowchart of a digital circuit design method provided in at least one embodiment of the present disclosure.

[0059] For example, a digital circuit can be a large-scale integrated circuit (LSI). For example, an integrated circuit can be designed using a hierarchical design approach. For example, the integrated circuit includes at least one sub-design (layout), each sub-design includes at least one logic module, and each sub-design is individually laid out and routed. For example, each sub-design, and even each logic module, can be designed and developed in parallel, with each module implementing a specific function.

[0060] For example, Figure 2 As shown, the digital circuit design method provided by the embodiment of the present disclosure includes at least steps S10 to S20.

[0061] In step S10 , at least one target logic module requiring engineering modification in at least one sub-design is determined.

[0062] For example, as mentioned above, after layout and routing, timing closure, etc. are completed, designers find that there are problems with the circuit that need to be modified. Based on the problem location, one or more logic modules that need engineering modification are selected as target logic modules.

[0063] In step S20, an engineering modification process is performed on each target logic module.

[0064] Figure 3 A schematic flowchart of an engineering modification process provided for at least one embodiment of the present disclosure.

[0065] For example, Figure 3 As shown, the program modification process provided by the embodiment of the present disclosure includes at least steps S201 to S203.

[0066] In step S201 , the difference between the target logic module before and after physical implementation is determined.

[0067] For example, step S201 may include: obtaining a front-end netlist and a first back-end netlist corresponding to the target sub-design where the target logic module is located; determining that the portion corresponding to the target logic module in the front-end netlist is the module front-end netlist, and determining that the portion corresponding to the target logic module in the first back-end netlist is the first module back-end netlist; comparing the module front-end netlist and the first module back-end netlist to determine the state elements added to the first module back-end netlist relative to the module front-end netlist, and using the added state elements as the difference.

[0068] For example, a state element includes an input port.

[0069] For example, if the target logic module is Figure 1A As shown in the logic module 1, the target sub-design is layout 1, the front-end netlist can be the front-end netlist (a), and the first back-end netlist can be the back-end netlist (b).

[0070] For example, the portion corresponding to logic module 1 is extracted from the front-end netlist (a) as the module front-end netlist, and the portion corresponding to logic module 1 is extracted from the back-end netlist (b) as the first module back-end netlist.

[0071] For example, Figure 1A As shown, at the logic module 1 level, some state elements are added to the back-end netlist (b) relative to the front-end netlist (a). For example, the added state elements include input port 1_1 and input port 1_2. Therefore, input port 1_1 and input port 1_2 are used as the difference between logic module 1 before and after physical implementation.

[0072] For example, if the target logic module is Figure 1B The target sub-design is the logic module 2 shown in the figure. Figure 2 , the front-end netlist may be the front-end netlist (c), and the first back-end netlist may be the back-end netlist (d).

[0073] For example, the portion corresponding to the logic module 2 is extracted from the front-end netlist (c) as the module front-end netlist, and the portion corresponding to the logic module 2 is extracted from the back-end netlist (d) as the first module back-end netlist.

[0074] For example, Figure 1B As shown, at the logic module 2 level, the back-end netlist (d) adds some state elements relative to the front-end netlist (c). For example, the added state elements include input port 3_1 and input port 3_2. Therefore, input port 3_1 and input port 3_2 are used as the difference between logic module 2 before and after physical implementation.

[0075] In step S202 , based on the differences, the target logic module is reconstructed to obtain a reconstructed logic module.

[0076] For example, the reconstructed logic module matches the state elements in the target logic module.

[0077] For example, in the design method of digital circuits provided in the present disclosure, the additional state elements added to the first back-end netlist due to physical implementation relative to the front-end netlist are captured, and the first module back-end netlist is rebuilt to obtain the second module back-end netlist, so that all state elements in the second module back-end netlist that requires engineering modification match those in the module front-end netlist.

[0078] For example, step S202 may include: modifying the state elements in the backend netlist of the first module based on the difference to obtain the backend netlist of the second module corresponding to the reconstructed logic module. For example, the backend netlist of the second module has a one-to-one mapping relationship with the state elements in the frontend netlist of the module.

[0079] For example, based on the difference, modifying the state elements in the back-end netlist of the first module to obtain the back-end netlist of the second module corresponding to the reconstructed logic module may include: removing the added state elements in the back-end netlist of the first module; modifying the connection relationship of the devices connected to the added state elements to obtain the back-end netlist of the second module.

[0080] For example, when the state element includes an input port, removing the state element added in the back-end netlist of the first module may include: removing the input port newly added in the back-end netlist of the first module relative to the front-end netlist of the module.

[0081] For example, modifying the connection relationship of the devices connected to the added state element to obtain the second module back-end netlist can include: determining at least one reserved input port in the first module back-end netlist that has the same interface definition as the newly added input port; connecting the devices connected to the added state element in the first module back-end netlist to the corresponding reserved input ports to obtain the second module back-end netlist; wherein, in the second module back-end netlist and the module front-end netlist, the number of input ports of the target logic module and the interface definition of the corresponding input ports are exactly the same.

[0082] For example, typically during the physical implementation process, considering factors such as circuit physical characteristics and timing convergence, at the logic module level, the back-end netlist of the first module will add some input ports and corresponding physical cross-links relative to the front-end netlist of the module to achieve better layout effects or timing states. In at least one embodiment of the present disclosure, these added input ports are removed, and the corresponding connection relationships of these input ports are modified, for example, connecting the devices connected to these newly added input ports to the reserved input ports, so that the number and definition of the input ports in the back-end netlist of the second module are exactly the same as the number and definition of the input ports in the front-end netlist of the module, and the input ports of the two have a one-to-one mapping relationship.

[0083] It should be noted that, in the present disclosure, the reserved input ports refer to the input ports that originally exist in the module front-end netlist. During the physical implementation process, input ports corresponding to the reserved input ports are added due to factors such as timing convergence. These newly added input ports receive the same or corresponding input signals as the reserved input ports. By adding these input ports corresponding to the reserved input ports, for example, the driving capability of the circuit can be improved.

[0084] The input ports of the second module backend netlist obtained by the digital circuit analysis method provided in at least one embodiment of the present disclosure match the input ports of the module frontend netlist, that is, the input ports of the two have a one-to-one mapping relationship, thereby achieving logical equivalence at the module granularity. Subsequently, because the input ports of the second module backend netlist now match the input ports of the module frontend netlist, an engineering modification tool can be used to automatically perform engineering modifications on the second module backend netlist, achieving engineering modifications at the module granularity, significantly reducing the processing scope of engineering modifications, and improving the efficiency of engineering modifications.

[0085] In step S203 , engineering modification is performed on the reconstructed logic module to obtain a modified logic module.

[0086] For example, step S203 may include: performing engineering modification on the reconstructed logic module using an engineering modification tool to obtain an intermediate logic module; and performing recovery processing on the intermediate logic module to obtain a modified logic module.

[0087] For example, the register transfer level description file corresponding to the reconstructed logic module, the backend netlist of the second module, the register transfer level description file corresponding to the intermediate logic module, and the backend netlist of the third module corresponding to the intermediate logic module are equivalent to each other.

[0088] For example, the register transfer level description file corresponding to the reconstructed logic module here is the aforementioned old RTL, the back-end netlist of the second module is the aforementioned old netlist, the register transfer level description file corresponding to the logic module after engineering modification is the aforementioned new RTL, and the back-end netlist of the third module corresponding to the intermediate logic module is the aforementioned new netlist. The old RTL, old netlist, new RTL and new netlist satisfy logical equivalence.

[0089] For example, restoring the intermediate logic module to obtain a modified logic module may include: based on the difference, restoring the backend netlist of the third module corresponding to the intermediate logic module to obtain a backend netlist of the fourth module. Here, the backend netlist of the fourth module matches all state elements in the backend netlist of the first module.

[0090] For example, when the state element includes an input port, based on the difference, the third module back-end netlist corresponding to the intermediate logic module is restored to obtain the fourth module back-end netlist, which may include: based on the difference, determining the input port added to the first module back-end netlist relative to the module front-end netlist; adding the added input port to the third module back-end netlist; determining at least one device in the first module back-end netlist connected to the added input port; determining at least one device corresponding to the at least one device in the third module back-end netlist as a device to be restored; and restoring the connection relationship of the device to be restored in the third module back-end netlist to the state in the first module back-end netlist to obtain the fourth module back-end netlist.

[0091] For example, the number and connection relationship of the input ports in the back-end netlist of the third module are restored to the state in the back-end netlist of the first module, that is, the state after physical implementation, so that the number and connection relationship of the input ports in the back-end netlist of the fourth module are the same as those in the back-end netlist of the first module, and the corresponding engineering modifications have been completed in the back-end netlist of the fourth module, thereby obtaining the back-end netlist of the fourth module which is equivalent to the engineering modification of the back-end netlist of the first module.

[0092] For example, the integrated circuit design method provided by at least one embodiment of the present disclosure is capable of performing the aforementioned engineering modification processing on at least one logic module in parallel. Since current engineering modification tools can only perform engineering modifications at the layout level, when it is necessary to perform engineering modifications on multiple logic modules belonging to the same level in a design or sub-design, these engineering modifications cannot be processed in parallel, and engineering modifications can only be performed on these multiple logic modules one by one. The integrated circuit design method provided by the present disclosure is capable of realizing engineering modifications at the module granularity, so that engineering modification processing can be performed on multiple logic modules belonging to the same level in parallel, further improving the efficiency of engineering modifications, reducing the time spent on engineering modifications, and accelerating project progress.

[0093] For example, after performing engineering modifications, the results of the engineering modifications can be further verified from the layout layer.

[0094] For example, Figure 2 As shown, the integrated circuit design method provided by at least one embodiment of the present disclosure further includes step S30.

[0095] In step S30 : Based on the modified logic module, formal equivalence verification is performed on the target sub-design.

[0096] For example, step S30 may include: updating the first module back-end netlist in the first back-end netlist corresponding to the target sub-design to the fourth module back-end netlist corresponding to the modified logic module to obtain a second back-end netlist; obtaining the register transfer level description file corresponding to the target sub-design after engineering modification, and performing formal equivalence verification based on the register transfer level description file and the second back-end netlist.

[0097] For example, formal equivalence verification is performed based on the second back-end netlist, the register transfer level description file corresponding to the target sub-design after engineering modification, the front-end netlist, and the register transfer level description file corresponding to the original target sub-design to confirm whether they are all equivalent. If these four files are all equivalent to each other, it means that the engineering modification is correct.

[0098] For example, when multiple logic modules in the target sub-design need to undergo engineering modifications, the multiple logic modules can all be used as target logic modules, and the aforementioned engineering modification processing can be performed on the multiple target logic modules in parallel, that is, executing steps S201-S203 to obtain multiple fourth module back-end netlists corresponding to the multiple target logic modules.

[0099] Afterwards, the multiple first module backend netlists corresponding to the multiple target logic modules in the first backend netlist corresponding to the target sub-design are updated to the corresponding fourth module backend netlist to obtain a second backend netlist, and equivalence verification at the layout level is performed based on the second backend netlist.

[0100] The integrated circuit design method provided by at least one embodiment of the present disclosure is capable of realizing engineering modifications at the module granularity and performing formal verification at the layout level on the target sub-design where each modified logic module is located to further confirm the correctness of the modification, thereby improving the correctness of the engineering modification and minimizing the progress risk of project development.

[0101] The following describes in detail the execution process of the integrated circuit design method provided by at least one embodiment of the present disclosure with reference to the accompanying drawings.

[0102] For example, take the target logic module as Figure 1A The logic module 1 shown is illustrated, the target sub-design is layout 1, the front-end netlist is the front-end netlist (a), and the first back-end netlist is the back-end netlist (b) as an example for explanation.

[0103] First, in step S10 , logic module 1 is determined to be a target logic module.

[0104] Afterwards, in step S20 , an engineering modification process is performed on the logic module 1 .

[0105] For example, when performing engineering modification processing on the logic module 1, first in step S201, the input port 1_1 and the input port 1_2 are used as the difference between the logic module 1 before and after physical implementation.

[0106] For example, in step S202, the back-end netlist of the second module corresponding to the reconstructed logic module is obtained. Figure 4A A schematic diagram of the back-end netlist of the second module provided in one embodiment of the present disclosure.

[0107] like Figure 4A As shown, the newly added input port 1_1 and input port 1_2 are removed from the second back-end netlist, and the connection relationship between the buffer 1_1 connected to the newly added input port 1_1 and the buffer 1_2 connected to the newly added input port 1_2 is modified.

[0108] For example, reference Figure 1AInput port 1 is a reserved input port. In the physical implementation process, in order to ensure that each clock signal can be transmitted to the register it drives in the shortest possible time, input port 1_1 and input port 1_2 corresponding to input port 1 are added to the back-end netlist (b), and corresponding physical string lines are added to establish a connection between the clock input end of register 1 and input port 1_1, and the clock input end of register 2 and input port 1_2, so as to optimize the clock tree.

[0109] For example, Figure 4A As shown, in the back-end netlist of the second module, both buffer 1_1 and buffer 1_2 are connected to the reserved input port, that is, input port 1, so that Figure 4A The second module backend netlist shown is the same as Figure 1A The input ports of the portion corresponding to logic module 1 in the front-end netlist (a) shown match, that is, both have only one input port 1.

[0110] For example, Figure 4A As shown, the connection of the buffer connected to the input port 1_1 and the input port 1_2 in the layout 1 is in a disconnected state, but since the engineering modification tool performs engineering modification on the logic module 1, the disconnection in the layout 1 will not affect the execution of the engineering modification.

[0111] For example, in step S203, the engineering modification tool is first used to perform engineering modification on the back-end netlist of the second module to obtain the back-end netlist of the third module corresponding to the intermediate logic module; then the back-end netlist of the third module is restored to obtain the back-end netlist of the fourth module corresponding to the modified logic module.

[0112] For example, Figure 4B A schematic diagram of a back-end netlist of a third module provided in an embodiment of the present disclosure, Figure 4C A schematic diagram of the back-end netlist of the fourth module provided in an embodiment of the present disclosure.

[0113] like Figure 4B As shown, the third module backend netlist has been modified relative to the second module backend netlist, for example, Figure 4B It is represented by ECO in .

[0114] like Figure 4C As shown, the input port of the fourth module back-end netlist has been restored to the first module back-end netlist ( Figure 1A Specifically, add input port 1_1 and input port 1_2 to the back-end netlist of the third module, that is, Figure 4CThe input port 1_1' and the input port 1_2' are shown; the buffer 1_1 and the buffer 1_2 are used as the devices to be restored, and according to the connection relationship in the back-end netlist of the first module, the buffer 1_1 is connected to the input port 1_1', and the buffer 1_2 is connected to the input port 1_2' to obtain the back-end netlist of the fourth module.

[0115] In addition, in the fourth module backend netlist, the buffers corresponding to the two buffers connected to input port 1_1 and input port 1_2 in backend netlist (b) also restore the connection relationship with the newly added input port 1_1 ′ and input port 1_2 ′.

[0116] like Figure 4C As shown, the input port in the back-end netlist of the fourth module matches the input port in the back-end netlist of the first module (the part corresponding to the logic module 1 in the back-end netlist (b)), that is, the input port 1 in the back-end netlist of the fourth module corresponds to the input port 1 in the back-end netlist of the first module, the input port 1_1' in the back-end netlist of the fourth module corresponds to the input port 1_1 in the back-end netlist of the first module, and the input port 1_2' in the back-end netlist of the fourth module corresponds to the input port 1_2 in the back-end netlist of the first module, and engineering modifications have been made in the back-end netlist of the fourth module.

[0117] Thereafter, in step S30 , formal equivalence verification is performed on the target sub-design based on the back-end netlist of the fourth module corresponding to the modified logic module.

[0118] For example, the second back-end netlist is as follows Figure 4C As shown, the portion corresponding to the logic module 1 in the second back-end netlist is the fourth module back-end netlist. Figure 4C The second back-end netlist shown, the register transfer level description file corresponding to the target sub-design after engineering modification, the front-end netlist (a), and the register transfer level description file corresponding to the original target sub-design are formally verified for equivalence to confirm whether they are still equivalent at the layout level.

[0119] It should be noted that Figure 1A-Figure 1C same, Figures 4A-4C The schematic diagram shown also shows the circuit connection relationship, which represents the connection relationship of the components in the netlist in a more intuitive way. It does not represent the register transfer level description file and the netlist itself.

[0120] Corresponding to the above-mentioned digital circuit design method, at least one embodiment of the present disclosure further provides a digital circuit design device. Figure 5A A schematic block diagram of a digital circuit design device provided in at least one embodiment of the present disclosure.

[0121] For example, Figure 5AAs shown, the digital circuit design device 500 at least includes: a determination unit 501 and an execution unit 502 .

[0122] The determining unit 501 is configured to determine at least one target logic module in at least one sub-design that requires engineering modification.

[0123] The execution unit 502 is configured to perform an engineering modification process on each target logic module.

[0124] Figure 5B A schematic block diagram of an execution unit provided in at least one embodiment of the present disclosure.

[0125] For example, Figure 5B As shown, the execution unit 502 includes a difference determination subunit 5021 , a reconstruction subunit 5022 and an engineering modification subunit 5023 .

[0126] The difference determining subunit 5021 is configured to determine the difference between the target logic module before and after physical implementation.

[0127] The reconstruction subunit 5022 is configured to reconstruct the target logic module based on the distinction to obtain a reconstructed logic module, wherein the reconstructed logic module matches the state element in the target logic module.

[0128] The engineering modification subunit 5023 is configured to perform engineering modification on the reconstructed logic module to obtain a modified logic module.

[0129] For example, when the difference determination sub-unit 5021 performs determination of the difference between the target logic module before and after physical implementation, it includes performing the following operations: obtaining the front-end netlist and the first back-end netlist corresponding to the target sub-design where the target logic module is located; determining the part corresponding to the target logic module in the front-end netlist as the module front-end netlist, and determining the part corresponding to the target logic module in the first back-end netlist as the first module back-end netlist; comparing the module front-end netlist and the first module back-end netlist to determine the state elements added to the first module back-end netlist relative to the module front-end netlist, and using the added state elements as the difference.

[0130] For example, the reconstruction sub-unit 5022 performs reconstruction on the target logic module based on the difference to obtain the reconstructed logic module, including performing the following operations: based on the difference, modifying the state elements in the back-end netlist of the first module to obtain the back-end netlist of the second module corresponding to the reconstructed logic module, wherein the state elements in the back-end netlist of the second module and the front-end netlist of the module have a one-to-one mapping relationship.

[0131] For example, when the reconstruction sub-unit 5022 performs modification of the state elements in the back-end netlist of the first module based on the difference to obtain the back-end netlist of the second module corresponding to the reconstructed logic module, it includes performing the following operations: removing the added state elements in the back-end netlist of the first module; modifying the connection relationship of the devices connected to the added state elements to obtain the back-end netlist of the second module.

[0132] For example, when the reconstruction subunit 5022 removes the state elements added in the backend netlist of the first module, the following operations are performed: removing the input ports newly added in the backend netlist of the first module relative to the frontend netlist of the module.

[0133] When the reconstruction sub-unit 5022 performs modification of the connection relationship of the devices connected to the added state element to obtain the second module back-end netlist, it includes the following operations: determining at least one reserved input port in the first module back-end netlist that has the same interface definition as the newly added input port; connecting the devices connected to the added state element in the first module back-end netlist to the corresponding reserved input ports to obtain the second module back-end netlist; wherein, in the second module back-end netlist and the module front-end netlist, the number of input ports of the target logic module and the interface definition of the corresponding input ports are exactly the same.

[0134] For example, when the engineering modification sub-unit 5023 performs engineering modification on the reconstructed logic module to obtain a modified logic module, it includes performing the following operations: using an engineering modification tool to perform engineering modification on the reconstructed logic module to obtain an intermediate logic module, wherein the register transfer level description file corresponding to the intermediate logic module, the back-end netlist of the second module, the register transfer level description file corresponding to the intermediate logic module, and the back-end netlist of the third module corresponding to the intermediate logic module are equivalent to each other; and restoring the intermediate logic module to obtain a modified logic module.

[0135] For example, when the engineering modification sub-unit 5023 performs recovery processing on the intermediate logic module to obtain the modified logic module, it can include the following operations: based on the difference, the back-end netlist of the third module is restored to obtain the back-end netlist of the fourth module corresponding to the modified logic module, wherein the back-end netlist of the fourth module matches all state elements in the back-end netlist of the first module.

[0136] For example, when the engineering modification sub-unit 5023 performs recovery processing on the third module back-end netlist corresponding to the intermediate logic module based on the difference to obtain the fourth module back-end netlist corresponding to the modified logic module, it can include the following operations: based on the difference, determining the input port added to the first module back-end netlist relative to the module front-end netlist; adding the added input port to the third module back-end netlist; determining at least one device in the first module back-end netlist connected to the added input port; determining at least one device corresponding to the at least one device in the third module back-end netlist as the device to be restored; restoring the connection relationship of the device to be restored in the third module back-end netlist to the state in the first module back-end netlist to obtain the fourth module back-end netlist.

[0137] For example, Figure 5A As shown, the digital circuit design device 500 may further include a verification unit 503 .

[0138] For example, the verification unit 503 is configured to perform formal equivalence verification on the target sub-design based on the modified logic module.

[0139] For example, when the verification unit 503 performs formal equivalence verification on the target sub-design based on the modified logic module, it includes performing the following operations: updating the first module back-end netlist in the first back-end netlist corresponding to the target sub-design to the fourth module back-end netlist corresponding to the modified logic module to obtain a second back-end netlist; obtaining the register transfer level description file corresponding to the target sub-design after engineering modification, and performing formal equivalence verification based on the register transfer level description file and the second back-end netlist.

[0140] For example, the determination unit 501, the execution unit 502, and the verification unit 503 include codes and programs stored in a memory; the processor can execute the codes and programs to implement some or all of the functions of the determination unit 501, the execution unit 502, and the verification unit 503 described above. For example, the determination unit 501, the execution unit 502, and the verification unit 503 can be dedicated hardware devices used to implement some or all of the functions of the determination unit 501, the execution unit 502, and the verification unit 503 described above. For example, the determination unit 501, the execution unit 502, and the verification unit 503 can be a circuit board or a combination of multiple circuit boards used to implement the functions described above. In an embodiment of the present application, the circuit board or the combination of multiple circuit boards may include: (1) one or more processors; (2) one or more non-temporary memories connected to the processor; and (3) firmware stored in the memory that can be executed by the processor.

[0141] It should be noted that the determining unit 501 is used to implement Figure 2 In step S10 shown, the execution unit 502 is used to implement Figure 2In step S20 shown, the verification unit 503 is used to implement Figure 2 Therefore, the specific description of the determination unit 501 can refer to the embodiment of the above-mentioned digital circuit design method. Figure 2 The description of step S10 shown in FIG. 5 and the specific description of the execution unit 502 can refer to the embodiment of the digital circuit design method described above. Figure 2 The relevant description of step S20 shown in FIG. 5 and the specific description of the verification unit 503 can be referred to in the embodiment of the design method of the digital circuit described above. Figure 2 The relevant description of step S30 is shown.

[0142] The distinguishing determination subunit 5021 is used to implement Figure 3 In step S201 shown, the reconstruction subunit 5022 is used to implement Figure 3 In step S202 shown, the engineering modification subunit 5023 is used to implement Figure 3 The step S203 shown. Therefore, the specific description of the distinguishing determination subunit 5021 can refer to the embodiment of the design method of the digital circuit described above. Figure 3 The description of step S201 shown in FIG. 5 and the detailed description of the reconstruction subunit 5022 can be referred to in the embodiment of the above-mentioned digital circuit design method. Figure 3 The description of step S202 shown in FIG. 5 and the specific description of the engineering modification subunit 5023 can be referred to in the embodiment of the digital circuit design method described above. Figure 3 The relevant description of step S203 is shown.

[0143] In addition, the digital circuit design device can achieve technical effects similar to the aforementioned digital circuit design method, which will not be described in detail here.

[0144] At least one embodiment of the present disclosure further provides an electronic device, Figure 6 A schematic block diagram of an electronic device provided in accordance with at least one embodiment of the present disclosure.

[0145] For example, Figure 6 As shown, the electronic device includes a processor 1001, a communication interface 1002, a memory 1003, and a communication bus 1004. The processor 1001, the communication interface 1002, and the memory 1003 communicate with each other via the communication bus 1004. The processor 1001, the communication interface 1002, the memory 1003, and other components can also communicate with each other via a network connection. The present disclosure does not limit the type and function of the network.

[0146] For example, the memory 1003 is configured to non-transiently store computer-executable instructions. When the processor 1001 is configured to execute the computer-executable instructions, the computer-executable instructions are executed by the processor 1001 to implement the digital circuit design method according to any of the above-described embodiments. The specific implementation and related explanations of each step of the digital circuit design method can be found in the above-described embodiments of the digital circuit design method and are not further described here.

[0147] For example, the implementation manner in which the processor 1001 executes the program stored in the memory 1003 to implement the digital circuit design method is the same as the implementation manner mentioned in the embodiment of the digital circuit design method, and will not be repeated here.

[0148] For example, the communication bus 1004 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industrial Standard Architecture (EISA) bus. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is used in the figure, but this does not mean that there is only one bus or only one type of bus.

[0149] For example, the communication interface 1002 is used to implement communication between the electronic device and other devices.

[0150] For example, the processor 1001 can control other components in the electronic device to perform desired functions. The processor 1001 can be a central processing unit (CPU), a network processor (NP), etc., and can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. The central processing unit (CPU) can be an X86 or ARM architecture, etc.

[0151] For example, the memory 1003 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, etc. One or more computer-executable instructions may be stored on the computer-readable storage medium, and the processor 1001 may execute the computer-executable instructions to implement various functions of the electronic device. Various applications and various data may also be stored in the storage medium.

[0152] For example, for a detailed description of the process of executing the design of a digital circuit by an electronic device, reference may be made to the relevant description in the embodiment of the method for designing a digital circuit, and repeated parts will not be repeated.

[0153] Figure 7 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. Figure 7 As shown, one or more computer-executable instructions 1101 may be non-transitory stored on the storage medium 1100. For example, when the computer-executable instructions 1101 are executed by a processor, one or more steps in the digital circuit design method described above may be performed.

[0154] For example, the storage medium 1100 may be applied to the aforementioned electronic device and / or digital circuit design apparatus 1400. For example, the storage medium 1100 may include the memory 1003 in the electronic device.

[0155] For example, the description of the storage medium 1100 may refer to the description of the memory in the embodiment of the electronic device, and the repeated parts will be omitted.

[0156] Regarding this disclosure, the following points need to be explained:

[0157] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0158] (2) For the sake of clarity, the thickness and size of layers or structures in the drawings used to describe the embodiments of the present invention are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0159] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0160] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A method for designing a digital circuit, wherein: The digital circuit includes at least one sub-design, each sub-design includes at least one logic module, and each sub-design is individually placed and routed. The design method includes: determining at least one target logic module requiring engineering modification in the at least one sub-design; Perform engineering modification processing on each target logic module; The engineering modification process includes: Determining the difference between the target logic module before and after physical implementation; Based on the difference, reconstructing the target logic module to obtain a reconstructed logic module, wherein the reconstructed logic module matches a state element in the target logic module, and the state element includes an input port; Perform engineering modification on the reconstructed logic module to obtain a modified logic module.

2. The design method according to claim 1, wherein: Determining the difference between the target logic module before and after physical implementation includes: Obtaining a front-end netlist and a first back-end netlist corresponding to the target sub-design where the target logic module is located; Determine that the portion corresponding to the target logic module in the front-end netlist is a module front-end netlist, and determine that the portion corresponding to the target logic module in the first back-end netlist is a first module back-end netlist; The module front-end netlist and the first module back-end netlist are compared to determine the state elements added to the first module back-end netlist relative to the module front-end netlist, and the added state elements are used as the difference.

3. The design method according to claim 2, wherein: Based on the difference, the target logic module is reconstructed to obtain a reconstructed logic module, including: Based on the difference, the state elements in the back-end netlist of the first module are modified to obtain the back-end netlist of the second module corresponding to the reconstructed logic module, wherein the back-end netlist of the second module has a one-to-one mapping relationship with the state elements in the front-end netlist of the module.

4. The design method according to claim 3, wherein: Based on the difference, modifying the state elements in the backend netlist of the first module to obtain the backend netlist of the second module corresponding to the reconstructed logic module includes: Remove the added state element in the back-end netlist of the first module; Modify the connection relationship of the devices connected to the added state element to obtain the second module back-end netlist.

5. The design method according to claim 4, wherein: Removing the added state element in the back-end netlist of the first module includes: The input port newly added to the back-end netlist of the first module relative to the front-end netlist of the module is removed.

6. The design method according to claim 5, wherein: Modifying the connection relationship of the devices connected to the added state element to obtain the second module back-end netlist includes: Determine at least one reserved input port in the back-end netlist of the first module that has the same interface definition as the newly added input port; Connecting the devices connected to the added state elements in the first module backend netlist to the corresponding reserved input ports to obtain the second module backend netlist; Among them, in the second module backend netlist and the module frontend netlist, the number of input ports of the target logic module and the interface definitions of the corresponding input ports are exactly the same.

7. The design method according to claim 3, wherein: Performing engineering modification on the reconstructed logic module to obtain a modified logic module, including: Performing engineering modification on the reconstructed logic module using an engineering modification tool to obtain an intermediate logic module, wherein a register transfer level description file corresponding to the intermediate logic module, a back-end netlist of the second module, a register transfer level description file corresponding to the intermediate logic module, and a back-end netlist of the third module corresponding to the intermediate logic module are pairwise equivalent; The intermediate logic module is restored to obtain the modified logic module.

8. The design method according to claim 7, wherein: Restoring the intermediate logic module to obtain the modified logic module includes: Based on the difference, the third module backend netlist is restored to obtain a fourth module backend netlist corresponding to the modified logic module, wherein the fourth module backend netlist matches all state elements in the first module backend netlist.

9. The design method according to claim 8, wherein: Based on the difference, restoring the third module backend netlist corresponding to the intermediate logic module to obtain a fourth module backend netlist corresponding to the modified logic module, including: Based on the difference, determining an input port added to the back-end netlist of the first module relative to the front-end netlist of the module; Adding the added input port to the third module backend netlist; Determine at least one device connected to the added input port in the back-end netlist of the first module; Determine at least one device corresponding to the at least one device in the back-end netlist of the third module as a device to be restored; The connection relationship of the components to be restored in the third module back-end netlist is restored to the state in the first module back-end netlist to obtain the fourth module back-end netlist.

10. The design method according to claim 2, further comprising: Performing formal equivalence verification on the target sub-design based on the modified logic module.

11. The design method according to claim 10, wherein: Performing formal equivalence verification on the target sub-design based on the modified logic module includes: Updating the first module backend netlist in the first backend netlist corresponding to the target sub-design to the fourth module backend netlist corresponding to the modified logic module to obtain a second backend netlist; Obtain a register transfer level description file corresponding to the target sub-design after the engineering modification, and perform formal equivalence verification based on the register transfer level description file and the second back-end netlist.

12. The design method according to any one of claims 1-4, 5-7, wherein: The engineering modification process is performed on the at least one logic module in parallel.

13. A digital circuit design device, wherein: The digital circuit includes at least one sub-design, each sub-design includes at least one logic module, and each sub-design is individually placed and routed. The design device comprises: a determining unit configured to determine at least one target logic module requiring engineering modification in the at least one sub-design; an execution unit configured to perform an engineering modification process on each target logic module; The engineering modification process includes: Determining the difference between the target logic module before and after physical implementation; Based on the difference, reconstructing the target logic module to obtain a reconstructed logic module, wherein the reconstructed logic module matches a state element in the target logic module, and the state element includes an input port; Perform engineering modification on the reconstructed logic module to obtain a modified logic module.

14. An electronic device comprising: a memory that non-transitorily stores computer-executable instructions; a processor configured to execute the computer-executable instructions, Wherein, when the computer executable instructions are executed by the processor, the digital circuit design method according to any one of claims 1 to 12 is implemented.

15. A non-transitory computer-readable storage medium, wherein: The non-transitory computer-readable storage medium stores computer-executable instructions, When the computer executable instructions are executed by a processor, the method for designing a digital circuit according to any one of claims 1 to 12 is implemented.

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