FPGA wiring method and system based on hybrid granularity tearing and rerouting

Abstract

The present invention discloses an FPGA wiring method and system based on hybrid granularity tearing and rerouting. The method counts the amount of wiring resource overflow on the current wiring path of the current network. When the wiring resource overflow is not zero, each congested wiring resource is traversed. When any congested wiring resource is not simultaneously located in multiple sub-paths, the number of sub-paths K' containing congested wiring resources in the K sub-paths of the current network is counted. When the number of sub-paths K' is greater than 1 / 2 of the number of sub-paths K of the current network, all paths of the current network are cleared and re-pathed in a coarse-grained manner. When the number of sub-paths K' is less than or equal to 1 / 2 of the number of sub-paths K of the current network, the sub-paths of the K' sub-paths are cleared and re-pathed in a fine-grained manner. The above steps are repeated to continue processing the next network. This effectively reduces the overall time consumption of the wiring process, thereby accelerating the FPGA development and design process.

Description

Technical Field

[0001] The present invention belongs to the field of electronic technology, and in particular relates to an FPGA wiring method and system based on hybrid granularity tearing and rerouting. Background Art

[0002] Field Programmable Gate Arrays (FPGAs) use reconfigurable technology to address the limited flexibility of Application Specific Integrated Circuits (ASICs), which often rely on fixed hardware functionality after tape-out. Consequently, FPGAs are used in embedded systems where hardware is expensive and requires frequent upgrades or functional changes. They are widely used in aerospace, large medical devices, autonomous vehicles, and the Internet of Things.

[0003] The general process of FPGA development is: developers design hardware in an integrated development environment, such as Xilinx's ISE, VIVADO and other tools. Figure 1 Develop a flowchart for the FPGA. After completing high-level synthesis, static simulation, layout, routing, and timing simulation, the tool generates an FPGA configuration binary file. After transferring it to the target chip, it is powered on and the contents of the file are read to solidify the configuration, ensuring the normal operation of the FPGA function.

[0004] FPGA chip technology has been continuously improving in recent years, leading to increased integration and a growing number of on-chip resources. This has led to increasing complexity in FPGA hardware design, and consequently, increased time consumption for high-level synthesis, placement, and routing within the FPGA development process. For example, routing tasks involving tens of thousands of nets using the existing PathFinder routing algorithm, widely used in industry and academia, often take hours.

[0005] With the rapid development of FPGAs in data centers, edge computing, and AI training clusters, tasks configured on FPGAs are rapidly iterating to meet the computational demands of real-time tasks. Because FPGAs rely on their configuration files to execute specific tasks, developers must redesign circuits and repeat the FPGA development process multiple times when algorithms or tasks are updated. The current compilation and development process, which can take several hours, severely impacts the timeliness of FPGA applications.

[0006] In several development processes, wiring is one of the most time-consuming links. Therefore, optimizing the wiring process has become a research hotspot. Many researchers have also proposed some methods to improve wiring efficiency, such as redesigning the wiring sequence of the wire network and optimizing the single-source shortest path algorithm used in wiring. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to address the deficiencies in the above-mentioned prior art and provide an FPGA wiring method and system based on hybrid granularity tearing and rerouting, so as to solve the technical problem that the wiring link in the current FPGA development process consumes too much time.

[0008] The present invention adopts the following technical solutions:

[0009] An FPGA routing method based on hybrid granularity tearing and rerouting includes the following steps:

[0010] Count the amount of routing resource overflow on the current routing path of the current net. When the routing resource overflow is not zero, traverse each congested routing resource. When any congested routing resource is not located in multiple sub-paths at the same time, count the number K' of sub-paths containing congested routing resources in the K sub-paths of the current net. When the number of sub-paths K' is greater than 1 / 2 of the number of sub-paths K of the current net, clear all paths and re-path the current net in a coarse-grained manner. When the number of sub-paths K' is less than or equal to 1 / 2 of the number of sub-paths K of the current net, clear and re-path the K' sub-paths in turn in a fine-grained manner. Repeat the above steps to continue processing the next net.

[0011] Specifically, the current routing path is the path obtained in the previous round of routing.

[0012] Specifically, when the wiring resource overflow amount is 0, the subsequent wiring process of the current line net is exited and the wiring process of the next line net is entered.

[0013] Specifically, after traversing each congested routing resource, when a congested routing resource is simultaneously located on multiple sub-paths of the current network, all paths of the current network are cleared and re-pathed in a coarse-grained manner, and then the routing process of the next network is entered.

[0014] Furthermore, the rerouting operation includes increasing or decreasing the number of times related wiring resources are used.

[0015] Specifically, the sub-path clearing and re-pathing operations are performed on the K' sub-paths in a fine-grained manner as follows:

[0016] When there is a congested node on the path of the network, only the path from the source node to the sink node using the corresponding congested node is cleared, and the source-sink node pair is rerouted.

[0017] Furthermore, the fine-grained approach only performs path clearing and rerouting operations on the paths between source-sink pairs containing congested nodes.

[0018] In a second aspect, an embodiment of the present invention provides an FPGA routing system based on hybrid granularity tearing and rerouting, comprising:

[0019] Statistics module, which counts the amount of wiring resource overflow on the current wiring path of the current network;

[0020] The traversal module, when the routing resource overflow obtained by the statistical module is not 0, traverses each congested routing resource. When any congested routing resource is not located in multiple sub-paths at the same time, counts the number K' of sub-paths containing congested routing resources in the K sub-paths of the current network.

[0021] The coarse-grained module clears all paths and re-paths the current network in a coarse-grained manner when the number of sub-paths K' obtained by the traversal module is greater than 1 / 2 of the number of sub-paths K of the current network.

[0022] The fine-grained module, when the number of sub-paths K' obtained by the traversal module is less than or equal to 1 / 2 of the number of sub-paths K of the current network, performs sub-path clearing and re-pathing operations on the K' sub-paths in a fine-grained manner, and then processes the next network.

[0023] In a third aspect, a computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned FPGA wiring method based on hybrid granularity tearing and rerouting when executing the computer program.

[0024] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, comprising a computer program, which, when executed by a processor, implements the steps of the above-mentioned FPGA wiring method based on hybrid granularity tearing and rerouting.

[0025] Compared with the prior art, the present invention has at least the following beneficial effects:

[0026] The present invention provides an FPGA wiring method based on hybrid granularity tearing and rerouting. The method counts the wiring resource overflow of the current line network and the number K' of sub-paths containing congested wiring resources. The current line network will select an appropriate tearing and rerouting granularity based on the relative size of K' to reduce the time overhead of the overall wiring process.

[0027] Furthermore, the paths of each round of routing are based on the paths obtained in the previous round of routing, so that the resource congestion information of the previous round of routing can be used to guide the tear rerouting in the current round of routing.

[0028] Furthermore, when the routing resource overflow is 0, the subsequent routing process of the current net is exited and the routing process of the next net is entered, which can avoid meaningless tearing and rerouting operations and reduce routing time overhead.

[0029] Furthermore, after traversing each congested routing resource, when a congested routing resource is simultaneously located on multiple sub-paths of the current network, all paths of the current network are cleared and re-pathed in a coarse-grained manner, and then the routing process of the next network is entered. In this way, the granularity of the tearing and rerouting that should be adopted for the network can be quickly determined based on the congestion characteristics of the network.

[0030] Furthermore, the rerouting operation includes increasing and decreasing the number of times the relevant wiring resources are used, so that the usage of the wiring resources can be updated in a timely manner and the wiring of subsequent lines can be guided.

[0031] Furthermore, fine-grained methods can reduce the number of redundant path tearing and rerouting operations for source-sink pairs. However, the additional operation of dividing paths into public and non-public components also increases the tearing and rerouting time for individual source-sink pairs. If the time cost of tearing and rerouting a network is defined as T = n * t, where n is the number of source-sink pairs that need tearing and rerouting, and t is the time it takes to tear and reroute a single source-sink pair, the fine-grained method reduces n but increases t compared to the coarse-grained method.

[0032] Furthermore, a fine-grained approach only performs path clearing and rerouting operations on the paths between source-sink node pairs containing congested nodes, which can accurately clear congested points on the routing path to reduce meaningless routing operations.

[0033] It can be understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

[0034] In summary, the present invention effectively reduces the overall time consumption of the wiring process and accelerates the FPGA development and design process.

[0035] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 Develop flow charts for FPGA;

[0037] Figure 2 This is a schematic diagram for wiring a network with three junctions;

[0038] Figure 3Schematic diagram of rerouting, where (a) is the current coarse-grained tearing rerouting and (b) is the fine-grained tearing rerouting proposed in the present invention;

[0039] Figure 4 This is a schematic diagram when the congested node is located on the public path;

[0040] Figure 5 This is a schematic diagram when multiple sub-paths contain congested nodes. DETAILED DESCRIPTION

[0041] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0042] In the description of the present invention, it is to be understood that the terms “include” and “comprise” indicate the presence of the described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or collections thereof.

[0043] It should also be understood that the terms used in the present specification are only for the purpose of describing particular embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0044] It should be further understood that the term "and / or" as used in the present specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items. For example, A and / or B may represent: A alone, A and B simultaneously, or B alone. In addition, the character " / " herein generally indicates that the associated items are in an "or" relationship.

[0045] It should be understood that although the terms "first," "second," and "third" may be used to describe preset ranges in embodiments of the present invention, these preset ranges should not be limited to these terms. These terms are merely used to distinguish one preset range from another. For example, without departing from the scope of embodiments of the present invention, the first preset range may also be referred to as the second preset range, and similarly, the second preset range may also be referred to as the first preset range.

[0046] The word "if," as used herein, may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to the determination" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)," depending on the context.

[0047] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments disclosed herein. These figures are not drawn to scale; for clarity, some details are exaggerated and some details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0048] The present invention provides an FPGA wiring method based on hybrid granularity tearing rerouting. First, based on the coarse-grained tearing rerouting method commonly used in industry and academia, a fine-grained tearing rerouting method without redundant operations is proposed; then, in order to reduce the overall wiring time, a hybrid granularity scheduling method is proposed. Different granularity tearing rerouting methods are used for wire networks with different congestion characteristics, effectively reducing the overall wiring time and thereby accelerating the FPGA development and design process.

[0049] See also Figure 2 , FPGA wiring is specifically as follows:

[0050] Find the paths from the source nodes in all the wire nets to be routed to all the sink nodes in the wire net. Figure 2 This is a schematic diagram of wiring a line network with 3 junctions.

[0051] Available wiring resources refer to the area that is not occupied by other wire nets and can be used for wiring;

[0052] Unavailable resources refer to areas where routing paths cannot pass through, such as registers;

[0053] A wiring path refers to the path for signal transmission between source and sink nodes; a common path refers to a path composed of wiring resources shared between multiple source and sink node paths in a network.

[0054] The tear rerouting is as follows:

[0055] In the new round of routing iterations, it is detected that the number of times some routing resources (nodes) were used in the previous round of iterations exceeds the maximum number of wire nets that the node can bear. Therefore, it is necessary to clear the paths and re-find the paths for the wire nets that use these routing resources (congested nodes).

[0056] It should be noted that although the routing resources on the common path (the path indicated by the slash in the figure) are shared by multiple source-to-sink paths, because they belong to the same wiring network, this part of the routing resources is still considered to be used only once by the network.

[0057] The tear rerouting in the current routing algorithm is coarse-grained, that is, when there are congested nodes on the path of the network, all paths of the network are cleared and then the path from the source node to each sink node is re-searched. Figure 3 (a) is a schematic diagram of the current coarse-grained tear rerouting. The specific steps are: first, all paths in the network are cleared, and then the paths from the source to each sink are found separately. The disadvantage is that excessive repetitive calculations will increase the routing time.

[0058] In order to minimize the overall routing time and considering the characteristics of network congestion, the present invention provides an FPGA routing method based on hybrid granularity tearing and rerouting, comprising the following steps:

[0059] S1. Count the amount of wiring resource overflow on the current wiring path of the current line network;

[0060] The path obtained in the previous round of routing is used as the current routing path.

[0061] The overflow of wiring resources represents the number of wiring resources that have exceeded the limit.

[0062] S2. When the wiring resource overflow amount obtained in step S1 is 0, exit the subsequent wiring process of the current net and enter the wiring process of the next net. If the wiring resource overflow amount obtained in step S1 is not 0, enter step S3.

[0063] S3. Traverse all congested routing resources. If a congested routing resource is located on multiple sub-paths of the current net, clear all paths and re-path the current net in a common coarse-grained manner, and then proceed to the routing process for the next net. If no congested routing resource is located on multiple sub-paths, proceed to step S4.

[0064] Congested routing resources are routing resources whose usage times exceed the limit; subpaths are paths from source nodes to various sink nodes; and rerouting operations include increasing or decreasing the usage times of related routing resources.

[0065] S4. Count the number K' of sub-paths containing congested wiring resources in the K sub-paths of the current network;

[0066] The K sub-paths are paths from the source node to the K sink nodes, and the congested routing resources are routing resources that have been used more times than the limit.

[0067] S5. When the number of sub-paths K' obtained in step S4 is greater than 1 / 2 of the number of sub-paths K in the current network, all paths in the current network are cleared and re-pathed in a coarse-grained manner. When the number of sub-paths K' obtained in step S4 is less than or equal to 1 / 2 of the number of sub-paths K in the current network, sub-path clearing and re-pathing are performed on the K' sub-paths in sequence in a fine-grained manner.

[0068] The fine-grained tear rerouting algorithm is as follows:

[0069] When a congested node is included in the path of the network, only the path from the source node to the sink node that uses the congested node is cleared, and the source-sink node pair is rerouted.

[0070] Figure 3 (b) is a schematic diagram of the fine-grained tear rerouting proposed by the present invention. Figure 3 In (b), the path from the source point to the sink point k3 is cleared first, and then the path from the source point to the sink point k3 is found again.

[0071] Figure 3 (a) and Figure 3 (b) shows the same congested node, which is represented by a dark solid circle and is located on the path from the source node to the sink node k3.

[0072] The pseudo code of fine-grained tearing rerouting is as follows:

[0073]

[0074]

[0075] Among them, the third line quickly determines whether the j-th network in Nets contains a congested node. If not, it jumps out of this loop and directly enters the next loop to process the j+1-th network;

[0076] Line 6 obtains the set ConSinks of all sinks containing congested nodes on the path in the network Nets[j-1] according to the function CongestedSinks;

[0077] Line 7 checks whether the number of elements in ConSinks is greater than 0. If it is greater than 0, it loops to clear the path for each sink in ConSinks and searches for a new path (lines 8-11).

[0078] When clearing the path of a sink in ConSinks in line 9, it is necessary to first divide the path into two parts: the public path and the non-public path, and then reduce the number of times the routing resource usage on the non-public path by one;

[0079] Line 14 indicates that after completing one iteration, it is determined whether the number of congested nodes on the paths of all the nets is 0. If it is 0, it indicates that the routing is completed and the loop iteration process can be exited.

[0080] The fine-grained method only clears and reroutes the paths between source-sink node pairs containing congested nodes, and no longer clears and reroutes the paths in the network that are not affected by congested nodes, which will greatly reduce the time overhead of a single routing iteration.

[0081] S6. After step S5 is completed, repeat the above steps to continue processing the next line network.

[0082] The pseudo code of the FPGA wiring method based on hybrid granularity tearing and rerouting of the present invention is as follows:

[0083]

[0084]

[0085]

[0086] Among them, the third line determines whether the current line network is congested. If it is not congested, the routing process of the current line network is skipped and the routing process of the next line network is directly entered;

[0087] Line 6 sets a Bool variable ifcoarse. The default value is False, which means the current network is rerouted in a fine-grained manner. If it is True, it means the current network is rerouted in a coarse-grained manner.

[0088] Lines 7-12 determine in a loop whether each congested node in the current network belongs to the common path of the current network. Once a congested node is found to belong to the common path of the current network, ifcoarse is set to True and the loop is exited immediately.

[0089] See also Figure 4 If the congested nodes represented by the dark-colored nodes are located on a common path, the network will be judged as suitable for coarse-grained tear rerouting when the pseudocode executes lines 7-12. Line 15 checks whether the number of blocked sink nodes in the current network is greater than 1 / 2 of the total number of sinks (1 / 2 is an empirical value that is suitable for most routing scenarios). If so, ifcoarse is set to True.

[0090] See also Figure 5 If there is a congested node (represented by a dark solid circle) on the path leading to sinks k1 and k3, the network will be determined to be suitable for coarse-grained tear rerouting when the pseudo code executes lines 13-18. Lines 19-23 select the corresponding granularity for tear rerouting based on the value of ifcoarse.

[0091] In another embodiment of the present invention, an FPGA wiring system based on hybrid granularity tearing rerouting is provided. The system can be used to implement the above-mentioned FPGA wiring method based on hybrid granularity tearing rerouting. Specifically, the FPGA wiring system based on hybrid granularity tearing rerouting includes a statistical module, a traversal module, a coarse-grained module and a fine-grained module.

[0092] Among them, the statistical module counts the wiring resource overflow on the current wiring path of the current line network;

[0093] The traversal module, when the routing resource overflow obtained by the statistical module is not 0, traverses each congested routing resource. When any congested routing resource is not located in multiple sub-paths at the same time, counts the number K' of sub-paths containing congested routing resources in the K sub-paths of the current network.

[0094] The coarse-grained module clears all paths and re-paths the current network in a coarse-grained manner when the number of sub-paths K' obtained by the traversal module is greater than 1 / 2 of the number of sub-paths K of the current network.

[0095] The fine-grained module, when the number of sub-paths K' obtained by the traversal module is less than or equal to 1 / 2 of the number of sub-paths K of the current network, performs sub-path clearing and re-pathing operations on the K' sub-paths in a fine-grained manner, and then processes the next network.

[0096] In another embodiment of the present invention, a terminal device is provided, which includes a processor and a memory, wherein the memory is used to store a computer program, the computer program includes program instructions, and the processor is used to execute the program instructions stored in the computer storage medium. The processor may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. It is the computing core and control core of the terminal, which is suitable for implementing one or more instructions, specifically suitable for loading and executing one or more instructions to implement the corresponding method flow or corresponding function; the processor described in the embodiment of the present invention can be used for the operation of the FPGA wiring method based on hybrid granularity tearing and rerouting, including:

[0097] Count the amount of routing resource overflow on the current routing path of the current net. When the routing resource overflow is not zero, traverse each congested routing resource. When any congested routing resource is not located in multiple sub-paths at the same time, count the number K' of sub-paths containing congested routing resources in the K sub-paths of the current net. When the number of sub-paths K' is greater than 1 / 2 of the number of sub-paths K of the current net, clear all paths and re-path the current net in a coarse-grained manner. When the number of sub-paths K' is less than or equal to 1 / 2 of the number of sub-paths K of the current net, clear and re-path the K' sub-paths in turn in a fine-grained manner. Repeat the above steps to continue processing the next net.

[0098] In another embodiment of the present invention, the present invention further provides a storage medium, specifically a computer-readable storage medium (Memory), which is a memory device in a terminal device for storing programs and data. It can be understood that the computer-readable storage medium here can include both the built-in storage medium in the terminal device and, of course, the extended storage medium supported by the terminal device. The computer-readable storage medium provides a storage space, which stores the operating system of the terminal. In addition, one or more instructions suitable for being loaded and executed by the processor are also stored in the storage space. These instructions can be one or more computer programs (including program codes). It should be noted that the computer-readable storage medium here can be a high-speed RAM memory or a non-volatile memory (Non-Volatile Memory), such as at least one disk memory.

[0099] The processor may load and execute one or more instructions stored in a computer-readable storage medium to implement the corresponding steps of the FPGA routing method based on hybrid granularity tearing and rerouting in the above embodiment; the processor may load and execute the following steps:

[0100] Count the amount of routing resource overflow on the current routing path of the current net. When the routing resource overflow is not zero, traverse each congested routing resource. When any congested routing resource is not located in multiple sub-paths at the same time, count the number K' of sub-paths containing congested routing resources in the K sub-paths of the current net. When the number of sub-paths K' is greater than 1 / 2 of the number of sub-paths K of the current net, clear all paths and re-path the current net in a coarse-grained manner. When the number of sub-paths K' is less than or equal to 1 / 2 of the number of sub-paths K of the current net, clear and re-path the K' sub-paths in turn in a fine-grained manner. Repeat the above steps to continue processing the next net.

[0101] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0102] Simulation experiment

[0103] In the experimental environment of the present invention, an Intel(R) Core(TM) i7-4790@3.60GHz CPU, 12GB DDR4 memory, and Ubuntu 18.04 operating system were used to conduct a comparative experiment using a dataset with wiring congestion provided by the universal wiring platform VTR. The experimental results are shown in Table 1.

[0104] Table 1

[0105]

[0106] The data in Table 1 show that the hybrid granularity tearing rerouting method proposed in this invention can effectively reduce the number of iterations required to reduce the number of congested nodes to 0. The total routing time is reduced by 20% compared with the traditional PathFinder method, and the average single-round iteration time is reduced by 14%. In addition, the number of routing resources used is roughly the same as that of the PathFinder method or even lower, while ensuring the correctness of the routing results.

[0107] In summary, the present invention presents an FPGA wiring method and system based on hybrid-granularity tear rerouting. First, a fine-grained tear rerouting method is proposed. Compared with traditional coarse-grained tear rerouting methods, it can more efficiently resolve network congestion issues. Furthermore, different tear rerouting methods with different granularities are selected for different networks based on their congestion characteristics, minimizing the time overhead of the wiring process. Simulation experiments have preliminarily verified that the present invention can reduce wiring time overhead while ensuring wiring quality, significantly accelerating the FPGA development and design process.

[0108] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0109] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0110] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0111] In the embodiments provided by the present invention, it should be understood that the disclosed devices / terminals and methods can be implemented in other ways. For example, the device / terminal embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical functional division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interface, indirect coupling or communication connection of devices or units, and can be electrical, mechanical, or other forms.

[0112] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0113] In addition, the functional units in the various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0114] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention implements all or part of the process in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, it can implement the steps of the above-mentioned various method embodiments. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium, etc. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals.

[0115] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0116] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0117] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0118] The above content is only for explaining the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. An FPGA wiring method based on hybrid granularity tearing and rerouting, characterized in that: The following steps are involved: Count the wiring resource overflow on the current wiring path of the current line network; When the routing resource overflow is not 0, traverse each congested routing resource. When any congested routing resource is not located in multiple sub-paths at the same time, count the number of sub-paths K' containing congested routing resources in the K sub-paths of the current network. When the number of sub-paths K' is greater than 1 / 2 of the number of sub-paths K in the current network, all paths in the current network are cleared and re-pathed in a coarse-grained manner; When the number of sub-paths K' is less than or equal to 1 / 2 of the number of sub-paths K of the current network, the sub-paths are cleared and re-pathed in a fine-grained manner for the K' sub-paths, and the above steps are repeated to continue processing the next network.

2. The FPGA wiring method based on hybrid granularity tearing and rerouting according to claim 1 is characterized in that: The current routing path is the path obtained in the previous round of routing.

3. The FPGA wiring method based on hybrid granularity tearing and rerouting according to claim 1, characterized in that: When the wiring resource overflow is 0, the subsequent wiring process of the current line net is exited and the wiring process of the next line net is entered.

4. The FPGA wiring method based on hybrid granularity tearing and rerouting according to claim 1, characterized in that: After traversing each congested routing resource, when a congested routing resource is simultaneously located on multiple sub-paths of the current net, all paths of the current net are cleared and re-pathed in a coarse-grained manner, and then the routing process of the next net is entered.

5. The FPGA wiring method based on hybrid granularity tearing and rerouting according to claim 4, characterized in that: The rerouting operation includes increasing or decreasing the number of times related routing resources are used.

6. The FPGA wiring method based on hybrid granularity tearing and rerouting according to claim 1, characterized in that: The sub-path clearing and re-pathing operations are performed on K' sub-paths in a fine-grained manner as follows: When there is a congested node on the path of the network, only the path from the source node to the sink node using the corresponding congested node is cleared, and the source-sink node pair is rerouted.

7. The FPGA wiring method based on hybrid granularity tearing and rerouting according to claim 6, characterized in that: The fine-grained approach only performs path clearing and re-routing operations on the paths between source-sink pairs containing congested nodes.

8. An FPGA routing system based on hybrid granularity tearing and rerouting, characterized in that: include: Statistics module, which counts the amount of wiring resource overflow on the current wiring path of the current network; The traversal module, when the routing resource overflow obtained by the statistical module is not 0, traverses each congested routing resource. When any congested routing resource is not located in multiple sub-paths at the same time, counts the number K' of sub-paths containing congested routing resources in the K sub-paths of the current network. The coarse-grained module clears all paths and re-paths the current network in a coarse-grained manner when the number of sub-paths K' obtained by the traversal module is greater than 1 / 2 of the number of sub-paths K of the current network. The fine-grained module, when the number of sub-paths K' obtained by the traversal module is less than or equal to 1 / 2 of the number of sub-paths K of the current network, performs sub-path clearing and re-pathing operations on the K' sub-paths in a fine-grained manner, and then processes the next network.

9. A computer-readable storage medium storing one or more programs, characterized in that: The one or more programs include instructions, which, when executed by a computing device, cause the computing device to perform the method of any one of claims 1 to 7.

10. A computing device, characterized in that include: One or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs include steps for executing the method according to any one of claims 1 to 7.

Images