Method for preparing semiconductor device and semiconductor device

Abstract

An embodiment of the present application discloses a method for preparing a semiconductor device, the method comprising: providing a substrate, the substrate comprising a storage array area, a plurality of bit lines formed on the storage array area, a first insulating material filled between the plurality of bit lines, the first insulating material having a plurality of grooves intersecting the bit lines; wherein the storage array area comprises an inner region and a boundary region outside the inner region; filling the grooves with a second insulating material to form a spacer line, the second insulating material is also deposited on the bit lines, the spacer line and the first insulating material to form a cap material layer; performing an etching process to form a node contact hole, comprising: etching the cap material layer to form a cap layer, the cap layer covering the bit lines, the spacer line and the first insulating material located in the boundary region; using the cap layer as a mask, etching and removing the first insulating material in the inner region to form a node contact hole.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a method for preparing a semiconductor device and a semiconductor device. Background Art

[0002] Due to the influence of the pattern load effect in the etching process, there is a certain difference between the pattern density of the boundary area of ​​the storage array area and the pattern density of the internal area, which makes the consistency of the node contact holes formed in the boundary area and the node contact holes formed in the internal area poor. Therefore, when forming the node contact holes, the prior art makes the node contact holes originally to be formed in the boundary area into virtual contact holes, which are not used as components of the circuit, thereby avoiding the problems caused by the poor consistency of the node contact holes.

[0003] However, the process flow of manufacturing node contact holes by using the above-mentioned prior art method is too complicated and the chip output efficiency is not high. Summary of the invention

[0004] In view of this, embodiments of the present application provide a method for manufacturing a semiconductor device and a semiconductor device to solve at least one problem existing in the background technology.

[0005] To achieve the above purpose, the technical solution of this application is implemented as follows:

[0006] An embodiment of the present application provides a method for manufacturing a semiconductor device, the method comprising: providing a substrate, the substrate comprising a storage array area, a plurality of bit lines formed on the storage array area, a first insulating material filled between the plurality of bit lines, the first insulating material having a plurality of grooves intersecting the bit lines; wherein the storage array area comprises an inner area and a boundary area outside the inner area;

[0007] Filling the groove with a second insulating material to form a spacer line, wherein the second insulating material is also deposited on the bit line, the spacer line and the first insulating material to form a cap material layer;

[0008] Perform an etching process to form a node contact hole, including: etching the cap material layer to form a cap layer, the cap layer covers the bit line, the spacer line and the first insulating material located in the boundary area; using the cap layer as a mask, etching and removing the first insulating material in the inner area to form the node contact hole.

[0009] In the above solution, the performing of the etching process includes: using a plasma etching device to perform the etching process.

[0010] In the above solution, before performing the etching process, the method further includes: forming a resist layer on the cap material layer in the boundary area.

[0011] In the above scheme, etching the capping material layer to form the capping layer includes: using the resist layer as a mask to etch and thin the capping material layer in the inner area so that a preset height difference is formed between the capping material layer in the inner area and the capping material layer in the boundary area; etching and removing the resist layer; continuing to etch the capping material layer to remove the bit lines, the spacer lines and the capping material layer above the first insulating material in the inner area, so as to form a capping layer covering the bit lines, the spacer lines and the first insulating material in the boundary area.

[0012] In the above scheme, the cap material layer is etched by an etching gas containing carbon fluoride; the resist layer is etched away by an etching gas containing oxygen; and the first insulating material in the inner area is etched away by an etching gas containing hydrogen fluoride and nitrogen trifluoride.

[0013] In the above solution, the preset height difference ranges from 6 to 10 nm.

[0014] In the above solution, the thickness of the cap material layer ranges from 12 to 20 nm.

[0015] In the above solution, the method further includes: filling the node contact hole with a conductive material to form a node contact plug.

[0016] The embodiment of the present application further provides a semiconductor device, the device comprising: a substrate, the substrate comprising a storage array area, the storage array area comprising an inner area and a boundary area outside the inner area;

[0017] A plurality of bit lines located in the memory array region;

[0018] A plurality of spacing lines are located in the storage array area and intersect with the plurality of bit lines to form a plurality of hole structures; wherein the hole structures located in the inner area are node contact holes;

[0019] A first insulating material is filled in the hole structure in the boundary area;

[0020] A capping layer covers the bit lines, the spacer lines and the first insulating material in the boundary area.

[0021] In the above solution, the first insulating material includes silicon oxide; and the material of the cap layer includes silicon nitride.

[0022] In the above solution, the thickness of the capping layer is between 6-10 nm.

[0023] In the above solution, the semiconductor device further comprises: a peripheral region, the peripheral region being adjacent to the boundary region of the memory array region;

[0024] The capping layer also covers the peripheral area.

[0025] In the above solution, the semiconductor device further comprises: a plurality of word lines buried in the substrate, wherein the word lines are located below the spacer lines.

[0026] In the above solution, the material of the spacer line is the same as the material of the cap layer.

[0027] In the above solution, the semiconductor device further comprises: a conductive material, wherein the conductive material is disposed in the node contact hole to form a node contact plug.

[0028] The method for preparing a semiconductor device and the semiconductor device provided in the embodiment of the present application, wherein the method comprises: providing a substrate, wherein the substrate comprises a storage array area, wherein a plurality of bit lines are formed on the storage array area, wherein a first insulating material is filled between the plurality of bit lines, wherein the first insulating material has a plurality of grooves intersecting the bit lines; wherein the storage array area comprises an inner area and a boundary area outside the inner area; wherein a second insulating material is filled in the groove to form a spacer line, wherein the second insulating material is also deposited on the bit line, the spacer line and the first insulating material to form a cap material layer; wherein an etching process is performed to form a node contact hole, comprising: etching the cap material layer to form a cap layer, wherein the cap layer covers the bit line, the spacer line and the first insulating material located in the boundary area; wherein the cap layer is used as a mask to etch and remove the first insulating material in the inner area to form the node contact hole. The embodiment of the present application optimizes the process flow of the node contact hole, so that the last step of etching to form the node contact hole can be completed in the same process and the same machine, which can save the machine procurement cost and improve the chip output efficiency.

[0029] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0031] Figure 1is a schematic top view of an exemplary semiconductor device;

[0032] Figure 2a-2d The semiconductor device is shown in FIG. Figure 1 Detailed cross-sectional view in the B1-B2 direction;

[0033] Figure 3 A flowchart of a method for preparing a semiconductor device according to an embodiment of the present application;

[0034] Figure 4 A schematic top view of a semiconductor device provided in an embodiment of the present application;

[0035] Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a , Fig.10a The semiconductor device provided in the embodiment of the present application is prepared along the Figure 4 A1-A2 direction detail section view, Figure 5b , Figure 6b , Figure 7b , Figure 8b , Figure 9b , Fig.10b The semiconductor device provided in the embodiment of the present application is prepared along the Figure 4 Detailed cross-sectional view in the B1-B2 direction; DETAILED DESCRIPTION

[0036] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.

[0037] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0038] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0039] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0040] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0041] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0042] In the process of forming semiconductor devices, such as memory, due to the influence of pattern loading effects in the etching process, there is a certain difference between the pattern density of the internal area of ​​the memory array area and the pattern density of the boundary area, resulting in poor consistency of the node contact holes finally formed in the internal area and the boundary area, affecting the electrical quality of the device.

[0043] To improve the consistency of node contact holes, refer to Figure 1-Figure 2d An exemplary method for preparing a semiconductor device is provided. When forming node contact holes, the node contact holes originally to be formed in the boundary area are made into virtual contact holes, which are not used as components of the circuit, thereby improving the consistency of the node contact holes. Figure 1 is a schematic top view of an exemplary semiconductor device, Figure 2a-2d The semiconductor device is shown in FIG. Figure 1 Detailed cross-sectional view along the B1-B2 direction.

[0044] First, if Figure 1 and Figure 2a As shown, a substrate 10 is provided, the substrate 10 includes a storage array area and a peripheral area, the storage array area includes an internal area and a boundary area; a plurality of bit lines 13 are formed in the storage array area; a first insulating material 18 is filled between the plurality of bit lines 13; a cap material layer 16 is also formed above the storage array area and the peripheral area.

[0045] Then, if Figure 2b As shown, an etching process is performed on the cap material layer 16 to form a cap layer 16a covering only the peripheral region.

[0046] Next, a resist material layer (not shown in the figure) is formed above the storage array area and the peripheral area, and the resist material layer (not shown in the figure) is trimmed to form a resist layer 19 located in the boundary area of ​​the storage array area and above the peripheral area. Figure 2c shown.

[0047] Then, the resist layer 19 is used as a mask to perform an etching process on the inner region of the storage array region to remove the first insulating material layer 18 in the inner region, so as to form a node contact hole 14 in the inner region. Figure 2c shown.

[0048] Finally, if Figure 2d As shown, the resist layer 19 is removed.

[0049] It can be seen that the first insulating material 18 in the boundary region of the storage array region is not removed, forming a virtual contact hole 14a.

[0050] However, when forming node contact holes, the preparation method of the above-mentioned exemplary semiconductor device needs to etch the cap material layer in a plasma etching device, form the resist layer in a coating device, a photolithography device, and a developing device, remove the first insulating material layer in a plasma etching device, and remove the resist layer in a wet cleaning device. That is, the preparation method of the above-mentioned exemplary semiconductor device needs to be performed and transferred in multiple devices, which increases the complexity of the process and reduces production efficiency.

[0051] Based on this, the following technical solutions of the embodiments of the present application are proposed.

[0052] The present invention provides a method for preparing a semiconductor device. Figure 3 As shown in the figure, the method includes the following steps:

[0053] Step 310: providing a substrate, the substrate comprising a storage array area, a plurality of bit lines formed on the storage array area, a first insulating material filled between the plurality of bit lines, the first insulating material having a plurality of grooves intersecting the bit lines; wherein the storage array area comprises an inner area and a boundary area outside the inner area;

[0054] Step 320: filling the trench with a second insulating material to form a spacer line, and the second insulating material is also deposited on the bit line, the spacer line and the first insulating material to form a cap material layer;

[0055] Step 330: Execute an etching process to form a node contact hole, including: etching the cap material layer to form a cap layer, wherein the cap layer covers the bit line, the spacer line and the first insulating material located in the boundary area; using the cap layer as a mask, etching and removing the first insulating material in the internal area to form the node contact hole.

[0056] The embodiment of the present application optimizes the process flow of node contact holes so that the final step of etching to form node contact holes can be completed in the same process and the same machine, which can save machine procurement costs and improve chip output efficiency.

[0057] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present application in detail, for the convenience of explanation, the schematic diagram will not be partially enlarged according to the general proportion, and the schematic diagram is only an example, which should not limit the scope of protection of the present application.

[0058] Figure 4 A schematic top view of a semiconductor device provided in an embodiment of the present application; Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a , Fig.10a The semiconductor device provided in the embodiment of the present application is prepared along the Figure 4 A1-A2 direction detail section view, Figure 5b , Figure 6b , Figure 7b , Figure 8b , Figure 9b , Fig.10b The semiconductor device provided in the embodiment of the present application is prepared along the Figure 4 Detailed cross-sectional view along the B1-B2 direction.

[0059] First, if Figure 4 , Figure 5a and Figure 5b As shown, step 310 is performed to provide a substrate 20, wherein the substrate 20 includes a storage array area, and the storage array area also includes an internal area and a boundary area outside the internal area. A plurality of bit lines 23 are formed on the storage array area, and a first insulating material 28 is filled between the plurality of bit lines 23. The first insulating material 28 includes, but is not limited to, materials such as silicon oxide.

[0060] The substrate 20 may further include a peripheral region adjacent to the memory array region.

[0061] Here, the substrate may be a semiconductor substrate; specifically, it may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In a specific embodiment, the substrate is a silicon substrate.

[0062] A plurality of active regions 201 are disposed in the substrate 20 , and insulating spacers 21 are filled between the plurality of active regions 201 , wherein the insulating spacers 21 include but are not limited to materials such as silicon oxide.

[0063] In one embodiment, the bit line 23 may include a polysilicon layer 231, an anti-diffusion barrier layer 232, and a metal layer 233 stacked in sequence from bottom to top. The material forming the anti-diffusion barrier layer 232 includes but is not limited to titanium nitride; the material forming the metal layer 233 includes but is not limited to metal tungsten, metal silicide, and tungsten nitride.

[0064] It should be understood that before forming the bit line 23 , a dielectric layer 22 may be formed on the substrate 20 . The dielectric layer 22 is used to electrically isolate the substrate 20 and other structures formed on the substrate 20 .

[0065] In the actual process, the bit line 23 may also include a bit line capping layer 234 located on the top of the metal layer 233 and a sidewall 235 covering the polysilicon layer 231, the anti-diffusion barrier layer 232, the metal layer 233 and the surface of the bit line capping layer 234. The bit line capping layer 234 and the sidewall 235 may be used to maintain electrical insulation between the polysilicon layer 231, the anti-diffusion barrier layer 232 and the metal layer 233 and other structures. Here, the material forming the bit line capping layer 234 and the sidewall 235 may be the same. Specifically, the material forming the bit line capping layer 234 and the sidewall 235 includes but is not limited to silicon nitride, silicon carbide, etc.

[0066] In some embodiments, the memory array area may further include a word line 27, which is buried in the substrate 20. The structure of the word line 27 includes a gate dielectric layer 271, a conductive layer 272, and a word line cap layer 273 stacked in sequence from bottom to top. The material forming the conductive layer 272 includes but is not limited to a polysilicon layer and a metal layer, and the material forming the metal layer includes but is not limited to metal tungsten, metal silicide, and tungsten nitride; the material forming the word line cap layer 273 may be the same as the material forming the bit line cap layer 234, which will not be described in detail here.

[0067] Continue to see Figure 5a The first insulating material 28 has a plurality of trenches 211 therein. In an actual process, the trenches 211 intersect the bit lines 23 and are located above the word lines 27.

[0068] Next, execute step 320, such as Figure 6a to Figure 6b As shown, the second insulating material is filled in the groove 211 to form a spacer line 274, and the second insulating material is also deposited on the bit line 23, the spacer line 274 and the first insulating material 28 to form a cap material layer 26. Optionally, the cap material layer 26 has a thickness ranging from 12nm to 20nm, for example, from 15nm to 18nm.

[0069] It is understood that the capping material layer 26 may also be deposited over the peripheral region.

[0070] The second insulating material includes but is not limited to silicon oxide, silicon nitride, silicon carbide, etc. In a specific embodiment, the second insulating material is silicon nitride.

[0071] The deposition process of the second insulating material includes, but is not limited to, a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, an atomic layer deposition (ALD) process, or a combination thereof.

[0072] At this point, the bit lines 23 and the spacer lines 274 intersect in the memory array region to define a region where the first insulating material 28 is located.

[0073] Continue to execute step 330, such as Figures 8a to 10b As shown, an etching process is performed to form a node contact hole 24, including: etching the cap material layer 26 to form a cap layer 26a, wherein the cap layer 26a is located above the bit line 23, the spacer line 274 and the first insulating material 28 in the boundary region, as shown in FIG. Figures 8a to 9b With the cap layer 26a as a mask, an etching process is performed on the first insulating material 28 to remove the first insulating material 28 in the inner region to form the node contact hole 24, as shown in FIG. Fig.10a and Fig.10b shown.

[0074] The first insulating material 28 in the boundary region of the storage array region is not removed, forming a virtual contact hole 24a.

[0075] In this step, the node contact holes are only formed in the internal area of ​​the storage array area. Since this area is less affected by the pattern loading effect (Pattern Loading Effects), the node contact holes formed have better consistency, which is conducive to the subsequent formation of semiconductor devices with good electrical quality. At the same time, this step can be performed in the same process and the same machine, which can save the cost of machine procurement and improve the output efficiency of the chip. In this embodiment, the same machine can be, for example, a plasma etching device. In other words, in the embodiment of the present application, the etching process of the cap material layer and the first insulating material is completed in a plasma etching device. It can be understood that when the etched materials are different, it is only necessary to change the type of etching gas introduced into the plasma etching device and optimize the etching parameters. For example, when the material of the cap material layer is silicon nitride and the first insulating material is silicon oxide, a gas containing carbon fluoride (CF 4 ) and argon (Ar) gas mixture to etch the cap material layer, using hydrogen fluoride (HF) and nitrogen trifluoride (NF 3 ) to remove the first insulating material.

[0076] In one embodiment, before performing the etching process, Figure 7a to Figure 7bAs shown, the method further includes: forming a resist layer 29 on the cap material layer 26 in the boundary region. Specifically, the resist layer 29 can be a photoresist layer. In some embodiments, the resist layer 29 is also formed on the peripheral region.

[0077] Combine the following Figures 8a to 9b , the formation process of the capping layer 26a is described in detail.

[0078] First, if Figure 8a to Figure 8b As shown, the resist layer 29 is used as a mask, and the cap material layer 26 located in the inner region is thinned by an etching process, so that the cap material layer 26 in the inner region and the border region forms a preset height difference h. Specifically, the cap material layer 26 is thinned by a plasma etching process. In a specific embodiment, a fluorinated carbon (CF 4 ) and argon (Ar) plasma etching gas to thin the cap material layer. Optionally, the carbon fluoride (CF 4 ) is 200 sccm, and the flow rate of argon is 400 sccm.

[0079] Then, if Figure 9a to Figure 9b As shown, the resist layer 29 is removed by etching. Specifically, the resist layer 29 is removed by a plasma etching process. In a specific embodiment, at a temperature of 200° C., a plasma etching process containing oxygen (O 2 ) plasma etching gas to remove the resist layer 29.

[0080] Then, the cap material layer 26 is further etched to remove the cap material layer 26 located above the bit line 23, the spacer line 274 and the first insulating material 28 in the inner region, so as to form a cap layer 26a covering the bit line 23, the spacer line 274 and the first insulating material 28 in the boundary region. Specifically, the cap material layer 26 is etched by a plasma etching process. In a specific embodiment, a fluorinated carbon (CF) is used. 4 ) and argon (Ar) plasma etching gas to form the cap material layer 26a. Optionally, the carbon fluoride (CF 4 ) is 200 sccm, and the flow rate of argon is 400 sccm.

[0081] It can be understood that after forming the cap layer 26a, the first insulating material 28 in the inner region is removed by using the cap layer 26a as a mask. Specifically, the first insulating material 28 is removed by using a plasma etching process. In a specific embodiment, a plasma etching process containing hydrogen fluoride (HF) and nitrogen trifluoride (NF 3) is used to remove the first insulating material 28.

[0082] In some embodiments, the preset height difference ranges from 6 nm to 10 nm, and the preset height difference can be used to ensure that the first insulating material 28 located in the boundary area is not exposed when the cap material layer is subsequently etched.

[0083] According to some embodiments, the method further includes: filling the node contact hole 24 with a conductive material to form a node contact plug. The conductive material for forming the node contact plug includes but is not limited to a polysilicon layer and a metal layer, and the material for forming the metal layer includes but is not limited to metal tungsten, metal silicide (such as TiSi 2 、CoSi 2 NISi 2 etc.) and tungsten nitride, etc.

[0084] In the step of etching to form node contact holes in the embodiment of the present application, the process of etching to remove the resist layer, etching to form the cap layer, and etching to form the node contact holes can be completed in the same machine and the same process. Therefore, the embodiment of the present application optimizes the process flow of forming node contact holes, improves the utilization rate of the machine, thereby saving the machine purchase cost, and can improve the output efficiency of the chip.

[0085] The present application also provides a semiconductor device, such as Figure 10a to Figure 10b As shown, the semiconductor device comprises:

[0086] A substrate 20, wherein the substrate 20 includes a storage array area, and the storage array area includes an inner area and a boundary area outside the inner area; a plurality of bit lines 23, located in the storage array area; a plurality of spacer lines 274, located in the storage array area and intersecting with the plurality of bit lines 23 to form a plurality of hole structures; wherein the hole structure located in the inner area is a node contact hole 24; a first insulating material 28, filled in the hole structure in the boundary area; and a cap layer 26a, covering the bit lines 23, the spacer lines 274 and the first insulating material 28 in the boundary area.

[0087] The first insulating material 28 is filled in the hole structure in the boundary area to form a virtual contact hole 24a. The first insulating material 28 includes but is not limited to silicon oxide and other materials. Optionally, the first insulating material 28 is silicon oxide.

[0088] According to some embodiments, the thickness of the cap layer 26a is between 6nm and 10nm. The material forming the cap layer 26a includes but is not limited to silicon oxide, silicon nitride, silicon carbide, etc. Specifically, the material is silicon nitride.

[0089] The presence of the cap layer 26a can protect the structure below it from damage and contamination in subsequent processes. In addition, the inner region will subsequently form a node contact plug and a landing pad located above the node contact plug. The presence of the cap layer 26a can reduce the height difference between the inner region and the boundary region, which is conducive to the stable execution of subsequent processes.

[0090] It should be understood that the material used to form the spacer line 274 can be the same as the material used to form the cap layer 26a, such as silicon oxide, silicon nitride, silicon carbide, etc. Optionally, the material is silicon nitride.

[0091] In the actual process, the formation of the cap layer 26a and the spacing line 274 can be formed using one or more thin film deposition processes; the multiple thin film deposition processes include but are not limited to chemical vapor deposition (CVD) process, plasma enhanced chemical vapor deposition (PECVD) process, atomic layer deposition (ALD) process or a combination thereof.

[0092] In addition, the semiconductor device further includes a peripheral region, and the peripheral region is adjacent to the boundary region of the memory array region. In actual processes, the cap layer 26a also covers the peripheral region.

[0093] The substrate 20 further includes a plurality of active regions 201 and insulating spacers 21 filled between the active regions 201 , wherein the insulating spacers 21 include but are not limited to materials such as silicon oxide.

[0094] refer to Fig.10b As shown, the bit line 23 may include a polysilicon layer 231, an anti-diffusion barrier layer 232 and a metal layer 233 stacked in sequence from bottom to top, wherein the material forming the anti-diffusion barrier layer 232 includes but is not limited to titanium nitride, etc.; the material forming the metal layer 233 includes but is not limited to metal tungsten, metal silicide and tungsten nitride, etc.

[0095] In some embodiments, the bit line 23 may further include a bit line capping layer 234 located on the top of the metal layer 233 and a sidewall 235 covering the polysilicon layer 231, the anti-diffusion barrier layer 232, the metal layer 233 and the bit line capping layer 234. The bit line capping layer 234 and the sidewall 235 may be used to maintain electrical insulation between the polysilicon layer 231, the anti-diffusion barrier layer 232 and the metal layer 233 and other structures. The material of the sidewall 235 includes but is not limited to silicon nitride, silicon carbide, etc.

[0096] It should be understood that a dielectric layer 22 is further formed between the bit line 23 and the substrate 20 , and the dielectric layer 22 is used to electrically isolate the bit line 23 from the substrate 20 .

[0097] In some embodiments, Fig.10a As shown, the semiconductor device may further include a word line 27, which is buried in the substrate 20 and is located below the spacer line 274. The word line 27 includes a gate dielectric layer 271, a conductive layer 272, and a word line cap layer 273 stacked in sequence from bottom to top, wherein the material forming the conductive layer 272 includes but is not limited to a polysilicon layer and a metal layer, and the material forming the metal layer includes but is not limited to metal tungsten, metal silicide, and tungsten nitride.

[0098] According to some embodiments, a conductive material may be disposed in the node contact hole 24 to form a node contact plug, and the node contact plug is used to realize the electrical connection between the information storage structure and the active area 201. The conductive material forming the node contact plug includes but is not limited to a polysilicon layer and a metal layer, and the material used to form the metal layer includes but is not limited to metal tungsten, metal silicide (e.g., TiSi 2 、CoSi 2 and NISi 2 etc.) and tungsten nitride, etc.

[0099] It should be noted that the method for preparing a semiconductor device provided in the embodiment of the present application can be applied to a DRAM structure or other semiconductor devices, and no further limitation is given here. The embodiment of the method for preparing a semiconductor device provided in the present application and the embodiment of the semiconductor device belong to the same concept; the technical features in the technical solutions recorded in the embodiments can be arbitrarily combined without conflict.

[0100] The above is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A method for preparing a semiconductor device, characterized in that: The method comprises: A substrate is provided, the substrate comprising a storage array area, a plurality of bit lines are formed on the storage array area, a first insulating material is filled between the plurality of bit lines, and the first insulating material has a plurality of grooves intersecting the bit lines; wherein the storage array area comprises an inner area and a boundary area outside the inner area; Filling the groove with a second insulating material to form a spacer line, wherein the second insulating material is also deposited on the bit line, the spacer line and the first insulating material to form a cap material layer; Perform an etching process to form a node contact hole, including: etching the cap material layer to form a cap layer, the cap layer covers the bit line, the spacer line and the first insulating material located in the boundary area; using the cap layer as a mask, etching and removing the first insulating material in the inner area to form the node contact hole.

2. The method according to claim 1, characterized in that The performing of the etching process includes: using a plasma etching device to perform the etching process.

3. The method according to claim 1, characterized in that Before performing the etching process, the method further includes: forming a resist layer on the cap material layer in the boundary area.

4. The method according to claim 3, characterized in that Etching the cap material layer to form a cap layer includes: using the resist layer as a mask to etch and thin the cap material layer in the inner area so that a preset height difference is formed between the cap material layer in the inner area and the cap material layer in the boundary area; etching and removing the resist layer; continuing to etch the cap material layer to remove the bit lines, the spacer lines and the cap material layer above the first insulating material in the inner area, so as to form a cap layer covering the bit lines, the spacer lines and the first insulating material in the boundary area.

5. The method according to claim 4, characterized in that The cap material layer is etched by using an etching gas containing carbon fluoride; the resist layer is etched away by using an etching gas containing oxygen; and the first insulating material in the inner region is etched away by using an etching gas containing hydrogen fluoride and nitrogen trifluoride.

6. The method according to claim 4, characterized in that The preset height difference ranges from 6 to 10 nm.

7. The method according to claim 1, characterized in that The thickness of the cap material layer is in the range of 12-20 nm.

8. The method according to claim 1, characterized in that The method further includes: filling the node contact hole with a conductive material to form a node contact plug.

9. A semiconductor device, characterized in that: include: A substrate, the substrate comprising a storage array area, the storage array area comprising an inner area and a boundary area outside the inner area; A plurality of bit lines located in the memory array region; A plurality of spacing lines are located in the storage array area and intersect with the plurality of bit lines to form a plurality of hole structures; wherein the hole structures located in the inner area are node contact holes; A first insulating material is filled in the hole structure in the boundary area; A capping layer covers the bit line, the spacer line and the first insulating material in the boundary area.

10. The semiconductor device according to claim 9, characterized in that The first insulating material includes silicon oxide; and the material of the capping layer includes silicon nitride.

11. The semiconductor device according to claim 9, characterized in that The thickness of the capping layer is between 6-10 nm.

12. The semiconductor device according to claim 9, characterized in that The semiconductor device further includes: a peripheral region, the peripheral region being adjacent to the boundary region of the memory array region; The capping layer also covers the peripheral area.

13. The semiconductor device according to claim 9, wherein: The semiconductor device further includes: a plurality of word lines buried in the substrate, wherein the word lines are located below the spacer lines.

14. The semiconductor device according to claim 9, characterized in that The material of the spacer line is the same as that of the cap layer.

15. The semiconductor device according to claim 9, wherein: The semiconductor device further includes a conductive material disposed in the node contact hole to form a node contact plug.

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