A digital back-end calibration system for Pipeline ADCs
By introducing an inverse hyperbolic tangent function and a feedback control function to optimize the step size in the Pipeline ADC, the accuracy degradation problem caused by inter-stage gain error in the Pipeline ADC is solved, achieving high convergence speed and high calibration accuracy digital back-end calibration, which is suitable for multi-carrier cellular infrastructure base stations and backhaul receivers.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHONGQING UNIV OF POSTS & TELECOMM
- Filing Date
- 2023-01-17
- Publication Date
- 2026-06-30
AI Technical Summary
Existing Pipeline ADCs suffer from accuracy degradation at high precision levels due to issues such as inter-stage gain error and capacitor mismatch. Traditional digital back-end calibration techniques struggle to simultaneously meet the requirements of high convergence speed and low steady-state error, and also suffer from random noise interference and insignificant calibration effects.
The nonlinear relationship between step size and error is established by using the inverse hyperbolic tangent function. The step size is updated in real time by combining the feedback control function and the normalization algorithm. The nonlinear relationship is introduced into the LMS adaptive filter to optimize the step size factor and improve the convergence speed and stability.
This technology increases the effective number of bits in the Pipeline ADC, accelerates convergence speed, improves calibration accuracy, automatically tracks nonlinear errors, and ensures that the real-time calibration process does not affect the original ADC conversion, thus significantly improving system performance.
Smart Images

Figure CN116054829B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of analog integrated circuit design technology, and specifically relates to a digital back-end calibration technology for Pipeline ADCs. Background Technology
[0002] Pipeline analog-to-digital converters (ADCs) achieve a balance between power consumption, speed, and accuracy, maintaining a certain level of precision while maintaining a high sampling rate. They are widely used in various high-speed, high-precision applications, such as multi-carrier cellular infrastructure base stations and backhaul receivers. However, when the accuracy of a pipeline ADC exceeds 12 bits, inter-stage gain errors caused by capacitor mismatch and limited operational amplifier gain become the main factors limiting ADC performance. The continuous decrease in CMOS process size and voltage also makes it difficult for traditional analog circuits to overcome bottlenecks and achieve high-performance design specifications. In recent years, digital calibration technology has become a research hotspot due to its high flexibility and the fact that it does not introduce additional analog circuit modules. Front-end calibration requires interrupting the normal operation of the ADC and cannot monitor the effects of parameter changes in real time. In contrast, back-end calibration allows the conversion and calibration processes to be performed simultaneously, offering significant advantages.
[0003] Digital calibration typically requires adaptive filtering algorithms. Among several adaptive filtering algorithms, the LMS algorithm introduced by Widrow and Hoff uses the squared error instead of the mean square error to find the minimum gradient. It does not require calculating the correlation matrix or the inverse matrix, and has significant advantages such as simplicity, high efficiency, and good performance under various operating conditions, thus being widely used in ADC digital calibration. Back-end calibration techniques usually use fixed-step LMS algorithms, which cannot simultaneously meet the requirements of high convergence speed and low steady-state error. Generally, variable-step LMS algorithms are based on the Sigmoid function to adjust and optimize the filtering step size, but it is difficult to balance convergence speed and steady-state misalignment, resulting in less than ideal calibration effects. Traditional digital back-end calibration techniques for pipelined ADCs use variable-step LMS algorithms, such as the Sign Variable-Step LMS algorithm (SVSS-LMS) and its system, which introduces a sign function (sign) to update the step size factor u(n), thereby enabling faster weight updates based on error. The algorithm has the following technical shortcomings: First, the step size in the iterative formula for the first long factor is only related to the current error, ignoring the influence of the error from the previous iteration. This limits its practicality and introduces some random noise interference. Second, the algorithm does not perform special processing on the update method of the filter weighting coefficients, which makes the step size curve change too slowly during the steady-state convergence phase in low signal-to-noise ratio environments, slowing down the convergence speed. Third, if the iteration increment is too large, the tap weight coefficients will oscillate repeatedly around the optimal value, slowing down the convergence speed and significantly reducing the calibration effect. An application example of this algorithm uses a 12-bit 100MS / s pipelined ADC. After calibration, the effective bit depth of the ADC reaches 11.52 bits, and the SFDR is 82.77dB.
[0004] This invention utilizes the inverse hyperbolic tangent function to establish a nonlinear relationship between step size and error, enabling real-time step size updates based on the error signal magnitude. Furthermore, by introducing a feedback control function into the original algorithm model, This makes the current step size correlated with the square of the current error and the previous error, greatly improving the convergence speed. It not only maintains the advantages of the original algorithm but also makes its performance more stable. To prevent the algorithm from diverging due to a sudden increase in input signal power, a normalization algorithm is added to limit u(n) when updating the weight coefficient vector. The increased step size selection range results in higher stability. This algorithm application example uses a 14-bit, 1GS / s pipelined ADC. After calibration, the effective bit depth of the ADC reaches 13.65 bits, with an SFDR of 85.49dB. Compared to the variable step size LMS algorithm with sign function, it has the following advantages:
[0005] 1) Fast convergence speed, can instantly change the step size, can determine the relationship between two adjacent step sizes, avoid the situation where the error is not zero or the step size factor is already zero or close to zero during the step size iteration process, so that the step size of the iteration at adjacent time moments is within a controllable range, and at the same time accelerates the convergence speed.
[0006] 2) High calibration accuracy: The algorithm of this invention has a more significant effect on improving the performance of the ADC system and the calibration effect is more obvious.
[0007] 3) Background calibration: The calibration process and the original ADC conversion process can be performed simultaneously without interruption, and can be calibrated in real time as the environment changes.
[0008] 4) It can automatically track nonlinear errors such as comparator misalignment and clock jitter, in addition to capacitor mismatch and operational amplifier limited gain.
[0009] Patent CN108540132A mentions an adaptive digital background calibration circuit with adjustable sampling rate. Based on the different relationships between error and reference level at different stages (e.g., initial, middle, and late calibration), it obtains the output of a downsampling rate regulator and continuously updates the filter weight coefficients to reduce error. However, it has the following shortcomings: First, the adaptive filter uses a fixed step size, which cannot simultaneously meet the requirements of low steady-state error and high convergence speed; second, as the calibration error decreases, the update speed of the adaptive filter weight coefficients slows down. If the iteration amount of the tap weight coefficients is too large, repeated oscillations around the optimal value will occur, slowing down the convergence speed and deteriorating the calibration effect; third, although this patent achieves lower power consumption while maintaining speed and accuracy compared to traditional adaptive digital background calibration technology, this is at the cost of sacrificing steady-state error and cannot avoid gradient noise interference with the input signal. This invention utilizes the inverse hyperbolic tangent function to establish a nonlinear relationship between step size and error, enabling real-time updating of the step size based on the error signal magnitude. Furthermore, by introducing a feedback control function into the original algorithm model, This makes the current step size correlated with the square of the current error and the previous error, greatly improving the convergence speed. It not only maintains the advantages of the original algorithm but also makes its performance more stable. To prevent the algorithm from diverging due to a sudden increase in input signal power, a normalization algorithm is added to limit u(n) when updating the weight coefficient vector. The range of step size options has been increased, resulting in higher stability. Summary of the Invention
[0010] This invention aims to solve the problems of the prior art mentioned above. A digital back-end calibration system for Pipeline ADCs is proposed. The technical solution of this invention is as follows:
[0011] A digital back-end calibration system for a pipeline ADC includes: a first frequency conversion unit (1), an ADC to be calibrated (2), a low-speed high-precision ADC (3), an LMS adaptive filter (4), a second frequency conversion unit (6), and a subtractor (5). The first frequency conversion unit (1) is used to reduce the frequency of the input signal Vin, so that the frequency-reduced analog input signal is converted from analog to digital, and the output digital signal is used as a reference signal for ADC calibration. The low-speed high-precision ADC (3) is connected to the first frequency conversion unit (1), the ADC to be calibrated (2) is connected to the LMS adaptive filter (4), and the LMS adaptive filter (4) is connected to the second frequency conversion unit (6) and the subtractor (5) respectively.
[0012] The ADC (2) to be calibrated performs analog-to-digital conversion on the analog input signal Vin and uses the converted digital output D(n) as the input signal of the LMS adaptive filter (4). The low-speed high-precision ADC (3) performs analog-to-digital conversion on the analog input signal after frequency reduction by the first frequency conversion unit (1). The digital signal output by the analog-to-digital conversion is used as the reference signal Dref(n) for ADC calibration.
[0013] After the analog signal is sampled and quantized by the ADC (2) to be calibrated, the output data is input into the LMS adaptive filter (4) to obtain the initial value. After being down-converted by the second frequency conversion unit (6), it is input into the subtractor (5). On the other hand, the low-speed high-precision ADC (3) also samples and quantizes the analog signal to obtain the output Dref(n). After being processed by the subtractor (5), the error signal e(n) is obtained and the error is fed back to the LMS adaptive filter (4) for updating the tap weight coefficients. This iterative process makes the output of the ADC (2) to be calibrated gradually approach the output of the high-precision ADC (3), and finally completes the calibration of the pipeline ADC.
[0014] Furthermore, the first frequency conversion unit (1) refers to the frequency reducer, which can reduce the frequency of the input signal so that the frequency of the analog input signal after frequency reduction is proportional to the sampling frequency of the low-speed high-precision ADC. The second frequency conversion unit (6) refers to the frequency reducer, which reduces the output of the LMS adaptive filter so that the two input signals of the subtractor are in a one-to-one correspondence in the time domain.
[0015] Furthermore, the LMS adaptive filter (4) is based on the LMS algorithm, and introduces an inverse hyperbolic tangent function to construct a nonlinear relationship between the step size factor and the error signal, so that the step size takes a larger value in the early stage of convergence, a smaller value during the convergence period, and is slowly adjusted when the error approaches zero.
[0016] u(n)=βartanh(α×[|e(n)|) γ (1)
[0017] In the formula, α and β are parameters of the control function amplitude, γ is a parameter of the control function curve, e(n) represents the error signal, u(n) represents the step size factor, and artanh represents the inverse hyperbolic tangent function.
[0018] Furthermore, in the LMS adaptive filter (4), starting with the two constant values of parameters α and β, β is kept constant, while α is transformed into a feedback control function that is proportional to the square of the ratio of the current error value to the previous error value: the bottom shape of the function is affected by the ratio of the current error signal to the previous error signal.
[0019]
[0020] The value of m affects the convergence speed, but has almost no effect on the steady-state error. As the value of m increases, the convergence speed gradually increases, but when the value of m increases to a certain extent, the convergence speed hardly increases anymore.
[0021] Furthermore, the step size factor has a non-linear relationship with the error signal, used to control the convergence speed and accuracy; the relationship model between step size and error is as follows:
[0022]
[0023] In the formula, e(n) represents the error signal, e(n-1) is the error between the output signal and the reference signal at the previous time step, and γ, m, and β are the influence values of the step size factor, which together control the shape of the step size curve.
[0024] Furthermore, after normalizing the algorithm step size, the filter weight coefficient vector can be updated as follows:
[0025]
[0026] τ represents a constant with a value of 0.01, and x(n) represents the input signal of the adaptive filter. Normalization can increase the range of step size values.
[0027] Furthermore, let x(n) and w(n) represent the input signal and weight vector of the adaptive filter, respectively, and L be the order of the adaptive filter, where x(nk) represents the input vector at time k, and w k Let w represent the weight vector at time k. L-1 Let y(n) represent the weight vector at time L-1, y(n) be the output signal of the adaptive filter, d(n) be the desired signal, and e(n) be the error signal. The basic form of the calibration algorithm is as follows:
[0028] x(n)=[x(n),x(n-1),...,x(n-L+1)] T (5)
[0029] w(n) = [w0(n), w1(n), ... w L-1 (n)] T (6)
[0030]
[0031]
[0032] e(n)=d(n)-y(n) (9)
[0033]
[0034] Formulas (5) to (10) represent the entire process of the calibration algorithm, where formula (8) represents the update of the step size factor and formula (10) represents the update of the weights, which is part of the calibration algorithm.
[0035] Furthermore, the ADC to be calibrated is a 14-bit 1GS / s pipelined ADC, and the low-speed, high-precision ADC is a 14-bit cyclic ADC.
[0036] The advantages and beneficial effects of this invention are as follows:
[0037] This invention proposes a digital back-end calibration system for pipeline ADCs, comprising a down-conversion unit, an ADC to be calibrated, a low-speed, high-precision ADC, an LMS adaptive filter, and a subtractor; it can solve the problem of system accuracy degradation caused by inter-stage gain errors in pipeline ADCs. Using the low-speed, high-precision ADC as a reference, it is connected in parallel with the ADC to be calibrated, and the difference between their digital outputs is sent to the LMS adaptive filter for processing. This ensures that the output of the ADC to be calibrated continuously approaches the output of the low-speed, high-precision ADC, while the original ADC's conversion process remains unaffected, thus achieving the purpose of digital calibration.
[0038] 1) The innovation of this paper lies in the fact that, unlike traditional background calibration techniques that use the LMS algorithm, the algorithm of this invention establishes a nonlinear relationship between step size and error, based on the inverse hyperbolic tangent function of the step size selection function, and can update the step size in real time according to the magnitude of the error signal. Furthermore, by introducing a feedback control function into the original algorithm model, This makes the current step size correlated with the square of the current error and the previous error, greatly improving the convergence speed. It not only maintains the advantages of the original algorithm but also offers more stable performance. The relationship between the step size factor and the error function is obtained as follows: It is the influence value of the step size factor, which together control the shape of the step size curve.
[0039] 2) Compared to the fixed-step-size LMS algorithm, some variable-step-size algorithms only slightly improve convergence speed, but also increase misalignment accuracy, failing to achieve a balance between convergence speed and misalignment accuracy. To prevent sudden increases in input signal power from causing algorithm divergence, this invention incorporates a normalization algorithm to constrain u(n) during weight coefficient vector updates, i.e. The range of step size options has been increased, resulting in higher stability.
[0040] 3) This invention can increase the effective number of bits in a pipeline ADC. It is a digital back-end calibration technology for pipeline ADCs that can solve the problem of decreased system accuracy caused by inter-stage gain error in pipeline ADCs. It can increase the effective number of bits in the ADC, with fast convergence speed and high calibration accuracy.
[0041] It has the following advantages:
[0042] 1) Fast convergence speed, can instantly change the step size, can determine the relationship between two adjacent step sizes, avoid the situation where the error is not zero or the step size factor is already zero or close to zero during the step size iteration process, so that the step size of the iteration at adjacent time moments is within a controllable range, and at the same time accelerates the convergence speed.
[0043] 2) High calibration accuracy: The algorithm of this invention has a more significant effect on improving the performance of the ADC system and the calibration effect is more obvious.
[0044] 3) Background calibration: The calibration process and the original ADC conversion process can be performed simultaneously without interruption, and can be calibrated in real time as the environment changes.
[0045] 4) It can automatically track nonlinear errors such as comparator misalignment and clock jitter, in addition to capacitor mismatch and operational amplifier limited gain. Attached Figure Description
[0046] Figure 1 This is a block diagram of the pipelined ADC calibration structure used in a preferred embodiment of the present invention;
[0047] Figure 2 This is a block diagram of the adaptive filter system used in this invention;
[0048] Figure 3 This is a flowchart of the LMS adaptive filtering algorithm used in this invention;
[0049] Figure 4 This is a comparison chart of the spectrum of the pipeline ADC before and after calibration in this invention. Detailed Implementation
[0050] The technical solutions of the present invention will be clearly and thoroughly described below with reference to the accompanying drawings. The described embodiments are merely some embodiments of the present invention.
[0051] The technical solution of the present invention to solve the above-mentioned technical problems is:
[0052] This application example uses a 14-bit 1GS / s pipelined ADC, which includes six 2.5-bit sub-stages and one 2-bit Flash ADC.
[0053] Example
[0054] like Figure 1 As shown, the pipelined ADC calibration structure using the LMS algorithm consists of the following parts: a first frequency conversion unit (1), an ADC to be calibrated (2), a low-speed high-precision ADC (3), an LMS adaptive filter (4), a second frequency conversion unit (6), and a subtractor (5). The first frequency conversion unit (1) is used to reduce the frequency of the input signal Vin, so that the down-frequency analog input signal is converted from analog to digital, and the output digital signal is used as the reference signal for ADC calibration. The low-speed high-precision ADC (3) is connected to the first frequency conversion unit (1), the ADC to be calibrated (2) is connected to the LMS adaptive filter (4), and the LMS adaptive filter (4) is connected to the second frequency conversion unit (6) and the subtractor (5) respectively. The ADC (2) to be calibrated performs analog-to-digital conversion on the analog input signal Vin and uses the converted digital output D(n) as the input signal of the LMS adaptive filter (4). The low-speed high-precision ADC performs analog-to-digital conversion on the analog input signal after frequency reduction by the first frequency conversion unit (1), and the digital signal output by the analog-to-digital conversion is used as the reference signal Dref(n) for ADC calibration.
[0055] The ADC (2) to be calibrated samples and quantizes the analog signal, and the output data is input into the LMS adaptive filter (4). After obtaining the initial value, it is down-converted by the second frequency conversion unit (6) and then input into the subtractor (5). On the other hand, the low-speed high-precision ADC (3) also samples and quantizes the analog signal to obtain the output Dref(n). After passing through the subtractor (5), the error signal e(n) is obtained, and the error is fed back to the LMS adaptive filter (4) for updating the tap weight coefficients. The inverse hyperbolic tangent function is introduced into the original algorithm model to construct a nonlinear functional relationship between the step size and the error signal, which together constrains the step size value so that the current step size value is related to the square of the ratio of the current error to the previous error, thereby improving the convergence speed of the algorithm. At the same time, the step size normalization process is combined to increase the range of step size selection and improve the stability. Such an iterative process makes the output of the ADC (2) to be calibrated gradually approach the output of the high-precision ADC (3), and finally completes the calibration of the pipeline ADC.
[0056] like Figure 2 The diagram shows the system block diagram of the adaptive filter. Its core principle is the steepest descent method, which adjusts the system weights along the negative gradient direction, replacing the mean square error with the squared error value. Here, x(n) is the sampled value of the fuze echo signal, y(n) is the output signal of the adaptive filter, v(n) is the noise input signal, W(n) is the tap weight coefficient of the adaptive filter, e(n) is the output error signal, and d(n) is the desired signal.
[0057] like Figure 3 The diagram shows the algorithm principle of the adaptive filter used in this invention. Unlike traditional background calibration techniques that use the LMS algorithm, the algorithm of this invention establishes a nonlinear relationship between step size and error, based on the inverse hyperbolic tangent function of the step size selection function, and can update the step size in real time according to the magnitude of the error signal. Furthermore, by introducing a feedback control function into the original algorithm model, This makes the current step size correlated with the square of the current error and the previous error, greatly improving the convergence speed. It not only maintains the advantages of the original algorithm but also offers more stable performance. The relationship between the step size factor and the error function is obtained as follows: These are the influence values of the step size factor, which together control the shape of the step size curve. To prevent a sudden increase in input signal power from causing algorithm divergence, a normalization algorithm is added to limit u(n) during the weight coefficient vector update, i.e. The range of step size selection is increased, resulting in higher stability. The algorithm steps of this invention are described in the following step:
[0058] Filtered output: y(n) = x(n)w T (n);
[0059] Let x(n) and w(n) represent the input signal and weight vector of the adaptive filter, respectively, and L be the order of the adaptive filter.
[0060] x(n)=[x(n)x(n-1)....x(n-M+1)];
[0061] w(n) = [w0(n)w1(n)...w M-1 (n)];
[0062] Estimation error: e(n) = d(n) - y(n);
[0063] y(n) is the output signal of the adaptive filter, d(n) is the desired signal, and e(n) represents the error signal.
[0064] Step-by-step update:
[0065] Tap weight coefficient update:
[0066] like Figure 4 The figure shown is a comparison of the spectrum before and after calibration of the 14-bit 1GS / s non-ideal pipelined ADC according to the present invention. Figure 4 (a) shows the FFT test results of an uncalibrated non-ideal pipeline ADC. It can be seen that under the influence of errors such as capacitor mismatch, interstage gain error and comparator offset, the effective number of bits decreased from 14 bits to 8.37 bits, and the SNDR was 52.08dB. Figure 4 (b) is the calibrated spectrum of an adaptive calibration technique proposed in this invention for pipeline ADCs. The effective number of bits is increased from 8.37 bits to 13.67 bits, and the SNDR is increased from 52.08 dB to 84.10 dB, which can effectively improve the accuracy of pipeline ADCs.
[0067] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.
[0068] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0069] The above embodiments should be understood as illustrative only and not as limiting the scope of protection of the present invention. After reading the description of the present invention, those skilled in the art can make various alterations or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.
Claims
1. A digital back-end calibration system for a pipeline ADC, characterized in that, include: The system comprises a first frequency conversion unit (1), an ADC to be calibrated (2), a low-speed high-precision ADC (3), an LMS adaptive filter (4), a second frequency conversion unit (6), and a subtractor (5). The first frequency conversion unit (1) is used to reduce the frequency of the input signal Vin, so that the down-frequency analog input signal is converted from analog to digital, and the output digital signal is used as the reference signal for ADC calibration. The low-speed high-precision ADC (3) is connected to the first frequency conversion unit (1), the ADC to be calibrated (2) is connected to the LMS adaptive filter (4), and the LMS adaptive filter (4) is connected to the second frequency conversion unit (6) and the subtractor (5) respectively. The ADC (2) to be calibrated performs analog-to-digital conversion on the analog input signal Vin and uses the converted digital output D(n) as the input signal of the LMS adaptive filter (4). The low-speed high-precision ADC (3) performs analog-to-digital conversion on the analog input signal after frequency reduction by the first frequency conversion unit (1). The digital signal output by the analog-to-digital conversion is used as the reference signal Dref(n) for ADC calibration. After the analog signal is sampled and quantized by the ADC (2) to be calibrated, the output data is input into the LMS adaptive filter (4) to obtain the initial value. After being down-converted by the second frequency conversion unit (6), it is input into the subtractor (5). On the other hand, the low-speed high-precision ADC (3) also samples and quantizes the analog signal to obtain the output Dref(n). After being processed by the subtractor (5), the error signal e(n) is obtained and the error is fed back to the LMS adaptive filter (4) for updating the tap weight coefficients. This iterative process makes the output of the ADC (2) to be calibrated gradually approach the output of the high-precision ADC (3), and finally completes the calibration of the pipeline ADC. The LMS adaptive filter (4) is based on the LMS algorithm, introducing an inverse hyperbolic tangent function to construct a nonlinear relationship between the step size factor and the error signal. This results in a larger step size in the early stage of convergence, a smaller step size during the convergence period, and a slow adjustment when the error approaches zero. ; In the formula, α and β are parameters of the control function amplitude, γ is a parameter of the control function curve, e(n) represents the error signal, u(n) represents the step size factor, and artanh represents the inverse hyperbolic tangent function; In the LMS adaptive filter (4), starting with the two constant values of parameters α and β, β is kept constant, while α is changed into a feedback control function that is proportional to the square of the ratio of the current error value to the previous error value: the bottom shape of the function is affected by the ratio of the current error signal to the previous error signal. The value of m affects the convergence speed, but has almost no effect on the steady-state error. As the value of m increases, the convergence speed gradually increases, but when the value of m increases to a certain extent, the convergence speed hardly increases anymore.
2. The digital back-end calibration system for a pipeline ADC according to claim 1, characterized in that, The first frequency conversion unit (1) refers to the frequency reducer, which can reduce the frequency of the input signal so that the frequency of the analog input signal after frequency reduction is proportional to the sampling frequency of the low-speed high-precision ADC. The second frequency conversion unit (6) refers to the frequency reducer, which reduces the output of the LMS adaptive filter so that the two input signals of the subtractor are in a one-to-one correspondence in the time domain.
3. A digital back-end calibration system for a pipeline ADC according to claim 1, characterized in that, The step size factor has a non-linear relationship with the error signal, used to control convergence speed and accuracy; the relationship model between step size and error is as follows: ; In the formula, e(n) represents the error signal, e(n-1) is the error between the output signal and the reference signal at the previous time step, and γ, m, and β are the influence values of the step size factor, which together control the shape of the step size curve.
4. A digital back-end calibration system for a pipeline ADC according to claim 3, characterized in that, After normalizing the algorithm step size, the filter weight coefficient vector can be updated as follows: ; τ represents a constant with a value of 0.01, and x(n) represents the input signal of the adaptive filter. Normalization can increase the range of step size values.
5. A digital back-end calibration system for a pipeline ADC according to claim 4, characterized in that, Let x(n) and w(n) represent the input signal and weight vector of the adaptive filter, respectively, and L represent the order of the adaptive filter, where x(n-k) represents the input vector at time k, w k (n-k) represents the weight vector at time k, w L-1 (n-L) represents the weight vector at time L-1, y(n) is the output signal of the adaptive filter, d(n) is the desired signal, and e(n) represents the error signal. The basic form of the calibration algorithm is as follows: Formulas (5) to (10) represent the entire process of the calibration algorithm, where formula (8) represents the update of the step size factor and formula (10) represents the update of the weights, which is part of the calibration algorithm.
6. A digital back-end calibration system for a Pipeline ADC according to claim 5, characterized in that, The ADC to be calibrated is a 14-bit 1GS / s pipelined ADC, and the low-speed, high-precision ADC is a 14-bit cyclic ADC.