A vehicle-mounted audio signal testing system and method

Abstract

The present application relates to the technical field of vehicle-mounted audio signal testing, and more particularly to a vehicle-mounted audio signal testing system and method. The system comprises a host computer, an audio signal processing module and a controllable analog load. The host computer is connected with the audio signal processing module for sending action instructions to the audio signal processing module and processing and analyzing test signals transmitted by the audio signal processing module. The signal acquisition end of the audio signal processing module is connected with the measured product through the controllable analog load, and the output end is connected with the control end of the controllable analog load for collecting and processing and analyzing test signals of the measured product through the controllable analog load and switching the resistance value of the controllable analog load according to the switching resistance value instruction sent by the host computer. The controllable analog load is used for switching the resistance value of the circuit connected with the measured product. The present application does not need to manually replace different loads for testing, is simple and easy to operate, and is beneficial to large-scale promotion and application.

Description

Technical Field

[0001] This invention relates to the technical field of vehicle audio signal testing, and more specifically, to a vehicle audio signal testing system and method. Background Technology

[0002] Currently, with the development of the automotive industry, the demand for in-vehicle audio signal testing is also increasing. Modules for acquiring, processing, and analyzing in-vehicle audio signals are expensive and have very long lead times, significantly increasing equipment and time costs. Existing test modules have a maximum of only 8 channels, and if full differential measurement is used, only 4 sets of differential signal channels can be covered.

[0003] Audio testing typically requires simulated load testing, and different products require different simulated loads. Existing testing systems require manually switching connections to different loads for testing, a time-consuming and cumbersome process that hinders large-scale deployment and application. Summary of the Invention

[0004] To overcome the problem of the discontinuation of the core module for testing audio signals and the lack of alternative equipment as described in the background art, this invention provides an in-vehicle audio signal testing system and method.

[0005] To solve the above-mentioned technical problems, the technical solution of the present invention is as follows:

[0006] In a first aspect, the present invention provides an in-vehicle audio signal testing system, the system comprising a host computer, an audio signal processing module, and a controllable analog load;

[0007] The host computer is connected to the audio signal processing module and is used to send action commands to the audio signal processing module and process and analyze the test signals transmitted by the audio signal processing module.

[0008] The signal acquisition end of the audio signal processing module is connected to the product under test via the controllable analog load, and the output end is connected to the control end of the controllable analog load. It is used to acquire, process and analyze the test signal of the product under test passing through the controllable analog load, and switch the resistance value of the controllable analog load according to the instruction to switch the resistance value sent by the host computer.

[0009] The controllable analog load is used to switch the resistance value of the circuit connected to the device under test according to the product under test.

[0010] Preferably, the audio signal processing module includes an FPGA chip, which is connected to the host computer via Ethernet, and its signal output terminal is connected to the control terminal of the controllable analog load.

[0011] Preferably, the audio signal processing module further includes a DSA module for signal acquisition, an ASP module for programming, a PGA module for signal amplification, and an ADC module for analog-to-digital conversion. The output of the controllable analog load is connected to the signal acquisition terminal of the FPGA chip in sequence through the DSA module, ASP module, PGA module, and ADC module.

[0012] Preferably, the audio signal processing module further includes a memory for storing hardware setting data, and the memory is data-connected to the FPGA chip.

[0013] Preferably, the type of the memory is an electrically erasable programmable read-only memory.

[0014] Preferably, the controllable analog load is provided with several load channels, and the FPGA chip switches the resistance value of the connected circuit by controlling the switch of each load channel.

[0015] Preferably, the load channel includes several resistors and several relays for controlling the connection of the resistors to the circuit, with both ends of the resistors connected in series with the relays and then connected in parallel to the circuit.

[0016] Preferably, the load channel includes a 0Ω channel, a 4Ω channel, and a 10kΩ channel.

[0017] In a second aspect, the present invention provides a method for testing vehicle audio signals, the method being applied to the vehicle audio signal testing system as described in the first aspect, comprising:

[0018] S1. The host computer sends an instruction to the audio signal processing module to switch the controllable analog load according to the product under test. After the controllable analog load switches the resistance value of the circuit, it sends an instruction to the audio signal processing module to collect the signal.

[0019] S2, the audio signal processing module collects, processes and analyzes the test signal of the product under test after passing through a controllable simulated load, and transmits the pre-processed test signal to the host computer;

[0020] S3. The host computer further processes and analyzes the test signals and obtains the test results.

[0021] Preferably, the instructions for acquiring signals include instructions for setting the sampling rate, the number of sampling points, the sampling mode, and the sampling channel.

[0022] Its beneficial effects are as follows:

[0023] 1. This invention uses a host computer and an audio signal processing module to acquire, process, and analyze the test signals of the product under test, and obtain the test results. The audio signal processing module uses a DSA module, ASP module, PGA module, ADC module, and FPGA chip to acquire, process, and analyze the test signals of the product under test, and transmits them to the host computer for further processing and analysis, thereby obtaining the test results.

[0024] 2. This invention uses a host computer to send commands to the audio signal processing module to switch the resistance value of the controllable analog load. The host computer sends commands to the audio signal processing module to switch the resistance value of the controllable analog load according to different products under test, eliminating the need to manually change and connect different loads for testing. This shortens testing time, is simple to operate, and facilitates large-scale promotion and application. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of the vehicle-mounted audio signal testing system provided by the present invention.

[0026] Figure 2 This is a first specific structural schematic diagram of the vehicle-mounted audio signal testing system provided by the present invention.

[0027] Figure 3 A schematic diagram of the controllable simulated load provided by the present invention.

[0028] Figure 4 This is a second specific structural diagram of the vehicle-mounted audio signal testing system provided by the present invention.

[0029] Figure 5 The flowchart illustrates the implementation of the vehicle audio signal testing method provided by this invention.

[0030] Figure 6 The flowchart illustrates the implementation of the host computer-controlled switching of controllable simulated loads provided by this invention.

[0031] Figure 7 The flowchart illustrates the implementation of sending sampling commands from the host computer, as provided in this invention.

[0032] Figure 8 The flowchart illustrates the operation of the host computer and audio signal processing module provided by this invention. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0034] In the accompanying drawings of the embodiments of this application, the same or similar reference numerals correspond to the same or similar components. In the description of this application, it should be understood that if terms such as "upper", "lower", "left", "right", "top", "bottom", "inner", "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting this patent.

[0035] Furthermore, if terms such as "first" or "second" are used for descriptive purposes only, they are mainly used to distinguish different devices, components or parts (the specific types and structures may be the same or different), and are not used to indicate or imply the relative importance or quantity of the indicated devices, components or parts, and should not be construed as indicating or implying relative importance.

[0036] Example 1

[0037] like Figure 1 As shown, this embodiment provides an in-vehicle audio signal testing system, which includes a host computer 10, an audio signal processing module 20, and a controllable analog load 30, used to test the product under test 40.

[0038] The host computer 10 is connected to the audio signal processing module 20 via data connection. It is mainly used to send action commands to the audio signal processing module 20 and to process and analyze the test signals transmitted by the audio signal processing module 20.

[0039] The signal acquisition end of the audio signal processing module 20 is connected to the product under test 40 via the controllable analog load 30, and the output end is connected to the control end of the controllable analog load 30. It is used to acquire, process and analyze the test signal of the product under test 40 passing through the controllable analog load 30, and switch the resistance value of the controllable analog load 30 according to the switching resistance value instruction sent by the host computer 10.

[0040] For details, please refer to Figure 2The audio signal processing module 20 includes an FPGA (Field Programmable Gate Array) chip. The FPGA chip is connected to the host computer 10 via Ethernet, and its signal output is connected to the control terminal of the controllable analog load 30. The audio signal processing module 20 includes a DSA (Dynamic Signal Acquisition) module, an ASP (Active Server Pages) module, a PGA (Programmable Gain Amplifier) ​​module, and an ADC (Analog-to-Digital Converter) module. The DSA module is mainly used for signal acquisition, the ASP module is mainly used for programming, the PGA module is mainly used for signal amplification, and the ADC module is mainly used for analog-to-digital conversion.

[0041] The audio signal processing module 20 is also equipped with a memory for storing hardware setting data. The memory is mainly used to store hardware setting data and is connected to the FPGA chip.

[0042] In some preferred embodiments, the memory type can be EEPROM (Electrically Erasable Programmable Read-Only Memory). EEPROM is a type of memory chip that does not lose data after power loss, and existing information can be erased and reprogrammed on a computer or dedicated device.

[0043] The controllable analog load 30 is used to switch the resistance value of the circuit connected to the device under test 40, and it is controlled by the FPGA chip. As an external expansion module, the analog load can be easily replaced as needed.

[0044] The input terminal of the controllable analog load 30 is connected to the output terminal of the product under test 40. The output terminal is connected to the signal acquisition terminal of the FPGA chip in sequence through the ASP module, PGA module, and ADC module. The test signal output by the product under test 40 is connected to the serial port connector of the audio signal processing module 20 after passing through the controllable analog load 30. The serial port connector adopts a DB37 female connector. Then, the signal is processed by the ASP module, PGA module, and ADC module. The ADC module then submits the signal to the FPGA chip for processing and analysis according to the protocol.

[0045] like Figure 3As shown, the controllable analog load 30 has several load channels, including 0Ω, 4Ω, and 10kΩ channels. Each load channel includes several resistors and several relays for controlling the connection of the resistors to the circuit. Relays are connected in series across both ends of the resistors, and then connected in parallel to the circuit. The FPGA chip controls whether the resistors are connected to the circuit by controlling the relays across the resistors. The size and number of loads can be selected as needed, supporting up to 16 loads to switch the resistance value connected to the circuit.

[0046] Based on the structural connections of the above modules, the working steps of this embodiment are as follows:

[0047] The host computer 10 issues a command to the FPGA chip to switch or not switch the load based on the type of the connected product under test 40. The FPGA chip then switches the resistance of the controllable analog load 30 in the circuit according to the switching command. The product under test 40 is connected through the controllable analog load 30. After the test signal passes through the controllable analog load 30, it is acquired by the DSA module and enters the test system. After being amplified by the ASP module and PGA module, the test signal is converted into a digital signal by the ADC module. The ADC module delivers the converted digital signal to the FPGA chip, and then sends it to the host computer 10 via Ethernet for further processing and analysis. The processing results are then organized and displayed, or can be presented more intuitively in a chart format. The data collected by the host computer 10 can also be saved to a specified Excel spreadsheet as needed for later data analysis.

[0048] Example 2

[0049] The difference between this embodiment and the first embodiment is that:

[0050] like Figure 4 As shown, the audio signal processing module 20 in this embodiment adopts dual signal processing channels.

[0051] The host computer 10 is connected to the audio signal processing module 20 via data connection. It is mainly used to send action commands to the audio signal processing module 20 and to process and analyze the test signals transmitted by the audio signal processing module 20.

[0052] The signal acquisition end of the audio signal processing module 20 is connected to the product under test 40 via the controllable analog load 30, and the output end is connected to the control end of the controllable analog load 30. It is used to acquire, process and analyze the test signal of the product under test 40 passing through the controllable analog load 30, and switch the resistance value of the controllable analog load 30 according to the switching resistance value instruction sent by the host computer 10.

[0053] The audio signal processing module 20 includes an FPGA chip, which is connected to the host computer 10 via Ethernet, and its signal output is connected to the control terminal of the controllable analog load 30. The audio signal processing module 20 includes a DSA module, an ASP module, a PGA module, and an ADC module. The DSA module is mainly used for signal acquisition, the ASP module is mainly used for programming, the PGA module is mainly used for signal amplification, and the ADC module is mainly used for analog-to-digital conversion. The test signal passes through the DB37 female connector and then through dual signal processing channels before entering the FPGA chip. The FPGA chip can also select one channel for signal processing.

[0054] The audio signal processing module 20 is also equipped with a memory for storing hardware setting data. The memory is mainly used to store hardware setting data and is connected to the FPGA chip.

[0055] In some preferred embodiments, the memory type can be EEPROM. EEPROM is a type of memory chip that does not lose data after power failure, and existing information can be erased and reprogrammed on a computer or dedicated device.

[0056] The controllable analog load 30 is used to switch the resistance value of the circuit connected to the device under test 40, and it is controlled by the FPGA chip. As an external expansion module, the analog load can be easily replaced as needed.

[0057] The input terminal of the controllable analog load 30 is connected to the output terminal of the product under test 40. The output terminal is connected to the signal acquisition terminal of the FPGA chip in sequence through the ASP module, PGA module, and ADC module. The test signal output by the product under test 40 is connected to the serial port connector of the audio signal processing module 20 after passing through the controllable analog load 30. The serial port connector adopts a DB37 female connector. Then, the signal is processed by the ASP module, PGA module, and ADC module. The ADC module then submits the signal to the FPGA chip for processing and analysis according to the protocol.

[0058] Based on the structural connections of the above modules, the working steps of this embodiment are as follows:

[0059] The host computer 10 sends a command to the FPGA chip to switch or not switch the load based on the type of the connected product under test 40. The FPGA chip then adjusts the resistance of the controllable analog load 30 in the circuit according to the switching command. Simultaneously, the host computer 10 sends a command to the FPGA chip to select the processing channel, and the FPGA chip selects the number of signal processing channels according to the command. The product under test 40 is connected through the controllable analog load 30. After the test signal passes through the controllable analog load 30, it is acquired by the DSA module and enters the test system. The single-channel or dual-channel signal is amplified by the ASP module and PGA module, and then converted into a digital signal by the ADC module. The ADC module delivers the converted digital signal to the FPGA chip, and then sends it to the host computer 10 via Ethernet for further processing and analysis. The processing results are then organized and displayed, or can be presented more intuitively in a chart format. The host computer 10 can also choose to save the collected data to a specified Excel spreadsheet for later data analysis.

[0060] Example 3:

[0061] This embodiment provides a method for testing vehicle audio signals, which is applied to the vehicle audio signal testing system as described in Embodiment 1 or Embodiment 2.

[0062] Please see Figure 5 The figure shows a flowchart of the implementation of the vehicle audio signal testing method of this embodiment.

[0063] like Figure 5 As shown, the method includes:

[0064] S1. The host computer 10 sends an instruction to the audio signal processing module 20 to switch the controllable analog load 30 according to the instruction from the product under test 40. After the controllable analog load 30 switches the resistance value of the circuit, it sends an instruction to the audio signal processing module 20 to collect the signal.

[0065] S2, the audio signal processing module 20 collects, processes and analyzes the test signal of the product under test 40 passing through the controllable analog load 30, and transmits the pre-processed test signal to the host computer 10.

[0066] S3 and the host computer 10 further process and analyze the test signals and obtain the test results.

[0067] In step S1, as Figure 6 As shown, the host computer 10 sends an instruction to the audio signal processing module 20 to switch the controllable analog load 30 according to the instruction sent by the product under test 40, including:

[0068] The host computer 10 sends a switching resistance value instruction to the FPGA chip of the audio signal processing module 20 via Ethernet according to the product under test 40. The FPGA chip receives and parses the instruction, and determines whether the resistance value to be connected to the analog load is greater than 0. If not, the FPGA chip does not output an instruction and the analog load does not operate. If yes, the FPGA chip further determines whether the resistance value to be connected to the analog load is greater than 4Ω. Based on the determination result, it sends an instruction to switch the analog load to the corresponding resistance value. If not, it sends an instruction to switch the analog load to the 4Ω channel. If yes, it sends an instruction to switch the analog load to the 10Ω channel.

[0069] like Figure 7 As shown, the host computer 10 sends a signal acquisition instruction to the audio signal processing module 20, including:

[0070] The host computer 10 communicates with the audio signal processing module 20 via Ethernet, configuring the module's IP address and port. It then sends commands to the audio signal processing module 20 to set the sampling rate, number of sampling points, sampling mode, and sampling channels. Following this, the host computer 10 calls acquisition functions to collect real-time data transmitted by the audio signal processing module 20 and calls analysis functions to calculate and analyze various performance indicators.

[0071] like Figure 8 As shown, in steps S2 and S3, after the host computer 10 establishes a connection with the audio signal processing module 20, and the controllable analog load 30 switches to the required load, the host computer 10 determines whether to send a signal acquisition command. If so, the host computer 10 sends the signal acquisition command to the FPGA chip. The product under test 40 is connected through the controllable analog load 30. After the test signal passes through the controllable analog load 30, it is acquired by the DSA module and enters the test system. The single-channel or dual-channel signal is amplified by the ASP module and the PGA module, and then the ADC module converts the test signal into a digital signal. The ADC module delivers the converted digital signal to the FPGA chip, and then sends it to the host computer 10 via Ethernet for further processing and analysis. The host computer 10 organizes and displays the processing results, or it can choose to display them more intuitively in a chart format. At the same time, the data collected by the host computer 10 can also be saved to a specified Excel spreadsheet as needed for convenient data analysis later.

[0072] The number and size of loads that can be connected using this method can be set according to needs, offering great flexibility. Furthermore, during testing, switching to the corresponding load is achieved simply by sending a command from the host computer (10), eliminating the need for manual connection switching and significantly improving production efficiency. This method also significantly reduces equipment costs compared to previous systems, while also shortening delivery time, resulting in substantial savings in both equipment and time costs and greatly facilitating its widespread application.

[0073] Although the description of the present invention has been given in conjunction with the specific embodiments described above, it is obvious to those skilled in the art that many substitutions, modifications, and variations can be made based on the above description. Therefore, all such substitutions, modifications, and variations are included within the spirit and scope of the appended claims. The above embodiments of the present invention are merely examples for clearly illustrating the invention and are not intended to limit the implementation of the invention. For those skilled in the art, other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the claims of the present invention.

Claims

1. A vehicle-mounted audio signal testing system, characterized in that, The system includes a host computer, an audio signal processing module, and a controllable analog load; The host computer is connected to the audio signal processing module and is used to send action commands to the audio signal processing module and process and analyze the test signals transmitted by the audio signal processing module. The audio signal processing module includes an FPGA chip, which is connected to the host computer via Ethernet, and its signal output terminal is connected to the control terminal of the controllable analog load. The signal acquisition terminal of the audio signal processing module is connected to the product under test via the controllable analog load, and is used to acquire, process and analyze the test signals of the product under test after passing through the controllable analog load. The controllable analog load is used to switch the resistance value of the circuit connected to the device under test according to the product under test. The host computer is further configured to: send a command to the FPGA chip to switch the controllable analog load according to the product under test; the FPGA chip receives and parses the command, determines whether the resistance value to be connected to the controllable analog load is greater than 0, if not, does not output the switching command, if so, further determines whether the resistance value to be connected is greater than 4Ω, and sends a command to switch the controllable analog load to the corresponding resistance channel according to the determination result; after the controllable analog load switches to the resistance value of the circuit, it sends a command to the audio signal processing module to collect the signal; The audio signal processing module has dual signal processing channels. The host computer is also used to send instructions to the FPGA chip to select the number of processing channels. The FPGA chip is also used to select single or dual channels to process the test signal according to the instructions.

2. The vehicle-mounted audio signal testing system according to claim 1, characterized in that, The audio signal processing module also includes a DSA module for signal acquisition, an ASP module for programming, a PGA module for signal amplification, and an ADC module for analog-to-digital conversion. The output of the controllable analog load is connected to the signal acquisition terminal of the FPGA chip in sequence through the DSA module, ASP module, PGA module, and ADC module.

3. The vehicle-mounted audio signal testing system according to claim 1, characterized in that, The audio signal processing module also includes a memory for storing hardware setting data, and the memory is connected to the FPGA chip.

4. The vehicle-mounted audio signal testing system according to claim 3, characterized in that, The memory type is electrically erasable programmable read-only memory.

5. The vehicle-mounted audio signal testing system according to claim 1, characterized in that, The controllable analog load is provided with several load channels, and the FPGA chip switches the resistance value of the connected circuit by controlling the switching of each load channel.

6. The vehicle-mounted audio signal testing system according to claim 5, characterized in that, The load channel includes several resistors and several relays for controlling the connection of the resistors to the circuit. The two ends of the resistors are connected in series with the relays and then connected in parallel to the circuit.

7. The vehicle-mounted audio signal testing system according to claim 5, characterized in that, The load channels include a 0Ω channel, a 4Ω channel, and a 10kΩ channel.

8. A method for testing vehicle-mounted audio signals, characterized in that, The method is applied to the vehicle audio signal testing system as described in any one of claims 1 to 7, comprising: S1. The host computer first sends a command to the audio signal processing module to switch the controllable analog load according to the product under test. After the controllable analog load switches the resistance value of the circuit, it sends a command to the audio signal processing module to collect the signal. S2, the audio signal processing module collects, processes and analyzes the test signal of the product under test after passing through a controllable simulated load, and transmits the pre-processed test signal to the host computer; S3. The host computer further processes and analyzes the test signals and obtains the test results.

9. The vehicle-mounted audio signal testing method according to claim 8, characterized in that, The instructions for acquiring signals include instructions for setting the sampling rate, number of sampling points, sampling mode, and sampling channels.

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