Display panel and wearable electronic device

Abstract

Embodiments of the present disclosure provide a display panel and a wearable electronic device, relating to the technical field of display, for realizing narrow frame of the display panel. The display panel comprises a first display part, a second display part and a binding part, the first display part extends in an arc shape in a flat state. The first display part has a first display area and a first peripheral area located at the end of the arc shape of the first display part. Each row of first sub-pixels of the first display part is arranged along a first direction, and each column of first sub-pixels is arranged along a second direction. The first direction is the radial direction of the arc shape, and the second direction is the extension direction of the arc shape. The display panel further comprises a first scan signal line extending substantially along the second direction and connected with at least one column of first sub-pixels, a first data signal line extending substantially along the first direction and connected with at least one row of first sub-pixels, and a first gate drive circuit provided in the first peripheral area and connected with the first scan signal line. The display panel is used for displaying images.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and a wearable electronic device. Background Technology

[0002] Organic light-emitting diode (OLED) display panels have gradually become one of the mainstream products in the display field due to their excellent performance, such as self-illumination, high contrast, thinness, wide viewing angle, fast response speed, applicability to flexible panels, wide operating temperature range, and relatively simple structure and manufacturing process. OLED display panels can be widely used in terminal products such as smartphones, tablets, televisions, and wearable devices (such as watches). Summary of the Invention

[0003] The purpose of the embodiments disclosed herein is to provide a display panel and a wearable electronic device for achieving a narrow bezel on the display panel and effectively solving the problem of signal crosstalk.

[0004] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions:

[0005] On one hand, a display panel is provided. The display panel includes: a first display portion and a second display portion, wherein the first display portion extends in an arc shape in a flattened state, surrounds the second display portion in an enclosed state, and forms an angle with the second display portion. The display panel further includes: a bonding portion connected to one side of the second display portion. The first display portion has a first display area and a first peripheral area, the first peripheral area being located at the end of the arc shape of the first display portion. The first display portion includes: a plurality of first sub-pixels disposed in the first display area and arranged in multiple rows and columns, each row of first sub-pixels being arranged along a first direction, and each column of first sub-pixels being arranged along a second direction. The first direction is the radial direction of the arc shape, and the second direction is the extension direction of the arc shape. The display panel further includes: a first scan signal line, a first data signal line, and a first gate driving circuit, the first scan signal line extending substantially along the second direction and connected to at least one column of first sub-pixels, the first data signal line extending substantially along the first direction and connected to at least one row of first sub-pixels, and the first gate driving circuit disposed in the first peripheral area and connected to the first scan signal line.

[0006] In the aforementioned display panel, by placing the first gate driving circuit in the first peripheral area, which is located at the arc-shaped end of the first display unit (i.e., the first gate driving circuit is located at the arc-shaped end of the first display unit), it is not necessary to occupy the space of the inner and outer bezels of the first display area. This allows the side bezels of the first display unit to be narrowed, resulting in a better display effect. Furthermore, since the first data signal line extends approximately along a first direction, which is the radial direction of the arc, the extension length of the first data signal line is shortened, reducing the voltage drop during signal transmission.

[0007] In some embodiments, the first display portion includes: a connecting sub-portion and two extending sub-portions. The connecting sub-portion is connected to one side of the second display portion and is located on opposite sides of the second display portion, respectively, along with the bonding portion. The two extending sub-portions are respectively connected to both ends of the connecting sub-portion. The display panel further includes: two adapter portions, each adapter portion connecting one of the extending sub-portions and the second display portion. The adapter portion is stretchable and deformable, and includes a data signal adapter cable, through which the first data signal line located in the two extending sub-portions is connected to the bonding portion.

[0008] In some embodiments, the second display unit has a second peripheral area. The second display unit includes a first fan-out line disposed in the second peripheral area, and the data signal adapter cable is connected to the bonding unit through the first fan-out line.

[0009] In some embodiments, the display panel further includes a transition section connected between the connecting sub-section and the second display section. The transition section includes a multiplexing circuit, and the first data signal line located in the connecting sub-section is connected to the multiplexing circuit. The second display section further includes a second data signal line, one end of which is connected to the multiplexing circuit, and the other end of which is connected to the bonding section.

[0010] In some embodiments, the transition section includes a plurality of multiplexing circuits, each of the multiplexing circuits being connected to one first data signal line and N second data signal lines, where N is an integer greater than or equal to 2.

[0011] In some embodiments, the second display unit includes a second fan-out line disposed in the second peripheral area, and the second data signal line is connected to the bonding unit through the second fan-out line.

[0012] In some embodiments, the two extended sub-sections are symmetrically arranged relative to the first center line, and the data signal transfer lines of the two adapter sections are symmetrically arranged relative to the first center line.

[0013] In some embodiments, the first display portion further includes: a third control signal line disposed in the first peripheral region and extending substantially along the first direction; the third control signal line is connected to the first gate driving circuit and the bonding portion.

[0014] In some embodiments, where the display panel further includes an adapter, the adapter includes a control signal adapter cable, and the third control signal line is connected to the bonding portion via the control signal adapter cable.

[0015] In some embodiments, the second display unit has a second peripheral area. The second display unit includes a third fan-out line disposed in the second peripheral area, and the control signal adapter cable is connected to the bonding unit through the third fan-out line.

[0016] In some embodiments, the first display portion has two first peripheral regions, respectively located at both ends of the arc formed by the first display portion. The first display portion includes two first gate driving circuits, respectively located in the two first peripheral regions.

[0017] In some embodiments, each of the first gate drive circuits includes a plurality of cascaded shift registers; each of the first scan signal lines extends from one of the first peripheral regions to the other of the first peripheral regions, and each end of the first scan signal line is connected to one of the shift registers.

[0018] In some embodiments, the adapter portion has multiple openings. When the display panel includes a data signal adapter cable and a control signal adapter cable, the data signal adapter cable and the control signal adapter cable are arranged to avoid the multiple openings.

[0019] In some embodiments, the second display portion includes opposing display surfaces and non-display surfaces, the binding portion can be bent to the non-display surface of the second display portion, and the adapter portion can be bent to the non-display surface of the second display portion.

[0020] In some embodiments, the plurality of first sub-pixels are arranged radially.

[0021] On the other hand, a wearable electronic device is provided, comprising: a display panel as described in any of the above embodiments. The wearable electronic device further comprises: a wearable structure connected to the display panel, the wearable structure being configured to be worn on a human body.

[0022] The wearable electronic devices described above have the same structure and beneficial technical effects as the display panels provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0024] Figure 1 This is a structural diagram of a watch provided according to some embodiments;

[0025] Figure 2 This is another structural diagram of a watch provided according to some embodiments;

[0026] Figure 3 This is yet another structural diagram of a watch provided according to some embodiments;

[0027] Figure 4 This is a structural diagram of a display device provided according to some embodiments of the present disclosure;

[0028] Figure 5 This is a structural diagram of a display panel provided according to some embodiments of the present disclosure;

[0029] Figure 6 This is another structural diagram of a display panel provided according to some embodiments of the present disclosure;

[0030] Figure 7 This is yet another structural diagram of a display panel provided according to some embodiments of the present disclosure;

[0031] Figure 8 This is a structural diagram of a first display unit provided according to some embodiments of the present disclosure;

[0032] Figure 9 This is a structural diagram of a wearable electronic device provided according to some embodiments of the present disclosure. Detailed Implementation

[0033] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0034] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0035] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0036] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0037] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0038] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0039] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0040] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0041] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0042] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0043] In some embodiments, such as Figure 1 As shown, this embodiment provides a watch 10, which includes a main display screen 11 and a secondary display screen 12 located at the edge of the main display screen 11 in an arc shape.

[0044] For example, the main display screen 11 and the secondary display screen 12 can display independently, and / or they can display synchronously. For instance, when the main display screen 11 and the secondary display screen 12 display independently, only the secondary display screen 12 can display information such as battery level, time, or other functional graphic information when the watch 10 is not in a wrist-raised state, thus reducing power consumption; when the wrist is raised, only the main display screen 11 displays information. Alternatively, the main display screen 11 and the secondary display screen 12 can display images synchronously, allowing the human eye to observe a 3D display due to the distance difference between the main display screen 11 and the secondary display screen 12 and the human eye.

[0045] For example, such as Figure 1 As shown, the watch 10 also includes a watch strap 30, the two ends of which are connected to the side of the secondary display screen 12 away from the main display screen 11. The watch strap 30 is designed to facilitate the wearing and securing of the watch 10.

[0046] Figure 2 This is a structural diagram of the main display screen 11 and the secondary display screen 12 of the watch 10 in a flattened state, as shown below. Figure 2 As shown, a connection area 14 is provided between the main display screen 11 and the secondary display screen 12, connecting the main display screen 11 and the secondary display screen 12. For example, the watch 10 in such... Figure 2 In the flattened state shown, the connection area 14 is located at the top of the main display screen 11, and the sub-display screen 12 is connected to the top of the main display screen 11 through the connection area 14.

[0047] In some examples, the main display screen 11 includes a main display screen area 15 and a first border area 16 surrounding the main display screen area 15, the main display screen area 15 and the first border area 16 being connected. The secondary display screen 12 includes a secondary display screen area 17, and an inner border area 18 and an outer border area 19 located on both sides of the secondary display screen area 17, the secondary display screen area 17 being connected to the inner border area 18 and the outer border area 19. The inner border area 18 is located on the side of the secondary display screen area 17 closer to the main display screen 11, and the outer border area 19 is located on the side of the secondary display screen area 17 farther from the main display screen 11.

[0048] In some examples, such as Figure 2 As shown, the watch 10 also includes a binding area 133, which is connected to the main display screen 11. A driver chip 13 is disposed in the binding area 133. The driver chip 13 is used to drive the main display screen 11 and the secondary display screen 12 to display images.

[0049] For example, such as Figure 3 As shown, a plurality of first sub-pixels 17P are provided in the display area 17 of the secondary display screen. The plurality of first sub-pixels 17P are arranged in an array along the fourth direction W and the second direction Y, wherein the fourth direction W is as follows: Figure 3 As shown in the horizontal direction, the second direction Y is parallel to the arc-shaped extension direction of the sub-display display area 17. For example, a plurality of first sub-pixels 17P arranged along the fourth direction W are called a row, and a plurality of first sub-pixels 17P arranged along the second direction Y are called a column.

[0050] The secondary display screen 17 is provided with multiple first data signal lines Data1, and each first data signal line Data1 is connected to at least one column of first sub-pixels 17P. Figure 3 The diagram illustrates a first data signal line, Data1, connected to a column of first sub-pixels 17P. Data1 is used to transmit data signals to the first sub-pixels 17P. Since Data1 is connected to a column of first sub-pixels 17P arranged along a second direction Y, which is parallel to the arcuate extension direction of the sub-display area 17, the arrangement of Data1 results in a large voltage drop.

[0051] A first gate driving circuit 121 is provided in the outer bezel area 19 of the sub-display 12. The first gate driving circuit 121 includes multiple cascaded shift registers GOA. One shift register GOA is connected to at least one row of first sub-pixels 17P through the first scan signal line Gate1. Figure 3 The diagram illustrates a shift register GOA connected to a first sub-pixel 17P in a row via a first scan signal line Gate1. A first gate drive circuit 121 is used to transmit gate signals to the first sub-pixel 17P.

[0052] A first control signal line 122 is also provided in the outer bezel area 19 of the secondary display screen 12. Exemplarily, the first control signal line 122 includes multiple control signal lines, including: multiple clock signal lines (e.g., first clock signal line CLCK1 and second clock signal line CLCK2), a first voltage bus VGH, a second voltage bus VGL, a start signal line, and a reset signal line, etc., without limitation. These multiple control signal lines are connected to the first gate driving circuit 121 and are used to provide the first gate driving circuit 121 with the control signals required for operation, so that the first gate driving circuit 121 outputs a gate signal.

[0053] Because the first gate driving circuit 121 is located in the outer frame area 19 of the sub-display 12, the outer frame area 19 of the sub-display 12 has a wider border.

[0054] Multiple second sub-pixels 15P are provided in the display area 15 of the main display screen. The multiple second sub-pixels 15P are arranged in an array along the fourth direction W and the third direction T. The fourth direction W is as follows: Figure 3 As shown in the horizontal direction, the third direction T is perpendicular to the fourth direction W. For example, multiple second sub-pixels 15P arranged along the fourth direction W are called a row, and multiple second sub-pixels 15P arranged along the third direction T are called a column.

[0055] Multiple second data signal lines Data2 are provided in the main display area 15, and each second data signal line Data2 is connected to at least one column of second sub-pixels 15P. Figure 3 The diagram illustrates a second data signal line, Data2, connected to a column of second sub-pixels 15P. The second data signal line, Data2, is used to transmit data signals to the second sub-pixels 15P.

[0056] A second gate driving circuit 123 is provided in the first bezel area 16 of the main display screen 11. The second gate driving circuit 123 includes multiple cascaded shift registers GOA. One shift register GOA is connected to at least one row of second sub-pixels 15P through the second scan signal line Gate2. Figure 3 The diagram illustrates a shift register GOA connected to a second sub-pixel 15P in a row via a second scan signal line Gate2. A second gate drive circuit 123 is used to transmit gate signals to the second sub-pixel 15P.

[0057] A second control signal line 128 is also provided in the first bezel area 16 of the main display screen 11. Exemplarily, the second control signal line 128 includes multiple control signal lines, such as multiple clock signal lines, a first voltage bus, and a second voltage bus, etc., without limitation. These multiple control signal lines are electrically connected to the second gate driving circuit 123, providing control signals required for its operation to the second gate driving circuit 123, thereby enabling the second gate driving circuit 123 to output gate signals. The second control signal line 128 is connected to the driver chip 13, which provides corresponding signals to the multiple control signal lines of the second control signal line 128.

[0058] In some examples, such as Figure 3 As shown, the main display screen 11 and the secondary display screen 12 share the same data signal.

[0059] A multiplexer circuit 20 is provided in the connection area 14, and multiple fourth fan-out lines 124 are also provided in the secondary display screen 12. The first data signal line Data1 is connected to the multiplexer circuit 20 through the fourth fan-out lines 124, which extend across the display area 17 of the secondary display screen to the connection area 14. A fifth fan-out line 126 and a second fan-out line 127 are also provided in the first bezel area 16 of the main display screen 11. The second data signal line Data2 is connected to the multiplexer circuit 20 through the fifth fan-out line 126, and to the driver chip 13 through the second fan-out line 127, thereby enabling the sharing of data signals between the main display screen 11 and the secondary display screen 12.

[0060] In some examples, such as Figure 3 As shown, the main display screen 11 and the secondary display screen 12 of the watch 10 are driven by the same driver chip 13. Therefore, the first control signal line 122 of the secondary display screen 12 needs to be connected to the driver chip 13. A first scanning fan-out line 125 is also provided in the first bezel area 16 of the secondary display screen 12 and the main display screen 11. It can be understood that the first scanning fan-out line 125 includes multiple fan-out lines, and each of the multiple fan-out lines of the first scanning fan-out line 125 is connected to a corresponding control signal line of the first control signal line 122. The other end of the first scanning fan-out line 125 is connected to the driver chip 13. The first scanning fan-out line 125 extends from the outer bezel area 19 of the secondary display screen 12, across the secondary display screen display area 17 and the inner bezel area 18, through the connection area 14, and along the first bezel area 16 of the main display screen 11. The signal line length is relatively long, resulting in a large voltage drop.

[0061] Moreover, such as Figure 3 As shown, in region S1 of the secondary display screen 12, which is farther from the main display screen 11 than the connection area 14, the first scan fan-out line 125 extends across the secondary display screen display area 17 to the connection area 14. Furthermore, in region S1, both the first scan signal line Gate1 and the fourth fan-out line 124 extend across the secondary display screen display area 17 to the connection area 14. Therefore, in region S1, there is a problem of multiple signal lines arranged in parallel, which can easily cause signal crosstalk.

[0062] Furthermore, to prevent the first scan fan-out line 125 and the fourth fan-out line 124 from intersecting with other signal lines (such as the first data signal line Data1) in the sub-display area 17, the first scan fan-out line 125 and the fourth fan-out line 124 need to be placed on a different film layer than the other signal lines in the sub-display area 17. For example, the first data signal line Data1 in the sub-display area 17 is located in the source / drain metal layer, and the first scan fan-out line 125 and the fourth fan-out line 124 are placed in the shielding layer. Therefore, signal line switching is required between the source / drain metal layer and the shielding layer, which further exacerbates the problem of large signal line voltage drop.

[0063] Based on this, such as Figure 4 , Figure 5 and Figure 6 As shown, some embodiments of this disclosure provide a display panel 100, which includes a first display portion 101, a second display portion 102, and a binding portion 103. The first display portion 101 extends in an arc shape in a flattened state, surrounds the second display portion 102 in an enclosed state, and has an angle with the second display portion 102.

[0064] For example, Figure 5 This is a structural diagram of the display panel 100 in a flattened state (the first display section 101 in a flattened state); Figure 6 This is a structural diagram of the display panel 100 with the first display unit 101 in its enclosed state, that is, a structural diagram of the first display unit 101 in its enclosed state. The first display unit 101 and the second display unit 102 can display images.

[0065] like Figure 5 As shown, the first display unit 101 and the second display unit 102 are connected, as follows: Figure 6 As shown, the first display part 101 can be bent to enclose the second display part 102, so that the first display part 101 can surround the second display part 102, and the first display part 101 and the second display part 102 have an angle.

[0066] It is understandable that, such as Figure 7 As shown, both the first display unit 101 and the second display unit 102 include a display surface M1 and a non-display surface N1 disposed opposite to each other. For example, after the first display unit 101 surrounds the second display unit 102, the included angle α between the non-display surface N1 of the first display unit 101 and the non-display surface N1 of the second display unit 102 can be 90°, 120°, 135° or 150°, etc., and the embodiments of this disclosure do not specifically limit this.

[0067] For example, in Figure 5 When displaying the display surface M1 of the first display unit 101 and the second display unit 102, Figure 5 The arrow Z in the diagram indicates the direction in which the two sides of the first display section 101 converge. In other words, the two sides of the first display section 101 are bent along the direction of arrow Z to form a shape like... Figure 6 The structure shown.

[0068] like Figure 5 As shown, the binding part 103 is connected to one side of the second display part 102.

[0069] For example, such as Figure 5As shown, the top end of the second display unit 102 is connected to the first display unit 101, and the binding part 103 is connected to the lower end of the second display unit 102. The second display unit 102 includes opposing display surfaces M1 and non-display surfaces N1 (e.g., ...). Figure 7 As shown, the binding part 103 can be bent to the non-display surface N1 of the second display part 102 to reduce the influence of the binding part 103 on the bezel width of the display panel 100, which is beneficial to achieving the goal of narrow bezel of the display panel 100.

[0070] like Figure 5 As shown, the first display unit 101 has a first display area AA1 and a first peripheral area BB1, with the first peripheral area BB1 located at the arc-shaped end of the first display unit 101. The first display unit 101 includes a plurality of first sub-pixels P1 disposed in the first display area AA1 and arranged in multiple rows and columns. Each row of first sub-pixels P1 is arranged along a first direction X, and each column of first sub-pixels P1 is arranged along a second direction Y. The first direction X is the radial direction of the arc, and the second direction Y is the extension direction of the arc.

[0071] For example, the first direction X is perpendicular to the second direction Y.

[0072] The display panel 100 further includes a first scan signal line GL1, a first data signal line DL1, and a first gate driving circuit 40. The first scan signal line GL1 extends generally along a second direction Y and is connected to at least one column of first sub-pixels P1. The first data signal line DL1 extends generally along a first direction X and is connected to at least one row of first sub-pixels P1. The first gate driving circuit 40 is disposed in a first peripheral region BB1 and is connected to the first scan signal line GL1.

[0073] For example, Figure 5 A first scan signal line GL1 is shown connected to a column of first sub-pixels P1. The first scan signal line GL1 is used to transmit gate signals to the first sub-pixels P1. A first data signal line DL1 is connected to a row of first sub-pixels P1. The first data signal line DL1 is used to transmit data signals to the first sub-pixels P1.

[0074] In the embodiments of this disclosure, by placing the first gate driving circuit 40 in the first peripheral region BB1, which is located at the arc-shaped end of the first display section 101, the first gate driving circuit 40 is placed at the arc-shaped end of the first display section 101. This eliminates the need to occupy the space of the inner and outer bezels of the first display area AA1, thereby narrowing the side bezels of the first display section 101 and achieving a better display effect. Furthermore, since the first data signal line DL1 extends approximately along the first direction X, which is the radial direction of the arc, the extension length of the first data signal line DL1 is shortened, reducing the voltage drop during signal transmission.

[0075] In some embodiments, such as Figure 5 As shown, the first display unit 101 includes a connecting sub-part 1011 and two extending sub-parts 1012. The connecting sub-part 1011 is connected to one side of the second display unit 102 and is located on opposite sides of the second display unit 102, respectively, along with the binding part 103. The two extending sub-parts 1012 are respectively connected to both ends of the connecting sub-part 1011.

[0076] The display panel 100 further includes two adapter sections 104, each adapter section 104 being connected between an extension sub-section 1012 and a second display section 102. The adapter section 104 is stretchable and deformable, and includes a data signal adapter cable 106, through which a first data signal line DL1 located in the two extension sub-sections 1012 is connected to a bonding section 103.

[0077] For example, such as Figure 5 As shown, the two adapter sections 104 are the first adapter section 1041 and the second adapter section 1042, respectively. The two extension subsections 1012 are the first extension subsection 112A and the second extension subsection 112B, respectively. The first extension subsection 112A is connected to the second display section 102 through the first adapter section 1041, and the first data signal line DL1 of the first extension subsection 112A is connected to the bonding section 103 through the data signal conversion cable 106 of the first adapter section 1041. The second extension subsection 112B is connected to the second display section 102 through the second adapter section 1042, and the first data signal line DL1 of the second extension subsection 112B is connected to the bonding section 103 through the data signal conversion cable 106 of the second adapter section 1042.

[0078] For example, the adapter 104 can be stretched and deformed, and the adapter 104 can be bent to the non-display surface N1 of the second display section 102 (e.g., Figure 7 (As shown), to reduce the impact of the adapter 104 on the bezel width. Moreover, the adapter 104 has stretchability, which allows the first display part 101 and the second display part 102 to fit better, and the display panel 100 to have a better display effect.

[0079] In the embodiments of this disclosure, by setting the data signal conversion cable 106 of the adapter 104, the first data signal line DL1 does not need to be fully connected to the multiplexing circuit and then connected to the second data signal line Data of the second display unit 102. Instead, the connection between the first data signal line DL1 and the binding unit 103 can be achieved through a shorter signal line. As a result, the transmission path of the data signal transmitted from the binding unit 103 to the first sub-pixel P1 of the extension sub-unit 1012 is greatly shortened, which is beneficial to reducing the voltage drop of signal transmission.

[0080] In some embodiments, such as Figure 5As shown, the second display unit 102 includes a second display area AA2 and a second peripheral area BB2 surrounding the second display area AA2. The second display area AA2 is provided with a plurality of second sub-pixels P2, with each column of second sub-pixels P2 arranged along a third direction T and each row of second sub-pixels P2 arranged along a fourth direction W. For example, the third direction T and the fourth direction W are perpendicular to each other.

[0081] The second display unit 102 includes a second data signal line DL2 and a second scan signal line GL2, wherein one second data signal line DL2 is connected to at least one column of second sub-pixels P2. Figure 5 This illustrates a scenario where a second data signal line DL2 is connected to a column of second sub-pixels P2. A second scan signal line GL2 is connected to at least one row of second sub-pixels P2. Figure 5 This illustrates a scenario where a second scan signal line GL2 is connected to a row of second sub-pixels P2.

[0082] The second peripheral region BB2 is provided with a second gate driving circuit 50, which includes multiple cascaded shift registers GOA2. The second scan signal line GL2 is connected to the shift registers GOA2 of the second gate driving circuit 50, and the second gate driving circuit 50 is connected to the bonding part 103. The shift registers GOA2 of the second gate driving circuit 50 are used to provide gate driving signals to the second sub-pixel P2.

[0083] In some embodiments, such as Figure 5 As shown, the second display unit 102 has a second peripheral area BB2. The second display unit 102 includes a first fan-out line 111 provided in the second peripheral area BB2, and a data signal conversion cable 106 is connected to the bonding unit 103 through the first fan-out line 111.

[0084] For example, such as Figure 5 As shown, the first data signal line DL1 is connected to the data signal conversion cable 106 of the conversion unit 104. The data signal conversion cable 106 is connected to the binding unit 103 through the first fan-out line 111, so as to realize the purpose of the binding unit 103 to transmit data signals to the first data signal line DL1.

[0085] In some embodiments, such as Figure 5 As shown, the display panel 100 further includes a transition section 107, connected between the connection sub-section 1011 and the second display section 102. The transition section 107 includes a multiplexer circuit 108, and a first data signal line DL1 located in the connection sub-section 1011 is connected to the multiplexer circuit 108. The second display section 102 further includes a second data signal line DL2, one end of which is connected to the multiplexer circuit 108, and the other end is connected to the bonding section 103.

[0086] The embodiments provided in this disclosure transmit data signals by connecting a plurality of first sub-pixels P1 of the first display unit 101 to the bonding unit 103 in two ways. The plurality of first sub-pixels P1 of the connecting sub-unit 1011 transmit data signals via the multiplexing circuit 108 of the transition unit 107. The plurality of first sub-pixels P1 of the extension sub-unit 1012 transmit data signals by connecting the bonding unit 103 via the data signal adapter cable 106 of the adapter unit 104. The plurality of first sub-pixels P1 of the extension sub-unit 1012 can be directly connected to the bonding unit 103 via the data signal adapter cable 106, without needing the multiplexing circuit 108; this arrangement reduces the voltage drop of the signal lines.

[0087] In some examples, such as Figure 5 As shown, the display panel 100 also includes a fourth fan-out line 124, through which the first data signal line DL1 is connected to the multiplexing circuit 108. The second display unit 102 also includes a fifth fan-out line 126 located in the second peripheral area BB2, through which the multiplexing circuit 108 is connected to the second data signal line DL2. The second display unit 102 also includes a second fan-out line 127 located in the second peripheral area BB2, through which the second data signal line DL2 is connected to the bonding unit 103. Through the above design, the data signals of the first sub-pixel P1 of the connecting sub-unit 1011 and the second sub-pixel P2 of the second display area AA2 are shared.

[0088] For example, the display panel 100 includes: a substrate, and a pixel circuit stack and a light-emitting device stack disposed sequentially on the substrate.

[0089] The pixel circuit stack includes: a shielding layer, a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer, a second source / drain metal layer, a third source / drain metal layer, and an ITO (indium tin oxide) layer, which are sequentially stacked along the direction away from the substrate.

[0090] The stack of light-emitting devices includes: an anode layer, a pixel defining layer, a light-emitting functional layer, and a cathode layer.

[0091] It should be noted that an insulating layer is provided between the shielding layer, the semiconductor layer, the first gate metal layer, the second gate metal layer, the first source / drain metal layer, the second source / drain metal layer, the third source / drain metal layer, the ITO layer, and the anode layer, and the film layers that need to be connected are connected through vias that penetrate the insulating layer.

[0092] For example, multiple fourth fan-out lines 124 can be disposed in the shielding layer, the third source / drain metal layer, and the ITO layer, and multiple fifth fan-out lines 126 can be disposed in the shielding layer, the third source / drain metal layer, and the ITO layer, so as to avoid multiple fourth fan-out lines 124 and multiple fifth fan-out lines 126 being located in the same film layer, so as to effectively prevent signal crosstalk caused by the dense arrangement of fourth fan-out lines 124 and fifth fan-out lines 126.

[0093] In some examples, the transition section 107 includes a plurality of multiplexer circuits 108, each multiplexer circuit 108 being connected to a first data signal line DL1 and N second data signal lines DL2, where N is an integer greater than or equal to 2.

[0094] For example, the control mode of the multiplexing circuit 108 can be 1:2, 1:3, 1:4, 1:6 or 1:8, etc. That is, one multiplexing circuit 108 can realize the connection between one first data line DL1 of the connecting sub-section 1011 and two, three, four, six or eight data signal lines DL2 of the second display section 102. The embodiments of this disclosure do not limit this.

[0095] For example, the value of N can be 2, 3, 4, 6 or 8, etc., and there is no limit here.

[0096] In some examples, all of the multiple second data signal lines DL2 of the second display unit 102 are connected to the multiplexing circuit 108, or some of the multiple second data signal lines DL2 of the second display unit 102 are connected to the multiplexing circuit 108, and there is no limitation here.

[0097] In some embodiments, such as Figure 5 As shown, the two extended sub-sections 1012 are symmetrically arranged with respect to the first center line L1, and the data signal conversion lines 106 of the two conversion sections 104 are symmetrically arranged with respect to the first center line L1.

[0098] For example, such as Figure 5 As shown, two extension sub-parts 1012 are symmetrically arranged at both ends of the connecting sub-part 1011. The line of symmetry between the two extension sub-parts 1012 is the first center line L1. The first adapter 1041 and the second adapter 1042 are symmetrically arranged with respect to the first center line L1. Furthermore, the data signal adapter cable 106 of the first adapter 1041 and the data signal adapter cable 106 of the second adapter 1042 are symmetrically arranged with respect to the first center line L1. This symmetrical arrangement is beneficial for manufacturing processes and can improve display quality.

[0099] In some embodiments, such as Figure 5As shown, the first display unit 101 further includes a third control signal line 109, which is disposed in the first peripheral region BB1 and extends substantially along the first direction X. The third control signal line 109 is connected to the first gate drive circuit 40 and the bonding unit 103.

[0100] For example, such as Figure 5 As shown, the third control signal line 109 includes multiple control signal lines, including: multiple clock signal lines (e.g., first clock signal line CLCK1 and second clock signal line CLCK2), a first voltage bus VGH, a second voltage bus VGL, a start signal line, and a reset signal line, etc., without limitation. The third control signal line 109 is used to transmit control signals to the first gate drive circuit 40. The control signals include at least one of the following signals: a clock signal provided by the clock signal line, a high voltage signal provided by the first voltage bus VGH, a low voltage signal provided by the second voltage bus VGL, a start signal provided by the start signal line, and a reset signal provided by the reset signal line.

[0101] In some embodiments, such as Figure 5 As shown, when the display panel 100 also includes an adapter 104, the adapter 104 includes a control signal adapter cable 105, and the third control signal line 109 is connected to the bonding part 103 through the control signal adapter cable 105.

[0102] For example, such as Figure 5 As shown, the first gate drive circuit 40 is connected to the third control signal line 109. The third control signal line 109 includes multiple control signal lines, such as multiple clock signal lines (e.g., the first clock signal line CLCK1 and the second clock signal line CLCK2), a first voltage bus VGH, a second voltage bus VGL, a start signal line, and a reset signal line, etc., without limitation. Correspondingly, the control signal adapter line 105 may include multiple adapter lines, which are connected one-to-one with the multiple control signal lines included in the third control signal line 109, for transmitting corresponding control signals to the first gate drive circuit 40.

[0103] For example, the control signal adapter cable 105 includes a first clock signal adapter cable, a first voltage adapter cable, and a reset signal adapter cable. The first clock signal adapter cable connects the first clock signal line CLCK1 and the bonding part 103 to transmit a clock signal. The first voltage adapter cable connects the first voltage bus VGH and the bonding part 103 to transmit a high-voltage signal. The reset signal adapter cable connects the reset signal line and the bonding part 103 to transmit a reset signal.

[0104] In some embodiments, such as Figure 5As shown, the second display unit 102 has a second peripheral area BB2, and the second display unit 102 includes a third fan-out line 110 disposed in the second peripheral area BB2. The control signal transfer line 105 is connected to the bonding unit 103 through the third fan-out line 110.

[0105] For example, such as Figure 5 As shown, the third fan-out line 110 includes multiple fan-out lines, and the multiple fan-out lines of the third fan-out line 110 are connected one-to-one with the multiple adapter lines of the control signal adapter line 105. The multiple fan-out lines of the third fan-out line 110 are connected to the binding part 103.

[0106] The embodiments of this disclosure achieve the connection between the bonding part 103 and the first gate driving circuit 40 by setting the control signal transfer line 105 of the adapter part 104, which is used to transmit control signals to the first gate driving circuit 40. The first gate driving circuit 40 is connected to a plurality of first sub-pixels P1 and is used to provide gate signals to the plurality of first sub-pixels P1.

[0107] Furthermore, the third control signal line 109 can be directly connected to the second peripheral area BB2 of the second display unit 102 via the control signal adapter line 105 of the adapter unit 104, and then connected to the bonding unit 103 via the third fan-out line 110. This eliminates the need for signal lines (e.g., the first scan fan-out line 125) that connect to the bonding unit 103 only from the second peripheral area BB2 of the first display unit 101 to the second display unit 102. Figure 3 As shown, this shortens the length of the signal line connecting the third control signal line 109 and the bonding part 103, thereby reducing the signal voltage drop.

[0108] In some embodiments, such as Figure 5 As shown, the first display unit 101 has two first peripheral regions BB1, which are located at the two ends of the arc formed by the first display unit 101. The first display unit 101 includes two first gate driving circuits 40, which are located in the two first peripheral regions BB1.

[0109] The first display section 101 has two arc-shaped ends, such as Figure 5 As shown, both ends of the arc formed by the first display section 101 are first peripheral areas BB1. For example, the first peripheral area BB1 at the left end of the arc formed by the first display section 101 is called the left peripheral area BB11, and the first peripheral area BB1 at the right end of the arc formed by the first display section 101 is called the right peripheral area BB12. The first gate driving circuit 40 can be disposed in the left peripheral area BB11, or the right peripheral area BB12, or simultaneously disposed in the left peripheral area BB11 and the right peripheral area BB12; Figure 5 The diagram shows the case where the first gate drive circuit 40 is simultaneously located in the left peripheral region BB11 and the right peripheral region BB12.

[0110] In some embodiments, such as Figure 5 As shown, each first gate drive circuit 40 includes a plurality of cascaded shift registers GOA1. Each first scan signal line GL1 extends from one of the first peripheral regions BB1 to another first peripheral region BB1, and each end of the first scan signal line GL1 is connected to a shift register GOA1.

[0111] For example, such as Figure 5 As shown, the first peripheral region BB1 includes a left peripheral region BB11 and a right peripheral region BB12, both of which are provided with a first gate drive circuit 40. Each first scan signal line GL1 extends from the left peripheral region BB11 to the right peripheral region BB12. The left end of the first scan signal line GL1 is connected to a shift register GOA1 of the left peripheral region BB11, and the right end of the first scan signal line GL1 is connected to a shift register GOA1 of the right peripheral region BB12.

[0112] The embodiments of this disclosure effectively solve the problem of gate signal transmission delay by setting a first scan signal line GL1 connected to two shift registers GOA1, ensuring the driving effect of shift register GOA1 on the first sub-pixel P1, and improving the display effect of the first display unit 101.

[0113] In other examples, in at least one column of first sub-pixels P1, the left half of the first sub-pixels P1 is connected to the shift register GOA1 of the left peripheral area BB11, and the right half of the first sub-pixels P1 in at least one column of first sub-pixels P1 is connected to the shift register GOA1 of the right peripheral area BB12, so that at least one column of first sub-pixels P1 is controlled by two shift registers GOA1 respectively. Since each shift register GOA1 only needs to control half of the first sub-pixels P1 in each column of first sub-pixels P1, the problem of gate signal transmission delay can be reduced.

[0114] In some embodiments, such as Figure 5 As shown, the adapter 104 is provided with multiple openings K. When the display panel 100 includes a data signal adapter cable 106, the data signal adapter cable 106 is arranged to avoid the multiple openings K. When the display panel 100 includes a control signal adapter cable 105, the control signal adapter cable 105 is arranged to avoid the multiple openings K.

[0115] The multiple openings K in the adapter 104 help reduce the stress on the adapter 104 during tensile deformation, reduce the risk of bending damage to the adapter 104, and reduce the risk of breakage of the control signal adapter cable 105 and the data signal adapter cable 106.

[0116] For example, the shape of the opening K can be any shape, such as a circle, ellipse, rectangle, square, parallelogram, trapezoid, etc., and the embodiments of this disclosure do not specifically limit it in this way. It is understood that... Figure 5 The shape and distribution of the openings shown are merely illustrative, and this application does not specifically limit the distribution of the openings K.

[0117] For example, the control signal adapter cable 105 and the data signal adapter cable 106 can be bent, which can effectively prevent the adapter cables from breaking.

[0118] For example, the adapter 104 includes a shielding layer and a third source / drain metal layer, etc. The data signal adapter 106 can be disposed on different metal layers and connected in parallel to reduce resistance.

[0119] In some embodiments, such as Figure 8 As shown, multiple first sub-pixels P1 are arranged radially. This facilitates the connection of the first data signal line DL1 to at least one row of first sub-pixels P1, and the first scan signal line GL1 to at least one column of first sub-pixels P1.

[0120] In some examples, such as Figure 8 As shown, along the first direction X, relatively away from the second display unit 102 (e.g. Figure 5 The arrangement density of the first sub-pixel P1 in a column (as shown) is less than or equal to that of the sub-pixel P1 closest to the second display section 102 (as shown). Figure 5 The arrangement density of the first sub-pixel P1 in a column (as shown).

[0121] For example, when the included angle α between the non-display surface N1 of the first display unit 101 and the non-display surface N1 of the second display unit 102 is 90°, a surface relatively far from the second display unit 102 (e.g., ...) can be provided. Figure 5 The arrangement density of the first sub-pixel P1 in a column (as shown) is equal to that of the sub-pixel P1 closest to the second display section 102 (as shown). Figure 5 The arrangement density of the first sub-pixel P1 in a column (as shown).

[0122] When the included angle α between the non-display surface N1 of the first display unit 101 and the non-display surface N1 of the second display unit 102 is greater than 90°, it is possible to set the surface relatively far away from the second display unit 102 (e.g., Figure 5 The arrangement density of the first sub-pixel P1 in a column (as shown) is smaller than that of the one relatively close to the second display section 102 (as shown). Figure 5 The arrangement density of the first sub-pixel P1 in a column (as shown).

[0123] In some embodiments, such as Figure 5 As shown, the display panel 100 also includes a driver chip 200, which is disposed on the bonding part 103 and configured to transmit signals to the bonding part 103.

[0124] For example, the driver chip 200 is used to provide a drive signal for display to the first display unit 101 and the second display unit 102. For example, the drive signal includes: power supply voltage signal (including high voltage signal and low voltage signal, etc.), data signal, start signal and clock signal, etc.

[0125] like Figure 9 As shown, some embodiments of this disclosure also provide a wearable electronic device 1000, which includes a display panel 100 as provided in any of the above embodiments. The wearable electronic device 1000 further includes a wearable structure 60 connected to the display panel 100, and the wearable structure 60 is configured to be worn on a human body.

[0126] For example, the wearable electronic device 1000 can be a watch, and the wearable structure 60 can be the watch strap.

[0127] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, characterized by, The display panel comprises: a first display part and a second display part, the first display part extends in an arc shape in a flat state, surrounds the second display part in an enclosed state, and has an included angle with the second display part; a binding part connected to one side of the second display part; wherein the first display part has a first display area and a first peripheral area, the first peripheral area is located at the end of the arc shape of the first display part; the first display part comprises: a plurality of first sub-pixels arranged in multiple rows and multiple columns in the first display area, each row of first sub-pixels is arranged along a first direction, and each column of first sub-pixels is arranged along a second direction; the first direction is the radial direction of the arc shape, and the second direction is the extension direction of the arc shape; a first scan signal line extending substantially along the second direction and connected to at least one column of first sub-pixels; a first data signal line extending substantially along the first direction and connected to at least one row of first sub-pixels; a first gate drive circuit arranged in the first peripheral area and connected to the first scan signal line.

2. The display panel of claim 1, wherein, The first display part comprises: a connecting sub-part connected to one side of the second display part and located on opposite sides of the second display part with the binding part respectively; two extension sub-parts connected to the two ends of the connecting sub-part respectively; The display panel further comprises two adapter parts, each adapter part is connected between one of the extension sub-parts and the second display part; the adapter part can be stretched to deform, the adapter part comprises a data signal adapter line, the first data signal line located in the two extension sub-parts is connected with the binding part through the data signal adapter line.

3. The display panel of claim 2, wherein, The second display part has a second peripheral area; The second display part comprises a first fan-out line arranged in the second peripheral area, and the data signal adapter line is connected with the binding part through the first fan-out line.

4. The display panel of claim 3, wherein, The display panel further comprises a transition part connected between the connecting sub-part and the second display part; The transition part comprises a multiplexing circuit, the first data signal line located in the connecting sub-part is connected with the multiplexing circuit; The second display part further comprises a second data signal line, one end of the second data signal line is connected with the multiplexing circuit, and the other end is connected with the binding part.

5. The display panel of claim 4, wherein, The transition part comprises a plurality of multiplexing circuits, each multiplexing circuit is connected with one first data signal line and N second data signal lines, N is an integer greater than or equal to 2.

6. The display panel of claim 4, wherein, The second display part comprises a second fan-out line arranged in the second peripheral area, and the second data signal line is connected with the binding part through the second fan-out line.

7. The display panel of claim 2, wherein, The two extension sub-parts are symmetrically arranged relative to a first middle line, and the data signal adapter lines of the two adapter parts are symmetrically arranged relative to the first middle line.

8. The display panel of claim 1, wherein, The first display part further comprises: a third control signal line arranged in the first peripheral area and extending substantially along the first direction; the third control signal line is connected with the first gate drive circuit and the binding part.

9. The display panel of claim 8, wherein, In the case that the display panel further comprises a transition part, the transition part comprises a control signal transition line, and the third control signal line is connected to the binding part through the control signal transition line.

10. The display panel of claim 9, wherein, The second display part has a second peripheral area; The second display part comprises a third fan-out line arranged in the second peripheral area, and the control signal transition line is connected to the binding part through the third fan-out line.

11. The display panel of claim 1, wherein, The first display part has two first peripheral areas, respectively located at two ends of the arc shape of the first display part; The first display part comprises two first gate drive circuits, respectively located at the two first peripheral areas; Each first gate drive circuit comprises a plurality of shift registers connected in cascade; Each first scan signal line extends from one of the first peripheral areas to the other first peripheral area, and two ends of the first scan signal line are connected to one of the shift registers, respectively.

12. The display panel of claim 2, wherein, The transition part is provided with a plurality of openings; in the case that the display panel comprises a data signal transition line and a control signal transition line, the data signal transition line and the control signal transition line are arranged to avoid the plurality of openings.

13. The display panel of claim 2, wherein, The second display part comprises opposite display surface and non-display surface, the binding part can be bent to the non-display surface of the second display part, and the transition part can be bent to the non-display surface of the second display part.

14. The display panel of claim 1, wherein, The plurality of first sub-pixels are arranged radially.

15. A wearable electronic device, comprising: Comprise: The display panel according to any one of claims 1-14; Wearing structure, connected with the display panel, the wearing structure is configured to be wearable on the human body.

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