Optical proximity correction method and system, mask, device and storage medium

Abstract

An optical proximity correction method and system, mask, device, and storage medium are disclosed. The optical proximity correction method includes: obtaining a first layer, including multiple first design graphics, wherein the distance between any two first design graphics is a first spacing, and at least one first spacing is less than the minimum spacing for photolithography; performing a layer splitting process to split the first layer into multiple sub-layers, and respectively placing the first design graphics on one of the sub-layers, wherein the graphic layout of the sub-layers after superposition is the same as the graphic layout of the first layer, wherein in the sub-layers, the distance between any two first design graphics is a second spacing, which is greater than the first spacing, and at least one second spacing is less than the minimum spacing for photolithography; and changing the graphic layout of the first design graphics in the sub-layers so that in each sub-layer, the distance between any two first design graphics is greater than or equal to the minimum spacing for photolithography. The present invention saves process costs.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to an optical proximity correction method and system, a mask, a device, and a storage medium. Background Art

[0002] Photolithography is a crucial technology in semiconductor manufacturing, enabling the transfer of patterns from a mask onto the surface of a silicon wafer, creating semiconductor products that meet design requirements. The photolithography process begins with an exposure step, where light passes through the light-transmitting areas of the mask onto a silicon wafer coated with photoresist, reacting photochemically with the photoresist. Next, a development step utilizes the solubility of the developer in the photosensitive and unsensitive photoresists to form a photoresist pattern, enabling the transfer of the mask pattern. Finally, an etching step involves etching the silicon wafer based on the pattern formed in the photoresist layer, further transferring the mask pattern to the wafer.

[0003] The accuracy of the photolithography process directly impacts the yield of semiconductor products. Errors in the photolithography process primarily include exposure and development errors, as well as etching errors. With the rapid advancement of integrated circuit design, mask layouts are shrinking in size, leading to an increasing incidence of the optical proximity effect. This refers to the process during the exposure and development steps where light passes through the transparent areas of the mask and forms the mask pattern on the photoresist layer on the silicon wafer. The resulting photolithographic pattern exhibits distortion and deviation compared to the mask layout, known as exposure and development errors. Furthermore, depending on the photolithographic pattern, etching the silicon wafer using chemical or physical etching also involves certain errors, known as etching errors. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide an optical proximity correction method and system, a mask, a device and a storage medium, so as to save process costs.

[0005] To solve the above problem, an embodiment of the present invention provides an optical proximity correction method, comprising: obtaining a first plate layer, the first plate layer including a plurality of first design graphics, the distance between any two of the first design graphics being a first spacing, and at least one of the first spacings being smaller than a minimum spacing for photolithography; performing plate layer splitting processing to split the first plate layer into a plurality of sub-plate layers, and respectively arranging each of the first design graphics on one of the sub-plate layers, wherein a graphic layout after superimposing the plurality of sub-plate layers is the same as a graphic layout in the first plate layer, wherein in the sub-plate layers, the distance between any two of the first design graphics being a second spacing, the second spacing being larger than the first spacing, and at least one of the second spacings being smaller than the minimum spacing for photolithography; and changing the graphic layout of the first design graphics in the sub-plate layers so that in each of the sub-plate layers, the distance between any two of the first design graphics is greater than or equal to the minimum spacing for photolithography.

[0006] Accordingly, an embodiment of the present invention further provides an optical proximity correction system, comprising: a layout providing module, configured to obtain a first layout layer, wherein the first layout layer comprises a plurality of first design graphics, wherein the distance between any two of the first design graphics is a first spacing, and at least one of the first spacings is smaller than the minimum spacing that can be photolithographically performed; a layout layer splitting module, configured to split the first layout layer into a plurality of sub-layout layers, and respectively arrange each of the first design graphics on one of the sub-layout layers, wherein the graphic layout after superimposing the plurality of sub-layout layers is the same as the graphic layout in the first layout layer, wherein in the sub-layout layers, the distance between any two of the first design graphics is a second spacing, wherein the second spacing is larger than the first spacing, and at least one of the second spacings is smaller than the minimum spacing that can be photolithographically performed; and a graphic layout changing module, configured to change the graphic layout of the first design graphics in the sub-layout layers, so that in each of the sub-layout layers, the distance between any two of the first design graphics is larger than or equal to the minimum spacing that can be photolithographically performed.

[0007] Correspondingly, an embodiment of the present invention further provides a mask, including a pattern obtained by using the optical proximity correction method provided by an embodiment of the present invention.

[0008] Accordingly, an embodiment of the present invention also provides a device comprising at least one memory and at least one processor, wherein the memory stores one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the optical proximity correction method provided in an embodiment of the present invention.

[0009] Correspondingly, an embodiment of the present invention further provides a storage medium, wherein the storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement the optical proximity correction method provided by the embodiment of the present invention.

[0010] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0011] In the optical proximity correction method provided by an embodiment of the present invention, in the step of obtaining a first layout layer, the distance between any two first design patterns is a first spacing, and at least one of the first spacings is less than the minimum spacing for photolithography. After the layout splitting process, the distance between any two first design patterns is a second spacing, and the second spacing is greater than the first spacing, and at least one of the second spacings is less than the minimum spacing for photolithography. By changing the graphic layout of the first design patterns, the distance between any two first design patterns is greater than or equal to the minimum spacing for photolithography. Compared to a solution in which the first layout layer is split into multiple sub-layout layers through layout splitting only, and the distance between any two first design patterns in a sub-layout layer is greater than or equal to the minimum spacing for photolithography, the embodiment of the present invention appropriately increases the distance between any two first design patterns through the layout splitting process. This allows the distance between any two first design patterns to be greater than or equal to the minimum spacing for photolithography by changing the graphic layout of the first design patterns in the sub-layout layer. This reduces the number of sub-layout layers required for the layout splitting process, thereby enabling photolithography of the first design patterns and saving process costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a flow chart of an optical proximity correction method;

[0013] Figures 2 to 3 is a schematic diagram corresponding to each step in an optical proximity correction method;

[0014] Figure 4 is a flow chart of an embodiment of an optical proximity correction method of the present invention;

[0015] Figures 5 to 10 1 is a schematic diagram corresponding to each step in an embodiment of an optical proximity correction method of the present invention;

[0016] Figure 11 is a functional block diagram of an embodiment of an optical proximity correction system of the present invention;

[0017] Figure 12 It is a hardware structure diagram of an embodiment of the device provided by the present invention. DETAILED DESCRIPTION

[0018] Currently, it is difficult to save process costs. This paper analyzes the reasons why it is difficult to save process costs by combining an optical proximity correction method.

[0019] Figure 1 This is a flow chart of an optical proximity correction method. Figure 2 and Figure 3 , which shows a schematic diagram corresponding to each step in the optical proximity correction method, the optical proximity correction method includes:

[0020] refer to Figure 2 , Figure 2 This is a schematic diagram corresponding to step st1. Step st1: obtain a plate layer (not shown), the plate layer includes multiple design graphics 10, the distance between any two design graphics 10 is a first spacing s1, and at least one first spacing s1 is smaller than the minimum spacing that can be photolithographically processed.

[0021] The design pattern 10 includes a contact hole pattern or an interconnection via pattern.

[0022] Contact hole patterns are used to form contact holes on the wafer, thereby forming contact plugs. Interconnection via patterns are used to form interconnection vias on the wafer, thereby forming an interconnection via structure. Typically, contact hole patterns or interconnection via patterns are numerous and densely packed in a layout layer. Therefore, the distance between any two contact hole patterns or interconnection via patterns is usually small.

[0023] refer to Figure 3 , Figure 3 This is a schematic diagram corresponding to step st2. Step st2: perform a plate layer splitting process to split the plate layer into multiple sub-plate layers (not shown), and set each design graphic 10 on one of the sub-plate layers. The graphic layout after the multiple sub-plate layers are superimposed is the same as the graphic layout in the plate layer. In the sub-plate layer, the distance s2 between any two design graphics 10 is greater than or equal to the minimum spacing that can be photolithographically processed.

[0024] in, Figure 3 It shows the graphic layout after multiple sub-layers are superimposed. Figure 3 In the figure, the design graphics 10 located in different sub-plate layers are indicated by different filling styles, and the design graphics 10 located in the same sub-plate layer are indicated by the same filling style.

[0025] In the layout layer, the distance between any two design graphics 10 is a first spacing s1. If at least one first spacing s1 is smaller than the minimum spacing that can be photolithographically processed, the photolithographic imaging of the design graphics 10 is prone to severe distortion, and there may even be cases where the design graphics 10 are difficult to be photolithographically processed, thereby causing a serious decline in the quality of the photolithographic graphics.

[0026] Therefore, the multi-patterning (MP) technology is used to split the layer, decomposing the design pattern 10 in the layer into multiple sub-layers, so that in each sub-layer, the distance between any two design patterns 10 is greater than or equal to the minimum spacing that can be photolithographically processed. Figure 3As shown, the version layer is split into 6 sub-version layers.

[0027] However, in order to achieve the effect that the distance between any two design graphics 10 in each sub-plate layer is greater than or equal to the minimum photolithographic spacing, it is usually necessary to split the plate layer into a larger number of sub-plate layers, resulting in a larger number of sub-plate layers and thus higher process costs.

[0028] If the template layers are not split, they need to be returned to the design company (design house) and the design graphic layout needs to be corrected, but this prolongs the manufacturing time of the mask and increases labor costs.

[0029] In order to solve the technical problem, an embodiment of the present invention provides an optical proximity correction method. Figure 4 , which shows a flow chart of an embodiment of the optical proximity correction method of the present invention.

[0030] In this embodiment, the optical proximity correction method includes the following basic steps:

[0031] Step ST1: Obtain a first layer, the first layer including a plurality of first design patterns, the distance between any two first design patterns being a first spacing, and at least one first spacing being smaller than a minimum spacing that can be photolithographically processed;

[0032] Step ST2: performing a layer splitting process, splitting the first layer into multiple sub-layers, and placing each first design graphic on one of the sub-layers. The graphic layout after the multiple sub-layers are superimposed is the same as the graphic layout in the first layer. In the sub-layers, the distance between any two first design graphics is a second spacing, which is greater than the first spacing, and at least one of the second spacings is less than the minimum spacing that can be photolithographically processed.

[0033] Step ST3: changing the graphic layout of the first design graphics in the sub-plate layer so that the distance between any two first design graphics in each sub-plate layer is greater than or equal to the minimum lithographic spacing.

[0034] Compared to a solution that only splits the first plate layer into multiple sub-plate layers through plate splitting processing so that the distance between any two first design graphics in the sub-plate layer is greater than or equal to the minimum spacing that can be photolithographically performed, the embodiment of the present invention appropriately increases the distance between any two first design graphics through plate layer splitting processing, so that in each sub-plate layer, by changing the graphic layout of the first design graphics in the sub-plate layer, the effect of the distance between any two first design graphics being greater than or equal to the minimum spacing that can be photolithographically performed can be achieved, thereby reducing the number of sub-plate layers required for plate layer splitting processing, and thus saving process costs while enabling the first design graphics to be photolithographically performed.

[0035] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0036] Figures 5 to 10 1 is a schematic diagram corresponding to each step in an embodiment of the optical proximity correction method of the present invention.

[0037] refer to Figure 5 , execute step ST1: obtain a first version layer (not shown), the first version layer includes multiple first design graphics 100, the distance between any two first design graphics 100 is a first spacing S1, and at least one first spacing S1 is smaller than the minimum spacing that can be photolithographically processed.

[0038] The first design pattern 100 is a first target pattern to be transferred onto the wafer. After optical proximity correction is performed on the first design pattern 100, the obtained pattern is used to make a mask, which is then used to perform a photolithography process to form a corresponding mask pattern on the wafer.

[0039] In this embodiment, the distance between any two first design patterns 100 is a first spacing S1. If at least one first spacing S1 is smaller than the minimum spacing that can be photolithographically processed, the photolithographic imaging of the first design patterns 100 is prone to severe distortion. There are even cases where the first design patterns 100 are difficult to be photolithographically processed, resulting in a serious decline in the quality of the photolithographic pattern. Therefore, the first spacing S1 needs to be increased subsequently so that all the first design patterns 100 can be photolithographically processed.

[0040] Here, the minimum photolithographic pitch refers to the minimum distance between any two first design patterns 100 when the first design patterns 100 can be photolithographically formed on a wafer during a photolithography process using a mask.

[0041] In this embodiment, the first design pattern 100 includes a contact hole pattern or an interconnection via pattern.

[0042] The contact hole pattern is used to form a contact hole on the wafer, and the contact hole is used to form a contact hole plug. The interconnection through-hole pattern is used to form an interconnection through-hole on the wafer, and the interconnection through-hole is used to form an interconnection through-hole structure. Usually, the number of contact hole patterns or interconnection through-hole patterns in the layout layer is large and relatively dense. Therefore, the distance between any two contact hole patterns or through-hole interconnection patterns is usually small.

[0043] As an example, the first design pattern 100 is an interconnection via pattern. The interconnection via structure is generally used to achieve electrical connection between two layers of metal lines.

[0044] To this end, in this embodiment, the step of obtaining the first version layer further includes: obtaining a second version layer (not labeled) and a third version layer (not labeled), the first version layer is located between the second version layer and the third version layer, and the second version layer includes a plurality of layers along the first direction (such as Figure 5 X direction) and extends along the second direction (as shown in FIG. Figure 5 The third layer includes a plurality of second metal line patterns 300 extending along the second direction and arranged along the first direction, and the interconnection through-hole pattern is located in the corresponding first metal line pattern 200 and / or second metal line pattern 300.

[0045] In the back-end process, the first metal line pattern 200 is used to form a first metal line on the wafer, and the second metal line pattern 300 is used to form a second metal line on the wafer.

[0046] In the semiconductor structure manufacturing process, an interconnection via structure is formed on the first metal line or the second metal line to achieve electrical connection between the first metal line or the second metal line and other structures, or to achieve electrical connection between the first metal line and the second metal line. Therefore, in this embodiment, in the layout layer, the interconnection via pattern is located in the corresponding first metal line pattern 200 and / or second metal line pattern 300.

[0047] refer to Figure 6 , executing step ST2: performing a layer splitting process, splitting the first layer into multiple sub-layers (not shown), and setting each first design graphic 100 on one of the sub-layers. The graphic layout after the multiple sub-layers are superimposed is the same as the graphic layout in the first layer. In the sub-layers, the distance between any two first design graphics 100 is a second spacing S2, which is greater than the first spacing S1, and at least one second spacing S2 is less than the minimum spacing that can be photolithographically processed.

[0048] in, Figure 6 It shows the graphic layout after multiple sub-layers are superimposed. Figure 6 In the figure, the first design graphics 100 located in different sub-plate layers are indicated by different filling styles, and the first design graphics 100 located in the same sub-plate layer are indicated by the same filling style.

[0049] In this embodiment, the layout layer splitting process uses multi-patterning (MP) technology to decompose the first design graphic 100 in the first layout layer into multiple sub-layout layers. If the graphic layout after the multiple sub-layout layers are superimposed is the same as the graphic layout in the first layout layer, the layout layer splitting process does not change the original graphic layout of the first layout layer.

[0050] Subsequently, the first design graphics 100 in each sub-plate layer needs to be translated separately. By translating the first design graphics 100, the distance between any two first design graphics 100 in the same sub-plate layer is greater than or equal to the minimum spacing that can be photolithographically processed. Before the translation, the plate layer is split first, and the first design graphics 100 in the first plate layer is decomposed into multiple sub-plate layers. The distance between any two first design graphics 100 is appropriately increased, which is conducive to reducing the difficulty of the subsequent translation process and ensuring that the translation process can be carried out smoothly.

[0051] Moreover, translation processing will be performed later. Therefore, the requirements for the plate layer splitting processing are relatively loose. It is not necessary to meet the requirement that the distance between any two first design graphics 100 in each sub-plate layer is greater than or equal to the minimum lithographic spacing. In this embodiment, in each sub-plate layer, the second spacing S2 is greater than the first spacing S1, and at least one second spacing S2 is less than the minimum lithographic spacing. Therefore, it is only necessary to appropriately increase the distance between any two first design graphics 100, thereby reducing the number of sub-plate layers required for the splitting processing and saving process costs.

[0052] In this embodiment, the plate layer splitting process is performed according to a preset threshold condition, where the threshold condition includes: the difference between the minimum lithographic pitch and the second pitch S2 is smaller than a preset value.

[0053] In this embodiment, corresponding preset values ​​are provided according to different graphic layouts so that after the sub-layer splitting process, the difference between the minimum lithographic pitch and the second pitch S2 is less than the preset value. This ensures that the spacing between adjacent first design graphics 100 in the sub-layer meets a certain standard and approaches the minimum lithographic pitch. This appropriately reduces the distance that needs to be adjusted for the first design graphics 100 during the subsequent translation process, thereby reducing the complexity of the subsequent translation process and improving the overall efficiency of the optical proximity correction process.

[0054] It should be noted that the preset value should not be too large or too small. If the preset value is too large, the requirements for the layout layer splitting process are too loose. In each sub-layout layer, the distance between any two first design graphics 100 is still small, resulting in a large distance that needs to be adjusted for the first design graphics 100 during subsequent translation processing, thereby increasing the amount of computation required for the translation processing and increasing the difficulty of the translation processing. If the preset value is too small, the requirements for the layout layer splitting process are too stringent, and too many sub-layout layers are required to ensure that the distance between any two first design graphics 100 in each sub-layout layer meets the threshold condition, which increases the time for the layout layer splitting process and increases the process cost. For this reason, in this embodiment, the preset value is 5nm to 10nm.

[0055] Combined with reference Figures 7 to 9, executing step ST3: changing the graphic layout of the first design graphics 100 in the sub-plate layer so that in each sub-plate layer, the distance between any two first design graphics 100 is greater than or equal to the minimum lithographic spacing.

[0056] It should be noted that for the convenience of illustration, Figures 7 to 9 For example, only the first design graphic 100 in one sub-plate layer is changed. For the steps of changing the graphic layout of the first design graphic 100 in other sub-plate layers, refer to Figures 7 to 9 The steps are not repeated in this embodiment.

[0057] Compared to a solution that only splits the first plate layer into multiple sub-plate layers through plate layer splitting processing so that the distance between any two first design graphics in the sub-plate layer is greater than or equal to the minimum pitch that can be photolithographically processed, this embodiment appropriately increases the distance between any two first design graphics 100 through plate layer splitting processing, so that in each sub-plate layer, by changing the graphic layout of the first design graphics 100 in the sub-plate layer, the distance between any two first design graphics 100 can be greater than or equal to the minimum pitch that can be photolithographically processed. This can reduce the number of sub-plate layers required for the plate layer splitting processing, thereby saving process costs while allowing the first design graphics 100 to be photolithographically processed.

[0058] In this embodiment, the graphic layout of the first design graphic 100 in each sub-plate layer is changed by performing translation processing on the first design graphic 100 in each sub-plate layer.

[0059] In this embodiment, the single translation direction includes one or both of a first direction and a second direction, and the first direction and the second direction are perpendicular to each other, wherein the first direction includes the +X direction or the -X direction, and the second direction includes the +Y direction or the -Y direction.

[0060] Among them, the +X direction or the -X direction is the opposite direction, and the +Y direction or the -Y direction is the opposite direction.

[0061] The single translation direction includes one or both of the first direction and the second direction, and the first direction and the second direction are perpendicular to each other, so that the position movement of the first design graphic 100 is more regular, avoiding excessive clutter due to graphic layout changes, thereby reducing changes to the circuit design.

[0062] In this embodiment, the step of performing translation processing on the first design graphics 100 in each sub-plate layer includes: performing one or more sub-processing in each sub-plate layer until the distance between any two first design graphics 100 is greater than or equal to the minimum lithographic spacing.

[0063] One or more sub-processings are used to ensure that the distance between any two first design graphics 100 is greater than or equal to the minimum photolithographic spacing requirement, thereby increasing the flexibility of the translation process operation. In each sub-plate layer, the number of sub-processings is adjusted according to different graphic layouts, so that the translation process can be adapted to each sub-plate layer, thereby increasing the operability of the translation process.

[0064] In this embodiment, the number of sub-processing is multiple, and the single translation direction of the previous sub-processing is the first direction, and the single translation direction of the next sub-processing is the second direction.

[0065] Usually, the number of first design graphics 100 included in the sub-plate layer is large, and the position of the first design graphics 100 needs to be adjusted multiple times so that the distance between any two first design graphics 100 is greater than or equal to the minimum lithographic spacing. In this embodiment, the first design graphics 100 are interconnected through-hole graphics, the number of interconnected through-hole graphics is usually large, and the distance between any two interconnected through-hole graphics is small. In this embodiment, multiple sub-processing is required.

[0066] Moreover, all first design graphics 100 in the sub-plate layer need to be translated, and the single translation directions of multiple sub-processings are alternately performed along the first direction and the second direction, which is beneficial to improving the uniformity of the distribution of the first design graphics 100 in the sub-plate layer.

[0067] In this embodiment, the first direction is the extension direction of the first metal wire pattern 200, and the second direction is the extension direction of the second metal wire pattern 300. The interconnection through-hole pattern is alternately translated along the extension direction of the first metal wire pattern 200 and the extension direction of the second metal wire pattern 300, so that the interconnection through-hole pattern after translation does not deviate too much from the first metal pattern 200 and the second metal wire pattern 300. This facilitates the subsequent slight adjustment of the boundary between the first metal pattern 200 and the second metal pattern 300, so that the interconnection through-hole pattern can still be located in the first metal pattern 200 and / or the second metal wire pattern 300.

[0068] In other embodiments, the number of sub-processings is multiple. According to operational requirements, the single translation direction of the previous sub-processing is the first direction, and the single translation direction of the next sub-processing may also be the first direction. Alternatively, the single translation direction of the previous sub-processing is the second direction, and the single translation direction of the next sub-processing may also be the second direction.

[0069] Specifically, refer to Figure 7 The sub-processing step includes: obtaining a single translation distance and a single translation direction corresponding to each first design pattern 100, and the single translation directions of any two first design patterns 100 are the same or opposite.

[0070] A single translation distance and a single translation direction corresponding to each first design pattern 100 are obtained, and the first design pattern 100 is translated according to the single translation distance and the single translation direction.

[0071] In this embodiment, the single translation directions of any two first design graphics 100 are the same or opposite, so that the single translation directions of the first design graphics 100 are relatively uniform, reducing the arbitrariness of the translation of the first design graphics 100 and reducing the computational complexity of the sub-process, thereby facilitating improved operational feasibility of the sub-process.

[0072] Specifically, the step of obtaining the single translation distance and single translation direction corresponding to each first design pattern 100 includes: constructing a penalty function with the distance between any two first design patterns 100 as a variable, and the penalty function has a penalty term under the condition that the distance between any two first design patterns 100 is less than the minimum lithographic spacing.

[0073] In this embodiment, the problem of obtaining the single translation distance and single translation direction corresponding to each first design pattern 100 is transformed into an optimization problem of the distance between any two first design patterns 100. The optimization problem is to ensure that the distance between any two first design patterns 100 is greater than or equal to the minimum lithographic spacing.

[0074] A function is constructed with the distance between any two first design patterns 100 as a variable, so that the optimization problem can be solved by solving the function.

[0075] In this embodiment, the optimization problem is solved by constructing a penalty function with the distance between any two first design patterns 100 as a variable.

[0076] The significance of constructing a penalty function is: when the variable is in the infeasible domain, a penalty term is set; when the variable is in the feasible domain, no penalty is imposed. The penalty function is the sum of the penalty terms. By gradually converging the penalty function to the extreme value, the variable is pulled back from the infeasible domain to the feasible domain.

[0077] It should be noted that the feasible domain refers to the set of variables that meet the preset requirements, and the infeasible domain refers to the set of variables that do not meet the preset requirements.

[0078] In this embodiment, the preset requirement is that the distance between any two first design patterns 100 must be greater than or equal to the minimum lithographic spacing. Therefore, in this embodiment, when the distance between any two first design patterns 100 is less than the minimum lithographic spacing, the preset requirement is not met. Only when the distance between any two first design patterns 100 is greater than or equal to the minimum lithographic spacing, the preset requirement is met. In other words, the infeasible region is when the variable is less than the minimum lithographic spacing, and the feasible region is when the variable is greater than or equal to the minimum lithographic spacing.

[0079] To this end, in this embodiment, the penalty function has a penalty term when the distance between any two first design patterns 100 is less than the minimum lithographic spacing. The penalty function of any first design pattern 100 is the sum of the penalty terms of the first design pattern 100 and the remaining first design patterns 100. When the variable runs into an infeasible domain, the penalty term is set to be greater than 0 as a penalty.

[0080] In this embodiment, the distance between any first design pattern 100 and the other first design patterns 100 is brought back to the feasible region by gradually converging the penalty function.

[0081] In this embodiment, the penalty term is a function that decreases as the variable increases, and the penalty function is a function that decreases as the variable increases. Therefore, when the penalty function gradually converges, the variable gradually increases, that is, the distance between any two first design patterns 100 gradually increases until the distance between any two first design patterns 100 is greater than or equal to the minimum lithographic spacing.

[0082] In this embodiment, the change in the variable when the penalty function approaches an extreme value is obtained, and the corresponding single translation distance and single translation direction of the first design pattern 100 are obtained according to the change.

[0083] The single translation distance is obtained according to the absolute value of the change, and the single translation direction is obtained according to the change direction of the variable.

[0084] In this embodiment, the penalty term is a function that decreases as the variable increases. When the penalty function gradually converges and the variable gradually increases, the penalty function tends to an extreme value. In the step of the change in the variable, the extreme value is the minimum value.

[0085] In this embodiment, a Gaussian function is used as a penalty term. The Gaussian function has a peak and is shaped like an inverted bell. The horizontal coordinate point corresponding to the peak is used as the base point, and the function value decreases as the distance between the remaining horizontal coordinate points and the base point increases. Therefore, in this embodiment, the distance between the remaining horizontal coordinate points and the base point is the distance between any two first design figures 100, that is, the variable. Therefore, the penalty term decreases as the variable increases, meeting the aforementioned requirements for constructing a penalty function.

[0086] As an example, the penalty function is expressed as P tot =∑ i＜j P i,j ,and

[0087]

[0088] Among them, P i,j is the penalty term, (x i ,yi ) and (x j ,y j ) are the coordinates of any two adjacent first design patterns in the coordinate system, the coordinate axes of the coordinate system include an x-axis parallel to the first direction and a y-axis parallel to the second direction, S min The minimum pitch that can be photolithographically processed.

[0089] Correspondingly, (x i -x j ) 2 +(y i -y j ) 2 is the distance between any two first design patterns 100, (x i -x j ) 2 +(y i -y j ) 2 min 2 is an infeasible region, (x i -x j ) 2 +(y i -y j ) 2 ≥S min 2 is the feasible domain.

[0090] In this embodiment, multiple sub-processes are performed, and the single translation directions of the multiple sub-processes are performed alternately along the x-axis and the y-axis.

[0091] It should be noted that, for any first design graphic 100 , in order to take into account the distances between the first design graphic 100 and all other first design graphics 100 and to avoid overlapping, the first design graphics 100 are numbered, i and j being the numbers of the first design graphics 100 , and i<j in the penalty function equation.

[0092] In this embodiment, when the first design pattern 100 is translated along the first direction, the partial derivative of the penalty function with respect to x is calculated to obtain the gradient derivative of the penalty function. When the gradient derivative is greater than 0, it means that the penalty function increases as x increases. When the gradient derivative is less than 0, it means that the penalty function decreases as x increases. Therefore, in order to reduce the penalty function, x needs to be moved in the opposite direction of the gradient derivative. For any point x i The change is:

[0093] Similar to translating the first design graphic 100 along the first direction, when translating the first design graphic 100 along the second direction, the change is: ​

[0094] Wherein, a is a constant coefficient, and a is a positive number. In this embodiment, the constant coefficient a is established, and a can be assigned a value according to different operation requirements to obtain a corresponding change amount, thereby adjusting the iteration rate of multiple sub-processing.

[0095] It should be noted that a should not be too large or too small. If a is too large, the absolute value of the change is too large, the distance required to move in the opposite direction of the gradient derivative is too large, and the change of the variable is too drastic. According to the change, the positions of all the first design graphics 100 need to be adjusted, which can easily lead to excessive oscillation of the overall adjustment, making it difficult for the penalty function to converge. If a is too small, the absolute value of the change is too small, the distance required to move in the opposite direction of the gradient derivative is too small, and the change of the variable is too slow, resulting in too many iterations of the sub-processing and too long a time consumption, affecting the overall efficiency of the optical proximity correction. For this reason, in this embodiment, 10 -3 ≤a≤10 -1 .

[0096] In this embodiment, the single translation direction is the direction of change of the variable. When the change is positive, the single movement direction is the positive direction of the x-axis or y-axis. When the change is negative, the single movement direction is the negative direction of the x-axis and y-axis.

[0097] That is, in this embodiment, when the first design pattern 100 is translated along the first direction, when Δx i >0, translation is performed along the +X direction. When Δx i <0, translate along the -X direction; or, in the case of translating the first design pattern 100 along the second direction, when Δy i >0, translate along the +Y direction. i When <0, translation is performed along the -Y direction.

[0098] Among them, the +X direction is the positive direction of the x-axis, the -X direction is the negative direction of the x-axis, the +Y direction is the positive direction of the y-axis, and the -Y direction is the negative direction of the y-axis.

[0099] It should be noted that the single translation distance should not be too large. If the single translation distance is too large, the distance between the first design pattern 100 and another first design pattern 100 will increase too much, which will easily cause the distance between the first design pattern 100 and the other first design patterns 100 to decrease too much, resulting in the single translation distance of the other first design patterns 100 being too large. In turn, it is easy to cause the translation oscillation of the entire first design pattern 100 to be too large, making it difficult for the distance between any two first design patterns 100 to converge to a distance greater than or equal to the minimum spacing that can be photolithographically processed. For this reason, the single translation distance has a maximum translation distance ΔS max .

[0100] Therefore, in this embodiment, when the first design pattern 100 is translated along the first direction, when |Δx i |<ΔS max When the single translation distance is |Δx i |, when |Δx i |≥ΔS max When the single translation distance is ΔS max In the case of translating the first design pattern 100 along the second direction, when |Δy i |<ΔS max When the single translation distance is |Δy i |, when |Δy i |≥ΔS max When the single translation distance is ΔS max .

[0101] It should be noted that the maximum translation distance ΔS max It should not be too large or too small. If the maximum translation distance ΔS max If it is too large, the constraint on the single translation distance is too loose, even if the single translation distance does not exceed the maximum translation distance ΔS max , the single translation distance is still too large, which can easily lead to excessive translation oscillation of the entire first design pattern 100, making it difficult for the distance between any two first design patterns 100 to converge to a value greater than or equal to the minimum lithographic spacing; if the maximum translation distance ΔS max If it is too small, the constraint on the single translation distance is too strict, even if the single translation distance does not reach the maximum translation distance ΔS max , the single translation distance is still too small, which can easily lead to the first design pattern 100 moving too slowly, resulting in too many sub-processing iterations and too long a time consumption, thus affecting the overall efficiency of optical proximity correction. Therefore, in this embodiment, the maximum translation distance ΔS max 2nm to 4nm.

[0102] refer to Figure 8 The sub-processing step further includes: translating the first design graphics 100 according to the single translation distance and the single translation direction corresponding to each first design graphic 100.

[0103] in, Figure 8 The dotted box in FIG. 1 is the position of the first design graphic 100 before translation.

[0104] The first design patterns 100 are translated according to the single translation distance and single translation direction corresponding to each first design pattern 100 so that the distance between any two first design patterns 100 approaches a target greater than or equal to the minimum lithographic spacing.

[0105] Correspondingly, as can be seen from the foregoing, a single translation direction includes one or both of the first direction and the second direction.

[0106] In this embodiment, after the first design graphics 100 are translated, the distance between any two first design graphics 100 is calculated.

[0107] After translating the first design patterns 100, the distance between any two first design patterns 100 is calculated. If the distance between any two first design patterns 100 is still less than the minimum lithographic pitch, the next sub-processing is required. If the distance between any two first design patterns 100 is greater than or equal to the minimum lithographic pitch, the translation process ends.

[0108] It should be noted that, in this embodiment, only the steps of one sub-process are described in detail. If multiple sub-processes are required, it is only necessary to repeat the steps of the above sub-processes.

[0109] Figure 9 A schematic diagram of one of the sub-layers after multiple sub-processing.

[0110] refer to Figure 10 After the first design pattern 100 is translated, the optical proximity correction method further includes: moving a portion of the boundary of the first metal wire pattern 200 and / or the second metal wire pattern 300 according to the position of the interconnection through-hole pattern, so that the interconnection through-hole pattern is still located in the first metal wire pattern 200 and / or the second metal wire pattern 300.

[0111] In the semiconductor structure manufacturing process, an interconnection via structure is formed on the first metal line or the second metal line to realize electrical connection between the first metal line or the second metal line and other structures, or to realize electrical connection between the first metal line and the second metal line. Therefore, in this embodiment, in the layout layer, the interconnection via pattern needs to be located in the corresponding first metal line pattern 200 and / or second metal line pattern 300.

[0112] In this embodiment, the interconnection via pattern is alternately translated along the extension direction of the first metal line pattern 200 and the second metal line pattern 300, so that the translated interconnection via pattern does not deviate too much from the first metal pattern 200 and the second metal line pattern 300. Therefore, by slightly adjusting the boundary between the first metal pattern 200 and the second metal pattern 300, the interconnection via pattern can still be located within the first metal pattern 200 and / or the second metal line pattern 300.

[0113] Correspondingly, the present invention also provides an optical proximity correction system. Figure 11 FIG. 4 is a functional block diagram of an optical proximity correction system according to an embodiment of the present invention.

[0114] In this embodiment, the optical proximity correction system 50 includes: a layout providing module 501 for obtaining a first layout layer, the first layout layer including a plurality of first design graphics, the distance between any two first design graphics being a first spacing, and at least one first spacing being less than a minimum spacing for photolithography; a layout splitting module 502 for splitting the first layout layer into a plurality of sub-layout layers, each of the first design graphics being disposed on one of the sub-layout layers, the graphic layout of the plurality of sub-layout layers being superimposed being the same as the graphic layout in the first layout layer, the distance between any two first design graphics in the sub-layout layers being a second spacing, the second spacing being greater than the first spacing, and at least one second spacing being less than the minimum spacing for photolithography; and a graphic layout changing module 503 for changing the graphic layout of the first design graphics in the sub-layout layers so that the distance between any two first design graphics in each sub-layout layer is greater than or equal to the minimum spacing for photolithography.

[0115] The layout providing module 501 is used to obtain a first layout layer, which includes multiple first design graphics. The distance between any two first design graphics is a first spacing, and at least one first spacing is smaller than the minimum spacing that can be photolithographically processed.

[0116] The first design pattern is the first target pattern transferred onto the wafer. After optical proximity correction is performed on the first design pattern, the obtained pattern is used to make a mask, which is then used to perform a photolithography process to form a corresponding mask pattern on the wafer.

[0117] In this embodiment, the distance between any two first design patterns is the first spacing, and at least one first spacing is smaller than the minimum spacing that can be photolithographically processed. The photolithographic imaging of the first design patterns is prone to severe distortion, and there are even cases where the first design patterns are difficult to be photolithographically processed, resulting in a serious decline in the quality of the photolithographic patterns. Therefore, the first spacing needs to be increased subsequently so that all the first design patterns can be photolithographically processed.

[0118] Here, the minimum photolithographic pitch refers to the minimum distance between any two first design patterns when the first design patterns can be photolithographically formed on a wafer during a photolithography process using a mask.

[0119] In this embodiment, the first design pattern includes a contact hole pattern or an interconnection through hole pattern.

[0120] The contact hole pattern is used to form a contact hole on the wafer, and the contact hole is used to form a contact hole plug. The interconnection through-hole pattern is used to form an interconnection through-hole on the wafer, and the interconnection through-hole is used to form an interconnection through-hole structure. Usually, the number of contact hole patterns or interconnection through-hole patterns in the layout layer is large and relatively dense. Therefore, the distance between any two contact hole patterns or through-hole interconnection patterns is usually small.

[0121] As an example, the first design pattern is an interconnection via pattern. The interconnection via structure is generally used to realize electrical connection between two layers of metal wires.

[0122] To this end, in this embodiment, the step of obtaining a first layout layer further includes: obtaining a second layout layer and a third layout layer, the first layout layer is located between the second layout layer and the third layout layer, the second layout layer includes a plurality of first metal wire patterns extending along a first direction and arranged in parallel along a second direction, the third layout layer includes a plurality of second metal wire patterns extending along the second direction and arranged along the first direction, and the interconnection through-hole patterns are located in the corresponding first metal wire patterns and / or second metal wire patterns.

[0123] In the back-end process, the first metal line pattern is used to form a first metal line on the wafer, and the second metal line pattern is used to form a second metal line on the wafer.

[0124] In the semiconductor structure manufacturing process, an interconnection via structure is formed on the first metal wire or the second metal wire to achieve electrical connection between the first metal wire or the second metal wire and other structures, or to achieve electrical connection between the first metal wire and the second metal wire. Therefore, in this embodiment, in the layout layer, the interconnection via pattern is located in the corresponding first metal wire pattern and / or second metal wire pattern.

[0125] The plate layer splitting module 502 is used to perform plate layer splitting processing, splitting the first plate layer into multiple sub-plate layers, and setting each first design graphic on one of the sub-plate layers. The graphic layout after the multiple sub-plate layers are superimposed is the same as the graphic layout in the first plate layer. In the sub-plate layer, the distance between any two first design graphics is a second spacing, which is larger than the first spacing, and at least one second spacing is smaller than the minimum spacing that can be photolithographically processed.

[0126] In this embodiment, the layout layer splitting process uses multiple graphics technology to decompose the first design graphic in the first layout layer into multiple sub-layout layers. The graphic layout after the multiple sub-layout layers are superimposed is the same as the graphic layout in the first layout layer. In this case, the layout layer splitting process does not change the original graphic layout of the first layout layer.

[0127] Subsequently, the first design graphics in each sub-plate layer need to be translated separately. By translating the first design graphics, the distance between any two first design graphics in the same sub-plate layer is greater than or equal to the minimum spacing that can be photolithographically processed. Before the translation, the plate layer is split first, and the first design graphics in the first plate layer are decomposed into multiple sub-plate layers. The distance between any two first design graphics is appropriately increased, which helps to reduce the difficulty of the subsequent translation process and ensures that the translation process can be carried out smoothly.

[0128] Moreover, translation processing will be performed later. Therefore, the requirements for the plate layer splitting processing are relatively loose. It is not necessary to meet the requirement that the distance between any two first design graphics in each sub-plate layer is greater than or equal to the minimum photolithographic spacing. In this embodiment, in each sub-plate layer, the second spacing is greater than the first spacing, and at least one second spacing is less than the minimum photolithographic spacing. Therefore, it is only necessary to appropriately increase the distance between any two first design graphics, thereby reducing the number of sub-plate layers required for the splitting processing and saving process costs.

[0129] In this embodiment, the plate layer splitting process is performed according to a preset threshold condition, where the threshold condition includes: the difference between the minimum lithographic pitch and the second pitch is smaller than a preset value.

[0130] In this embodiment, corresponding preset values ​​are provided according to different graphic layouts, so that after the plate layer splitting process is performed, the difference between the minimum lithographic pitch and the second pitch is less than the preset value. Therefore, in the sub-plate layer, the spacing between adjacent first design graphics meets a certain standard and approaches the minimum lithographic pitch. This appropriately reduces the distance that needs to be adjusted for the first design graphics during the subsequent translation process, which is conducive to reducing the complexity of the subsequent translation process and improving the overall efficiency of the optical proximity correction process.

[0131] It should be noted that the preset value should not be too large or too small. If the preset value is too large, the requirements for the layout layer splitting process are too loose, and the distance between any two first design graphics in each sub-layout layer is still small. As a result, when the subsequent translation process is performed, the distance of the first design graphics that needs to be adjusted is large, thereby increasing the amount of translation processing operations and increasing the difficulty of translation processing; if the preset value is too small, the requirements for the layout layer splitting process are too stringent, and too many sub-layout layers are required to ensure that the distance between any two first design graphics in each sub-layout layer meets the threshold condition, which increases the time for the layout layer splitting process and increases the process cost. For this reason, in this embodiment, the preset value is 5nm to 10nm.

[0132] The pattern layout changing module 503 is used to change the pattern layout of the first design pattern in the sub-plate layer so that the distance between any two first design patterns in each sub-plate layer is greater than or equal to the minimum lithographic spacing.

[0133] Compared with the solution of merely splitting the first plate layer into multiple sub-plate layers through plate layer splitting processing so that the distance between any two first design graphics in the sub-plate layer is greater than or equal to the minimum spacing that can be photolithographically processed, this embodiment appropriately increases the distance between any two first design graphics through plate layer splitting processing, so that in each sub-plate layer, by changing the graphic layout of the first design graphics in the sub-plate layer, the effect of the distance between any two first design graphics being greater than or equal to the minimum spacing that can be photolithographically processed can be achieved, thereby reducing the number of sub-plate layers required for plate layer splitting processing, and thus saving process costs while enabling the first design graphics to be photolithographically processed.

[0134] In this embodiment, the graphic layout of the first design graphic in each sub-plate layer is changed by performing translation processing on the first design graphic in each sub-plate layer.

[0135] In this embodiment, the single translation direction includes one or both of a first direction and a second direction, and the first direction and the second direction are perpendicular to each other, wherein the first direction includes the +X direction or the -X direction, and the second direction includes the +Y direction or the -Y direction.

[0136] Among them, the +X direction or the -X direction is the opposite direction, and the +Y direction or the -Y direction is the opposite direction.

[0137] The single translation direction includes one or both of a first direction and a second direction, and the first direction and the second direction are perpendicular to each other, so that the position movement of the first design graphic is more regular, avoiding excessive clutter due to changes in the graphic layout, thereby reducing changes to the circuit design.

[0138] In this embodiment, the step of performing translation processing on the first design pattern in each sub-plate layer includes: performing one or more sub-processings in each sub-plate layer until the distance between any two first design patterns is greater than or equal to the minimum lithographic spacing.

[0139] One or more sub-processings are used to ensure that the distance between any two first design graphics is greater than or equal to the minimum photolithographic spacing, thereby increasing the flexibility of the translation processing operation. In each sub-plate layer, the number of sub-processings is adjusted according to different graphic layouts, so that the translation processing can be adapted to each sub-plate layer, thereby increasing the operability of the translation processing.

[0140] In this embodiment, the number of sub-processing is multiple, and the single translation direction of the previous sub-processing is the first direction, and the single translation direction of the next sub-processing is the second direction.

[0141] Usually, the number of first design graphics included in the sub-plate layer is large, and the position of the first design graphics needs to be adjusted multiple times so that the distance between any two first design graphics is greater than or equal to the minimum lithographic spacing. In this embodiment, the first design graphics are interconnected through-hole graphics, the number of interconnected through-hole graphics is usually large, and the distance between any two interconnected through-hole graphics is small. In this embodiment, multiple sub-processing is required.

[0142] Moreover, all the first design graphics in the sub-plate layer need to be translated, and the single translation directions of multiple sub-processings are alternately performed along the first direction and the second direction, which is beneficial to improving the uniformity of the distribution of the first design graphics in the sub-plate layer.

[0143] In this embodiment, the first direction is the extension direction of the first metal wire pattern, and the second direction is the extension direction of the second metal wire pattern. The interconnection through-hole pattern is alternately translated along the extension direction of the first metal wire pattern and the extension direction of the second metal wire pattern, so that the interconnection through-hole pattern after translation does not deviate too much from the first metal pattern and the second metal wire pattern, which is conducive to the subsequent slight adjustment of the boundary between the first metal pattern and the second metal pattern, so that the interconnection through-hole pattern can still be located in the first metal pattern and / or the second metal wire pattern.

[0144] In other embodiments, the number of sub-processings is multiple. According to operational requirements, the single translation direction of the previous sub-processing is the first direction, and the single translation direction of the next sub-processing may also be the first direction. Alternatively, the single translation direction of the previous sub-processing is the second direction, and the single translation direction of the next sub-processing may also be the second direction.

[0145] Specifically, the sub-processing step includes: obtaining a single translation distance and a single translation direction corresponding to each first design pattern, and the single translation directions of any two first design patterns are the same or opposite.

[0146] A single translation distance and a single translation direction corresponding to each first design pattern are obtained, and the first design pattern is translated according to the single translation distance and the single translation direction.

[0147] In this embodiment, the single translation directions of any two first design graphics are the same or opposite, so that the single translation directions of the first design graphics are relatively uniform, reducing the arbitrariness of the translation of the first design graphics and reducing the amount of computation in the sub-processing process, thereby facilitating improved operational feasibility of the sub-processing.

[0148] Specifically, the step of obtaining the single translation distance and single translation direction corresponding to each first design pattern includes: constructing a penalty function with the distance between any two first design patterns as a variable, and the penalty function has a penalty term under the condition that the distance between any two first design patterns is less than the minimum lithographic spacing.

[0149] In this embodiment, the problem of obtaining the single translation distance and single translation direction corresponding to each first design pattern is converted into an optimization problem of the distance between any two first design patterns. The optimization problem is to make the distance between any two first design patterns greater than or equal to the minimum lithographic spacing.

[0150] A function is constructed with the distance between any two first design figures as a variable, so that the optimization problem can be solved by solving the function.

[0151] In this embodiment, the optimization problem is solved by constructing a penalty function with the distance between any two first design patterns as a variable.

[0152] The significance of constructing a penalty function is: when the variable is in the infeasible domain, a penalty term is set; when the variable is in the feasible domain, no penalty is imposed. The penalty function is the sum of the penalty terms. By gradually converging the penalty function to the extreme value, the variable is pulled back from the infeasible domain to the feasible domain.

[0153] It should be noted that the feasible domain refers to the set of variables that meet the preset requirements, and the infeasible domain refers to the set of variables that do not meet the preset requirements.

[0154] In this embodiment, the preset requirement is that the distance between any two first design patterns must be greater than or equal to the minimum photolithographic spacing. Therefore, in this embodiment, when the distance between any two first design patterns is less than the minimum photolithographic spacing, the preset requirement is not met. Only when the distance between any two first design patterns is greater than or equal to the minimum photolithographic spacing, the preset requirement is met. That is to say, the infeasible region is when the variable is less than the minimum photolithographic spacing, and the feasible region is when the variable is greater than or equal to the minimum photolithographic spacing.

[0155] To this end, in this embodiment, the penalty function has a penalty term under the condition that the distance between any two first design patterns is less than the minimum lithographic spacing. The penalty function of any first design pattern is the sum of the penalty terms of the first design pattern and the remaining first design patterns. When the variable runs to an infeasible domain, the penalty term is set to be greater than 0 as a penalty.

[0156] Therefore, in this embodiment, by gradually converging the penalty function, the distance between any first design pattern and the other first design patterns is brought back to the feasible region.

[0157] In this embodiment, the penalty term is a function that decreases as the variable increases, and the penalty function is a function that decreases as the variable increases. Therefore, when the penalty function gradually converges, the variable gradually increases, that is, the distance between any two first design patterns gradually increases until the distance between any two first design patterns is greater than or equal to the minimum lithographic spacing.

[0158] In this embodiment, the variation of the variable when the penalty function approaches an extreme value is obtained, and the corresponding single translation distance and single translation direction of the first design pattern are obtained according to the variation.

[0159] The single translation distance is obtained according to the absolute value of the change, and the single translation direction is obtained according to the direction of the change.

[0160] In this embodiment, the penalty term is a function that decreases as the variable increases. When the penalty function gradually converges and the variable gradually increases, the penalty function tends to an extreme value. In the step of the change in the variable, the extreme value is the minimum value.

[0161] In this embodiment, a Gaussian function is used as a penalty term. The Gaussian function has a peak and is shaped like an inverted bell. The horizontal coordinate point corresponding to the peak is used as the base point, and the function value decreases as the distance between the remaining horizontal coordinate points and the base point increases. Therefore, in this embodiment, the distance between the remaining horizontal coordinate points and the base point is the distance between any two first design figures, that is, the variable, so that the penalty term decreases as the variable increases, meeting the aforementioned requirements for constructing a penalty function.

[0162] As an example, the penalty function is expressed as P tot =∑ i＜j P i,j ,and

[0163]

[0164] Among them, P i,j is the penalty term, (x i ,y i ) and (x j ,y j ) are the coordinates of any two adjacent first design patterns in the coordinate system, the coordinate axes of the coordinate system include an x-axis parallel to the first direction and a y-axis parallel to the second direction, S min The minimum pitch that can be photolithographically processed.

[0165] Correspondingly, (x i -x j ) 2 +(y i -y j ) 2 is the distance between any two first design figures, (x i -xj ) 2 +(y i -y j ) 2 min 2 is an infeasible region, (x i -x j ) 2 +(y i -y j ) 2 ≥S min 2 is the feasible domain.

[0166] In this embodiment, multiple sub-processes are performed, and the single translation directions of the multiple sub-processes are performed alternately along the x-axis and the y-axis.

[0167] It should be noted that, for any first design figure, in order to take into account the distance between the first design figure and all other first design figures and avoid repeated overlap, the first design figures are numbered, i and j are the numbers of the first design figures, and in the penalty function relationship, i<j is defined.

[0168] In this embodiment, when the first design figure is translated along the first direction, the partial derivative of the penalty function with respect to x is calculated to obtain the gradient derivative of the penalty function. When the gradient derivative is greater than 0, it means that the penalty function increases as x increases. When the gradient derivative is less than 0, it means that the penalty function decreases as x increases. Therefore, in order to reduce the penalty function, x needs to be moved in the opposite direction of the gradient derivative. For any point x i The change is:

[0169] Similar to translating the first design graphic along the first direction, when translating the first design graphic along the second direction, the change is:

[0170] Wherein, a is a constant coefficient, and a is a positive number. In this embodiment, the constant coefficient a is established, and a can be assigned a value according to different operation requirements to obtain a corresponding change amount, thereby adjusting the iteration rate of multiple sub-processing.

[0171] ​It should be noted that a should not be too large or too small. If a is too large, the absolute value of the change is too large, the distance required to move in the opposite direction of the gradient derivative is too large, the change of the variable is too drastic, and the positions of all the first design graphics need to be adjusted according to the change, which can easily lead to excessive oscillation of the overall adjustment, making it difficult for the penalty function to converge; if a is too small, the absolute value of the change is too small, the distance required to move in the opposite direction of the gradient derivative is too small, and the change of the variable is too slow, resulting in too many sub-processing iterations and too long a time consumption, affecting the overall efficiency of the optical proximity correction. For this reason, in this embodiment, 10 -3 ≤a≤10 -1 .

[0172] In this embodiment, the single translation direction is the direction of change of the variable. When the change is positive, the single movement direction is the positive direction of the x-axis or y-axis. When the change is negative, the single movement direction is the negative direction of the x-axis and y-axis.

[0173] That is, in this embodiment, when the first design pattern is translated along the first direction, when Δx i >0, translation is performed along the +X direction. When Δx i <0, translate along the -X direction; or, in the case of translating the first design pattern along the second direction, when Δy i >0, translate along the +Y direction. i When <0, translation is performed along the -Y direction.

[0174] Among them, the +X direction is the positive direction of the x-axis, the -X direction is the negative direction of the x-axis, the +Y direction is the positive direction of the y-axis, and the -Y direction is the negative direction of the y-axis.

[0175] It should be noted that the single translation distance should not be too large. If the single translation distance is too large, the distance between the first design pattern and another first design pattern will increase too much, which will easily cause the distance between the first design pattern and other first design patterns to decrease too much, resulting in the single translation distance of other first design patterns being too large. Iteratively, it is easy to cause the translation oscillation of the entire first design pattern to be too large, making it difficult for the distance between any two first design patterns to converge to a distance greater than or equal to the minimum spacing that can be photolithographically processed. For this reason, the single translation distance has a maximum translation distance ΔS max .

[0176] Therefore, in this embodiment, when the first design pattern is translated along the first direction, when |Δx i |<ΔS max When the single translation distance is |Δx i |, when |Δx i |≥ΔS max When the single translation distance is ΔSmax In the case of translating the first design pattern 100 along the second direction, when |Δy i |<ΔS max When the single translation distance is |Δy i |, when |Δy i |≥ΔS max When the single translation distance is ΔS max .

[0177] It should be noted that the maximum translation distance ΔS max It should not be too large or too small. If the maximum translation distance ΔS max If it is too large, the constraint on the single translation distance is too loose, even if the single translation distance does not exceed the maximum translation distance ΔS max , the single translation distance is still too large, which can easily lead to excessive translation oscillation of the entire first design pattern, making it difficult for the distance between any two first design patterns to converge to a value greater than or equal to the minimum spacing that can be photolithographically processed; if the maximum translation distance ΔS max If it is too small, the constraint on the single translation distance is too strict, even if the single translation distance does not reach the maximum translation distance ΔS max , the single translation distance is still too small, which can easily lead to the first design pattern moving too slowly, resulting in too many sub-processing iterations and too long a time consumption, thus affecting the overall efficiency of optical proximity correction. Therefore, in this embodiment, the maximum translation distance ΔS max 2nm to 4nm.

[0178] The sub-processing step further includes: translating the first design graphics according to the single translation distance and the single translation direction corresponding to each first design graphic.

[0179] The first design patterns are translated according to the single translation distance and single translation direction corresponding to each first design pattern, so that the distance between any two first design patterns approaches a target greater than or equal to the minimum lithographic spacing.

[0180] Correspondingly, as can be seen from the foregoing, a single translation direction includes one or both of the first direction and the second direction.

[0181] In this embodiment, after the first design graphics are translated, the distance between any two first design graphics is calculated.

[0182] After translating the first design patterns, the distance between any two first design patterns is calculated. If the distance between any two first design patterns is still less than the minimum lithographic pitch, the next sub-processing is required. If the distance between any two first design patterns is greater than or equal to the minimum lithographic pitch, the translation process ends.

[0183] It should be noted that, in this embodiment, only the steps of one sub-process are described in detail. If multiple sub-processes are required, it is only necessary to repeat the steps of the above sub-processes.

[0184] In this embodiment, the optical proximity correction system also includes: a graphic boundary movement module, which is used to move part of the boundary of the first metal wire pattern and / or the second metal wire pattern according to the position of the interconnection through-hole pattern after the first design pattern is translated, so that the interconnection through-hole pattern is still located in the first metal wire pattern and / or the second metal wire pattern.

[0185] In the semiconductor structure manufacturing process, an interconnection via structure is formed on the first metal wire or the second metal wire to realize electrical connection between the first metal wire or the second metal wire and other structures, or to realize electrical connection between the first metal wire and the second metal wire. Therefore, in this embodiment, in the layout layer, the interconnection via pattern needs to be located in the corresponding first metal wire pattern and / or second metal wire pattern.

[0186] In this embodiment, the interconnection via pattern is alternately translated along the extension direction of the first metal line pattern and the second metal line pattern, so that the translated interconnection via pattern does not deviate too much from the first metal pattern and the second metal line pattern. Therefore, by slightly adjusting the boundary between the first metal pattern and the second metal pattern, the interconnection via pattern can still be located within the first metal pattern and / or the second metal line pattern.

[0187] Correspondingly, the present invention further provides a mask, comprising: a pattern obtained by using the optical proximity correction method provided by an embodiment of the present invention.

[0188] As can be seen from the aforementioned embodiment, in the step of obtaining the first layout layer, the distance between any two first design patterns is a first spacing, and at least one of the first spacings is less than the minimum spacing for photolithography. After the layout splitting process, the distance between any two first design patterns is a second spacing, the second spacing is greater than the first spacing, and at least one of the second spacings is less than the minimum spacing for photolithography. By changing the graphic layout of the first design patterns, the distance between any two first design patterns is greater than or equal to the minimum spacing for photolithography. Compared to a solution in which the first layout layer is split into multiple sub-layout layers solely through layout splitting, and the distance between any two first design patterns in a sub-layout layer is greater than or equal to the minimum spacing for photolithography, the embodiment of the present invention appropriately increases the distance between any two first design patterns through the layout layer splitting process, so that in the sub-layout layer, by changing the graphic layout of the first design patterns in the sub-layout layer, the distance between any two first design patterns is greater than or equal to the minimum spacing for photolithography. This reduces the number of sub-layout layers required for the layout layer splitting process, thereby saving process costs while enabling photolithography of the first design patterns.

[0189] The embodiment of the present invention further provides a device that can implement the optical proximity correction method provided by the embodiment of the present invention by loading the above optical proximity correction method in the form of a program. An optional hardware structure of the terminal device provided by the embodiment of the present invention can be as follows Figure 12 As shown, it includes: at least one processor 01, at least one communication interface 02, at least one memory 03 and at least one communication bus 04.

[0190] In this embodiment, the number of processor 01, communication interface 02, memory 03, and communication bus 04 is at least one, and the processor 01, communication interface 02, and memory 03 communicate with each other via the communication bus 04. The communication interface 02 can be an interface of a communication module for network communication, such as an interface of a GSM module. The processor 01 can be a central processing unit (CPU), or an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present invention. The memory 03 can include a high-speed RAM memory, or can also include a non-volatile memory (NVM), such as at least one disk storage. The memory 03 stores one or more computer instructions, and the one or more computer instructions are executed by the processor 01 to implement the optical proximity correction method provided in the embodiments of the present invention.

[0191] It should be noted that the above-mentioned terminal device may also include other devices (not shown) that may not be necessary for understanding the contents disclosed in the embodiments of the present invention; given that these other devices may not be necessary for understanding the contents disclosed in the embodiments of the present invention, the embodiments of the present invention will not introduce them one by one.

[0192] An embodiment of the present invention further provides a storage medium, wherein the storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement the optical proximity correction method provided by the embodiment of the present invention.

[0193] In the optical proximity correction method provided by an embodiment of the present invention, in the step of obtaining a first layout layer, the distance between any two first design patterns is a first spacing, and at least one of the first spacings is less than the minimum spacing for photolithography. After the layout splitting process, the distance between any two first design patterns is a second spacing, and the second spacing is greater than the first spacing, and at least one of the second spacings is less than the minimum spacing for photolithography. By changing the graphic layout of the first design patterns, the distance between any two first design patterns is greater than or equal to the minimum spacing for photolithography. Compared to a solution in which the first layout layer is split into multiple sub-layout layers through layout splitting only, and the distance between any two first design patterns in a sub-layout layer is greater than or equal to the minimum spacing for photolithography, the embodiment of the present invention appropriately increases the distance between any two first design patterns through the layout splitting process. This allows the distance between any two first design patterns to be greater than or equal to the minimum spacing for photolithography by changing the graphic layout of the first design patterns in the sub-layout layer. This reduces the number of sub-layout layers required for the layout splitting process, thereby enabling photolithography of the first design patterns while saving process costs.

[0194] The embodiments of the present invention described above are combinations of elements and features of the present invention. Unless otherwise mentioned, elements or features may be considered as optional. Each element or feature may be put into practice without being combined with other elements or features. In addition, embodiments of the present invention may be constructed by combining some elements and / or features. The order of operations described in the embodiments of the present invention may be rearranged. Some configurations of any one embodiment may be included in another embodiment and may be replaced by the corresponding configuration of another embodiment. It is obvious to those skilled in the art that claims that do not have a clear reference relationship to each other in the appended claims may be combined into embodiments of the present invention, or may be included as new claims in amendments after submitting this application.

[0195] The embodiments of the present invention can be implemented by various means such as hardware, firmware, software or a combination thereof. In a hardware configuration, the method according to the exemplary embodiment of the present invention can be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, etc. In a firmware or software configuration, the embodiments of the present invention can be implemented in the form of modules, processes, functions, etc. The software code can be stored in a memory unit and executed by a processor. The memory unit is located inside or outside the processor and can send data to the processor and receive data from the processor via various known means.

[0196] The above description of the disclosed embodiments will enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein, but is to be construed in the widest possible manner consistent with the principles and novel features disclosed herein.

[0197] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. An optical proximity correction method, characterized in that: include: Acquire a first layer, wherein the first layer includes a plurality of first design patterns, wherein a distance between any two of the first design patterns is a first spacing, and at least one of the first spacings is smaller than a minimum spacing that can be photolithographically processed; Performing a layer splitting process to split the first layer into multiple sub-layers, and respectively placing each of the first design graphics on one of the sub-layers, wherein the graphic layout after superimposing the multiple sub-layers is the same as the graphic layout in the first layer, and in the sub-layers, the distance between any two of the first design graphics is a second spacing, the second spacing is greater than the first spacing, and at least one of the second spacings is less than the minimum spacing that can be photolithographically processed; The graphic layout of the first design graphics in the sub-plate layer is changed so that the distance between any two first design graphics in each sub-plate layer is greater than or equal to the minimum lithographic spacing.

2. The optical proximity correction method according to claim 1, wherein: The plate layer splitting process is performed according to a preset threshold condition, wherein the threshold condition includes: a difference between the minimum lithographic spacing and the second spacing is smaller than a preset value.

3. The optical proximity correction method according to claim 2, wherein: The preset value is 5nm to 10nm.

4. The optical proximity correction method according to claim 1, wherein: By performing translation processing on the first design graphic in each of the sub-plate layers respectively, the graphic layout of the first design graphic in the sub-plate layer is changed.

5. The optical proximity correction method according to claim 4, wherein: The step of performing translation processing on the first design pattern in each of the sub-plate layers comprises: performing one or more sub-processings in each of the sub-plate layers until the distance between any two first design patterns is greater than or equal to the minimum lithographic spacing; The sub-processing step includes: obtaining a single translation distance and a single translation direction corresponding to each of the first design patterns, and the single translation directions of any two of the first design patterns are the same or opposite; translating the first design graphics according to the single translation distance and single translation direction corresponding to each of the first design graphics; After translating the first design figures, the distance between any two first design figures is calculated.

6. The optical proximity correction method according to claim 5, wherein: The single translation direction includes one or both of a first direction and a second direction, and the first direction and the second direction are perpendicular to each other, wherein the first direction includes a +X direction or a -X direction, and the second direction includes a +Y direction or a -Y direction.

7. The optical proximity correction method according to claim 6, wherein: The sub-processing is performed multiple times, and the single translation direction of the previous sub-processing is the first direction, and the single translation direction of the next sub-processing is the second direction.

8. The optical proximity correction method according to claim 6, wherein: The step of obtaining a single translation distance and a single translation direction corresponding to each of the first design patterns includes: constructing a penalty function with the distance between any two first design patterns as a variable, the penalty function having a penalty term under the condition that the distance between any two first design patterns is less than the minimum lithographic pitch; Obtaining a change in the variable when the penalty function approaches an extreme value; A corresponding single translation direction and single translation distance of the first design pattern are obtained according to the variation.

9. The optical proximity correction method according to claim 8, wherein: The penalty term is a function that decreases as the variable increases; In the step of obtaining the change in the variable when the penalty function tends to an extreme value, the extreme value is a minimum value.

10. The optical proximity correction method according to claim 9, wherein: In the step of constructing a penalty function with the distance between any two first design patterns as a variable, the relationship of the penalty function is: P tot =∑ i＜j P i,j ,and Among them, P i,j is the penalty term, (x i ,y i ) and (x j ,y j ) are the coordinates of any two adjacent first design patterns in a coordinate system, wherein the coordinate axes of the coordinate system include an x-axis parallel to the first direction and a y-axis parallel to the second direction, S min The minimum pitch that can be photolithographically processed; In the step of obtaining the change in the variable when the penalty function approaches a minimum value, the change corresponding to the first direction is: The change corresponding to the second direction is: Wherein, a is a constant coefficient, and a is a positive number; In the step of obtaining the single translation distance and translation direction corresponding to each first design pattern according to the variation, when the first design pattern is translated along the first direction, when Δx i >0, the single translation direction is the +X direction, when Δx i <0, the single translation direction is -X direction; or, in the case of translating the first design pattern along the second direction, when Δy i >0, the translation direction is +Y direction, when Δy i <0, the translation direction is the -Y direction.

11. The optical proximity correction method according to claim 10, wherein: In the step of obtaining the change in the variable when the penalty function tends to a minimum value, 10 -3 ≤a≤10 -1 .

12. The optical proximity correction method according to claim 10, wherein: In the step of obtaining a single translation distance and a single translation direction corresponding to each first design pattern according to the variation, the single translation distance has a maximum translation distance ΔS max ; In the case of translating the first design pattern along the first direction, when |Δx i |<ΔS max When the single translation distance is |Δx i |; when |Δx i |≥ΔS max When the single translation distance is ΔS max the maximum translation distance; or, In the case of translating the first design pattern along the second direction, when |Δy i |<ΔS max When the single translation distance is |Δy i |; when|Δy i |≥ΔS max When the single translation distance is ΔS max .

13. The optical proximity correction method according to claim 12, wherein: The maximum translation distance ΔS max 2nm to 4nm.

14. The optical proximity correction method according to claim 1, wherein: In the step of obtaining the first layer, the first design pattern includes a contact hole pattern or an interconnection through-hole pattern.

15. The optical proximity correction method according to claim 4, wherein: In the step of obtaining the first layer, the first design pattern is an interconnected through-hole pattern; The step of obtaining the first layout layer further includes: obtaining a second layout layer and a third layout layer, wherein the first layout layer is located between the second layout layer and the third layout layer, the second layout layer includes a plurality of first metal line patterns extending along a first direction and arranged in parallel along a second direction, the third layout layer includes a plurality of second metal line patterns extending along the second direction and arranged along the first direction, and the interconnection via pattern is located in the corresponding first metal line pattern and / or second metal line pattern; In the step of performing translation processing on the first design pattern, a single translation direction includes one or both of the first direction and the second direction.

16. The optical proximity correction method according to claim 15, wherein: After the first design pattern is translated, the optical proximity correction method further includes: moving a portion of the boundary of the first metal line pattern and / or the second metal line pattern according to the position of the interconnection through-hole pattern, so that the interconnection through-hole pattern is still located in the first metal line pattern and / or the second metal line pattern.

17. An optical proximity correction system, characterized in that: include: A layout providing module is configured to obtain a first layout layer, wherein the first layout layer includes a plurality of first design patterns, wherein the distance between any two of the first design patterns is a first spacing, and at least one of the first spacings is smaller than a minimum spacing that can be photolithographically processed; a plate layer splitting module, configured to split the first plate layer into a plurality of sub-plate layers, and respectively arrange each of the first design graphics on one of the sub-plate layers, wherein the graphic layout after superposition of the plurality of sub-plate layers is the same as the graphic layout in the first plate layer, and wherein in the sub-plate layers, the distance between any two of the first design graphics is a second spacing, the second spacing is greater than the first spacing, and at least one of the second spacings is less than the minimum spacing that can be photolithographically processed; The graphic layout changing module is used to change the graphic layout of the first design graphic in the sub-plate layer so that the distance between any two first design graphics in each sub-plate layer is greater than or equal to the minimum lithographic spacing.

18. A mask, characterized in that: include: A pattern obtained using the optical proximity correction method according to any one of claims 1 to 16.

19. A terminal device, characterized in that: The method comprises at least one memory and at least one processor, wherein the memory stores one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the optical proximity correction method according to any one of claims 1 to 16.

20. A storage medium, characterized in that The storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement the optical proximity correction method according to any one of claims 1 to 16.

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