Touch display screen driving method and circuit and touch display screen

Abstract

The application discloses a touch display screen driving method, a circuit and a touch display screen. The method comprises the following steps: determining a switching cycle period of a display stage and a touch stage in one frame of the touch display screen; and according to the switching cycle period, compensating a second P point voltage of a row GOA circuit corresponding to the display stage from the second display stage, so that the second P point voltage reaches or approaches a first P point voltage of a row GOA circuit corresponding to a first display stage. By compensating the P point voltage, the P point voltage of the GOA circuit of the row of the second display stage can still reach or approach the P point voltage of the first display stage after the scanning time of the touch stage, so that the appearance of display horizontal lines is avoided.

Description

Technical Field

[0001] This invention relates to the field of display panel technology, and in particular to a touch display driving method, circuit, and touch display. Background Technology

[0002] Embedded touch display devices are favored by consumers because they integrate display and touch functions into a single display screen. Existing GOA (Gateway for Access) driving methods use a time-sharing approach for touch and display, meaning that within a single image frame, display and touch cycles are performed sequentially, repeating multiple times. The principle is that the high and low levels of the CK signal (clock level signal) for the entire GOA drive are the same. However, transitioning from the display stage to the touch scanning stage (or from touch to display) can cause insufficient gate drive output. (Refer to...) Figure 1 Due to the presence of display time (touch time), a voltage drop occurs at point P, resulting in a significant difference between Gn-1 and Gn. Usually, the output voltage of Gn is lower than that of Gn-1, leading to horizontal lines and reducing the user experience.

[0003] Therefore, a solution is needed to eliminate / reduce horizontal lines caused by the switching between the touch and display stages in order to improve the display quality of touch screens. Summary of the Invention

[0004] When existing touch displays switch between the touch scanning phase and the display scanning phase, horizontal lines appear on the display due to the voltage drop at point P.

[0005] To address the aforementioned issues, this application proposes a touch display driving method, circuit, and touch display.

[0006] Firstly, a method for driving a touch display screen, employing a GOA circuit to scan and drive the touch display screen, comprising:

[0007] Step 100: Determine the switching cycle period of the display stage-touch stage within one frame of the touch screen;

[0008] Step 200: According to the switching cycle, starting from the second display stage, compensate the second P-point voltage of the row GOA circuit corresponding to the display stage, so that the second P-point voltage reaches or approaches the first P-point voltage of the row GOA circuit corresponding to the first display stage.

[0009] Wherein, the voltage at the first point P is the turn-on voltage of the main transistor of the row GOA circuit corresponding to the first display stage in the switching cycle;

[0010] The voltage at point P is the turn-on voltage of the main transistor of the row GOA circuit corresponding to the second display stage in the switching cycle.

[0011] The first display phase is the first display phase in the switching cycle;

[0012] The second display stage is a display stage following the first display stage in the switching cycle.

[0013] In conjunction with the touch display driving method described in the first aspect of the present invention, in a first possible embodiment, step 200 includes:

[0014] Step 210: Use the timing control chip to input the first pulse timing level to the clock level terminal;

[0015] Step 220: Determine the first timing signal whose first pulse timing level is located in the second display stage;

[0016] Step 230: Increase the first pulse voltage signal of the first timing signal by ΔV to make the voltage at the second point P reach or approach the voltage at the first point P.

[0017] In conjunction with the touch display driving method described in the first aspect of the present invention, in a second possible embodiment, step 200 further includes:

[0018] Step 240: Use the timing control chip to input the second pulse timing level to the clock level terminal;

[0019] Step 250: Determine the second timing signal whose second pulse timing level is located in the second display stage;

[0020] Step 260: Increase the second pulse voltage signal of the second timing signal by ΔV to make the voltage at the second point P reach or approach the voltage at the first point P;

[0021] The timing sequence of the first pulse level is the opposite of that of the timing sequence of the second pulse level.

[0022] In conjunction with the first possible embodiment of the first aspect of the present invention, in a third possible embodiment, step 230 includes:

[0023] Step 231: Obtain the first pulse voltage sequence of the first timing signal during the second display stage;

[0024] Step 232: Take the first high-level pulse signal in the first pulse voltage sequence as the first pulse voltage signal.

[0025] In conjunction with the second possible implementation of the first aspect of the present invention, in the fourth possible implementation, step 260 includes:

[0026] Step 261: Obtain the second pulse voltage sequence of the second timing signal during the second display stage;

[0027] Step 262: Take the first high-level pulse signal in the second pulse voltage sequence as the second pulse voltage signal.

[0028] In a second aspect, a touch display screen driving circuit, employing the driving method described in the first aspect to scan and drive the touch display screen, includes:

[0029] Define the unit;

[0030] Compensation unit;

[0031] GOA circuit;

[0032] The compensation unit is electrically connected to the determining unit and the GOA circuit respectively;

[0033] The determining unit is used to determine the switching cycle period of the display stage-touch stage within one frame of the touch screen image;

[0034] The compensation unit is used to compensate the second P-point voltage of the row GOA circuit corresponding to the display stage, starting from the second display stage, according to the switching cycle, so that the second P-point voltage reaches or is close to the first P-point voltage of the row GOA circuit corresponding to the first display stage.

[0035] In conjunction with the touch display driving circuit described in the second aspect of the present invention, in a first possible embodiment, the GOA circuit includes:

[0036] Start-up unit;

[0037] Drop-down unit;

[0038] Output unit;

[0039] The start-up unit is electrically connected to the pull-down unit and the output unit, respectively.

[0040] The startup unit is used to start the main transistor and drive the output gate by inputting a high-level signal to pull up the input level of the main transistor of the output unit.

[0041] The pull-down unit is used to pull down the input level of the main transistor after the output gate of the output unit is driven, so as to turn off the main transistor and prevent malfunction.

[0042] In conjunction with the first possible embodiment of the second aspect of the present invention, in the second possible embodiment, the activation unit includes:

[0043] Clock level terminal, start level terminal, forward scan signal terminal, reverse scan signal terminal, first transistor, second transistor;

[0044] The drop-down unit includes:

[0045] Set level terminal, input level terminal, low level terminal, third transistor, fourth transistor, fifth transistor, sixth transistor and first capacitor;

[0046] The output unit includes:

[0047] Main transistor, output terminal and second capacitor;

[0048] The clock level terminal is electrically connected to the first terminal of the first capacitor and the source of the main transistor;

[0049] The start-up level terminal is electrically connected to the gate of the first transistor;

[0050] The forward scan signal terminal is electrically connected to the drain of the first transistor;

[0051] The reverse scan signal terminal is electrically connected to the source of the second transistor;

[0052] The set level terminal is electrically connected to the gate of the second transistor;

[0053] The source of the first transistor, the drain of the second transistor, the drain of the third transistor, the gate of the main transistor, the gate of the fourth transistor, and the first terminal of the second capacitor are all connected to point P.

[0054] The second terminal of the first capacitor, the gate of the third transistor, the drain of the fourth transistor, and the gate of the fifth transistor are all connected to point A.

[0055] The source of the third transistor, the source of the fourth transistor, the drain of the fifth transistor, and the drain of the sixth transistor are all connected to the low-level terminal.

[0056] The input level terminal is electrically connected to the gate of the sixth transistor;

[0057] The source of the sixth transistor, the source of the fifth transistor, the second terminal of the second capacitor, and the drain of the main transistor are all connected to the output terminal.

[0058] In conjunction with the second possible embodiment of the second aspect of the present invention, in a third possible embodiment, the compensation unit includes:

[0059] Timing control chip;

[0060] The timing control chip is electrically connected to the clock level terminal and is used to output the first pulse timing level and the second pulse timing level respectively.

[0061] Thirdly, a touch display screen is driven by the driving method described in the first aspect.

[0062] By implementing the touch display driving method, circuit and touch display described in this invention, the clock level compensation ΔV when switching to the display stage increases the potential of point P by ΔV', thereby making the voltage of the second point P reach or approach the voltage of the first point P of the row GOA circuit corresponding to the first display stage, which helps to eliminate horizontal lines caused by the scanning time of the touch stage. Attached Figure Description

[0063] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0064] Figure 1 This is a timing diagram of the driving method of the present invention;

[0065] Figure 2 This is a schematic diagram of the GOA circuit of the present invention;

[0066] Figure 3 This is a first schematic diagram of the driving method of the present invention;

[0067] Figure 4 This is a second schematic diagram of the driving method of the present invention;

[0068] Figure 5 This is a third schematic diagram of the driving method of the present invention;

[0069] Figure 6 This is a fourth schematic diagram of the driving method of the present invention;

[0070] Figure 7 This is the fifth schematic diagram of the driving method of the present invention;

[0071] Figure 8 This is a schematic diagram of the connection of the drive circuit module of the present invention;

[0072] Figure 9 This is a schematic diagram of the GOA circuit module connection of the present invention; Detailed Implementation

[0073] The technical solutions of this invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are all within the scope of protection of this invention.

[0074] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0075] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0076] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0077] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0078] When existing touch displays switch between the touch scanning phase and the display scanning phase, horizontal lines appear on the display due to the voltage drop at point P.

[0079] To address the aforementioned issues, this application proposes a touch display driving method, circuit, and touch display.

[0080] Method Example 1

[0081] Firstly, a touch display screen driving method employs a GOA circuit 13 to scan and drive the touch display screen, such as... Figure 3 , Figure 3This is a first schematic diagram of the driving method of the present invention; it includes: step 100, determining the switching cycle period of the display stage-touch stage within a frame of an image on the touch screen; step 200, according to the switching cycle period, starting from the second display stage, compensating the second P-point voltage 23 of the row GOA circuit 13 corresponding to the display stage, so that the second P-point voltage 23 reaches or approaches the first P-point voltage 24 of the row GOA circuit 13 corresponding to the first display stage; wherein, the first P-point voltage 24 is the turn-on voltage of the main transistor of the row GOA circuit 13 corresponding to the first display stage in the switching cycle; the second P-point voltage 23 is the turn-on voltage of the main transistor of the row GOA circuit 13 corresponding to the second display stage in the switching cycle; the first display stage is the first display stage in the switching cycle; the second display stage is a certain display stage after the first display stage in the switching cycle.

[0082] The touch screen cycles through a display phase, touch phase, display phase, touch phase, and display phase within a single frame.

[0083] The first P-point voltage 24 is the P-point voltage of the GOA circuit 13 corresponding to the row of the first display stage (first display stage).

[0084] The voltage at point P is the gate input voltage of the main transistor in GOA circuit 13, used to turn on the main transistor.

[0085] The second display stage is a display stage that follows the first display stage. It can correspond to the first pulse timing level input at the clock level terminal during the display stage, or it can correspond to the second pulse timing level input at the input level terminal during the display stage.

[0086] like Figure 1 , Figure 1 This is a timing diagram of the driving method of the present invention; by compensating the voltage at point P, the voltage at point P of the GOA circuit 13 of the row in the subsequent second display stage can still reach or approach the voltage at point P of the first display stage after the touch stage scanning time, thus avoiding the appearance of horizontal lines on the display.

[0087] Method Example 2

[0088] Based on Example 1, in this example, preferably, as follows: Figure 4 , Figure 4 This is a second schematic diagram of the driving method of the present invention; step 200 includes: step 210, using a timing control chip to input a first pulse timing level to the clock level terminal; step 220, determining that the first pulse timing level is a first timing signal in the second display stage; step 230, increasing the first pulse voltage signal 21 of the first timing signal by ΔV, so that the second P point voltage 23 reaches or approaches the first P point voltage 24.

[0089] The clock level can be Figure 2 In this embodiment, CK outputs the first pulse timing level.

[0090] refer to Figure 1 The timing control chip inputs the first pulse timing level CK1 to the clock level terminal CK, which is controlled by... Figure 2 , Figure 2 The diagram shows the GOA circuit of this invention. As can be seen, the clock level terminal CK is electrically connected to the source of the main transistor M7. By increasing the CK1 signal entering the second display stage by ΔV, the potential of the corresponding point P will increase by ΔV', thereby making up for the original potential drop and helping to eliminate abnormal phenomena such as horizontal lines on the display.

[0091] Preferably, such as Figure 5 , Figure 5 This is a third schematic diagram of the driving method of the present invention; step 230 includes: step 231, obtaining the first pulse voltage sequence of the first timing signal in the second display stage; step 232, taking the first high-level pulse signal in the first pulse voltage sequence as the first pulse voltage signal 21.

[0092] Method Example 3

[0093] Based on Example 1, in this example, preferably, as follows: Figure 6 , Figure 6 This is a fourth schematic diagram of the driving method of the present invention; step 200 further includes: step 240, using a timing control chip to input a second pulse timing level to the clock level terminal; step 250, determining that the second pulse timing level is a second timing signal in the second display stage; step 260, increasing the second pulse voltage signal 22 of the second timing signal by ΔV, so that the second P-point voltage 23 reaches or approaches the first P-point voltage 24; wherein, the first pulse level timing is out of phase with the second pulse level timing.

[0094] In this embodiment, the second pulse timing level CK1B input by the timing control chip to the clock level terminal CK is... Figure 2 It can be seen that the clock level terminal CK is electrically connected to the source of the main transistor M7. By increasing the CK1B signal entering the second display stage by ΔV, the potential of the corresponding P point will increase by ΔV', thereby making up for the original potential drop and helping to eliminate abnormal phenomena such as horizontal lines on the display.

[0095] Preferably, such as Figure 7 , Figure 7This is a fifth schematic diagram of the driving method of the present invention; step 260 includes: step 261, obtaining the second pulse voltage sequence of the second timing signal in the second display stage; step 262, taking the first high-level pulse signal in the second pulse voltage sequence as the second pulse voltage signal 22.

[0096] Drive circuit embodiment 4

[0097] A touch display screen driving circuit uses the driving method of the first aspect to scan and drive the touch display screen, such as... Figure 8 , Figure 8 This is a schematic diagram of the drive circuit module connection of the present invention; it includes a determining unit 11, a compensation unit 12, and a GOA circuit 13; the compensation unit 12 is electrically connected to the determining unit 11 and the GOA circuit 13 respectively; the determining unit 11 is used to determine the switching cycle period of the display stage-touch stage within a frame of the touch screen; the compensation unit 12 is used to compensate the second P-point voltage 23 of the row GOA circuit 13 corresponding to the display stage according to the switching cycle period, starting from the second display stage, so that the second P-point voltage 23 reaches or approaches the first P-point voltage 24 of the row GOA circuit 13 corresponding to the first display stage.

[0098] By compensating for the voltage at point P, the voltage at point P of the GOA circuit 13 in the subsequent second display stage can still reach or approach the voltage at point P of the first display stage after the touch stage scanning time, thus avoiding the appearance of horizontal lines on the display.

[0099] For details, please refer to Figure 1 The timing control chip can input either the first pulse timing level CK1 or the second pulse timing level CK1B to the clock level CK, and then... Figure 2 It can be seen that the clock level terminal CK is electrically connected to the source of the main transistor M7. By increasing the CK1 / CK1B signal entering the second display stage by ΔV, the potential of the corresponding P point will increase by ΔV', thereby making up for the original potential drop and helping to eliminate abnormal phenomena such as horizontal lines on the display.

[0100] Preferably, such as Figure 9 , Figure 9 This is a schematic diagram of the GOA circuit module connection of the present invention; the GOA circuit 13 includes a startup unit 131, a pull-down unit 132, and an output unit 133; the startup unit 131 is electrically connected to the pull-down unit 132 and the output unit 133 respectively; the startup unit 131 is used to start the main transistor and drive the output gate by pulling up the input terminal level of the main transistor of the output unit 133 through a high-level input signal; the pull-down unit 132 is used to turn off the main transistor and prevent malfunction after the output gate of the output unit 133 is driven;

[0101] Specifically,

[0102] The startup unit 131 includes:

[0103] Clock level terminal CK, start level terminal STV, forward scan signal terminal FW, reverse scan signal terminal BW, first transistor M1, second transistor M2;

[0104] The dropdown unit 132 includes:

[0105] The set level terminal RST, the input level terminal CLB, the low level terminal VGL, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the first capacitor C1;

[0106] Output unit 133 includes:

[0107] Main transistor M7, output terminal Gout, and second capacitor C2;

[0108] The clock level terminal CK is electrically connected to the first terminal of the first capacitor C1 and the source of the main transistor M7;

[0109] The start-up level terminal STV is electrically connected to the gate of the first transistor M1;

[0110] The forward scan signal terminal FW is electrically connected to the drain of the first transistor M1;

[0111] The reverse scan signal terminal BW is electrically connected to the source of the second transistor M2;

[0112] The set level terminal RST is electrically connected to the gate of the second transistor M2;

[0113] The source of the first transistor M1, the drain of the second transistor M2, the drain of the third transistor M3, the gate of the main transistor M7, the gate of the fourth transistor M4, and the first terminal of the second capacitor C2 are all connected to point P.

[0114] The second terminal of the first capacitor C1, the gate of the third transistor M3, the drain of the fourth transistor M4, and the gate of the fifth transistor M5 are all connected to point A.

[0115] The source of the third transistor M3, the source of the fourth transistor M4, the drain of the fifth transistor M5, and the drain of the sixth transistor M6 are all connected to the low-level terminal VGL.

[0116] The input level terminal CLB is electrically connected to the gate of the sixth transistor M6;

[0117] The source of the sixth transistor M6, the source of the fifth transistor M5, the second terminal of the second capacitor C2, and the drain of the main transistor M7 are all connected to the output terminal Gout.

[0118] Preferably, the compensation unit 12 includes a timing control chip; the timing control chip is electrically connected to the clock level terminal and is used to output the first pulse timing level and the second pulse timing level respectively.

[0119] GOA Circuit 13 Gate Drive Principle:

[0120] Pull-up section: Taking forward scan as an example, the forward scan signal terminal FW is high, and the reverse scan signal terminal BW is low. The high level of the start-up level terminal STV turns on the first transistor M1. The high level of the forward scan signal terminal FW pulls point P high through the first transistor M1. Then, the high level of CK1 passes through the main transistor M7 and is coupled through the second capacitor C2, causing point P to be boosted a second time, ensuring that the main transistor M7 is fully turned on. At this time, Gout outputs a high level. Thus, the current GOA unit completes the high-level output. At the same time, the high level of point P turns on the fourth transistor M4. The low level terminal VGL pulls point A low through the fourth transistor M4, preventing the high level of point A from causing point P and the output terminal Gout to output signals incorrectly.

[0121] Pull-down section: A high level at the input CLB turns on the sixth transistor M6. A low level at the input VGL pulls the output Gout low through the sixth transistor M6. At the same time, the output Gout of the next stage is connected to the gate set level RST position of the second transistor M2, turning on the second transistor M2. A low level signal at the reverse sweep signal BW pulls point P low to prevent subsequent CK1 / CK1B from being output incorrectly through the main transistor M7. Meanwhile, the periodic high level at the clock level CK pulls point A high, turning on the third transistor M3 and the fifth transistor M5. A low level at the input VGL pulls point P low through the third transistor M3, and the low level at the input VGL pulls Gout low through the fifth transistor M5.

[0122] Thirdly, a touch display screen is driven by the driving method of the first aspect for scanning.

[0123] The present invention provides a touch display driving method, circuit, and touch display screen. By compensating the clock level ΔV when switching to the display stage, the potential of point P will increase by ΔV', thereby making the voltage of the second point P 23 reach or approach the voltage of the first point P 24 of the row GOA circuit 13 corresponding to the first display stage. This helps to eliminate horizontal lines caused by the scanning time of the touch stage.

[0124] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for driving a touch display screen, comprising using a GOA circuit to scan and drive the touch display screen, characterized in that, include: Step 100: Determine the switching cycle period of the display stage-touch stage within one frame of the touch screen; Step 200: According to the switching cycle, starting from the second display stage, compensate the second P-point voltage of the row GOA circuit corresponding to the display stage, so that the second P-point voltage reaches or approaches the first P-point voltage of the row GOA circuit corresponding to the first display stage. Wherein, the voltage at the first point P is the turn-on voltage of the main transistor of the row GOA circuit corresponding to the first display stage in the switching cycle; The voltage at point P is the turn-on voltage of the main transistor of the row GOA circuit corresponding to the second display stage in the switching cycle. The first display phase is the first display phase in the switching cycle; The second display stage is a display stage following the first display stage in the switching cycle; Step 200 includes: Step 210: Use the timing control chip to input the first pulse timing level to the clock level terminal; Step 220: Determine the first timing signal whose first pulse timing level is located in the second display stage; Step 230: Increase the first pulse voltage signal of the first timing signal by ΔV to make the voltage at the second point P reach or approach the voltage at the first point P; Step 240: Use the timing control chip to input the second pulse timing level to the clock level terminal; Step 250: Determine the second timing signal whose second pulse timing level is located in the second display stage; Step 260: Increase the second pulse voltage signal of the second timing signal by ΔV to make the voltage at the second point P reach or approach the voltage at the first point P; Wherein, the timing sequence of the first pulse level is out of phase with the timing sequence of the second pulse level; Step 230 includes: Step 231: Obtain the first pulse voltage sequence of the first timing signal during the second display stage; Step 232: Take the first high-level pulse signal in the first pulse voltage sequence as the first pulse voltage signal; Step 260 includes: Step 261: Obtain the second pulse voltage sequence of the second timing signal during the second display stage; Step 262: Take the first high-level pulse signal in the second pulse voltage sequence as the second pulse voltage signal.

2. A touch display screen driving circuit, characterized in that, The method described in claim 1 is used to scan and drive a touch screen, comprising: Define the unit; Compensation unit; GOA circuit; The compensation unit is electrically connected to the determining unit and the GOA circuit respectively; The determining unit is used to determine the switching cycle period of the display stage-touch stage within one frame of the touch screen image; The compensation unit is used to compensate the second P-point voltage of the row GOA circuit corresponding to the display stage, starting from the second display stage, according to the switching cycle, so that the second P-point voltage reaches or is close to the first P-point voltage of the row GOA circuit corresponding to the first display stage.

3. The touch display screen driving circuit according to claim 2, characterized in that, The GOA circuit includes: Start-up unit; Drop-down unit; Output unit; The start-up unit is electrically connected to the pull-down unit and the output unit, respectively. The startup unit is used to start the main transistor and drive the output gate by inputting a high-level signal to pull up the input level of the main transistor of the output unit. The pull-down unit is used to pull down the input level of the main transistor after the output gate of the output unit is driven, so as to turn off the main transistor and prevent malfunction.

4. The touch display screen driving circuit according to claim 3, characterized in that, The startup unit includes: Clock level terminal, start level terminal, forward scan signal terminal, reverse scan signal terminal, first transistor, second transistor; The drop-down unit includes: Set level terminal, input level terminal, low level terminal, third transistor, fourth transistor, fifth transistor, sixth transistor and first capacitor; The output unit includes: Main transistor, output terminal and second capacitor; The clock level terminal is electrically connected to the first terminal of the first capacitor and the source of the main transistor; The start-up level terminal is electrically connected to the gate of the first transistor; The forward scan signal terminal is electrically connected to the drain of the first transistor; The reverse scan signal terminal is electrically connected to the source of the second transistor; The set level terminal is electrically connected to the gate of the second transistor; The source of the first transistor, the drain of the second transistor, the drain of the third transistor, the gate of the main transistor, the gate of the fourth transistor, and the first terminal of the second capacitor are all connected to point P. The second terminal of the first capacitor, the gate of the third transistor, the drain of the fourth transistor, and the gate of the fifth transistor are all connected to point A. The source of the third transistor, the source of the fourth transistor, the drain of the fifth transistor, and the drain of the sixth transistor are all connected to the low-level terminal. The input level terminal is electrically connected to the gate of the sixth transistor; The source of the sixth transistor, the source of the fifth transistor, the second terminal of the second capacitor, and the drain of the main transistor are all connected to the output terminal.

5. The touch display screen driving circuit according to claim 4, characterized in that, The compensation unit includes: Timing control chip; The timing control chip is electrically connected to the clock level terminal and is used to output the first pulse timing level and the second pulse timing level respectively.

6. A touch display screen, characterized in that, The driving method described in claim 1 is used to scan and drive the touch display screen.

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