Object-oriented integrated circuit physical verification rule checking method and system

Abstract

The application discloses a kind of object-oriented integrated circuit physical verification rule checking method and system, the physical verification rule checking system includes: the layout file to be verified, layout file parser, rule file, rule parser and physical verification engine, to the geometry definition basic geometry processing object of integrated circuit physical verification, provide a kind of method of accessing the common attribute and / or unique attribute of basic geometry processing object;By establishing the hierarchical mapping relationship of the layout file of integrated circuit, and according to this object-oriented method, the rule statement is programmed, to form a rule description file;Rule parser is responsible for the syntax and lexical analysis of this rule description file;Rule verification engine forms specific physical verification rule checking task according to the rule statement after rule parser analysis.The application makes the programming of rule and the algorithm of physical verification rule checking more easily realized, and later maintenance is more friendly.

Description

Technical Field

[0001] This invention relates to the technical field of physical verification of integrated circuits, and in particular to a physical verification rule checking method for integrated circuits that can concisely describe process hotspots. Background Technology

[0002] In the chip design process, physical design is the step closest to the manufacturing process. In addition to ensuring that there are no short circuits or open circuits, most of the work is geared towards manufacturing and requires solving various problems that may arise during manufacturing. These problems are all reflected in a series of rules.

[0003] like Figure 1 As shown, the input to physical design is generally a layout file and a rule file describing process rules, device rules, etc. The layout file is checked against the rules one by one, and then the type, number, and location of violations are reported.

[0004] The layout files are usually in GDS format. Due to data compression considerations, the OASIS format was later developed. Regardless of the format, they are both descriptions of the layout, and both formats are open industry standards.

[0005] The rule files vary greatly and are related to the specific process manufacturer, process feature size, and the EDA tool used. For example, in terms of process manufacturer, the number and content of 28nm rules differ between SMIC and TSMC, with SMIC having significantly more rules to compensate for manufacturing capability limitations. In terms of feature size, the process rules for 28nm and 65nm within SMIC, or for LL and HK processes under 65nm, are quite different. Furthermore, the syntax of rule files differs between different EDA tools.

[0006] Compared to layout files, it's clear that there's no consensus within the industry on how rule files are described. However, for the same rule, the expression methods, keywords used, and overall schemes are very similar, all describing the rule as edges. For example, first find the corresponding edges, then process adjacency relationships, and finally consider special cases to filter violations in specific regions. The advantage of this method is that it reduces the coupling between software development and chip design. No matter how complex the rule, it can be simplified by breaking down complex natural language into constraint descriptions of specific edges. Software development only needs to develop measurement methods; while chip design uses different measurement methods based on the rule description to implement the specific checking functions of the rule.

[0007] However, its drawbacks are also obvious. In advanced processes, especially when introducing optical correction OPC procedures, it falls short when dealing with more complex rules or optical hotspot detection. For example... Figure 2 This rule, the description of a physical verification EDA tool is close to a hundred lines long, and its readability and maintainability are very poor.

[0008] Therefore, how to provide a new physical verification method is a technical problem that needs to be solved in the industry. Summary of the Invention

[0009] To address the technical problems of complex descriptions and poor readability in existing physical verification EDA tools, this invention proposes an object-oriented physical verification rule checking method and system for integrated circuits.

[0010] The object-oriented physical verification rule checking method for integrated circuits proposed in this invention includes:

[0011] The basic geometric processing objects are defined based on the geometry of the physical verification of the integrated circuit, as well as the common and / or unique properties of each basic geometric processing object.

[0012] A rule parser is created so that when the layout of an integrated circuit is based on the rules described in the rule file for physical verification, the rule parser performs lexical and syntactic analysis on the basic geometric processing objects and their common and / or unique attributes of the programming statements in the rule file.

[0013] When physical verification of integrated circuits is required, a rule file is created, and the hierarchical mapping relationship of the integrated circuit layout file and the verification rules are established in the rule file.

[0014] The rule verification engine performs physical verification on the basic geometric processing objects in the layout file of the integrated circuit according to the verification rules and the rule parser.

[0015] Furthermore, the basic geometric processing object includes at least one of the following: layer, graphic, edge, angle, edge pair, set of edge pairs on the outer sides of two image objects, set of edge pairs on the inner sides of two graphic objects, set of edge pairs from the outer side of one graphic to the inner side of another graphic, set of edge pairs from the inner side of one graphic to the outer side of another graphic, square, oblique rectangle, trapezoid, ring, and polygon.

[0016] Furthermore, the common attributes of the graphics, squares, oblique rectangles, trapezoids, rings, and polygons include the area of ​​basic geometric processing objects.

[0017] Furthermore, the graphic's unique properties include the length of the longest side of the basic geometric processing object.

[0018] Furthermore, the unique attributes of the edge include the edge's length, width, and the previous edge of the current edge.

[0019] Furthermore, the unique attributes of the angle include whether the current angle object is 90 degrees, whether the current angle object is 270 degrees, obtaining the previous angle object of the current angle object, and obtaining the next angle object of the current angle object.

[0020] Furthermore, the common attribute of the set of edge pairs outside the two image objects, the set of edge pairs inside the two graphic objects, the set of edge pairs from the outside of one graphic to the inside of another graphic, and the set of edge pairs from the inside of one graphic to the outside of another graphic includes obtaining the distance between the edge pairs.

[0021] Furthermore, the access symbol table corresponding to the basic geometry processing object in the rule file inherits from the TCL scripting language, and the basic geometry processing object is accessed through two different symbols.

[0022] Furthermore, the command keywords for describing the physical verification rules of integrated circuits based on the basic geometric processing object and its corresponding attributes include at least one of the following: design rule constraint logic, create rule, create rule group, create database, create layer graph, and create layer.

[0023] The object-oriented physical verification rule checking system for integrated circuits proposed in this invention includes:

[0024] The layout file to be verified, the layout file parser, the rule file, the rule parser, and the physical verification engine;

[0025] The rule parser and physical verification engine use the object-oriented integrated circuit physical verification method described in the above technical solution to perform physical verification on the layout file to be verified.

[0026] The verification rules of this invention are intuitive, concise, and maintainable, reducing the complexity of rule implementation. They also offer sufficient flexibility for complex rules, enabling rapid modeling. In contrast, traditional rule description methods, which use edges to describe both complex and simple problems, offer only one path, leading to complex rule descriptions and consequently, complex implementations. This invention directly constructs basic geometric processing objects, allowing users to manipulate them directly. This simplifies the geometry of physical verification, enabling direct acquisition of line-ends, angles, and features of multiple consecutive angles, resulting in greater flexibility and easier development. Furthermore, this invention supports abstracting complex hotspots, either existing or potential, into specific types of topological descriptions, providing a higher level of abstraction for business problems. This makes rule description and construction more intuitive and easier, optimizes algorithms, and improves maintainability. Attached Figure Description

[0027] The present invention will now be described in detail with reference to the embodiments and accompanying drawings, wherein:

[0028] Figure 1 It consists of existing technical process rules documents and basic physical verification procedures.

[0029] Figure 2 It is a rule-based description method for natural language in existing technologies.

[0030] Figure 3 This is a flowchart of the present invention.

[0031] Figure 4 This is a schematic diagram of the edge pair object and its attributes according to the present invention.

[0032] Figure 5 This is a schematic diagram of the set of edge pairs on the outer side of two image objects in the double layer of the present invention.

[0033] Figure 6 This is a schematic diagram of the set of edge pairs inside two single-layer graphic objects according to the present invention.

[0034] Figure 7 This is a schematic diagram of the set of edge pairs on the inner sides of the two graphic objects in the double layer of the present invention.

[0035] Figure 8 This is a schematic diagram of the set of edge pairs from the outer side of one graphic to the inner side of another graphic in the double-layer design of this invention.

[0036] Figure 9 This is a schematic diagram of the set of edge pairs from the inside of one graphic to the outside of another graphic in the double-layer design of this invention. Detailed Implementation

[0037] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0038] Therefore, a feature pointed out in this specification is used to describe one feature of one embodiment of the invention, and does not imply that every embodiment of the invention must have the described feature. Furthermore, it should be noted that this specification describes many features. Although certain features may be combined to illustrate possible system designs, these features may also be used in other combinations not explicitly stated. Therefore, unless otherwise stated, the described combinations are not intended to be limiting.

[0039] like Figure 3 As shown, the rule description method for physical verification of integrated circuits of the present invention includes:

[0040] The basic geometric processing objects are defined based on the geometry of the physical verification of the integrated circuit, as well as the common and / or unique properties of each basic geometric processing object.

[0041] A rule parser is created so that when the layout of an integrated circuit is based on the rules described in the rule file for physical verification, the rule parser performs lexical and syntactic analysis on the basic geometric processing objects and their common and / or unique attributes of the programming statements in the rule file.

[0042] When physical verification of integrated circuits is required, a rule file is created, and the hierarchical mapping relationship of the integrated circuit layout file and the verification rules are established in the rule file.

[0043] The rule verification engine performs physical verification on the basic geometric processing objects in the layout file of the integrated circuit according to the verification rules and the rule parser.

[0044] Based on this invention, a new rule file can be obtained, which is a new physical verification format (Object Oriented Verification Format, abbreviated as OOVF) for integrated circuits. This invention provides common geometric shapes and attributes in physical verification, and also has the characteristics of being programmable with a scripting language. In addition, it also extends many commands and attributes specifically for physical verification.

[0045] In one embodiment, the access symbol table corresponding to the basic geometry processing object of the present invention inherits from the TCL scripting language, and the basic geometry processing object is accessed through two different symbols.

[0046] For example, the present invention can access basic geometry processing objects using [] and ., as shown in the table below.

[0047] Serial Number symbol illustrate 1 [] Direct access symbols for object properties 2 . Object property indirect access symbols

[0048] Table 1 Physical Verification Object Access Symbol Table

[0049] This invention opens up all built-in geometric objects other than edges. The basic geometric processing objects provided by this invention include at least one of the following: layers, graphics, edges, angles, edge pairs, sets of edge pairs on the outer sides of two image objects, sets of edge pairs on the inner sides of two graphic objects, sets of edge pairs from the outer side of one graphic to the inner side of another graphic, sets of edge pairs from the inner side of one graphic to the outer side of another graphic, squares, oblique rectangles, trapezoids, rings, and polygons.

[0050] This invention provides a method for accessing the common and / or unique attributes of each basic geometric processing object in a rule file. The principle is that basic geometric processing objects can be described using existing rules, such as angle objects, and then the corresponding description is encapsulated into an object; for example, an angle object is composed of two edges. Then, the hot issues of the angle object are summarized into corresponding attributes. For example, after describing the characteristics of the angle's corresponding attributes using existing rules, it is encapsulated as an attribute of the angle object. The lexical and syntactic analysis of the basic geometric processing objects, their corresponding attributes, and related statements in this invention is mainly based on existing technologies.

[0051] Some commonly used typical objects can be found in the table below.

[0052]

[0053]

[0054]

[0055] Table 2 Keyword List of Physical Verification Objects

[0056] The command keywords for describing the physical verification rules of integrated circuits based on basic geometric processing objects and their corresponding attributes in this invention include at least one of the following: design rule constraint logic, create rule, create rule group, create database, create layer graph, and create layer.

[0057] Given the basic geometric processing objects and corresponding attributes already provided, describing physical design rules becomes much easier and more direct. The commands provided by this invention are shown in the table below.

[0058]

[0059]

[0060] Table 3 Keyword List for Physical Verification Commands

[0061] Although only edge-based solutions are feasible in the existing technology, they become increasingly complex as process hotspots become more difficult to describe. Just as assembly language can do many things, no one would use it specifically to write large software programs. Languages ​​like C++ are necessary for more efficient software development. Therefore, the rule file provided by this invention makes the description of objects more efficient.

[0062] This invention also constructs topological descriptions for different process hotspots based on the unique properties of basic geometric processing objects. By abstracting hotspots into descriptions of topological attributes or relationships, the modeling problem of complex rules can be solved. In early processes, rules were very simple, basically just width or spacing checks. As process linewidths become smaller, many hotspots have emerged, and each hotspot can be abstracted into a specific topological structure, such as rule checks for wide metal types (wide metal) and rule checks for line ends of metal connections (line end), etc.

[0063] The properties of the basic geometric processing object provided by this invention include at least one of the following.

[0064] For example, common properties of shapes, squares, oblique rectangles, trapezoids, rings, and polygons include the area of ​​the basic geometric manipulation object. Specific properties of shapes may also include the length of the longest side of the basic geometric manipulation object.

[0065] The unique properties of an edge can include its length, width, and the previous edge.

[0066] The unique properties of an angle can include whether the current angle object is 90 degrees, whether the current angle object is 270 degrees, getting the previous angle object of the current angle object, and getting the next angle object of the current angle object.

[0067] The common properties of the set of edge pairs on the outer sides of two image objects, the set of edge pairs on the inner sides of two graphic objects, the set of edge pairs from the outer side of one graphic to the inner side of another graphic, and the set of edge pairs from the inner side of one graphic to the outer side of another graphic can include getting the distance between the edge pairs.

[0068] For a polygon, if the physical verification rule returns the longest edge of the polygon, an edge-based implementation would be cumbersome, requiring consideration of symmetry and adjacency semantics. However, by adopting the object-oriented approach of this invention, the constraints are abstracted into filtering a class of corner objects, and the length of the edge of each corner filtered out from the polygon (topology) is checked in the results. This object-oriented approach makes it easy to describe even more complex topologies, greatly simplifying the amount of code and making it very easy to understand and maintain.

[0069] This invention also accelerates the verification of abstract hotspot descriptions. It allows for a single global filter across the same layer and rule type of the layout, minimizing the number of range queries and optimizing performance.

[0070] The present invention can also provide a large number of keywords to describe different basic geometric processing objects and their attributes. The basic geometric processing objects described include, but are not limited to, layers, shapes, objects, edges, corners, edge pairs, sets of edge pairs on the outer sides of two image objects, sets of edge pairs on the inner sides of two graphic objects, sets of edge pairs from the outer side of one graphic to the inner side of another graphic, sets of edge pairs from the inner side of one graphic to the outer side of another graphic, at least one of regular rectangles, oblique rectangles, trapezoids, rings, and polygons.

[0071] The object-oriented integrated circuit physical verification rule checking system proposed in this invention includes: a layout file to be verified, a layout file parser, a rule file, a rule parser, and a physical verification engine. The rule parser and the physical verification engine employ the object-oriented integrated circuit physical verification method described above to physically verify the layout file to be verified.

[0072] The physical verification rule checking system of this invention is based on the basic geometric processing object defined by the geometric shape of the physical verification of integrated circuits. It provides a method for accessing the common and / or unique attributes of the basic geometric processing object. By establishing a hierarchical mapping relationship in the layout file of the integrated circuit and programming rule statements according to this object-oriented method, a rule description file is formed. A rule parser is responsible for parsing the syntax and lexical aspects of this rule description file. The rule verification engine forms specific physical verification rule checking tasks based on the rule statements parsed by the rule parser. The layout file to be verified in this invention is consistent with existing layout files.

[0073] The layout file parser can convert geometric objects in a layout file into an internal, in-memory layout database format, such as the data format of a layout GDSII file.

[0074] The rule file of this invention differs from existing rule files. It adopts an object-oriented concept, meaning that the physical verification objects in the rule file are all basic geometric processing objects. By accessing the relevant attributes of these basic geometric processing objects, the physical verification problem corresponding to the layout can be solved. This invention defines basic geometric processing objects in the rule file based on the geometry of the integrated circuit's physical verification, and provides methods for accessing the common and / or unique attributes of these basic geometric processing objects.

[0075] The rule parser of this invention primarily performs lexical and syntactic analysis on the physical verification rules in the rule file. Based on a clear understanding of the verification object of this invention, existing methods such as Lex and Yacc can be used for lexical and syntactic analysis. The rule parser enables the integrated circuit layout to parse the programming statements related to the basic geometric processing objects and their common and / or unique attributes when the physical verification rules are described in the rule file.

[0076] The physical verification engine of this invention includes a rule verification engine, etc. When physical verification of an integrated circuit is required, it performs physical verification on the basic geometric processing objects in the layout file of the integrated circuit based on the hierarchical mapping relationship of the layout file of the integrated circuit established by the rule file and the verification rules, according to the verification rules and the rule parser.

[0077] Based on the above, the object-oriented integrated circuit physical verification rule checking system of the present invention may further include a result display module, which can store the result of each rule and display it to the user in a text or graphical interface. The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for checking physical verification rules of integrated circuits in an object-oriented manner, characterized in that, include: Based on the geometry of the physical verification of the integrated circuit, define basic geometry processing objects in an object-oriented manner, as well as the common and / or unique properties of each basic geometry processing object. A rule parser is created so that when the layout of the integrated circuit is based on the rules for physical verification described in the rule file, the rule parser performs lexical and syntactic analysis on the basic geometric processing objects and their common and / or unique attributes of the programming statements in the rule file. When physical verification of the integrated circuit is required, a rule file is created, and a hierarchical mapping relationship of the layout file of the integrated circuit is established in the rule file; The system constructs topologies for different process hotspots, builds verification rules based on the topologies, and uses the drc_topology command to program one or more attributes of one or more basic geometric processing objects to describe the same type of process hotspot. The drc_topology command acts as a high-priority global filter, performing a unified global filter on the same layer and the same type of rules in the layout to reduce the number of interval queries. The rule verification engine performs physical verification on the basic geometric processing objects in the layout file of the integrated circuit according to the verification rules and the rule parser.

2. The object-oriented integrated circuit physical verification rule checking method as described in claim 1, characterized in that, The basic geometric processing objects include at least one of the following: layer, graphic, edge, angle, edge pair, set of edge pairs on the outer sides of two image objects, set of edge pairs on the inner sides of two graphic objects, set of edge pairs from the outer side of one graphic to the inner side of another graphic, set of edge pairs from the inner side of one graphic to the outer side of another graphic, square, oblique rectangle, trapezoid, ring, and polygon.

3. The object-oriented integrated circuit physical verification rule checking method as described in claim 2, characterized in that, The common properties of the shapes, squares, oblique rectangles, trapezoids, rings, and polygons include the area of ​​the basic geometric processing objects.

4. The object-oriented integrated circuit physical verification rule checking method as described in claim 2, characterized in that, The graphic's unique properties include the length of the longest side of the basic geometric processing object.

5. The object-oriented integrated circuit physical verification rule checking method as described in claim 2, characterized in that, The unique properties of an edge include its length, width, and the previous edge.

6. The object-oriented integrated circuit physical verification rule checking method as described in claim 2, characterized in that, The unique attributes of the angle include whether the current angle object is 90 degrees, whether the current angle object is 270 degrees, getting the previous angle object of the current angle object, and getting the next angle object of the current angle object.

7. The object-oriented integrated circuit physical verification rule checking method as described in claim 2, characterized in that, The common property of the set of edge pairs outside the two image objects, the set of edge pairs inside the two graphic objects, the set of edge pairs from the outside of one graphic to the inside of another graphic, and the set of edge pairs from the inside of one graphic to the outside of another graphic includes obtaining the distance between the edge pairs.

8. The object-oriented integrated circuit physical verification rule checking method as described in claim 1, characterized in that, The access symbol table corresponding to the basic geometry processing object in the rule file inherits from the TCL scripting language, and the basic geometry processing object is accessed through two different symbols.

9. The object-oriented integrated circuit physical verification rule checking method as described in claim 1, characterized in that, The command keywords for describing the physical verification rules of integrated circuits based on the basic geometric processing object and its corresponding attributes include at least one of the following: design rule constraint logic, create rule, create rule group, create database, create layer graph, and create layer.

10. An object-oriented physical verification rule checking system for integrated circuits, characterized in that, include: The layout file to be verified, the layout file parser, the rule file, the rule parser, and the physical verification engine; The rule parser and physical verification engine use the object-oriented integrated circuit physical verification rule checking method as described in any one of claims 1 to 9 to perform physical verification on the layout file to be verified.

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