A 12T radiation-resistant SRAM cell, module, and circuit using polarity reinforcement technology

Abstract

The present invention relates to the field of analog integrated circuit technology, and more specifically, to a 12T radiation-resistant SRAM cell utilizing polarity reinforcement technology, a module utilizing this cell circuit layout, and a radiation-resistant circuit designed based on this cell circuit. The present invention reinforces the storage nodes Q and QB with NMOS transistors based on the polarity reinforcement technology, generating only negative pulses that, due to the presence of gate capacitance, cannot affect the states of other transistors. This effectively prevents the storage nodes Q and QB from flipping. Simultaneously, data feedback from peripheral nodes S0 and S1 ensures that internal nodes Q and QB can return to their initial states after flipping. This improves the cell's radiation resistance while ensuring that its tolerance performance remains unchanged, enabling recovery even from SEUs occurring on some dual nodes.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design technology, and more specifically, to a 12T radiation-resistant SRAM cell (abbreviated as RHD-12T) using polarity reinforcement technology, a module using the cell circuit layout, and a radiation-resistant circuit designed based on the cell circuit layout. Background Art

[0002] With the rapid development of electronic technology, integrated circuit products have become ubiquitous in people's lives. At the same time, people's requirements for the reliability of electronic technology are becoming increasingly higher. This is especially true as spacecraft spend extended periods in orbit and the radiation environment in space becomes increasingly complex.

[0003] In an environment without atmospheric protection, various radiation sources in space can penetrate spacecraft and their internal electronic devices, particularly static random access memory (SRAM). As device integration increases, SRAM is increasingly susceptible to single event effects (SETs), leading to a higher probability of single event upsets (SEUs). When radiation penetrates a semiconductor device exposed to radiation, a violent ionization reaction occurs instantaneously in the path of the incident path, filling the device's oxide layer with electron-hole pairs. When the electric field in the exposed area is no longer present, the electron-hole pairs gradually recombine and return to normal. When the exposed area is within the active electric field, some of the charge is absorbed by the device's electrodes. When the accumulated charge reaches a critical level, sensitive nodes experience severe transient voltage or current disturbances, causing circuit logic errors or even permanent failures.

[0004] In order to improve the unit's ability to resist SEU, the existing technology mainly includes the following solutions:

[0005] 1) Figure 1 The QUATRO 10T circuit shown in the figure consists of four PMOS transistors and six NMOS transistors, two of which serve as pass transistors. This circuit has better SEU immunity than the traditional six-transistor cell structure, but its failure rate is higher at high frequencies.

[0006] 2) Figure 2 The DICE 12T circuit shown has four storage nodes and four transmission transistors. When an SEU occurs on a single storage node, that node will eventually recover from the fault. However, its tolerance to multiple node upsets is poor.

[0007] 3) Figure 3 The RSP 14T circuit shown in the figure introduces redundant nodes S0 and S1 by adding two PMOS transistors and connecting the gates of two NMOS transistors to nodes Q and QB to increase the circuit's write speed. However, this increases overall power consumption and the layout area.

[0008] 4) Figure 4 The SEA 14T circuit shown, although it reduces the number of sensitive nodes, has the disadvantage of a lower RSNM value.

[0009] The above circuits all have the same disadvantage: although a single storage node has SEU resistance, its recovery capability is weak when SEU occurs simultaneously on two nodes in the circuit. Summary of the Invention

[0010] Based on this, it is necessary to provide a 12T radiation-resistant SRAM unit, module, and circuit using polarity reinforcement technology to address the problem that the SEU resistance of the dual storage nodes of the existing circuit has room for improvement.

[0011] The present invention is achieved by adopting the following technical solutions:

[0012] In a first aspect, the present invention provides a 12T radiation-resistant SRAM cell using polarity reinforcement technology, including four PMOS transistors P1 to P4 and eight NMOS transistors N1 to N8.

[0013] The source of P1 is electrically connected to VDD. The source of P2 is electrically connected to VDD, and its gate is electrically connected to the drain of P1. The source of P3 is electrically connected to the drain of P1, and its gate is electrically connected to the gate of P1. The source of P4 is electrically connected to the drain of P2, and its gate is electrically connected to the drain of P1. The source of N1 is electrically connected to the drain of P3, and its gate is electrically connected to the gate of P4. The source of N2 is electrically connected to the drain of P4, and its gate is electrically connected to the gate of P3. The drain of N3 is electrically connected to the drain of N1, and is provided with a storage node Q. The gate is electrically connected to the drain of N2, and its source is electrically connected to GND. The drain of N4 is electrically connected to the drain of N2, and is provided with a storage node QB. The gate is electrically connected to the drain of N1, and its source is electrically connected to GND. The drain of N5 is electrically connected to the drain of P1, and is provided with a storage node S0. The gate is electrically connected to the drain of N2, and its source is electrically connected to GND. N6's drain is electrically connected to P2's drain and has storage node S1. Its gate is electrically connected to N1's drain, and its source is electrically connected to GND. N7's source is electrically connected to bit line BL, its gate is electrically connected to word line WL, and its drain is electrically connected to N1's drain. N8's source is electrically connected to bit line BLB, its gate is electrically connected to word line WL, and its drain is electrically connected to N2's drain.

[0014] The storage node Q is surrounded by N1, N3, N4, and N7, and the storage node QB is surrounded by N2, N3, N4, and N8, forming a polarity reinforcement structure.

[0015] The implementation of the 12T radiation-hardened SRAM cell using polarity hardening technology is based on the method or process of an embodiment of the present disclosure.

[0016] In a second aspect, the present invention discloses a module that adopts the circuit layout of the 12T radiation-resistant SRAM cell using polarity reinforcement technology disclosed in the first aspect.

[0017] The 12T radiation-hardened SRAM cell module has five interfaces. The first interface is electrically connected to the word line WL. The second interface is electrically connected to the bit line BL. The third interface is electrically connected to the bit line BLB. The fourth interface is used to electrically connect to VDD. The fifth interface is used to electrically connect to GND.

[0018] The implementation of such a module is in accordance with the method or process of an embodiment of the present disclosure.

[0019] In a third aspect, the present invention discloses a radiation-hardened circuit comprising memory cells arranged in an array. The memory cells are the 12T radiation-hardened SRAM cells utilizing polarity hardening technology disclosed in the first aspect. Memory cells in the same column share the same bit lines BL and BLB; memory cells in the same row share the same word line WL.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] The present invention strengthens the NMOS tubes of the storage nodes Q and QB based on the polarity reinforcement technology, which only generates negative pulses. However, due to the existence of gate capacitance, the pulses cannot affect the states of other transistors, which effectively prevents the storage nodes Q and QB from flipping. At the same time, the data feedback of the peripheral nodes S0 and S1 ensures that the internal nodes Q and QB can be restored to their initial states after flipping, thereby ensuring that the unit does not fall behind in tolerance performance and achieving improved radiation resistance, and can achieve recovery even when SEU occurs in some dual nodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 A schematic diagram of the structure of a QUATRO 10T circuit in the prior art provided as background technology for the present invention;

[0024] Figure 2A schematic diagram of the structure of a DICE 12T circuit in the prior art provided as background technology for the present invention;

[0025] Figure 3 A schematic diagram of the structure of the RSP 14T circuit in the prior art provided as background technology of the present invention;

[0026] Figure 4 A schematic diagram of the structure of a SEA 14T circuit in the prior art provided as background technology for the present invention;

[0027] Figure 5 A schematic diagram of the structure of the RHD-12T provided in an embodiment of the present invention;

[0028] Figure 6 for Figure 5 The timing waveform of RHBD-12T.

[0029] Figure 7 for Figure 5 Transient waveform simulation diagram of the RHBD-12T node at different times when double-exponential current source pulses are injected.

[0030] Figure 8 for Figure 5 Transient waveform simulation diagram of some dual nodes of RHBD-12T with double-exponential current source pulse injection at different times.

[0031] Figure 9 For existing technology circuits and Figure 5 Comparison chart of HSNM, RSNM, and WSNM of RHBD-12T.

[0032] Figure 10 Based on Figure 5 Schematic diagram of the structure of the anti-radiation circuit built with RHD-12T. DETAILED DESCRIPTION

[0033] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0034] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component. When a component is considered to be "fixed to" another component, it may be directly fixed to the other component or there may be a central component.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0036] See Figure 5 Figure 2 shows the structure of a 12T radiation-hardened SRAM cell using polarity hardening technology disclosed in this invention. The RHD-12T in this invention includes four PMOS transistors and eight NMOS transistors. The four PMOS transistors are labeled P1 through P4, and the eight NMOS transistors are labeled N1 through N8.

[0037] In this embodiment, the specifications of the transistors are designed as follows: the gate length of all MOS transistors is 65nm, among which the gate width of P1 to P4 is 80nm, the gate width of N1 and N2 is 80nm, the gate width of N3, N4, N5, and N6 is 280nm, and the gate width of N7 and N8 is 140nm.

[0038] The connection relationship of each transistor is as follows:

[0039] The drain of P1 is electrically connected to the gate of P2, the source of P3, the gate of P4, the gate of N1, and the drain of N5, and the gate of P1 is electrically connected to the drain of P2, the gate of P3, the source of P4, the gate of N2, and the drain of N6;

[0040] The drain of P2 is electrically connected to the gate of P1, the gate of P3, the source of P4, the gate of N2, and the drain of N6, and the gate of P2 is electrically connected to the drain of P1, the source of P3, the gate of P4, the gate of N1, and the drain of N5;

[0041] The drain of P3 is electrically connected to the source of N1, and the gate of P3 is electrically connected to the gate of P1, the drain of P2, the source of P4, the gate of N2, and the drain of N6;

[0042] The drain of P4 is electrically connected to the source of N2, and the gate of P4 is electrically connected to the gate of P2, the drain of P1, the source of P3, the gate of N1, and the drain of N5;

[0043] The drain of N1 is electrically connected to the drain of N3, the gate of N4, and the gate of N6, and the gate of N1 is electrically connected to the gate of P2, the drain of P1, the source of P3, the gate of P4, and the drain of N5;

[0044] The drain of N2 is electrically connected to the gate of N3, the drain of N4, and the gate of N5, and the gate of N2 is electrically connected to the gate of P1, the drain of P2, the source of P4, the gate of P3, and the drain of N6;

[0045] The drain of N3 is electrically connected to the drain of N1, the gate of N4, and the gate of N6, and the gate of N3 is electrically connected to the drain of N2, the drain of N4, and the gate of N5;

[0046] The drain of N4 is electrically connected to the gate of N3, the drain of N2, and the gate of N5, and the gate of N4 is electrically connected to the drain of N1, the gate of N3, and the gate of N6;

[0047] The drain of N5 is electrically connected to the drain of P1, the gate of P2, the source of P3, the gate of P4, and the gate of N1, and the gate of N5 is electrically connected to the gate of N3, the drain of N2, and the drain of N4.

[0048] The drain of N6 is electrically connected to the gate of P1, the drain of P2, the gate of P3, the source of P4, and the gate of N2, and the gate of N6 is electrically connected to the drain of N1, the drain of N3, and the gate of N4.

[0049] The bit line BL is electrically connected to the source of the transfer transistor N7; the bit line BLB is electrically connected to the source of the transistor N8; the word line WL is electrically connected to the gates of the transfer transistors N7 and N8; the drain of the transfer transistor N7 is electrically connected to the drains of N1 and N3; the drain of the transfer transistor N8 is electrically connected to the drains of N2 and N4; VDD is electrically connected to the sources of P1 and P2; the sources of N3, N4, N5 and N6 are grounded.

[0050] It should be noted that there is some duplication in the above connection relationships, but it is retained for ease of understanding.

[0051] For the RHD-12T, P1, P2, P3, P4, and N1 and N2 serve as pull-up transistors, while N3, N4, N5, and N6 serve as pull-down transistors. N1 and P3 form an inverter, while N2 and P4 form another inverter, and the two inverters are cross-coupled. Redundant nodes S0 and S1 (located on the periphery of the circuit, also known as peripheral nodes) are cross-coupled by P1 and P2, while storage nodes Q and QB (located inside the circuit, also known as internal nodes) are cross-coupled by N3 and N4. Storage nodes Q and QB are completely surrounded by NMOS transistors, that is, storage node Q is surrounded by N1, N3, N4, and N7, and storage node QB is surrounded by N2, N3, N4, and N8, forming a polarity-reinforced structure. Storage node Q is connected to bit line BL via N7, and storage node QB is connected to bit line BLB via N8. N7 and N8 are controlled by word line WL.

[0052] See Figure 6The timing waveform (simulation conditions are: Corner: TT; Temperature: 27℃; VDD: 1.2V), the working mode of RHD-12T is as follows:

[0053] In the holding phase of the cell, the bit lines BL and BLB are precharged to a high level, the word line WL is at a low level, and the cell maintains an initial state and does not operate.

[0054] When the cell is in the data read phase, the bit lines BL and BLB are precharged to a high level, the word line WL is high, and N7 and N8 are turned on. Discharge occurs according to the stored data, creating a voltage difference between the bit lines BL and BLB. In this embodiment, the cell is connected to a sense amplifier. The sense amplifier reads the stored data based on the voltage difference between the bit lines BL and BLB. Specifically, if the stored data is '0', then "Q = S0 = 0, QB = S1 = 1", and the bit line BL is discharged to ground through N7 and N3, creating a voltage difference between the bit lines BL and BLB. If the stored data is '1', then "Q = S0 = 1, QB = S1 = 0", and the bit line BLB is discharged to ground through N8 and N4, creating a voltage difference between the bit lines BL and BLB. It should be noted that these two voltage differences are different; the sense amplifier reads a "0" based on the former and a "1" based on the latter.

[0055] When the cell is in the data write phase, word line WL is high; the storage node is written based on the level of bit lines BL and BLB. Specifically, if bit line BL is high and bit line BLB is low, a '1' is written to storage node Q and redundant node S0 via N7, and the corresponding storage node QB and redundant node S1 are set to '0'. If bit line BL is low and bit line BLB is high, a '1' is written to storage node QB and redundant node S1 via N8, and the corresponding storage node Q and redundant node S0 are set to '0'.

[0056] The inventor simulated the node anti-SEU situation of RHD-12T, and the simulation condition was: VDD: 1.2V. Figure 7 , Q, QB, S0, S1 can be restored when they radiate individually. Figure 8, storage node Q and redundant node S0 can be recovered when radiation occurs simultaneously, and storage node QB and redundant node S1 can be recovered when radiation occurs simultaneously. This is because if the storage node of the cell is bombarded by particles, since storage nodes Q and QB are surrounded by NMOS transistors, according to the principle of polarity reinforcement, the spatial particles bombarding the NMOS transistors will only generate "1-0" and "0-0" voltage pulses at the nodes, that is, only negative pulses will be generated. Due to the existence of gate capacitance, this pulse cannot affect the state of other transistors, which effectively prevents the storage nodes Q and QB from flipping. At the same time, the data feedback of peripheral nodes S0 and S1 ensures that internal nodes Q and QB can return to their initial state after flipping, thereby improving the cell's ability to resist SEU. If other non-critical nodes (referring to endpoints other than Q, QB, S0, and S1, such as the gates of N7 and N8) are bombarded by particles, the cell is even less susceptible to impact.

[0057] In addition, the inventors also simulated the tolerance performance of RHD-12T and compared it with the existing circuit. The simulation conditions were: Corner: TT; Temperature: 27℃; VDD: 1.2V. Figure 9 As can be seen, the performance of RHD-12T is similar to that of the existing circuit technology. Therefore, RHD-12T achieves improved radiation resistance while ensuring that the tolerance performance is not lost.

[0058] Furthermore, based on the aforementioned 12T radiation-hardened SRAM cell utilizing polarity hardening technology, this embodiment also discloses a module that utilizes the aforementioned 12T radiation-hardened SRAM cell layout utilizing polarity hardening technology. This module packaging facilitates the promotion and application of the 12T radiation-hardened SRAM cell utilizing polarity hardening technology.

[0059] The 12T radiation-hardened SRAM cell module has five interfaces. The first interface is electrically connected to the word line WL. The second interface is electrically connected to the bit line BL. The third interface is electrically connected to the bit line BLB. The fourth interface is used to electrically connect to VDD. The fifth interface is used to electrically connect to GND.

[0060] Radiation-hardened circuits can also be constructed based on the aforementioned 12T radiation-hardened SRAM cells using polarity hardening technology. Specifically, the radiation-hardened circuit includes memory cells arranged in an array. These memory cells utilize the aforementioned 12T radiation-hardened SRAM cells using polarity hardening technology. Memory cells in the same column share the same bit lines BL and BLB; memory cells in the same row share the same word line WL.

[0061] The radiation-hardening circuit also includes a precharge circuit, a wordline data control module, and a sense amplifier. The precharge circuit is used to precharge the bitlines BL and BLB. The wordline data control module controls the voltage level of the wordline WL. The sense amplifier is used to read data based on the voltage difference between the bitlines BL and BLB. Each column is equipped with a sense amplifier, whose two input terminals are connected to the bitlines BL and BLB, respectively.

[0062] See Figure 10 , for the case of two columns. In the case of circuit hold, the word line WL remains closed and the information inside the storage cell remains unchanged. When a read operation is required, the word line WL of the corresponding row is turned on, where the bit line voltage is pulled to a high level by the precharge circuit. The word lines BL and BLB corresponding to the selected column will generate a voltage difference. When the voltage difference reaches the minimum voltage difference that the sense amplifier can recognize (usually 200mv), the information in the storage cell will be read out. In the case of a write operation, the word line WL of the corresponding row is turned on, the corresponding column will store the write information value, and it will be written to RHD-12 through the word line WL.

[0063] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0064] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A 12T radiation-hardened SRAM cell using polarity hardening technology, characterized in that: include: A PMOS transistor P1, whose source is electrically connected to VDD; a PMOS transistor P2 having a source electrically connected to VDD and a gate electrically connected to the drain of P1; a PMOS transistor P3, whose source is electrically connected to the drain of P1 and whose gate is electrically connected to the gate of P1 and the drain of P2; a PMOS transistor P4, whose source is electrically connected to the drain of P2 and whose gate is electrically connected to the drain of P1; an NMOS transistor N1 , a source of which is electrically connected to the drain of P3 , and a gate of which is electrically connected to the gate of P4 ; an NMOS transistor N2, a source of which is electrically connected to the drain of P4, and a gate of which is electrically connected to the gate of P3; an NMOS transistor N3 , a drain of which is electrically connected to the drain of N1 and provided with a storage node Q, a gate of which is electrically connected to the drain of N2 , and a source of which is electrically connected to GND; An NMOS transistor N4 , having a drain electrically connected to the drain of N2 and provided with a storage node QB, a gate electrically connected to the drain of N1 , and a source electrically connected to GND; An NMOS transistor N5 , having a drain electrically connected to the drain of P1 and provided with a redundant node S0 , a gate electrically connected to the drain of N2 , and a source electrically connected to GND; An NMOS transistor N6, whose drain is electrically connected to the drain of P2 and is provided with a redundant node S1, whose gate is electrically connected to the drain of N1, and whose source is electrically connected to GND; NMOS transistor N7, having a source electrically connected to bit line BL, a gate electrically connected to word line WL, and a drain electrically connected to the drain of N1; as well as NMOS transistor N8, having a source electrically connected to bit line BLB, a gate electrically connected to word line WL, and a drain electrically connected to the drain of N2; The storage node Q is surrounded by N1, N3, N4, and N7, and the storage node QB is surrounded by N2, N3, N4, and N8, forming a polarity reinforcement structure.

2. The 12T radiation-hardened SRAM cell using polarity hardening technology according to claim 1, wherein: P1, P2, P3, P4 and NMOS transistors N1 and N2 act as pull-up transistors, while N3, N4, N5 and N6 act as pull-down transistors; N1 and P3 form an inverter, N2 and P4 form another inverter, and the two inverters are cross-coupled; the storage node Q is connected to the bit line BL through N7, and the storage node QB is connected to the bit line BLB through N8. N7 and N8 are controlled by the word line WL.

3. The 12T radiation-hardened SRAM cell using polarity hardening technology according to claim 1, wherein: The gate lengths of P1, P2, P3, P4, N1, N2, N3, N4, N5, N6, N7, and N8 are all 65nm; Among them, the gate widths of P1, P2, P3, and P4 are all 80nm, the gate widths of N1 and N2 are 80nm, the gate widths of N3, N4, N5, and N6 are 280nm, and the gate widths of N7 and N8 are 140nm.

4. The 12T radiation-hardened SRAM cell using polarity hardening technology according to claim 1, wherein: In the holding phase of the cell, the bit lines BL and BLB are precharged to a high level, the word line WL is at a low level, and the cell maintains an initial state and does not operate.

5. The 12T radiation-hardened SRAM cell using polarity hardening technology according to claim 1, wherein: When the cell is in the data reading stage, the bit lines BL and BLB are precharged to a high level, the word line WL is at a high level, and N7 and N8 are turned on; the bit lines BL and BLB are discharged according to the stored data, so that a voltage difference is generated between the bit lines BL and BLB; The cell is connected to a sense amplifier for sensing stored data according to the voltage difference between the bit lines BL and BLB.

6. The 12T radiation-hardened SRAM cell using polarity hardening technology according to claim 5, characterized in that: If the stored data is '0', then "Q=S0=0, QB=S1=1", the bit line BL is discharged to the ground through N7 and N3, so that a voltage difference is generated between the bit lines BL and BLB; If the stored data is '1', then "Q=S0=1, QB=S1=0", and the bit line BLB is discharged to the ground through N8 and N4, so that a voltage difference is generated between the bit lines BL and BLB.

7. The 12T radiation-hardened SRAM cell using polarity hardening technology according to claim 1, wherein: When the cell is in the data writing phase, the word line WL is at a high level; the storage node is written according to the levels of the bit lines BL and BLB.

8. The 12T radiation-hardened SRAM cell using polarity hardening technology according to claim 7, wherein: If the bit line BL is high and the bit line BLB is low, '1' is written to the storage node Q and the redundant node S0 through N7; If the bit line BL is at a low level and the bit line BLB is at a high level, '1' is written to the storage node QB and the redundant node S1 through N8.

9. A 12T radiation-hardened SRAM cell module, characterized in that: A circuit layout of a 12T radiation-hardened SRAM cell using polarity hardening technology according to any one of claims 1 to 8 is adopted; The interfaces of the 12T radiation-hardened SRAM cell module include: a first interface electrically connected to the word line WL; a second interface electrically connected to the bit line BL; a third interface electrically connected to the bit line BLB; a fourth interface configured to be electrically connected to VDD; and The fifth interface is used for being electrically connected to GND.

10. A radiation-resistant circuit, characterized in that: The invention comprises memory cells distributed in an array; the memory cells are 12T radiation-resistant SRAM cells using polarity reinforcement technology according to any one of claims 1 to 8; Memory cells in the same column share the same bit line BL and bit line BLB; memory cells in the same row share the same word line WL.

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