Thin film transistor and display device including the same

Abstract

A thin film transistor and a display device including the same are provided. The thin film transistor includes an active layer over a substrate; and a first gate at least partially overlapping the active layer, wherein the active layer includes a channel portion, a first connection portion in contact with one side of the channel portion, and a second connection portion in contact with another side of the channel portion, wherein a first region of the channel portion is in contact with the first connection portion and a second region of the channel portion is in contact with the second connection portion, wherein the thin film transistor further includes a conductive material layer between the substrate and the active layer, wherein the conductive material layer overlaps the second region of the channel portion and does not overlap the first region of the channel portion, and the conductive material layer is connected to the second connection portion.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0147157, filed on October 29, 2021, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] This invention relates to a thin-film transistor and a display device including a thin-film transistor. Background Technology

[0004] In the field of electronic devices, transistors are widely used as switching or driving devices. In particular, because thin-film transistors can be fabricated on glass or plastic substrates, they are widely used as switching devices in display devices such as liquid crystal displays or organic light-emitting diodes.

[0005] Display devices may include, for example, switching thin-film transistors (TFTs) and driving thin-film transistors (TFTs). Advantageously, the switching TFTs have a smaller S-factor to improve on-off characteristics, while the driving TFTs have a larger S-factor to represent grayscale levels.

[0006] Thin-film transistors (TFTs) typically have a small S-factor to ensure on-off characteristics. Therefore, when these TFTs are used as driver transistors in display devices, it is difficult to reproduce the grayscale levels of the display.

[0007] Therefore, thin-film transistors (TFTs) with large S-factors are needed to drive TFTs in display devices and easily reproduce grayscale levels. Furthermore, even if a TFT has a large S-factor, it must also possess excellent current characteristics in the on-state. Summary of the Invention

[0008] The present invention was made in view of the above problems. One object of the present invention is to provide a thin-film transistor having a large S-factor and excellent current characteristics in the on state.

[0009] Another object of the present invention is to provide a thin-film transistor having a large S-factor and a large current value in the on state.

[0010] Another object of the present invention is to provide a thin-film transistor that has a relatively large S-factor when the effective gate voltage on one side of the channel is lower than the effective gate voltage on the other side of the channel, and has excellent on-current characteristics due to the small spacing between the gate and the active layer.

[0011] Another object of the present invention is to provide a thin-film transistor that has a large S-factor and excellent on-current characteristics by disposing a conductive material layer or an auxiliary gate on one side of the channel.

[0012] Another object of the present invention is to provide a display device that has excellent grayscale rendering capability and excellent current characteristics by including a driving thin-film transistor having a large S-factor and a large on-current characteristic.

[0013] In addition to the objectives of the invention as described above, those skilled in the art will clearly understand additional objectives and features of the invention from the following description.

[0014] According to one aspect of the invention, the above and other objectives can be achieved by providing a thin-film transistor comprising: an active layer on a substrate; and a first gate at least partially overlapping the active layer, wherein the active layer comprises: a channel portion; a first connection portion contacting one side of the channel portion; and a second connection portion contacting the other side of the channel portion, wherein a first region of the channel portion contacts the first connection portion, and a second region of the channel portion contacts the second connection portion, wherein the thin-film transistor further comprises a conductive material layer located between the substrate and the active layer, wherein the conductive material layer overlaps with the second region of the channel portion but not with the first region of the channel portion, and the conductive material layer is connected to the second connection portion.

[0015] The thin-film transistor can be configured such that the effective gate voltage applied to a first region of the channel is greater than the effective gate voltage applied to a second region of the channel.

[0016] The conductive material layer may include a material with light-shielding properties.

[0017] The thin-film transistor may further include a second gate disposed between the first gate and the active layer, wherein the second gate may overlap with the first region of the channel portion.

[0018] The second gate may not overlap with the second region of the channel portion.

[0019] At least a portion of the second gate may overlap with the first gate, and at least a portion of the second gate may not overlap with the first gate.

[0020] The thin-film transistor can be configured such that the same voltage can be applied to the first gate and the second gate.

[0021] The thin-film transistor may further include a second gate located between the first gate and the active layer, wherein the second gate may overlap with the first region of the channel portion and may not overlap with the second region of the channel portion.

[0022] The thin-film transistor may further include a second conductive material layer located between the substrate and the active layer, wherein the second conductive material layer may overlap with a first region of the channel portion and may not overlap with a second region of the channel portion, and the thin-film transistor is configured such that a voltage identical to the voltage applied to the first gate can be applied to the second conductive material layer.

[0023] The first gate may have a step profile, and the distance between the first gate and the first region may be smaller than the distance between the first gate and the second region.

[0024] The thin-film transistor may further include a gate insulating layer located between the first gate and the active layer, wherein the gate insulating layer may have a stepped profile, and the thickness of the gate insulating layer in the first region may be less than the thickness of the gate insulating layer in the second region.

[0025] The thin-film transistor may further include: a third conductive material layer located between the substrate and the active layer; and a buffer layer located between the third conductive material layer and the active layer, wherein the buffer layer may have a stepped profile, and the thickness of the buffer layer overlapping the first region may be less than the thickness of the buffer layer overlapping the second region.

[0026] The third conductive material layer can be connected to the first gate.

[0027] The channel portion of the active layer may have a stepped profile.

[0028] The thin-film transistor may further include: a third conductive material layer located between the substrate and the active layer; and a buffer layer located between the third conductive material layer and the active layer, wherein the buffer layer may have a stepped profile, the thickness of the buffer layer overlapping the first region may be less than the thickness of the buffer layer overlapping the second region, and the third conductive material layer may be connected to the first gate.

[0029] The channel portion of the active layer may have a stepped profile, and the first gate may have a stepped profile.

[0030] The active layer may contain an oxide semiconductor material.

[0031] The oxide semiconductor material may include at least one of IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GZO (GaZnO)-based, ITZO (InSnZnO)-based, and FIZO (FeInZnO)-based oxide semiconductor materials.

[0032] The active layer may include: a first oxide semiconductor layer; and a second oxide semiconductor layer on the first oxide semiconductor layer.

[0033] The active layer may further include a third oxide semiconductor layer on the second oxide semiconductor layer.

[0034] According to another aspect of the invention, the above and other objectives can be achieved by providing a display device including the aforementioned thin-film transistors. Attached Figure Description

[0035] The above and other objects, features, and advantages of the invention will become more clearly understood from the following detailed description given with reference to the accompanying drawings. In the drawings:

[0036] Figure 1A This is a plan view illustrating a thin-film transistor according to one embodiment of the present invention;

[0037] Figure 1B , 1C 1D and 1E are cross-sectional views illustrating a thin-film transistor according to an embodiment of the present invention;

[0038] Figure 2 This is a cross-sectional view illustrating a thin-film transistor according to another embodiment of the present invention;

[0039] Figure 3 This is a cross-sectional view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0040] Figure 4A This is a plan view illustrating a thin-film transistor according to yet another embodiment of the present invention. Figure 4B This is a cross-sectional view of a thin-film transistor according to yet another embodiment of the present invention;

[0041] Figure 5 This is a cross-sectional view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0042] Figure 6A This is a plan view illustrating a thin-film transistor according to yet another embodiment of the present invention. Figure 6B This is a cross-sectional view of a thin-film transistor according to yet another embodiment of the present invention;

[0043] Figure 7 It is a graph illustrating the threshold voltage of a thin-film transistor;

[0044] Figure 8A and 8B This is a schematic diagram illustrating the effective gate voltage of a thin-film transistor;

[0045] Figure 9A and 9B This is a schematic diagram illustrating the effective gate voltage of a thin-film transistor according to an embodiment of the present invention;

[0046] Figure 10A and 10B This is a schematic diagram illustrating the effective gate voltage of a thin-film transistor according to another embodiment of the present invention;

[0047] Figure 11 This is a schematic diagram illustrating a display device according to another embodiment of the present invention;

[0048] Figure 12 It is a diagram Figure 11 The circuit diagram of any pixel;

[0049] Figure 13 It is a diagram Figure 12 A planar image of pixels;

[0050] Figure 14 It is along Figure 13 A sectional view taken by line I-I';

[0051] Figure 15 This is a circuit diagram illustrating any pixel of a display device according to yet another embodiment of the present invention;

[0052] Figure 16 It is along Figure 15 A sectional view taken from line II-II';

[0053] Figure 17 This is a circuit diagram illustrating any pixel of a display device according to yet another embodiment of the present invention;

[0054] Figure 18 This is a circuit diagram illustrating any pixel of a display device according to another embodiment of the present invention. Detailed Implementation

[0055] The advantages and features of the invention, as well as its implementation, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments listed herein. Rather, these embodiments are provided to make the disclosure of the invention comprehensive and complete, and to fully convey the scope of the invention to those skilled in the art. Furthermore, the invention is defined only by the scope of the claims.

[0056] The shapes, sizes, proportions, angles, and quantities disclosed in the drawings to describe various embodiments of the invention are merely examples, and therefore the invention is not limited to the details illustrated. Similar reference numerals refer to similar elements throughout. In the following description, detailed descriptions of related known functions or constructions will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the focus of the invention.

[0057] Where the terms “including,” “having,” and “contains” are used in the description in this application, other parts may be added unless “only” is used.

[0058] When interpreting a factor, even if not explicitly stated, the factor should be interpreted as including a range of error.

[0059] When describing positional relationships, such as when the positional relationship is described as "on," "above," "below," and "after," one or more additional parts may be placed between the two parts, unless "exactly" or "directly" is used.

[0060] This document may use spatially relative terms such as “below,” “lower,” “below,” “above,” and “upper” to readily describe the relationship of one or more elements shown in the figures to other elements. It will be understood that these terms are intended to cover different orientations of the device beyond those depicted in the figures. For example, if the device shown in the figures is reversed, a device described as being “below” or “lower” to other devices may be arranged to be “above” to other devices. Thus, the exemplary term “below or lower” may include both “below or lower” and “upper” orientations. Similarly, the exemplary term “upper” or “above” may include both “above” and “below or lower” orientations.

[0061] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous situations may be included unless “exactly” or “directly” is used.

[0062] It will be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0063] The term "at least one" should be understood to include any one and all combinations of one or more of the relevant listed items. For example, "at least one of the first, second and third items" means a combination of all items selected from the first, second and third items, as well as the first, second or third item.

[0064] Those skilled in the art will fully understand that the features of the various embodiments of the present invention can be combined or integrated with each other, either partially or entirely, and can be technically interoperable and driven in various ways. The various embodiments of the present invention can be implemented independently of each other, or implemented jointly in a mutually dependent relationship.

[0065] A thin-film transistor and a display device including a thin-film transistor according to embodiments of the present invention are described in detail with reference to the accompanying drawings. In the drawings, even in different figures, the same or similar elements are referred to by the same reference numerals.

[0066] In embodiments of the present invention, for ease of description, the source and drain are distinguished from each other. However, the source and drain can be used interchangeably. The source can be the drain, and the drain can be the source. Furthermore, the source in any embodiment of the present invention can be the drain in another embodiment of the present invention, and the drain in any embodiment of the present invention can be the source in another embodiment of the present invention.

[0067] For ease of description, in some embodiments of the present invention, the source region is separated from the source, and the drain region is separated from the drain. However, the embodiments of the present invention are not limited to this structure. For example, the source region can be the source, and the drain region can be the drain. Furthermore, the source region can be the drain, and the drain region can be the source.

[0068] Figure 1A This is a plan view illustrating a thin-film transistor according to one embodiment of the present invention; Figure 1B , 1C 1D and 1E are cross-sectional views illustrating a thin-film transistor according to an embodiment of the present invention. Specifically, Figure 1B It is along Figure 1A A sectional view taken by line A-A'.

[0069] A thin-film transistor 100 according to one embodiment of the present invention includes an active layer 130 on a substrate 110 and a first gate 151 at least partially overlapping the active layer 130. The active layer 130 includes: a channel portion 130n; a first connection portion 131 contacting one side of the channel portion 130n; and a second connection portion 132 contacting the other side of the channel portion 130n. According to one embodiment of the present invention, the effective gate voltage applied to a first region of the channel portion 130n contacting the first connection portion 131 is greater than the effective gate voltage applied to a second region of the channel portion 130n contacting the second connection portion 132.

[0070] According to one embodiment of the present invention, the thin-film transistor 100 further includes a first conductive material layer 171 located between the substrate 110 and the active layer 120. The first conductive material layer 171 overlaps with a second region of the channel portion 130n without overlapping with a first region of the channel portion 130n. The first conductive material layer 171 may be connected to a second connection portion 132.

[0071] The following will refer to Figure 1A and 1B A thin-film transistor 100 according to one embodiment of the present invention will be described in more detail.

[0072] Glass or plastic can be used as substrate 110. Transparent plastics with flexible properties, such as polyimide, can be used as plastic. When polyimide is used as substrate 110, heat-resistant polyimide that can withstand high temperatures can be used, taking into account the high-temperature deposition process performed on substrate 110.

[0073] A light-shielding layer 111 may be disposed on the substrate 110. The light-shielding layer 111 overlaps with the channel portion 130n. The light-shielding layer 111 blocks light incident from the outside to protect the channel portion 130n.

[0074] The light-shielding layer 111 may be made of a material with light-shielding properties. The light-shielding layer 111 may contain at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), and iron (Fe). According to one embodiment of the invention, the light-shielding layer 111 may be conductive.

[0075] The light-shielding layer 111 can be omitted. Although Figure 1B Not shown in the diagram, the lower buffer layer 220 may be disposed between the substrate 110 and the light-shielding layer 111 (see [reference]). Figure 14 and 16 Although not shown, the light-shielding layer 111 may be electrically connected to either the drain 161 or the source 162. The light-shielding layer 111 may also be electrically connected to the first gate 151.

[0076] A first buffer layer 121 is disposed on the light-shielding layer 111. The first buffer layer 121 may include at least one of silicon oxide, silicon nitride, and metal-based oxide. According to one embodiment of the present invention, the first buffer layer 121 may include at least one of silicon oxide and silicon nitride. The first buffer layer 121 may have a single-layer structure or a multi-layer structure.

[0077] The first buffer layer 121 protects the active layer 130. In addition, the upper surface of the substrate 110, on which the light-shielding layer 111 is disposed, can be made uniform by the first buffer layer 121.

[0078] The first conductive material layer 171 is disposed on the first buffer layer 121.

[0079] According to one embodiment of the present invention, the first conductive material layer 171 may be conductive. The first conductive material layer 171 may comprise at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), and iron (Fe). The first conductive material layer 171 may have a multilayer structure comprising at least two conductive layers with different physical properties.

[0080] Furthermore, the first conductive material layer 171 may include a material with light-shielding properties. Therefore, the first conductive material layer 171 can be used as a light-shielding layer. The first conductive material layer 171 can block light incident on the substrate 110 to protect the channel portion 130n.

[0081] A first conductive material layer 171 is disposed between the substrate 110 and the active layer 130, and overlaps with a portion of the channel portion 130n of the active layer 130. The electrical characteristics of the first conductive material layer 171 will be described later.

[0082] A second buffer layer 122 is disposed on the first conductive material layer 171. The second buffer layer 122 may include at least one of an insulating material selected from silicon oxide, silicon nitride, and metal-based oxides. According to one embodiment of the present invention, the second buffer layer 122 may include at least one of silicon oxide and silicon nitride. The second buffer layer 122 may have a single-layer structure or a multi-layer structure.

[0083] The second buffer layer 122 protects the active layer 130. Furthermore, the upper surface of the substrate 110 can be made more uniform through the second buffer layer 122. The second buffer layer 122 is formed such that the first conductive material layer 171 and the channel portion 130 are spaced apart from and insulated from each other.

[0084] According to one embodiment of the present invention, the first buffer layer 121 and the second buffer layer 122 are collectively referred to as buffer layer 120, but one embodiment of the present invention is not limited thereto, and each of the first buffer layer 121 and the second buffer layer 122 may be referred to as a buffer layer. According to one embodiment of the present invention, each insulating layer disposed between the substrate 110 and the active layer 130 may be referred to as a buffer layer.

[0085] The active layer 130 is disposed on the second buffer layer 122.

[0086] The active layer 130 may be formed of a semiconductor material. The active layer 130 may include any one of amorphous silicon semiconductor material, polycrystalline silicon semiconductor material, and oxide semiconductor material.

[0087] According to one embodiment of the present invention, the active layer 130 may include an oxide semiconductor material. The oxide semiconductor material may include, for example, at least one of IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GZO (GaZnO)-based, ITZO (InSnZnO)-based, and FIZO (FeInZnO)-based oxide semiconductor materials. However, one embodiment of the present invention is not limited thereto, and the active layer 130 may be made of other oxide semiconductor materials known in the art.

[0088] The active layer 130 may include a channel portion 130n, a first connection portion 131, and a second connection portion 132. The channel portion 130n overlaps with the first gate 151.

[0089] A portion of the channel portion 130n does not overlap with the first conductive material layer 171, while another portion of the channel portion 130n overlaps with the first conductive material layer 171. According to one embodiment of the present invention, the region of the channel portion 130n that does not overlap with the first conductive material layer 171 may be referred to as a first region, and the region of the channel portion 130n that overlaps with the first conductive material layer 171 may be referred to as a second region.

[0090] According to one embodiment of the present invention, a first region of the channel portion 130n contacts a first connecting portion 131, and a second region of the channel portion 130n contacts a second connecting portion 132.

[0091] The first connection portion 131 and the second connection portion 132 of the active layer 130 can be designed not to overlap with the first gate 151. The first connection portion 131 and the second connection portion 132 can be formed by selectively conductiveizing the semiconductor material. Providing conductivity to selected portions of the active layer 130 refers to selective conductiveizing. Selective conductiveizing can be performed by doping, plasma treatment, etc.

[0092] According to one embodiment of the present invention, the first connection portion 131 of the active layer 130 may be a drain region, and the second connection portion 132 may be a source region. According to one embodiment of the present invention, the first connection portion 131 may be referred to as the drain, and the second connection portion 132 may be referred to as the source.

[0093] However, one embodiment of the present invention is not limited to the above example; the first connection portion 131 may be a source region, and the second connection portion 132 may be a drain region. Furthermore, the first connection portion 131 may be referred to as the source, and the second connection portion 132 may be referred to as the drain.

[0094] A gate insulating layer 140 is disposed on the active layer 130. The gate insulating layer 140 may comprise at least one of silicon oxide, silicon nitride, and metal-based oxide. The gate insulating layer 140 may have a single-layer structure or a multi-layer structure.

[0095] Reference Figure 1B The gate insulating layer 140 is not patterned and may be integrally formed on the entire surface of the substrate 110, but one embodiment of the invention is not limited thereto, and the gate insulating layer 140 may be patterned. For example, the gate insulating layer 140 may be patterned to a shape corresponding to the first gate 151.

[0096] The gate insulating layer 140 protects the channel portion 130n.

[0097] The first gate 151 is disposed on the gate insulating layer 140. The first gate 151 overlaps with the channel portion 130n of the active layer 130.

[0098] The first gate 151 may comprise at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The first gate 151 may have a multilayer structure comprising at least two conductive layers with different physical properties from each other.

[0099] An interlayer insulating layer 180 is disposed on the first gate 151. The interlayer insulating layer 180 is an insulating layer made of insulating material. The interlayer insulating layer 180 may be made of organic material, may be made of inorganic material, or may be made of a stack of organic and inorganic layers.

[0100] Drain 161 and source 162 are disposed on interlayer insulating layer 180.

[0101] The drain 161 is connected to the active layer 130 via the contact hole CH1. Specifically, the drain 161 can be electrically connected to the first connection portion 131 of the active layer 130 via the contact hole CH1.

[0102] The source electrode 162 is separated from the drain electrode 161 and connected to the active layer 130 via a contact hole CH2. Specifically, the source electrode 162 can be electrically connected to the second connection portion 132 of the active layer 130 via the contact hole CH2. The source electrode 162 is connected to the first conductive material layer 171 via another contact hole CH3. As a result, the first conductive material layer 171 can be connected to the second connection portion 132 of the active layer 130.

[0103] Each of the drain 161 and the source 162 may contain at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. Each of the drain 161 and the source 162 may be composed of a single layer made of metal or metal alloy, or may be formed as a multilayer of two or more layers.

[0104] Reference Figure 1A and 1B The first connection portion 131 and the drain 161 are shown as distinct from each other, but one embodiment of the invention is not limited thereto. The first connection portion 131 may be the drain, and the electrode indicated by the reference numeral "161" may be a connecting electrode or a bridge.

[0105] Reference Figure 1A and 1B The second connection portion 132 and the source electrode 162 are shown as distinct from each other, but one embodiment of the invention is not limited thereto. The second connection portion 132 may be the source electrode, and the electrode indicated by the reference numeral "162" may be a connecting electrode or a bridge.

[0106] According to one embodiment of the present invention, a first conductive material layer 171 having conductivity is disposed between the substrate 110 and the active layer 130. Specifically, the first conductive material layer 171 may be designed to overlap with a portion of the channel portion 130n, but not with other portions of the channel portion 130n.

[0107] According to one embodiment of the present invention, the region of the channel portion 130n that does not overlap with the first conductive material layer 171 may be referred to as the first region, and the region of the channel portion 130n that overlaps with the first conductive material layer 171 may be referred to as the second region. Therefore, the first conductive material layer 171 may not overlap with the first region of the channel portion 130n, but may overlap with the second region of the channel portion 130n.

[0108] According to one embodiment of the present invention, a first region of the channel portion 130n contacts the first connection portion 131, and a second region of the channel portion 130n contacts the second connection portion 132. Furthermore, a first conductive material layer 171 is connected to the source electrode 162. As a result, the same voltage can be applied to the first conductive material layer 171, the second connection portion 132, and the source electrode 162.

[0109] The voltage applied to the first conductive material layer 171 affects a portion of the channel portion 130n. The voltage applied to the first conductive material layer 171 can affect a second region that is a region of the channel portion 130n overlapping with the first conductive material layer 171.

[0110] For example, the electric field effect applied to the channel portion 130n through the first gate 151 can be reduced due to the electrical influence of the first conductive material layer 171. Specifically, the electric field is applied to the channel portion 130n through the first gate 151, and the electric field effect applied to the second region of the channel portion 130n can be reduced due to the electrical influence of the first conductive material layer 171.

[0111] Therefore, according to one embodiment of the present invention, the effective gate voltage Veff applied to the first region of the channel portion 130n in contact with the first connection portion 131 can be greater than the effective gate voltage applied to the second region of the channel portion 130n in contact with the second connection portion 132. According to one embodiment of the present invention, the effective gate voltage Veff applied to the second region of the channel portion 130n can be less than the effective gate voltage Veff applied to the first region of the channel portion 130n.

[0112] As a result, the S-factor of the thin-film transistor 100 can be increased.

[0113] The S factor will be described in detail below.

[0114] In the drain-source current curve corresponding to the gate voltage of the thin-film transistor 100, the S-factor (sub-shreshold swing) is obtained by taking the inverse slope (reciprocal) of the slope of the curve with respect to the threshold voltage Vth. For example, for the threshold voltage Vth of the thin-film transistor 100, the S-factor can be used as an index representing the rate of change of the drain-source current corresponding to the gate voltage.

[0115] As the S-factor increases, the rate of change of the drain-source current Ids corresponding to the gate voltage decreases.

[0116] The S-factor can be obtained, for example, through... Figure 7 The current change curve shown is used to describe this. Figure 7 This is a threshold voltage curve of a thin-film transistor. Specifically, Figure 7This example illustrates the drain-source current Ids corresponding to the gate voltage Vgs. For Figure 7 The slope of the curve representing the drain-source current Ids corresponding to the threshold voltage Vth and gate voltage Vgs, as shown in the graph, is the inverted slope (reciprocal) of the curve, which is the S-factor. A steeper slope results in a smaller S-factor; a gentler slope results in a larger S-factor. A larger S-factor indicates a lower rate of change in the drain-source current Ids corresponding to the gate voltage.

[0117] When the S factor increases, the rate of change of the drain-source current Ids corresponding to the gate voltage decreases, so it is easy to adjust the amplitude of the drain-source current Ids by adjusting the gate voltage Vgs.

[0118] In current-driven display devices, such as organic light-emitting diode (OLED) displays, the grayscale level of a pixel can be controlled by adjusting the amplitude of the drain-source current Ids of the driving thin-film transistor (TFT). The amplitude of the drain-source current Ids of the driving TFT is determined by the gate voltage. Therefore, in current-driven OLED displays, as the S-factor of the driving TFT increases, the grayscale level of the pixel becomes easier to adjust.

[0119] According to one embodiment of the present invention, since the first conductive material layer 171 overlaps with the second region of the channel portion 130n adjacent to the source 162, when a voltage identical to the voltage applied to the source 162 is applied to the first conductive material layer 171, the first conductive material layer 171 can electrically influence the second region of the channel portion 130n. Due to the electrical influence of the first conductive material layer 171, the electric field effect applied to the second region of the channel portion 130n by the first gate 151 can be reduced. As a result, the S-factor of the thin-film transistor 100 including the first conductive material layer 171 can be increased.

[0120] The influence of the first conductive material layer 171 on the S-factor of the thin-film transistor 100 can be achieved through... Figure 8A , 8B It is described using 9A and 9B.

[0121] Figure 8A and 8B The diagram has a similar Figure 1B A schematic diagram of the effective gate voltage Veff of a thin-film transistor (Comparative Example 1) that has a structure but does not have a first conductive material layer 171.

[0122] Figure 8A The diagram schematically illustrates the capacitance Cap that can be generated when a gate voltage VGS is applied to a thin-film transistor. The gate voltage VGS is the voltage between the source 162 and the first gate 151. According to one embodiment of the invention, the gate voltage VGS may be referred to as the voltage between the second connection 132 and the first gate 151.

[0123] Figure 8A The diagram illustrates the relationship between the threshold voltage Vth and the capacitance Cap near the threshold voltage Vth before the thin-film transistor is fully turned on.

[0124] like Figure 8A As shown, when the gate voltage VGS is applied to a thin-film transistor (Comparative Example 1) that does not have a first conductive material layer 171, a capacitor CGI is formed between the channel portion 130n (CH) of the active layer 130 and the first gate 151 (gate), and a capacitor CCH is also formed between the channel portion 130n and the second connection portion 132 (source).

[0125] The capacitor CCH formed between the channel portion 130n and the second connection portion 132 (source) can be referred to as the capacitor formed between the source 162, which is a high-voltage terminal, and the drain 161, which is a low-voltage terminal, in the channel portion 130n of the oxide semiconductor layer having N-type semiconductor characteristics.

[0126] Figure 8A The relationship between the voltage and capacitance Cap shown can be displayed as follows: Figure 8B As shown. (Refer to...) Figure 8B Due to the capacitance CCH between the channel portion 130n and the second connection portion 132 (source), not all of the gate voltage VGS is effectively applied to the channel portion 130n. As a result, voltage loss may occur.

[0127] Reference Figure 8B When a portion of the gate voltage VGS effectively applied to the channel portion 130n during the driving of the thin-film transistor is called the effective gate voltage Veff, the effective gate voltage Veff can be obtained by Equation 1 below.

[0128] [Equation 1]

[0129] Veff = [CGI / (CGI+CCH)] x VGS

[0130] Figure 9A and 9B This is a schematic diagram illustrating the effective gate voltage Veff of a thin-film transistor 100 according to an embodiment of the present invention.

[0131] Figure 9A and 9B The diagram illustrates the capacitance Cap that can be generated when a gate voltage VGS is applied to a thin-film transistor according to an embodiment of the present invention. Figure 9A The diagram illustrates the relationship between the threshold voltage Vth and the capacitance Cap near the threshold voltage Vth before the thin-film transistor is fully turned on.

[0132] like Figure 9A As shown, when the gate voltage VGS is applied to the thin film transistor, a capacitor CGI can be formed between the channel portion 130n of the active layer 130 and the first gate 151, a capacitor CCH can be formed between the channel portion 130n and the second connection portion 132 (source), and a capacitor CBUF can be additionally formed between the channel portion 130n and the first conductive material layer 171.

[0133] Figure 9A The relationship between the voltage and capacitance Cap shown can be displayed as follows: Figure 9B As shown. (Refer to...) Figure 9B Due to the capacitance CCH between the channel portion 130n and the second connection portion 132 (source) and the capacitance CBUF between the channel portion 130n and the first conductive material layer 171, not all of the gate voltage VGS is effectively applied to the channel portion 130n. As a result, voltage loss may occur.

[0134] According to one embodiment of the present invention, the first conductive material layer 171 is electrically connected to the source electrode 162 and the second connection portion 132. As a result, an additional capacitance CBUF is generated between the channel portion 130n and the first conductive material layer 171, thereby increasing the capacitance Cap of voltage loss (CCH+CBUF).

[0135] Therefore, refer to Figure 9B When one of the gate voltages VGS effectively applied to the channel portion 130n is called the effective gate voltage Veff, the effective gate voltage Veff can be obtained by the following equation 2.

[0136] [Equation 2]

[0137] Veff=[CGI / (CGI+CCH+CBUF)]x VGS

[0138] Referring to Equation 2, the denominator of Equation 2 increases due to the capacitance CBUF between the channel portion 130n and the first conductive material layer 171. Therefore, the decrease in the effective gate voltage Veff is relatively greater than that in Equation 1. Consequently, when a gate voltage VGS is applied, in the thin-film transistor 100 according to an embodiment of the present invention, the rate of increase (change rate) of the drain-source current Ids corresponding to the gate voltage VGS decreases, resulting in an increase in the S-factor.

[0139] According to one embodiment of the present invention, the first conductive material layer 171 overlaps with a second region of the channel portion 130n. As a result, in the second region of the channel portion 130n in which the source 162 and the second connection portion 132 are connected to each other, the effective gate voltage Veff can be significantly reduced.

[0140] Therefore, according to one embodiment of the present invention, the increase in current near the source 162 is delayed before the thin-film transistor 100 is fully turned on, thereby significantly slowing down the rate of increase (change rate) of the drain-source current Ids, thus achieving an increase in the S-factor. As described above, the first conductive material layer 171 can be used to increase the S-factor of the thin-film transistor 100 according to one embodiment of the present invention.

[0141] On the other hand, the first region in which the drain 161 and the first connection portion 131 of the channel portion 130n are connected to each other may not overlap with the first conductive material layer 171. Therefore, the reduction in effective gate Veff is not significant in the first region of the channel portion 130n. As a result, when the thin-film transistor 100 according to an embodiment of the present invention is in the on state, charge moves sufficiently and effectively through the drain 161 and the first region, so that the on current of the thin-film transistor 100 does not decrease.

[0142] In related technologies, increasing the distance between the gate and the channel is used to increase the S-factor of a thin-film transistor (TFT). While this increases the S-factor, it also leads to a decrease in the TFT's on-state current.

[0143] On the other hand, according to one embodiment of the present invention, the first conductive material layer 171 is configured to overlap with the second region where the source 162 and the second connection portion 132 of the channel portion 130n are connected, thereby increasing the S factor of the thin film transistor 100 and not decreasing the conduction current of the thin film transistor 100, thereby enabling the thin film transistor 100 to have excellent conduction current characteristics.

[0144] Since the thin-film transistor 100 according to one embodiment of the present invention has a large S-factor, the thin-film transistor 100 can be used as a driving transistor for a display device.

[0145] Figure 1C This is a cross-sectional view illustrating a thin-film transistor according to another embodiment of the present invention. To avoid repetition, descriptions of already described elements will be omitted.

[0146] Reference Figure 1C The gate insulating layer (GI) 140 is patterned. Figure 1C In the thin-film transistor shown, the gate insulating layer 140 can be patterned by etching using the first gate 151 as a mask.

[0147] Figure 1D and 1E This is a cross-sectional view illustrating a thin-film transistor according to another embodiment of the present invention.

[0148] Figure 1D Compared to thin-film transistors Figure 1BThe thin-film transistor 100 has a multilayer structure.

[0149] Reference Figure 1D The active layer 130 includes a first oxide semiconductor layer 130a on the substrate 110 and a second oxide semiconductor layer 130b on the first oxide semiconductor layer 130a. The first oxide semiconductor layer 130a and the second oxide semiconductor layer 130b may contain the same semiconductor material or may contain different semiconductor materials.

[0150] The first oxide semiconductor layer 130a supports the second oxide semiconductor layer 130b. Therefore, the first oxide semiconductor layer 130a is referred to as a "support layer". A channel portion 130n may be formed in the second oxide semiconductor layer 130b. Therefore, the second oxide semiconductor layer 130b is referred to as a "channel layer", but one embodiment of the present invention is not limited thereto, and the channel portion 130n may be formed in the first oxide semiconductor layer 130a.

[0151] The structure of the active layer 130, which includes a first oxide semiconductor layer 130a and a second oxide semiconductor layer 130b, is called a bi-layer structure.

[0152] exist Figure 1E In thin-film transistors, compared to Figure 1D The thin-film transistor has an active layer that further includes a third oxide semiconductor layer located on the second oxide semiconductor layer 130b.

[0153] Reference Figure 1E The active layer 130 includes a first oxide semiconductor layer 130a, a second oxide semiconductor layer 130b, and a third oxide semiconductor layer 130c. However, another embodiment of the invention is not limited to this, and the active layer 130 may further include other semiconductor layers. Using the three oxide semiconductor layers, the intermediate layer 130b can be protected during manufacturing to avoid damage in both directions. For example, the bottom oxide semiconductor layer protects the intermediate semiconductor layer during manufacturing, and the top oxide semiconductor layer protects the intermediate semiconductor layer from etchants or gases during manufacturing.

[0154] Figure 2 This is a cross-sectional view illustrating a thin-film transistor 200 according to another embodiment of the present invention.

[0155] compared to Figure 1B Thin-film transistor 100, Figure 2 The thin-film transistor 200 further includes a second gate 152 disposed between the first gate 151 and the active layer 130. (See reference...) Figure 2The first gate insulating layer 141 may be disposed on the active layer 130, the second gate 152 may be disposed on the first gate insulating layer 141, the second gate insulating layer 142 may be disposed on the second gate 152, and the first gate 151 may be disposed on the second gate insulating layer 142. Figure 2 The thin-film transistor 200 includes a first conductive material layer 171.

[0156] According to one embodiment of the present invention, the second gate 152 overlaps with a first region of the channel portion 130n. Alternatively, the second gate 152 may be designed not to overlap with a second region of the channel portion 130n. In this case, the second gate 152 may not overlap with the first conductive material layer 171.

[0157] Reference Figure 2 At least a portion of the second gate 152 overlaps with the first gate 151, and at least a portion of the second gate 152 may not overlap with the first gate 151. According to one embodiment of the present invention, only a portion of the second gate 152 may overlap with the first gate 151.

[0158] According to one embodiment of the present invention, the same voltage can be applied to the first gate 151 and the second gate 152. (Refer to...) Figure 2 The first gate 151 and the second gate 152 can be electrically connected to each other through the gate connection electrode 163 and the contact holes CH4 and CH5.

[0159] The second gate 152, together with the first gate 151, can be used as a gate to apply an electric field to the channel portion 130n of the active layer 130.

[0160] According to one embodiment of the present invention, the second gate 152 overlaps with a first region of the channel portion 130n in which the drain 161 and the first connection portion 131 are connected. Since the second gate 152 is positioned closer to the channel portion 130n than the first gate 152, an electric field can be applied more effectively to the first region of the channel portion 130n compared to the first gate 151. As a result, the on-state current of the thin-film transistor 200 can be improved through the second gate 152.

[0161] On the other hand, the second gate 152 can be designed not to overlap with the second region of the channel portion 130n. Therefore, the second gate 152 will not affect the electric field effect applied to the second region of the channel portion 130n. Alternatively, even if the second gate 152 overlaps with the second region of the channel portion 130n, the overlap area can be minimized to minimize the electric field effect generated by the second gate 152 on the second region of the channel portion 130n. As a result, even if a gate voltage is applied to the second gate 152, the rate of increase of the drain-source current Ids will not be affected. Therefore, even if the second gate 152 is provided, the S-factor of the thin-film transistor 200 will not be reduced.

[0162] As described above, the second gate 152, which is disposed between the first gate 151 and the active layer 130 by overlapping with the first region of the channel portion 130n, can improve the conduction current of the thin film transistor 200 without reducing the S factor of the thin film transistor 200.

[0163] Figure 3 This is a cross-sectional view illustrating a thin-film transistor 300 according to another embodiment of the present invention.

[0164] compared to Figure 1B Thin-film transistor 100, Figure 3 The thin-film transistor 300 further includes a second gate 152 disposed between the first gate 151 and the active layer 130. Furthermore, Figure 3 Compared to the thin-film transistor 300 Figure 1B The thin-film transistor 100 may not include the first conductive material layer 171.

[0165] Reference Figure 3 The light-shielding layer 111 can be connected to the source 162 via the contact hole CH, but one embodiment of the present invention is not limited thereto. The light-shielding layer 111 can be electrically connected to the drain 161 or the first gate 151.

[0166] Reference Figure 3 The first gate insulating layer 141 may be disposed on the active layer 130, the second gate 152 may be disposed on the first gate insulating layer 141, the second gate insulating layer 142 may be disposed on the second gate 152, and the first gate 151 may be disposed on the second gate insulating layer 142.

[0167] According to one embodiment of the present invention, the second gate 152 overlaps with the first region of the channel portion 130n. Figure 3 In the thin-film transistor 300, the region of the channel portion 130n that overlaps with the second gate 152 can be referred to as the first region, and the region of the channel portion 130n that does not overlap with the second gate 152 can be referred to as the second region.

[0168] Specifically, the region of the channel portion 130n that overlaps with the first gate 151 but does not overlap with the second gate 152 may be referred to as the second region.

[0169] Reference Figure 3 At least a portion of the second gate 152 may overlap with the first gate 151, and at least a portion of the second gate 152 may not overlap with the first gate 151. According to one embodiment of the present invention, only a portion of the second gate 152 may overlap with the first gate 151.

[0170] According to one embodiment of the present invention, the same voltage can be applied to the first gate 151 and the second gate 152. (Refer to...) Figure 3 The first gate 151 and the second gate 152 can be electrically connected to each other through the gate connection electrode 163 and the contact holes CH4 and CH5.

[0171] The second gate 152, together with the first gate 151, can be used as a gate to apply an electric field to the channel portion 130n of the active layer 130.

[0172] Since the second gate 152 is positioned closer to the channel portion 130n than the first gate 152, the electric field can be applied more effectively to the first region of the channel portion 130n compared to the first gate 151. Because the first region, to which a high voltage is applied, has a larger electric field effect through the second gate 152, the on-state current of the thin-film transistor 200 can be improved.

[0173] The second region of the channel 130n overlaps with the first gate 151 without overlapping with the second gate 152. The second region of the channel 130n experiences the electric field effect applied by the first gate 151. However, the first gate 151 is farther from the second gate 152 in the channel 130n. Therefore, the electric field effect applied to the second region of the channel 130n is less than the electric field effect applied to the first region of the channel 130n. As a result, when a gate voltage is applied to the first gate 151 and the second gate 152, the rate of increase (change rate) of the drain-source current Ids is very small due to the smaller electric field effect applied to the second region, and therefore the slope of the threshold voltage curve is smaller. Therefore, Figure 3 The thin-film transistor 300 shown can have a large S-factor.

[0174] As described above, it includes a second gate 152 disposed between the first gate 151 and the active layer 130 by overlapping with the first region of the channel portion 130n. Figure 3 The thin-film transistor 300 can have a relatively large S-factor and excellent on-current characteristics.

[0175] Figure 4AThis is a plan view illustrating a thin-film transistor 100 according to another embodiment of the present invention. Figure 4B This is a cross-sectional view illustrating a thin-film transistor 400 according to another embodiment of the present invention. Specifically, Figure 4B It is along Figure 4A The sectional view taken by line B-B'.

[0176] Reference Figure 4A and 4B The thin-film transistor 400 may include a second conductive material layer 172 located between the substrate 110 and the active layer 130. The second conductive material layer 172 may overlap with a first region of the channel portion 130n, but may not overlap with a second region of the channel portion 130n. Figure 1B Compared to the thin-film transistor 100, Figure 4B The thin-film transistor 400 does not include a first conductive material layer 171, but includes a second conductive material layer 172.

[0177] According to another embodiment of the present invention, the region of the channel portion 130n that overlaps with the second conductive material layer 172 may be referred to as the first region, and the region of the channel portion 130n that does not overlap with the second conductive material layer 172 may be referred to as the second region.

[0178] According to another embodiment of the present invention, the second conductive material layer 172 may be configured to have the same voltage as the first gate 151. (Refer to...) Figure 4B The second conductive material layer 172 can be connected to the first gate 151. Specifically, the second conductive material layer 172 can be connected to the first gate 151 through the connection electrode 164 located on the interlayer insulating layer 180 and the contact holes CH6 and CH7.

[0179] The same voltage applied to the first gate 150 can be applied to the second conductive material layer 172. Figure 4B The thin-film transistor 400 may have a dual-gate structure. Due to the dual-gate structure, the applied... Figure 4B The electric field effect in the first region of the channel section 130n can be increased.

[0180] The effective gate voltage Veff applied by the second conductive material layer 172 can... Figure 10A and 10B As described in the text.

[0181] Figure 10A A schematic diagram illustrating the effect of applying a gate voltage VGS to... Figure 4B The capacitance Cap that can be generated by a thin-film transistor 400. Figure 10A The diagram schematically illustrates the relationship between the threshold voltage Vth and the capacitance Cap near the threshold voltage Vth before the thin-film transistor 400 is fully turned on.

[0182] like Figure 10A As shown, when the gate voltage VGS is applied to the thin-film transistor 400, a capacitor CGI is formed between the channel portion 130n and the first gate 151, and a capacitor CCH is formed between the channel portion 130n and the second connection portion 132.

[0183] In addition, refer to Figure 10A The capacitor CBUF can be formed between the channel portion 130n and the second conductive material layer 172 (gate 2). The capacitor CBUF between the channel portion 130n and the second conductive material layer 172 can refer to the capacitor formed between the first region of the channel portion 130n and the second conductive material layer 172.

[0184] Figure 10A The relationship between the voltage and capacitance Cap shown can be displayed as follows: Figure 10B As shown.

[0185] According to one embodiment of the present invention, since the second conductive material layer 172 and the first gate 151 are electrically connected to each other, an effect such as applying a gate voltage to a first region of the channel portion 130n is generated through the second conductive material layer 172. As a result, an effect of increasing the effective gate voltage Veff corresponding to the capacitance CBUF between the channel portion 130n and the second conductive material layer 172 is generated.

[0186] Reference Figure 10B When driving the thin-film transistor 400, the effective gate voltage Veff applied to the first region of the channel portion 130n can be obtained by Equation 3 below.

[0187] [Equation 3]

[0188] Veff=[CGI+CBUF) / (CGI+CCH+CBUF)]x VGS

[0189] Referring to Equation 3, the numerator of Equation 3 is larger than that of Equation 2 due to the capacitance CBUF between the channel portion 130n and the second conductive material layer 172. In this way, the on-state current of the thin-film transistor 400 can be improved due to the increased effective gate voltage Veff applied to the first region of the channel portion 130n.

[0190] Therefore, even if the spacing between the channel portion 130n of the active layer 130 and the first gate 151 is significantly increased in order to increase the S-factor of the thin film transistor 400, the on-current of the thin film transistor 400 will not decrease.

[0191] Reference Figure 4BAs the spacing between the channel portion 130n and the first gate 151 in the active layer 130 is significantly increased, the S-factor of the thin-film transistor 400 can be increased. Furthermore, a second conductive material layer 172 can be provided that overlaps with the first region of the channel portion 130n and is connected to the first gate 151, so that the on-state current of the thin-film transistor 400 does not decrease.

[0192] As mentioned above, Figure 4B The thin-film transistor 400 may include a second conductive material layer 172 that overlaps with the first region of the channel portion 130n and is connected to the first gate 151, thereby the thin-film transistor 400 may have a relatively large S-factor and excellent on-current characteristics.

[0193] Figure 5 This is a cross-sectional view illustrating a thin-film transistor 500 according to another embodiment of the present invention.

[0194] Reference Figure 5 According to another embodiment of the present invention, the thin-film transistor 500 includes a first gate 151 having a stepped profile.

[0195] Reference Figure 5 The gate insulating layer 140 between the first gate 151 and the active layer 130 has a stepped cross-section. Specifically, the gate insulating layer 140 may include a first gate insulating layer 141 and a second gate insulating layer 142. The first gate insulating layer 141 may cover the entire area of ​​the channel portion 130n. The second gate insulating layer 142 may cover only a portion of the channel portion 130n. More specifically, the second gate insulating layer may cover only the area adjacent to the second connection portion 132 of the channel portion 130n.

[0196] Reference Figure 5 The region of the channel portion 130n that does not overlap with the second gate insulating layer 142 may be referred to as the first region, and the region of the channel portion 130n that overlaps with the second gate insulating layer 142 may be referred to as the second region.

[0197] Therefore, in Figure 5 In the thin-film transistor 500 shown, the thickness of the gate insulating layer 140 disposed on the first region of the channel portion 130n is less than the thickness of the gate insulating layer 140 disposed on the second region of the channel portion 130n. Furthermore, the distance between the first gate 151 and the first region of the channel portion 130n is less than the distance between the first gate 151 and the second region of the channel portion 130n.

[0198] Figure 5 The thin-film transistor 500 shown may have the same characteristics as... Figure 3 The effect is similar to that of the thin-film transistor 300, which includes a second gate 152.

[0199] Specifically, since the first region of the channel portion 130n is positioned close to the first gate 151, the electric field effect applied to the first region is relatively large. As described above, since the first region, to which a high voltage is applied, experiences a large electric field effect, the on-state current of the thin-film transistor 500 can be improved.

[0200] Because the second region of the channel 130n is relatively far from the first gate 151, the electric field effect applied to the second region of the channel 130n is relatively small. As a result, when a gate voltage is applied to the first gate 151, the electric field effect applied to the second region is small, and the rate of increase (change rate) of the drain-source current Ids is very small, thus resulting in a smaller slope of the threshold voltage curve. Therefore, Figure 5 The thin-film transistor 500 shown can have a large S-factor.

[0201] In this way, Figure 5 The thin-film transistor 500 has a relatively large S-factor and excellent on-current characteristics.

[0202] Figure 6A This is a plan view illustrating a thin-film transistor 600 according to yet another embodiment of the present invention. Figure 6B This is a cross-sectional view of a thin-film transistor 600 according to another embodiment of the present invention. Figure 6B It is along Figure 6A A sectional view taken by line C-C'.

[0203] Figure 6A and 6B The thin-film transistor 600 includes a third conductive material layer 173 disposed between a substrate 110 and an active layer 130. A buffer layer 120 (BUF) is disposed between the third conductive material layer 173 and the active layer 130. The buffer layer 120 has a step profile.

[0204] Specifically, a third conductive material layer 173 is disposed on the substrate 110, and a buffer layer 120 is disposed on the third conductive material layer 173. The buffer layer 120 may include, for example, a first buffer layer 121 and a second buffer layer 122.

[0205] The first buffer layer 121 may be configured to completely overlap with the channel portion 130n. The second buffer layer 122 may be configured to overlap with a portion of the channel portion 130n. More specifically, the second buffer layer 122 overlaps with the region of the channel portion 130n adjacent to the second connecting portion 132, and may not overlap with the region of the channel portion 130n adjacent to the first connecting portion 131.

[0206] Reference Figure 6BThe area of ​​the channel portion 130n that does not overlap with the second buffer layer 122 can be referred to as the first region, and the area of ​​the channel portion 130n that overlaps with the second buffer layer 122 can be referred to as the second region.

[0207] Therefore, in Figure 6B In the thin-film transistor 600 shown, the thickness of the buffer layer 120 overlapping with the first region of the channel portion 130n is less than the thickness of the buffer layer 120 overlapping with the second region of the channel portion 130n.

[0208] The active layer 130 is disposed on the buffer layer 120. For example... Figure 6B As shown, since the buffer layer 120 has a stepped profile, the active layer 130 can also have a stepped profile. More specifically, the channel portion of the active layer 130 can have a stepped profile.

[0209] Because the buffer layer 120 has a stepped profile, the distance between the first region of the third conductive material layer 173 and the channel portion 130n can be smaller than the distance between the second region of the third conductive material layer 173 and the channel portion 130n.

[0210] Reference Figure 6B Due to the stepped profile of the buffer layer 120, the channel portion 130n of the active layer 130 and the first gate 151 can both have stepped profiles.

[0211] Reference Figure 6B The third conductive material layer 173 can be connected to the first gate 151. Specifically, the third conductive material layer 173 can be connected to the first gate 151 through the connection electrode 165 and contact holes CH6 and CH9 on the interlayer insulating layer 180.

[0212] According to another embodiment of the present invention, the third conductive material layer 173 may be configured to have the same voltage as the first gate 151. The same gate voltage as applied to the first gate 151 may be applied to the third conductive material layer 173. Figure 6B The thin-film transistor 600 may have a dual-gate structure.

[0213] There is no significant difference in the distance between the corresponding regions of the first gate 151 and the channel portion 130n. On the other hand, there is a difference in the distance between the corresponding regions of the third conductive material layer 173 and the channel portion 130n.

[0214] Because the first region of the channel portion 130n is positioned close to the third conductive material layer 173, the electric field effect applied to the first region is relatively large. As described above, since the first region subjected to a high voltage experiences a large electric field effect, the conduction current of the thin-film transistor 600 can be improved.

[0215] Because the second region of the channel portion 130n is relatively far from the third conductive material layer 173, the electric field effect applied to the second region of the channel portion 130n is relatively small. As a result, when a gate voltage is applied to the third conductive material layer 173, the electric field effect applied to the second region is small, and the rate of increase (change rate) of the drain-source current Ids is very small, thus resulting in a smaller slope of the threshold voltage curve. Therefore, Figure 6B The thin-film transistor 600 shown can have a large S-factor.

[0216] As mentioned above, Figure 6B The thin-film transistor 600 has a relatively large S-factor and excellent on-current characteristics.

[0217] Figure 7 This is a threshold voltage curve of a thin-film transistor (TFT). The threshold voltage curve of a TFT is represented by a curve of the drain-source current Ids corresponding to the gate voltage VGS.

[0218] exist Figure 7 In the above, implementation method 1 is Figure 1B The threshold voltage curve of the thin-film transistor 100. Figure 7 In this example, Comparative Example 1 is based on the threshold voltage curve of the thin-film transistor of Comparative Example 1. (Compared to...) Figure 1B Compared to the thin-film transistor 100, the thin-film transistor according to Comparative Example 1 has a larger thickness of the gate insulating layer 140 to increase the S-factor of the thin-film transistor that does not have the first conductive material layer 171, thereby increasing the spacing between the channel portion 130n and the first gate 151.

[0219] Reference Figure 7 Please note that there is no difference in the S-factor between Embodiment 1 and Comparative Example 1 during the period before the thin-film transistor is fully turned on. On the other hand, please note that the on-current of Comparative Example 1 is less than that of Embodiment 1.

[0220] As described above, according to one embodiment of the present invention, a thin-film transistor with a large S-factor and excellent on-current characteristics can be manufactured.

[0221] The following will describe in detail display devices including the thin-film transistors 100, 200, 300, 400, 500 and 600 described above. Display devices may include LED, OLED, LCD, PDP, micro-LED or mini-LED display devices.

[0222] Figure 11 This is a schematic diagram illustrating a display device 700 according to another embodiment of the present invention.

[0223] like Figure 11As shown, a display device 700 according to another embodiment of the present invention includes a display panel 310, a gate driver 320, a data driver 330, and a controller 340.

[0224] Gate lines GL and data lines DL are disposed in the display panel 310, and multiple pixels P are disposed in the intersection area of ​​gate lines GL and data lines DL. Images are displayed by driving the pixels P.

[0225] The controller 340 controls the gate driver 320 and the data driver 330.

[0226] The controller 340 outputs a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330 using signals provided from an external system (not shown). Furthermore, the controller 340 samples input image data from the external system, rearranges the sampled data, and provides the rearranged digital image data (RGB) to the data driver 330.

[0227] The gate control signal GCS includes the gate start pulse GSP, the gate shift clock GSC, the gate output enable signal GOE, the start signal Vst, and the gate clock GCLK. Additionally, control signals for controlling the shift register may be included in the gate control signal GCS.

[0228] The data control signal DCS includes the source start pulse SSP, the source shift clock signal SSC, the source output enable signal SOE, and the polarity control signal POL.

[0229] The data driver 330 provides data voltage to the data line DL of the display panel 310. Specifically, the data driver 330 converts the image data RGB input from the controller 340 into analog data voltage and provides the data voltage to the data line DL.

[0230] Gate driver 320 may include shift register 350.

[0231] The shift register 350 sequentially provides gate pulses to the gate line GL within a frame using a start signal and a gate clock transmitted from the controller 340. In this case, a frame refers to the time period during which an image is output through the display panel 310. The gate pulses have an on-state voltage capable of turning on the switching elements (thin-film transistors) disposed in the pixel P.

[0232] In addition, shift register 350 provides a gate cutoff signal to gate line GL during other periods of a frame when no gate pulse is provided, which enables the switching element to turn off. Hereinafter, the gate pulse and gate cutoff signal will be collectively referred to as the scan signal SS or Scan.

[0233] According to one embodiment of the present invention, the gate driver 320 may be packaged on the substrate 110. In this way, the structure in which the gate driver 320 is directly packaged on the substrate 110 is referred to as a gate-in-panel (GIP) structure.

[0234] Figure 12 It is a diagram Figure 11 The circuit diagram of any pixel P. Figure 13 It is a diagram Figure 12 A planar image of pixel P. Figure 14 It is along Figure 13 A sectional view taken from line I-I'.

[0235] Figure 12 The circuit diagram is an equivalent circuit diagram of the pixel P of the display device 700, which includes an organic light-emitting diode (OLED) as a display element 710.

[0236] Pixel P includes a display element 710 and a pixel driving circuit PDC for driving the display element 710.

[0237] Figure 12 The pixel driving circuit PDC includes a first thin-film transistor TR1 as a switching transistor and a second thin-film transistor TR2 as a driving transistor. For example, the thin-film transistors 100, 200, 300, 400, 500 and 600 described in the embodiments can be used as the second thin-film transistor TR2.

[0238] The first thin-film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off by the scan signal SS provided via the gate line GL.

[0239] The data line DL provides the data voltage Vdata to the pixel driving circuit PDC, and the first thin-film transistor TR1 controls the application of the data voltage Vdata.

[0240] The driving power line PL provides a driving voltage Vdd to the display element 710, and the second thin-film transistor TR2 controls the driving voltage Vdd. The driving voltage Vdd is the pixel driving voltage used to drive the organic light-emitting diode (OLED) that serves as the display element 710.

[0241] When the first thin-film transistor TR1 is turned on by the scan signal SS applied from the gate driver 320 via the gate line GL, the data voltage Vdata provided via the data line DL is supplied to the gate G2 of the second thin-film transistor TR2, which is connected to the display element 710. The data voltage Vdata is charged into the first capacitor C1 formed between the gate G2 and the source S2 of the second thin-film transistor TR2. The first capacitor C1 is a storage capacitor Cst.

[0242] The amount of current supplied to the organic light-emitting diode (OLED) of the display element 710 via the second thin-film transistor TR2 is controlled according to the data voltage Vdata, thereby controlling the gray level of the light emitted from the display element 710.

[0243] Reference Figure 13 and 14 The first thin-film transistor TR1 and the second thin-film transistor TR2 are disposed on the substrate 110.

[0244] The substrate 110 may be made of glass or plastic. Plastics with flexible properties, such as polyimide (PI), may be used as the substrate 110.

[0245] A lower buffer layer 220 is disposed on the substrate 110, and a light-shielding layer 111 is disposed on the lower buffer layer 220. The light-shielding layer 111 may include a material with light-shielding properties. The light-shielding layer 111 can block light incident from the outside to protect the active layers A1 and A2.

[0246] The first buffer layer 121 is disposed on the light-shielding layer 111. The first buffer layer 121 is made of insulating material and protects the active layers A1 and A2 from external moisture or oxygen.

[0247] The first conductive material layer 171 is disposed on the first buffer layer 121.

[0248] According to one embodiment of the present invention, the first conductive material layer 171 may be conductive. Since the structure and function of the first conductive material layer 171 have already been described, a detailed description of the first conductive material layer 171 will be omitted to avoid repetition.

[0249] A second buffer layer 122 is disposed on the first conductive material layer 171. The second buffer layer 122 may include at least one of an insulating material selected from silicon oxide, silicon nitride, and metal-based oxides.

[0250] The first active layer A1 of the first thin-film transistor TR1 and the second active layer A2 of the second thin-film transistor TR2 are disposed on the second buffer layer 122.

[0251] Each of the first active layer A1 and the second active layer A2 may, for example, comprise an oxide semiconductor material. Each of the first active layer A1 and the second active layer A2 may be constituted by an oxide semiconductor layer made of an oxide semiconductor material.

[0252] In the first thin-film transistor TR1, the first active layer A1 may include a channel portion, a first connection portion, and a second connection portion. The channel portion of the first active layer A1 overlaps with the gate G1. According to another embodiment of the present invention, the first connection portion may be referred to as the first source S1, and the second connection portion may be referred to as the first drain D1.

[0253] In the second thin-film transistor TR2, the second active layer A2 may include a channel portion, a first connection portion, and a second connection portion. The channel portion of the second active layer A2 overlaps with the gate G2. According to another embodiment of the present invention, the first connection portion may be referred to as the second drain D2, and the second connection portion may be referred to as the second source S2.

[0254] A portion of the channel portion of the second active layer A2 overlaps with the first conductive material layer 171.

[0255] The region of the channel portion of the second active layer A2 that does not overlap with the first conductive material layer 171 can be referred to as the first region, and the region of the channel portion of the second active layer A2 that overlaps with the first conductive material layer 171 can be referred to as the second region. Therefore, the first conductive material layer 171 may not overlap with the first region of the channel portion of the second active layer A2, but may overlap with the second region of the channel portion of the second active layer A2.

[0256] Reference Figure 13 and 14 A portion of the first active layer A1 can be made conductive to become the first capacitor electrode C11 of the first capacitor C1.

[0257] A gate insulating layer 140 is disposed on the first active layer A1 and the second active layer A2. The gate insulating layer 140 may cover the entire upper surface of the first active layer A1 and the second active layer A2, or it may cover only a portion of the first active layer A1 and the second active layer A2.

[0258] The gate G1 of the first thin-film transistor TR1 and the gate G2 of the second thin-film transistor TR2 are disposed on the gate insulating layer 140.

[0259] The gate G1 of the first thin-film transistor TR1 overlaps with at least a portion of the first active layer A1 of the first thin-film transistor TR1. The gate G2 of the second thin-film transistor TR2 overlaps with at least a portion of the second active layer A2 of the second thin-film transistor TR2.

[0260] An interlayer insulating layer 180 is disposed on gates G1 and G2.

[0261] The data cable DL and the drive power cable PL are mounted on the interlayer insulation layer 180.

[0262] The data line DL contacts the first source S1 formed in the first active layer A1 via the first contact hole H1. According to another embodiment of the present invention, the portion of the data line DL that overlaps with the first active layer A1 may be referred to as the first source S1.

[0263] The drive power line PL contacts the second drain electrode D2 formed in the second active layer A2 via the fifth contact hole H5. According to another embodiment of the present invention, the portion of the drive power line PL that overlaps with the second active layer A2 may be referred to as the second drain electrode D2.

[0264] Reference Figure 13 and 14 The second capacitor electrode C12 of the first capacitor C1, the first bridge BR1 and the second bridge BR2 are disposed on the interlayer insulating layer 180.

[0265] The second capacitor electrode C12 overlaps with the first capacitor electrode C11 to form the first capacitor C1.

[0266] The first bridge BR1 can be integrally formed with the second capacitor electrode C2. The first bridge BR1 is connected to the light-shielding layer 111 via the second contact hole H2, to the first conductive material layer 171 via the eleventh contact hole H11, and to the second source electrode S2 via the third contact hole H3. As a result, the first conductive material layer 171 can be connected to the second source electrode S2 of the second thin film transistor TR2.

[0267] The second bridge BR2 is connected to the gate G2 of the second thin-film transistor TR2 via the fourth contact hole H4, and is connected to the first capacitor electrode C11 of the first capacitor C1 via the seventh contact hole H7.

[0268] In addition, refer to Figure 13 The third bridge BR3 is disposed on the interlayer insulating layer 180. The third bridge BR3 is connected to the gate line GL via the eighth contact hole H8, thereby connecting to the gate G1, and is connected to the light-shielding layer 111 of the first thin-film transistor TR1 via the ninth contact hole H9. Although Figure 13 The diagram illustrates the connection of the light-shielding layer 111 to the gate G1. However, one embodiment of the present invention is not limited to this, and the light-shielding layer 111 may also be connected to the first source S1 or the first drain D1.

[0269] A planarization layer 175 is disposed on the data line DL, the drive power line PL, the second capacitor electrode C12, the first bridge BR1, the second bridge BR2, and the third bridge BR3. The planarization layer 175 planarizes the upper portions of the first thin-film transistor TR1 and the second thin-film transistor TR2, and protects the first thin-film transistor TR1 and the second thin-film transistor TR2.

[0270] The first electrode 711 of the display element 710 is disposed on the planarization layer 175. The first electrode 711 of the display element 710 contacts the second capacitor electrode C12 integrally formed with the first bridge BR1 via a sixth contact hole H6 formed in the planarization layer 175. As a result, the first electrode 711 can be connected to the second source S2 of the second thin film transistor TR2.

[0271] The embankment 750 is disposed at the edge of the first electrode 711. The embankment 750 defines the light-emitting area of ​​the display element 710.

[0272] An organic light-emitting layer 712 is disposed on the first electrode 711, and a second electrode 713 is disposed on the organic light-emitting layer 712. Thus, the display element 710 is completed. Figure 14 The display element 710 shown is an organic light-emitting diode (OLED). Therefore, the display device 700 according to one embodiment of the present invention is an organic light-emitting display device.

[0273] According to another embodiment of the present invention, the second thin-film transistor TR2 may have a large S-factor. The second thin-film transistor TR2 can be used as a driving transistor to improve the grayscale rendering capability of the display device 700.

[0274] Figure 15 This is a circuit diagram illustrating any pixel P of a display device 800 according to another embodiment of the present invention. Figure 16 It is along Figure 15 The sectional view taken from line II-II'.

[0275] and Figure 13 and 14 Compared to the display device 700 shown, Figure 15 and 16 The display device 800 shown does not include the first conductive material layer 171, and further includes a second gate 152 (G2-2).

[0276] Figure 15 and 16 The gate insulating layer 140 of the display device 800 shown includes a first gate insulating layer 141 and a second gate insulating layer 142.

[0277] In the second thin-film transistor TR2, the second gate 152 (G2-2) is disposed on the first gate insulating layer 141, the second gate insulating layer 142 is disposed on the second gate 152 (G2-2), and the gate G2 of the second thin-film transistor TR2 is disposed on the second gate insulating layer 142.

[0278] The second gate 152 (G2-2) can be connected to the gate G2 of the second thin film transistor TR2 via the second bridge BR2. Specifically, the second bridge BR2 is connected to the gate G2 of the second thin film transistor TR2 via the fourth contact hole H4, connected to the second gate 152 (G2-2) via the twelfth contact hole H12, and connected to the first capacitor electrode C11 of the first capacitor C1 via the seventh contact hole H7.

[0279] Figure 17This is a circuit diagram illustrating any pixel P of a display device 900 according to another embodiment of the present invention.

[0280] Figure 17 This is the equivalent circuit diagram of pixel P in an organic light-emitting display device.

[0281] Figure 17 The pixel P of the display device 900 shown includes an organic light-emitting diode (OLED) as a display element 710 and a pixel driving circuit PDC for driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0282] In pixel P, signal lines DL, GL, PL, RL, and SCL are set to provide signals to the pixel driving circuit PDC.

[0283] The data voltage Vdata is provided to the data line DL, the scan signal SS is provided to the gate line GL, the driving voltage Vdd for driving the pixel is provided to the driving power line PL, the reference voltage Vref is provided to the reference line RL, and the sensing control signal SCS is provided to the sensing control line SCL.

[0284] Reference Figure 17 Assume that the gate line of the nth pixel P is GLn, and the gate line of the (n-1)th pixel P adjacent to the nth pixel P is GLn-1. The gate line GLn-1 of the (n-1)th pixel P is used as the sensing control line SCL of the nth pixel P.

[0285] The pixel driving circuit PDC includes, for example, a first thin-film transistor TR1 (switching transistor) connected to the gate line GL and the data line DL; a second thin-film transistor TR2 (driving transistor) for controlling the amplitude of the current output to the display element 710 according to the data voltage Vdata transmitted via the first thin-film transistor TR1; and a third thin-film transistor TR3 (reference transistor) for sensing the characteristics of the second thin-film transistor TR2.

[0286] A first capacitor C1 is disposed between the gate G2 of the second thin-film transistor TR2 and the display element 710. The first capacitor C1 is referred to as the storage capacitor Cst.

[0287] The first thin-film transistor TR1 is turned on by a scan signal SS provided to the gate line GL to transmit the data voltage Vdata provided to the data line DL to the gate G2 of the second thin-film transistor TR2.

[0288] The third thin-film transistor TR3 is connected to the first node n1 and the reference line RL located between the second thin-film transistor TR2 and the display element 710, thereby being turned on or off by the sensing control signal SCS, and sensing the characteristics of the second thin-film transistor TR2 as a driving transistor during the sensing period.

[0289] A second node n2, connected to the gate G2 of the second thin-film transistor TR2, is connected to the first thin-film transistor TR1. A first capacitor C1 is formed between the second node n2 and the first node n1.

[0290] When the first thin-film transistor TR1 is turned on, the data voltage Vdata supplied via the data line DL is provided to the gate G2 of the second thin-film transistor TR2. The data voltage Vdata is charged into the first capacitor C1 formed between the gate G2 and the source S2 of the second thin-film transistor TR2.

[0291] When the second thin-film transistor TR2 is turned on, current is supplied to the display element 710 via the second thin-film transistor TR2 according to the driving voltage Vdd used to drive the pixel, thereby outputting light from the display element 710.

[0292] Figure 18 This is a circuit diagram illustrating the pixels of a display device 1000 according to another embodiment of the present invention.

[0293] Figure 18 The pixel P of the display device 1000 shown includes an organic light-emitting diode (OLED) as a display element 710 and a pixel driving circuit PDC for driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0294] The pixel drive circuit PDC includes thin-film transistors TR1, TR2, TR3, and TR4.

[0295] In pixel P, signal lines DL, EL, GL, PL, SCL, and RL are set to provide drive signals to the pixel drive circuit PDC.

[0296] and Figure 17 Compared to the pixel P, Figure 18 The pixel P further includes an emission control line EL. An emission control signal EM is provided to the emission control line EL.

[0297] In addition, with Figure 17 Compared to the pixel drive circuit PDC, Figure 18 The pixel driving circuit PDC further includes a fourth thin-film transistor TR4 as a light-emitting control transistor for controlling the light-emitting timing of the second thin-film transistor TR2.

[0298] Reference Figure 18Assume that the gate line of the nth pixel P is GLn, and the gate line of the (n-1)th pixel P adjacent to the nth pixel P is GLn-1. The gate line GLn-1 of the (n-1)th pixel P is used as the sensing control line SCL of the nth pixel P.

[0299] The first capacitor C1 is disposed between the gate G2 of the second thin-film transistor TR2 and the display element 710. The second capacitor C2 is disposed between a terminal of the fourth thin-film transistor TR4, which is supplied with a drive voltage Vdd, and an electrode of the display element 710.

[0300] The first thin-film transistor TR1 is turned on by a scan signal SS provided to the gate line GL to transmit the data voltage Vdata provided to the data line DL to the gate G2 of the second thin-film transistor TR2.

[0301] The third thin-film transistor TR3 is connected to the reference line RL, thereby being turned on or off by the sensing control signal SCS, and sensing the characteristics of the second thin-film transistor TR2, which is the driving transistor, during the sensing period.

[0302] The fourth thin-film transistor TR4 transmits a driving voltage Vdd to the second thin-film transistor TR2 according to the light emission control signal EM, or shields the driving voltage Vdd. When the fourth thin-film transistor TR4 is turned on, current is supplied to the second thin-film transistor TR2, thereby outputting light from the display element 710.

[0303] In addition to the structure described above, the pixel driving circuit PDC according to another embodiment of the present invention can be formed in various structures. For example, the pixel driving circuit PDC may include five or more thin-film transistors.

[0304] According to the present invention, the following beneficial effects can be obtained.

[0305] The thin-film transistor according to one embodiment of the present invention has a large S-factor and a large on-current characteristic in the on-state. Therefore, when such a thin-film transistor is used, the grayscale rendering capability of the display device can be improved, and the current characteristics can also be improved.

[0306] It will be apparent to those skilled in the art that the disclosure described above is not limited to the embodiments and drawings described herein; various substitutions, modifications, and variations may be made in this invention without departing from the spirit or scope thereof. Therefore, the scope of this invention is defined by the appended claims, and all variations or modifications derived from the meaning, scope, and equivalent concepts of the claims are intended to fall within the scope of this invention.

Claims

1. A thin-film transistor, comprising: Active layer on substrate; as well as The first gate that at least partially overlaps with the active layer The active layer includes: Channel section; The first connecting portion that contacts one side of the channel portion; and The second connecting portion that contacts the other side of the channel portion, The first region of the channel portion contacts the first connecting portion, and the second region of the channel portion contacts the second connecting portion. The thin-film transistor further includes a conductive material layer located between the substrate and the active layer. The conductive material layer overlaps with the second region of the channel portion but not with the first region of the channel portion. The conductive material layer is connected to the second connection portion. The thin-film transistor further includes a second gate disposed between the first gate and the active layer, wherein the second gate overlaps with a first region of the channel portion and does not overlap with a second region of the channel portion, and the first gate and the second gate are subjected to the same voltage.

2. The thin-film transistor of claim 1, wherein the conductive material layer comprises a material having light-shielding properties.

3. The thin-film transistor of claim 1, wherein at least a portion of the second gate overlaps with the first gate, and at least a portion of the second gate does not overlap with the first gate.

4. The thin-film transistor of claim 1, wherein the active layer comprises an oxide semiconductor material.

5. The thin-film transistor according to claim 4, wherein the oxide semiconductor material comprises at least one of IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GZO (GaZnO)-based, ITZO (InSnZnO)-based, and FIZO (FeInZnO)-based oxide semiconductor materials.

6. The thin-film transistor of claim 1, wherein the active layer comprises: First oxide semiconductor layer; as well as A second oxide semiconductor layer on top of the first oxide semiconductor layer.

7. The thin-film transistor of claim 6, wherein the active layer further comprises a third oxide semiconductor layer on the second oxide semiconductor layer.

8. The thin-film transistor of claim 1, wherein the thin-film transistor is configured such that the effective gate voltage applied to the first region of the channel is greater than the effective gate voltage applied to the second region of the channel.

9. A display device comprising a thin-film transistor according to any one of claims 1-8.

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