Clock synchronization system and method based on IEEE 1588 protocol

Abstract

The application provides a clock synchronization system and method based on IEEE1588 protocol, comprising: a timestamp determination module, configured to receive an external input second pulse signal and determine a corresponding timestamp of the second pulse signal under a local clock timestamp; a difference value calculation module, connected to the timestamp determination module, configured to calculate a time difference value containing frequency difference information according to the timestamp; an adjustment module, connected to the difference value calculation module, configured to process the time difference value under the local clock and output an adjustment value when the maximum frequency of the local clock meets a preset frequency difference threshold; and a step value determination module, connected to the adjustment module, configured to process a preset step value according to the adjustment value, obtain a frequency difference ratio step value, and adjust a step value of a time counter corresponding to the local clock according to the frequency difference ratio step value, so as to synchronize the frequency of the local clock with that of a master clock. Advantage: The application generates accurate timestamps based on the second pulse signal, and the clock synchronization precision is high.

Description

Technical Field

[0001] This invention relates to the field of clock synchronization technology, and in particular to a clock synchronization system and method based on the IEEE 1588 protocol. Background Technology

[0002] Regarding 1588 synchronization processing, most existing technical solutions focus on forwarding and calculating 1588 messages containing timestamp information, while neglecting the accurate generation of the core timestamp information. Alternatively, the circuit structure for generating timestamps is complex and the steps are cumbersome.

[0003] Therefore, in order to address the above problems, there is an urgent need to design a clock synchronization system and method based on the IEEE 1588 protocol to meet the needs of practical applications. Summary of the Invention

[0004] To address the above technical problems, this invention provides a clock synchronization system and method based on the IEEE 1588 protocol.

[0005] The technical problem solved by this invention can be achieved by the following technical solutions:

[0006] A clock synchronization system based on the IEEE 1588 protocol includes:

[0007] The timestamp determination module is used to receive an externally input second pulse signal and determine the timestamp corresponding to the second pulse signal under the local clock time scale;

[0008] The difference calculation module is connected to the timestamp determination module and is used to calculate a time difference value containing frequency difference information based on the timestamp.

[0009] The adjustment module is connected to the difference calculation module and is used to process the time difference under the action of the local clock, and output an adjustment value when the maximum frequency of the local clock meets a preset frequency difference threshold.

[0010] A step value determination module, connected to the adjustment module, is used to process a pre-step value according to the adjustment value to obtain a frequency difference ratio step value, and adjust the step value of the time counter corresponding to the local clock according to the frequency difference ratio step value, so as to synchronize the frequency of the local clock with that of the master clock.

[0011] Preferably, it further includes:

[0012] The phase synchronization module, connected to the step value determination module, is used to generate timestamp-related information based on the frequency difference ratio step value, and to synchronously process the data according to the IEEE 1588 protocol to obtain a message containing the timestamp-related information and forward it to the master clock, so as to synchronize the phase of the local clock with the master clock.

[0013] Preferably, the adjustment module includes:

[0014] The first multiplication unit is used to perform calculations on the time difference to obtain a first calculation result;

[0015] The first addition unit, connected to the first multiplication unit, is used to obtain a first superposition result based on the first operation result and the delayed signal output by the first addition unit itself.

[0016] The second multiplication unit is used to perform calculations on the time difference to obtain a second calculation result;

[0017] The second addition unit is connected to the first addition unit and the second multiplication unit respectively, and is used to obtain a second superposition result based on the first superposition result and the second operation result, and use the second superposition result as the adjustment value.

[0018] Preferably, the first multiplication unit is an integral operation circuit.

[0019] Preferably, the second multiplication unit is a proportional operation circuit.

[0020] Preferably, the step value determination module includes:

[0021] The third addition unit is used to superimpose the pre-step value and the adjustment value to generate the frequency difference ratio step value.

[0022] This invention provides a clock synchronization method based on the IEEE 1588 protocol, applied to the clock synchronization system based on the IEEE 1588 protocol as described above. The method includes:

[0023] Step S1: Receive an externally input second pulse signal and determine the timestamp corresponding to the second pulse signal under the local clock time scale;

[0024] Step S2: Calculate the time difference value containing frequency difference information based on the timestamp;

[0025] Step S3: Process the time difference value under the action of the local clock, and output an adjustment value when the maximum frequency of the local clock meets a preset frequency difference threshold.

[0026] Step S4: Process a pre-step value according to the adjustment value to obtain a frequency difference ratio step value so that the local clock is synchronized with the frequency of the master clock.

[0027] Preferably, after step S4, the method further includes:

[0028] Step S5: Generate timestamp-related information based on the frequency difference ratio step value, and synchronize the local clock with the master clock by embedding message forwarding and calculation containing timestamp information based on the IEEE 1588 protocol synchronization processing.

[0029] Preferably, step S3 includes:

[0030] Step S31: Perform calculation on the time difference to obtain a first calculation result;

[0031] Step S32: Obtain a first superposition result based on the first calculation result and the delayed signal output by the first addition unit itself;

[0032] Step S33: Perform calculations on the time difference to obtain a second calculation result;

[0033] Step S34: Obtain a second superposition result based on the first superposition result and the second calculation result, and use the second superposition result as the adjustment value.

[0034] Preferably, step S4 includes:

[0035] The frequency difference ratio step value is generated by superimposing the pre-step value and the adjustment value.

[0036] The advantages or beneficial effects of the technical solution of this invention are as follows:

[0037] This invention generates accurate timestamps based on second pulse signals, and achieves frequency synchronization between the local clock and the master clock before the 1588 protocol, which facilitates the subsequent phase synchronization processing of the 1588 clock. The 1588 clock has high synchronization accuracy and a simple circuit structure. Attached Figure Description

[0038] Figure 1 This is a block diagram of a clock synchronization system based on the IEEE 1588 protocol, as shown in a preferred embodiment of the present invention.

[0039] Figure 2 This is a structural block diagram of a clock synchronization system based on the IEEE 1588 protocol, which is a preferred embodiment of the present invention.

[0040] Figure 3 This is a flowchart of clock synchronization in a clock synchronization method based on the IEEE 1588 protocol, as described in a preferred embodiment of the present invention.

[0041] Figure 4 In a preferred embodiment of the present invention, a flowchart of clock synchronization and phase synchronization in a clock synchronization method based on the IEEE 1588 protocol is provided.

[0042] Figure 5The flowchart below shows the specific implementation of step S3 in a preferred embodiment of the present invention. Detailed Implementation

[0043] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0045] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0046] See Figure 1 In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, a clock synchronization system based on the IEEE 1588 protocol is provided, specifically including:

[0047] The timestamp determination module 1 is used to receive an externally input second pulse signal and determine the timestamp corresponding to the second pulse signal under the local clock time scale;

[0048] The difference calculation module 2 is connected to the timestamp determination module 1 and is used to calculate the time difference value containing frequency difference information based on the timestamp.

[0049] Adjustment module 3 is connected to difference calculation module 2 and is used to process time difference under the action of local clock, and output an adjustment value when the maximum frequency of local clock meets a preset frequency difference threshold.

[0050] The step value determination module 4 is connected to the adjustment module 3. It is used to process a pre-step value according to the adjustment value to obtain the frequency difference ratio step value, and adjust the step value of the time counter corresponding to the local clock according to the frequency difference ratio step value so that the local clock is synchronized with the frequency of the master clock.

[0051] Specifically, in this embodiment of the invention, the sampling of an externally input pulse per second (PPS) signal is processed by the timestamp determination module 1 to obtain a timestamp corresponding to the local clock. Then, the timestamp is sent to the difference calculation module 2 to obtain the time difference between the pulse per second signal and the second moment of the local clock. The relevant frequency difference information is also included and reflected in the time difference value for subsequent synchronization processing. Since each local module operates in the local clock domain, during the operation under the action of the local clock, the frequency of the local clock is adjusted by the adjustment module 3 according to the time difference value until the maximum frequency of the local clock meets a preset frequency difference threshold, at which point the current corresponding adjustment value is output. The step value determination module 4 is used to add the pre-configured step value to the adjustment value generated by the adjustment module 3 based on the pulse per second (PPS) signal to obtain the accurate step value. Thus, the local clock can be directly synchronized with the clock frequency based on the pulse per second signal before the 1588 protocol related operations, improving the 1588 synchronization accuracy.

[0052] In a preferred embodiment, it further includes:

[0053] The phase synchronization module (not shown in the figure) is connected to the step value determination module 4. It is used to generate timestamp-related information based on the frequency difference ratio step value, and to process the data synchronously based on the IEEE1588 protocol to obtain a message containing timestamp-related information and forward it to the master clock so that the local clock is phase synchronized with the master clock.

[0054] Specifically, in this embodiment, the local clock generates timestamp-related information based on precise step values. The 1588 synchronization process achieves phase synchronization with the master clock by embedding and calculating message forwarding containing timestamp information. In this embodiment of the invention, the accuracy of the timestamp-related information embedded in the message forwarding by the 1588 is high due to the precise synchronization of the local clock based on the second pulse signal, thereby achieving excellent synchronization with the master clock. Experiments show that the synchronization accuracy error is within ±10ns.

[0055] In a preferred embodiment, such as Figure 2 As shown, adjustment module 3 includes:

[0056] The first multiplication unit 31 is used to process the time difference and obtain a first calculation result;

[0057] The first addition unit 32 is connected to the first multiplication unit 31 and is used to obtain a first superposition result based on the first operation result and the delayed signal output by the first addition unit 32 itself.

[0058] The second multiplication unit 34 is used to process the time difference and obtain a second calculation result;

[0059] The second addition unit 35 is connected to the first addition unit 32 and the second multiplication unit 34 respectively, and is used to obtain a second superposition result based on the first superposition result and the second operation result, and use the second superposition result as an adjustment value.

[0060] Furthermore, it also includes: a delay unit 33, the input of which is connected to the output of the first adder unit 32, and the output of which is connected to the input of the first adder unit 32, for delaying the output of the first adder unit 32 to obtain the aforementioned delayed signal.

[0061] In a preferred embodiment, the first multiplication unit 31 is an integral operation circuit.

[0062] Specifically, in this embodiment, the integration circuit can be implemented using existing circuits, and its integration coefficient Ki can be flexibly configured according to actual use. This invention does not limit its specific value.

[0063] In a preferred embodiment, the second multiplication unit 34 is a proportional operation circuit.

[0064] Specifically, in this embodiment, the proportional calculation circuit can be implemented using existing circuits, and its proportional coefficient Kp can be flexibly configured according to actual use. This invention does not limit its specific value.

[0065] Furthermore, in a preferred embodiment, the aforementioned preset frequency difference threshold can be set to one or more, with multiple preset frequency difference thresholds constituting multiple segment levels. Each segment level corresponds to an integral coefficient Ki and a proportional coefficient Kp, allowing for multi-level adjustment. Preferably, the specific value of the aforementioned preset frequency difference threshold can be configured according to actual needs, and this invention does not limit it.

[0066] In a preferred embodiment, such as Figure 2 As shown, the step value determination module 4 includes:

[0067] The third addition unit 41 is used to superimpose the pre-step value and the adjustment value to generate the frequency difference ratio step value.

[0068] Furthermore, the system may also include: a comparison module, connected between the difference calculation module 2 and the adjustment module 3, used to compare the time difference with a preset frequency difference threshold; when the time difference exceeds the range of the preset frequency difference threshold, the time difference is sent to the adjustment module for subsequent processing; when the time difference is within the range of the preset frequency difference threshold, no processing is performed.

[0069] See Figure 3This invention provides a clock synchronization method based on the IEEE 1588 protocol, applied to the clock synchronization system based on the IEEE 1588 protocol as described above. The method includes:

[0070] Step S1: Receive an externally input second pulse signal and determine the timestamp corresponding to the second pulse signal under the local clock time scale;

[0071] Step S2: Calculate the time difference value containing frequency difference information based on the timestamp;

[0072] Step S3: Process the time difference value under the action of the local clock, and output an adjustment value when the maximum frequency of the local clock meets a preset frequency difference threshold.

[0073] Step S4: Process a pre-step value according to the adjustment value to obtain the frequency difference ratio step value so that the local clock and the master clock are synchronized.

[0074] Specifically, this embodiment of the invention samples an externally input pulse per second (PPS) signal, processes it to obtain a timestamp corresponding to the local clock, and then calculates the difference between the timestamp and the second of the local clock. Relevant frequency difference information is also included in the time difference value for subsequent synchronization processing. Since each local module operates in the local clock domain, during operation under the local clock, the frequency of the local clock is adjusted according to the time difference until the maximum frequency of the local clock meets a preset frequency difference threshold, at which point the corresponding adjustment value is output. Adding the pre-configured step value to the adjustment value generated based on the PPS signal yields a precise step value. This allows the local clock to directly synchronize its frequency based on the PPS signal before 1588 protocol-related calculations, improving 1588 synchronization accuracy.

[0075] In a preferred embodiment, such as Figure 4 As shown, after step S4, the following steps are also included:

[0076] Step S5: Generate timestamp-related information based on the frequency difference ratio step value, and synchronize the local clock with the master clock by embedding and calculating messages containing timestamp information based on the IEEE 1588 protocol synchronization processing.

[0077] Specifically, in this embodiment, the local clock generates timestamp-related information based on precise step values. The 1588 synchronization process achieves phase synchronization with the master clock by embedding and calculating message forwarding containing timestamp information. In this embodiment of the invention, the accuracy of the timestamp-related information embedded in the message forwarding by the 1588 is high due to the precise synchronization of the local clock based on the second pulse signal, thereby achieving excellent synchronization with the master clock. Experiments show that the synchronization accuracy error is within ±10ns.

[0078] In a preferred embodiment, such as Figure 5 As shown, step S3 includes:

[0079] Step S31: Perform calculations on the time difference to obtain a first calculation result;

[0080] Step S32: Obtain a first superposition result based on the first calculation result and the delayed signal output by the first addition unit itself;

[0081] Step S33: Perform calculations on the time difference to obtain a second calculation result;

[0082] Step S34: Obtain a second superposition result based on the first superposition result and the second operation result, and use the second superposition result as the adjustment value.

[0083] In a preferred embodiment, step S4 includes:

[0084] The frequency difference ratio step value is generated by superimposing the pre-step value and the adjustment value.

[0085] The beneficial effects of the technical solution of the present invention are as follows: it generates an accurate timestamp based on the second pulse signal, realizes frequency synchronization between the local clock and the master clock before the 1588 protocol, facilitates the subsequent phase synchronization processing of the 1588 clock, and has high synchronization accuracy of the 1588 clock; and the circuit structure is simple.

[0086] The above are merely preferred embodiments of the present invention and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should recognize that any equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present invention.

Claims

1. A clock synchronization system based on the IEEE 1588 protocol, characterized in that, include: The timestamp determination module is used to receive an externally input second pulse signal and determine the timestamp corresponding to the second pulse signal under the local clock time scale; The difference calculation module is connected to the timestamp determination module and is used to calculate a time difference value containing frequency difference information based on the timestamp. The adjustment module is connected to the difference calculation module and is used to process the time difference under the action of the local clock, and output an adjustment value when the maximum frequency of the local clock meets a preset frequency difference threshold. A step value determination module, connected to the adjustment module, is used to process a pre-step value according to the adjustment value to obtain a frequency difference ratio step value, and adjust the step value of the time counter corresponding to the local clock according to the frequency difference ratio step value so that the local clock is synchronized with the frequency of the master clock. The adjustment module includes: The first multiplication unit is used to perform calculations on the time difference to obtain a first calculation result; The first addition unit, connected to the first multiplication unit, is used to obtain a first superposition result based on the first operation result and the delayed signal output by the first addition unit itself. The second multiplication unit is used to perform calculations on the time difference to obtain a second calculation result; The second addition unit is connected to the first addition unit and the second multiplication unit respectively, and is used to obtain a second superposition result based on the first superposition result and the second operation result, and use the second superposition result as the adjustment value.

2. The clock synchronization system based on the IEEE 1588 protocol according to claim 1, characterized in that, Also includes: The phase synchronization module, connected to the step value determination module, is used to generate timestamp-related information based on the frequency difference ratio step value, and to synchronously process the data according to the IEEE 1588 protocol to obtain a message containing the timestamp-related information and forward it to the master clock, so as to synchronize the phase of the local clock with the master clock.

3. The clock synchronization system based on the IEEE 1588 protocol according to claim 1, characterized in that, The first multiplication unit is an integral operation circuit.

4. The clock synchronization system based on the IEEE 1588 protocol according to claim 1, characterized in that, The second multiplication unit is a proportional operation circuit.

5. The clock synchronization system based on the IEEE 1588 protocol according to claim 1, characterized in that, The step value determination module includes: The third addition unit is used to superimpose the pre-step value and the adjustment value to generate the frequency difference ratio step value.

6. A clock synchronization method based on the IEEE 1588 protocol, applied to a clock synchronization system based on the IEEE 1588 protocol as described in any one of claims 1-5, the method comprising: Step S1: Receive an externally input second pulse signal and determine the timestamp corresponding to the second pulse signal under the local clock time scale; Step S2: Calculate the time difference value containing frequency difference information based on the timestamp; Step S3: Process the time difference value under the action of the local clock, and output an adjustment value when the maximum frequency of the local clock meets a preset frequency difference threshold. Step S4: Process a pre-step value according to the adjustment value to obtain a frequency difference ratio step value so that the local clock is synchronized with the frequency of the master clock.

7. The clock synchronization method based on the IEEE 1588 protocol according to claim 6, characterized in that, After step S4, the method further includes: Step S5: Generate timestamp-related information based on the frequency difference ratio step value, and synchronize the local clock with the master clock by embedding message forwarding and calculation containing timestamp information based on the IEEE 1588 protocol synchronization processing.

8. The clock synchronization method based on the IEEE 1588 protocol according to claim 6, characterized in that, Step S3 includes: Step S31: Perform calculation on the time difference to obtain a first calculation result; Step S32: Obtain a first superposition result based on the first calculation result and the delayed signal output by the first addition unit itself; Step S33: Perform calculations on the time difference to obtain a second calculation result; Step S34: Obtain a second superposition result based on the first superposition result and the second calculation result, and use the second superposition result as the adjustment value.

9. The clock synchronization method based on the IEEE 1588 protocol according to claim 6, characterized in that, Step S4 includes: The frequency difference ratio step value is generated by superimposing the pre-step value and the adjustment value.

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