Integrated circuit device, computer unit, network and method for processing video data

Abstract

The present invention relates to an integrated circuit device for processing video data, comprising: a plurality of video interfaces for receiving and / or transmitting video data from a plurality of data streams; and a frame buffer control device and a frame buffer interface. The frame buffer control device controls access to a frame buffer having a plurality of layers by means of the frame buffer interface, so that the video data from the plurality of data streams is written to different layers of the frame buffer, and the video data of the first layer has a defined color value in a first image region that changes frame by frame. Access to the frame buffer is controlled such that the first image region is determined using the defined color value, and a composite frame of the video data is read from the frame buffer. In the first image region, the composite frame is formed from the video data of the second layer, and in the second region, the composite frame is formed using the video data of the first layer. In addition, the present invention relates to a network device, a network, a computer unit, and a method for processing video data.

Description

Technical Field

[0001] The invention relates to an integrated circuit arrangement, a network device and a network, as well as a computer unit and a method for processing video data. Background Art

[0002] In video technology, at least the following steps are typically performed to transmit a video signal. First, a video signal is read in from a source, such as a camera or other recording device, or generated using software. Subsequently, in another step, the video signal is output to a receiver, such as a monitor, display, or data storage device. However, in practice, not only a point-to-point connection is often desired, in which a source is connected to a receiver, but in many applications, it is also necessary to distribute the video signal from one or more sources to multiple receivers. In practice, between reading in and outputting the video signal, the video signal is often processed, i.e., for example, amplified, reduced, cropped, converted to different frame rates, etc. In particular, video signals from different sources are also merged or combined.

[0003] In practice, software is often used to generate a combined video signal from different video signals. To this end, the video signals are first digitized, for example using a so-called frame grabber. Combining with the aid of software has the advantage that image components, such as user interfaces whose position or arrangement varies between individual frames or images, can be flexibly adjusted when combining the respective video signals. To this end, the corresponding devices must have hardware—which may be expensive depending on the application—on which the software is executed. Furthermore, when such processing is performed with the aid of software, latency is disadvantageously significantly increased, particularly with broadband video signals.

[0004] The combination of video signals is also generally known using integrated circuits. However, to do this, the location of the individual video signals had to be known in advance using the circuit configuration. This advantageously results in low latency. However, the combination of image components whose position or arrangement varies between individual frames or images has not been known using integrated circuits. Summary of the Invention

[0005] It is therefore an object of the present invention to enable a low-latency combination of video signals with image components that vary between individual frames or images.

[0006] The object is achieved by an integrated circuit arrangement, a network device, a computer unit, a network according to an embodiment, and a method for processing video data according to an embodiment.

[0007] The integrated circuit arrangement mentioned above is in particular designed as an integrated circuit, for example in the form of an FPGA or ASIC, and is used to process video data. The integrated circuit arrangement is particularly designed to be able to receive and / or transmit video data in uncompressed form, if desired. To this end, the integrated circuit arrangement has multiple video interfaces for receiving and / or transmitting video data from multiple data streams.

[0008] The integrated circuit device also includes a frame buffer control device and a frame buffer interface. The frame buffer control device controls access to a frame buffer having multiple layers via the frame buffer interface, so that video data from multiple data streams is written to different layers of the frame buffer. The video data of the first layer has defined color values ​​in a first image region that changes from frame to frame.

[0009] A composite frame of video data is read from the frame buffer. To this end, a first image region is defined using defined color values. In the first image region, the composite frame is formed from the video data of the second layer. Conversely, in the remaining regions, the composite frame is formed using the video data of the first layer.

[0010] The embodiment of the integrated circuit arrangement as an FPGA is particularly flexible, since the FPGA can still be configured depending on the application. The embodiment of the integrated circuit arrangement as an ASIC can be produced at low production costs, especially in large quantities.

[0011] The video interface can be essentially any video interface, for example, a digital interface such as DisplayPort, DVI, HDMI, SDI, or an analog interface such as VGA, XGA, S-Video, etc. They are preferably configured to receive or transmit uncompressed video signals. The number of video interfaces can be configured as needed.

[0012] The video interface can also be designed as a network interface, for example. This means that the integrated circuit arrangement includes, for example, a plurality of network interfaces for connecting the integrated circuit arrangement to a plurality of essentially identical, spatially separated integrated circuit arrangements for transmitting data, which includes at least video data.

[0013] The integrated circuit arrangement or a network device comprising the integrated circuit arrangement is preferably connected to another integrated circuit arrangement, in particular according to the present invention, by means of a network interface. The circuit arrangements being "substantially identical" means that the circuit arrangements may differ in the number and / or design of their video interfaces, network interfaces, and / or video processing units, but are otherwise designed to be of the same type.

[0014] Preferably, the integrated circuit device has a plurality of video interfaces for receiving video signals and a plurality of video interfaces for transmitting video signals. The term "plurality" generally means "one or more" within the scope of the present invention.

[0015] Video data is usually present in the form of a data stream (also video stream or Videostream), wherein the image sequence of the video data is transmitted serially image by image and frame by frame, and preferably line by line within a frame, and particularly preferably pixel by pixel within a line, that is, picture element by picture element.

[0016] A frame is a single image that is stored in a frame buffer and read from the frame buffer, in particular at the frame rate at which the transmission is based. A sequence of individually combined frames thus forms a combined video signal or a combined video data stream.

[0017] By means of the frame buffer interface, the video data of each input data stream is written into the frame buffer. For this purpose, the data streams are respectively assigned to different areas in the frame buffer by means of the frame buffer control device.

[0018] To this end, the frame buffer is divided into multiple layers, or sublayers, or layers, meaning at least two layers, or sublayers, or layers. A layer is a region of the frame buffer that preferably contains the video data for a complete frame at the resolution to be read. Within a layer, the position of the video data in the frame to be read can also be determined, for example, based on the position at which the video data of the data stream was written into the frame buffer.

[0019] A combined frame of video data is read from the frame buffer, the combined frame comprising video data from the different layers. To this end, the layers are arranged in a display hierarchy or ranking. This means, for example, that the first or highest layer has priority in the combination over other or lower layers. Video data from lower-ranking layers is only received in the combination in areas of the higher-ranking or prioritized layer marked by a defined color value, i.e., areas whose pixels are filled with the defined color value. Therefore, the video data of the various layers is preferably combined solely based on the display hierarchy and the defined color values ​​of the layers.

[0020] In particular, the video data of the first layer has image areas that vary from frame to frame. This means, for example, that the number, arrangement, and / or size of first image areas of the first layer vary from frame to frame and are not received when combined into a combined frame. Accordingly, and complementary thereto, the number, arrangement, and / or size of second or further image areas of the first layer can vary from frame to frame and are received when combined into a combined frame.

[0021] The frame-to-frame variability of the image region of the first layer is preferably not brought about by a change in the configuration of the frame buffer control device, but rather solely by marking the first image region with a defined color value.

[0022] Although the video data of the first layer are output in the second image area in a combined frame, the first image area is masked with a defined color value in order to be overwritten with the video data of a lower-level layer, such as the video data of the second layer.

[0023] The defined color values ​​represent color values ​​selected according to the color space or color model used. Thus, the color values ​​can be, for example, specific grayscale values, RGB values, Y'CbCr values, etc.

[0024] In other words, the frame buffer control device and the frame buffer interface enable different input video signals or video data streams to be combined into a common or combined video signal according to their display level determined by the layers in the frame buffer and based on image areas marked by defined color values.

[0025] The integrated circuit arrangement according to the present invention thus enables the combination of individual video signals into a composite frame outside of and independently of a computing unit, for example, in the form of a PC. The combination into a composite frame using defined color values ​​is preferably performed without the use of software, but solely with the aid of hardware components.

[0026] The network device mentioned above has an integrated circuit arrangement according to the invention and a physical interface connected to a corresponding interface of the integrated circuit arrangement. The network device also includes a multi-layer frame buffer connected to the frame buffer interface of the integrated circuit arrangement.

[0027] Depending on the type of the further interface, the network device can thus be connected to a video source, a video receiver, further network devices and, preferably using additional suitable interfaces, also to devices such as a computer unit, a USB device or a PC etc.

[0028] In principle, a video source can be any device that outputs a video signal. Such a video source can include, for example, a camera, a medical imaging modality such as an X-ray device, a computed tomography scanner, a magnetic resonance tomography scanner, an ultrasound device, etc., video signals generated by software and / or measuring devices such as an ECG or EEG, video signals retrieved from a data memory, etc. In particular, the video data of the first layer is preferably generated using software, as will be described in detail later.

[0029] In principle, any device that outputs a video signal serves as a video receiver, which can include, for example, a monitor, a display or other display device, a data memory, a connection to an external network, etc.

[0030] The aforementioned computer unit is designed to generate a first layer of video data for transmission to the integrated circuit arrangement according to the present invention. The first layer of video data has defined color values ​​in a first image region that can be varied from frame to frame. In a second region, the first layer of video data includes software-generated data, in particular UI data.

[0031] Therefore, the computer unit generates video data for the first layer of the frame buffer by means of software. In a second image area, preferably different from the first image area, the video data particularly include UI data (user interface data), i.e. video data of an operator interface and / or user interface.

[0032] Based on user interaction or software-generated events, the second image area populated with UI data may change as necessary. This can be achieved by, for example, opening or closing a pop-up menu, a pull-down menu, or the like, enlarging or reducing the size and / or changing the layout of the first and / or second image areas. Because these changes to the user interface often contain important information, they are preferably stored in the second image area of ​​the first layer of the frame buffer, i.e., with the highest priority, and subsequently read or displayed in the combined frame.

[0033] However, the video data of the user interface and the second image area occupied by it are variable, so that they can change from frame to frame. In addition, the user interface has a complex shape, for example in the case of multiple foldable submenus. Under these requirements, in particular, the second image area occupied by the UI data is not implemented by means of configuring the frame buffer control device. On the contrary, according to the present invention, the second image area is cleared by masking the first image area with a defined color value in such a way that only other video data from a lower-level layer of the frame buffer is displayed in the first image area. Therefore, the first image area includes in particular an image area in which no UI data is displayed.

[0034] The aforementioned components form the network mentioned above, in which high-resolution video signals are particularly preferably transmitted. The network comprises a plurality of network devices according to the present invention, which are interconnected in a preferably known network topology. Optionally, the network may also include other components, as described above. Using suitable routing, video data from different data streams can be transmitted from the respective video sources to the circuit arrangement according to the present invention. Furthermore, the combined frames generated in the circuit arrangement according to the present invention, or the video streams derived from such combined frames, can be transmitted via the network to the desired video receiver and output there.

[0035] The method for processing video data mentioned above includes the following steps, which are performed using an integrated circuit device, particularly an FPGA or an ASIC. In a first step, video data from multiple data streams is received. In a further step, the video data from the multiple data streams is written to different layers of a frame buffer. The video data of the first layer has defined color values ​​in a first image region that can vary from frame to frame.

[0036] Furthermore, a combined frame of video data is read from the frame buffer. To this end, a first image region is determined using the defined color values. In the first image region, the combined frame is formed from the video data of the second layer, and in the remaining regions, the combined frame is formed using the video data of the first layer.

[0037] Most of the aforementioned components of the network device can be implemented completely or partially in the form of integrated circuits or logic arrays.

[0038] In principle, however, some of these components can also be implemented as software-supported hardware, such as FPGAs, ASICs, etc., especially when they involve particularly fast calculations. Likewise, required interfaces, such as those that merely receive data from other software components, can also be implemented as software interfaces. However, they can also be implemented as hardware-based interfaces controlled by suitable software.

[0039] A primarily software-based implementation has the advantage that previously used network devices can be easily adapted to operate in accordance with the present invention by partial modification and software upgrades or by reconfiguring the integrated circuit device (FPGA). This object is also achieved by a corresponding computer program product that can be configured in a programmable logic device of a network device and contains program segments or logic instructions for executing the steps of the method according to the present invention when executing the logic for the network device. In addition to the computer program, such a computer program product may also include additional components, such as files and / or additional components, as well as hardware components, such as a hardware key (dongle, etc.) for using the software.

[0040] For transport to the network device and / or for storage in the network device, a computer-readable medium, such as a memory stick, a hard disk, or other transportable or permanently installed data carrier, on which program segments of a computer program that can be programmed and executed on an integrated circuit device are stored can be used. For this purpose, the integrated circuit device can have, for example, one or more logic elements operating together.

[0041] In addition, other particularly advantageous designs and improvements of the present invention are shown in the following description, in which claims of one claim category can also be improved in a similar manner to claims and description parts belonging to another claim category, and in particular, individual features of different embodiments or variants can also be combined to form new embodiments or variants.

[0042] In the second image area, the video data of the first layer preferably include software-generated data, in particular UI data, as already described above in conjunction with the computer unit.

[0043] In principle, it is possible to check for each pixel individually whether its color value corresponds to a defined color value. However, with such pixel-by-pixel color values, artifacts may occur if, for example, one or a small number of pixels in the image or graphic actually provided in the second image area accidentally have a defined color value.

[0044] Thus, the first image region preferably has a plurality of pixels, i.e., at least two, particularly preferably at least four, more particularly preferably at least six, and most preferably at least eight, successive pixels with defined color values, row by row. Video data for the second layer is only received in the combined frame if the corresponding plurality of pixels in a row has the defined color value. This reduces or prevents the unintended reception of video data from lower-level layers at pixels that actually belong to the second image region.

[0045] Preferably, the UI data or user interface of the software have a color scheme that is known or can be determined, in particular during programming. It is therefore known which color values ​​often occur and which color values ​​rarely or never occur.

[0046] The frame buffer preferably includes more than two layers. In this case, the respective higher-level layer has a first image area with defined color values, in which the composite frame is formed from the video data of the lower-level layers. This means that the highest-level layer, i.e., the first or topmost layer, is received with the highest priority in the composite frame, while the video data of the second layer is received only in image areas masked by defined color values. The video data of the second layer is received with the next lower priority, and the video data of the third layer is received only in image areas masked by defined color values ​​in the first and second layers, and so on.

[0047] Preferably, the video interface comprises a network interface for receiving video data from a separate network device. Here, "separate" means separated in space. The devices are connected to each other via the network interface, i.e., connected to each other via a network suitable for video transmission.

[0048] The video data of the lower-level layers—ie, the layers other than the first layer—are preferably combined within the first image region as a linear combination. This can be done, for example, using the following formula.

[0049] VC(x)=α*L3(x)+(1-α)*L2(x).

[0050] Here, VC(x) represents the color value at pixel x in the combined frame. This color value is a linear combination of the color value (or three RGB values) at pixel x in the second layer L2(x) and the color value at pixel x in the third layer L3(x). Here, α is a value between 0 and 1, and weights the color value of the third layer L3 relative to the color value of the second layer L2. In other words, alpha blending or partially transparent superposition is performed between the two layers.

[0051] By means of alpha blending in the first image region, it is thus achieved that the corresponding video data acquires a partially transparent or semi-transparent optical effect.

[0052] The frame buffer interface and the frame buffer are preferably designed such that write access and read access are possible at least in different areas of the frame buffer at the same time. This allows access to the frame buffer to be controlled in a time-efficient manner.

[0053] If the frame buffer comprises more than two layers, all layers can use exactly one common color value as defined color value for masking the first image area.

[0054] Alternatively, each layer preferably has its own defined color value. This advantageously allows for a defined color value to be determined for each layer that is as complementary as possible to the video data of the second image region stored in the corresponding layer. The determination of the corresponding color values ​​has already been described in detail above.

[0055] In the lowest layer or the layer with the lowest priority, the image area that does not store video data can be filled with a background color or background pattern. With the help of this default color or default pattern, a more visually attractive appearance can be achieved in the combined frame.

[0056] The computer unit preferably generates the UI data such that it includes video data of the mouse pointer. This means that the position of the mouse pointer, detected as a result of a user input using the mouse, is determined by the computer unit. The mouse pointer is written to the frame buffer as the first layer of video data and is not masked with a defined color value, so that it is output in the composite frame. Depending on the display background or the position of the mouse pointer, the mouse pointer can be assigned different symbols using software.

[0057] Preferably, the video data includes at least high-resolution video data or video signals (according to the HD Video Standard). For the purposes of the present invention, video data is understood to mean video data having at least an image resolution of 1280 x 720 pixels at an image repetition rate or frame rate of 50 fps, typical for HDTV. However, the resolution is preferably 1920 x 1080 pixels. Of course, video signals with lower resolutions can still be processed and transmitted using the integrated circuit arrangement.

[0058] The video data particularly preferably includes ultra-high-resolution video data (according to the UHD video standard). "Ultra-high-resolution video data" is understood to mean video data with a resolution of 4K or higher. "4K" means a resolution in the order of 4,000 pixels per line, for example, 3,840, 4,096, etc. The video data particularly preferably also includes video data with a resolution of 8K (approximately 8,000 pixels per line). This is particularly advantageous for achieving detail-accurate display even on larger display devices.

[0059] Preferably, a frame buffer control device is used to assign positions in the frame buffer to the data streams of the video data, thereby defining the arrangement of the video data of the corresponding data stream in the frame. The frame buffer control device is configured—particularly preferably based on user preferences—to control the positions of the frames of the original video signals in the generated combined frame based on the corresponding positions stored in the frame buffer. Thus, the various video signals can be advantageously combined as desired.

[0060] Additionally or alternatively, the integrated circuit arrangement preferably has a window control unit that resets a vacated position when the position of the data stream of the video data in the frame buffer is shifted. The shifting of the data stream position is performed by changing the configuration of the frame buffer control unit.

[0061] The window control unit can thus advantageously ensure that only current information is contained in the combined video signal. This can be done, for example, by setting the corresponding position to a background value or by setting the alpha value of a previously stored video signal to zero.

[0062] Preferably, the network device includes a processor connected to the integrated circuit device. In addition, the network device also configures parameters for image processing and / or routing of video data of each data stream by means of a UDP unit included in the integrated circuit device as required.

[0063] The processor processes user input and sends corresponding UDP data to the UDP unit. The UDP unit translates the UDP data into a format suitable for write access for configuring other components of the network device.

[0064] Corresponding instructions for reconfiguring the routing of video data or parameters for image processing can be transmitted as UDP data via the network to other network devices or corresponding target network devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] The present invention will be described in detail below based on an embodiment with reference to the accompanying drawings. In this case, identical components are provided with identical reference numerals in different figures.

[0066] The drawings are generally not drawn to scale. The drawings show:

[0067] Figure 1 A schematic block diagram showing an embodiment of a network according to the present invention;

[0068] Figure 2 A schematic block diagram showing an embodiment of a network device according to the present invention;

[0069] Figure 3 A schematic block diagram shows an embodiment of a circuit arrangement according to the present invention;

[0070] Figure 4 a schematic block diagram showing a frame buffer with multiple layers and a combined frame being read; and

[0071] Figure 5 A schematic flow chart showing an embodiment of a method for processing video data according to the present invention is shown. DETAILED DESCRIPTION

[0072] exist Figure 1 2 shows a network 20 according to the present invention as an example block diagram. In this exemplary embodiment, network 20 includes five network devices 50, which are essentially identical in design. However, the number and arrangement of network devices 50 can be easily adjusted depending on requirements or application. One of the network devices is connected to a computer unit 25 or computer 25. This is also referred to below as a proxy network device 50. With the help of computer unit 25, Ethernet data E, in particular instructions for configuring network 20, can be sent to network device 50 via an Ethernet connection.

[0073] Two of the network devices 50 are connected to a video signal source 21. The video signal source 21 can be designed, for example, as a camera, but can also be, for example, software-generated video data—hereinafter also referred to as a video signal—which can originate from a medical imaging modality, such as an X-ray device, or can be output as video data by a measuring device, such as an ECG or EEG.

[0074] The video signal source 21 transmits its video signals V1 and V2 to the network devices 50 connected thereto. The network device 50 to which the video data V2 is transmitted is directly connected to the proxy network device 50. The network device 50 to which the video data V1 is transmitted is indirectly connected to the proxy network device 50 via another network device 50.

[0075] Network devices 50 transmit network data N to each other. The network data N is a specific data packet that also includes useful data such as video data V1, V2, V3, and V4, Ethernet data E, and USB data. In addition to the network data N including the useful data, there is also transmission control data including address data, a checksum, and the like.

[0076] A computer unit 25 is connected to a medical imaging modality 24 in the form of an X-ray device 24. The X-ray device 24 records video data V4, for example, video data from within a patient's body, and sends it to a frame buffer 28. Software-generated video data V3 are also written to the frame buffer 28. In this embodiment, these video data include elements of a user interface, i.e., UI data. The UI data are arranged in the second image area B2 and are to be output or displayed with the highest priority. According to the present invention, the computer unit 25 therefore generates the video data V3 such that the video data V3 have defined color values ​​only in the first image area B1. The defined color values ​​identify the first image area so that it is overwritten by the other video data V1, V2, V4, V0 when forming the combined frame VC.

[0077] The video data V3, V4 of the two video data streams are stored in two different frames. Therefore, the frame buffer 28 is written at the frame rate of the respective video signal and read at different frame rates as needed, wherein arbitration logic can prevent possible conflicts between read and write accesses.

[0078] The video signals V3 and V4 are sent to the proxy network device 50. In the proxy network device 50, the video signal V3 is written into the first layer L1 of the frame buffer 51, while the video signal V4 is written into the second layer L2 together with the video signals V1 and V2 from the other video signal sources 21. Information about the assignment of the video signals V1, V2, V3, and V4 to the respective prescribed layers L1 and L2 and the respective prescribed positions within the respective layers is stored in the configuration of the frame buffer control device 87 (see Figure 3 ).

[0079] The video data V3 of the first layer L1 has a second image area B2, which extends as a function bar over the entire width in the upper area of ​​the first layer L1. This can be a menu bar, for example. For example, a mouse pointer can also be included in the video data V3 or UI data of the first layer L1. The remaining area of ​​the first layer L1 is marked with a defined color value as the first image area B1. In the second layer L2, the upper area (corresponding to the second image area B2 of the first layer L1) is left empty, and the video signals V1, V2, V4 are arranged as rectangles of essentially the same size below the upper area. The terms "upper", "lower", etc. here refer to the display of the video signals in accordance with the regulations. No input video signal is provided in the area V0. Therefore, a default color value or a graphic is inserted as a background and used, if necessary, when generating the composite frame VC.

[0080] The video signals V1, V2, V3, V4, V0 can in principle be scaled as desired, for example by means of the video processing units 90, 91, 92 described in detail below (see Figure 3 ) and can be set arbitrarily in the corresponding layers L1, L2 of the frame buffer 51 and thus also in the combined frame VC generated therefrom by means of the frame buffer control device 87.

[0081] The combined frame VC or combined video signal VC is packed into network data N for transmission and transmitted to the network device 50. The combined video signal VC is output by means of a video signal receiver 23 or an output device 23 connected to the network device 50, for example in the form of a monitor, display, etc. Alternatively or additionally, the combined video signal VC can also be output by means of an output device 23 directly connected to the proxy network device 50.

[0082] By means of the network 20 according to the invention, video signals V1, V2, V3, V4 from different video signal sources 21, 26, 27 can thus be detected, processed and / or combined as required, transmitted over different routes through the network and outputted via a video receiver 23 selected by the user. Figure 2 The functions of the network device 50 will be explained in detail.

[0083] Network 20 is configured according to its requirements-based design 32 and therefore has a known topology. Routes between network devices 50, the components they contain, and the components connected thereto can be determined and recorded in an addressing scheme. With the help of the addressing scheme, routes from one point in network 20 to another can be determined, and corresponding data flows can be forwarded as required.

[0084] Figure 2 The network device 50 according to the present invention is shown as an example and schematic block diagram. The network device 50 comprises an integrated circuit arrangement 70 as a central component, which is designed as an integrated circuit 70, in particular as an FPGA. Figure 3 The integrated circuit 70 is described in detail.

[0085] The network device 50 has physical plug-in terminals 52, 53, 54, and 55 for video signals. Two DisplayPort inputs 52 and two HDMI inputs 53 are used to receive video signals. The DisplayPort inputs 52 and HDMI inputs 53 are each connected to a common multiplexer 61, with only one of these inputs 52, 53 being used at any one time. HDMI and DisplayPort each have four signal pins or lanes. The lanes of the used plug-in terminals 52 and 53 are combined onto a single signal line by means of the multiplexer 61 and transmitted to the integrated circuit 70.

[0086] In turn, integrated circuit 70 outputs the multiplexed video signal to demultiplexer 62, which distributes the combined video signal to different channels according to the standards of the corresponding connected output terminals 54 and 55. Two DisplayPort output terminals 54 and two HDMI output terminals 55 are provided for transmitting video signals, wherein each DisplayPort output terminal 54 and each HDMI output terminal 55 are connected to a common demultiplexer 62, but only one of the output terminals is used at any one time.

[0087] The DisplayPort terminal supports so-called DisplayPort Multi-Stream (DP Multi-Stream, DP-MST), in which at least two video signals can be transmitted by means of the DisplayPort terminal.

[0088] The described design of video signal inputs 52, 53 and video signal outputs 54, 55 ensures that a single connection type is always available at the installation location of network 20. In principle, network device 50 can also be used in a single configuration at different locations where different connection types may be required. Alternatively, other video connectors, such as VGA, S-Video, or DVI, can be adapted.

[0089] The network device 50 also has eight network terminals 63 and 64. Four of these are designed as SFP modules 63 and can be equipped with SFP transceivers as needed, saving the cost of relatively expensive transceivers. Depending on the distance to be bridged, the SFP transceivers can be single-mode or multimode and can, if required, have transmission rates of, for example, 5 Gbit / s or 10 Gbit / s. The remaining four network terminals are designed, for example, as PCIe terminals 64, so that the network device 50 can be integrated as a plug-in module into suitable devices, such as a computer unit or medical imaging modality, if necessary.

[0090] The number of video terminals 52 , 53 , 54 , 55 and network terminals 63 , 64 of the network device 50 depends substantially on the processing performance of the integrated circuit 70 and can also be selected arbitrarily when designing the network device 50 .

[0091] The network device 50 further comprises a frame buffer 51 in the form of one or more DDR-RAM modules, which is constructed as a multi-layer frame buffer. Figure 3 Detailed description.

[0092] Figure 3 As an example and schematic block diagram, an integrated circuit 70 according to the present invention in the form of an FPGA is shown. The integrated circuit 70 has a video module 71 and a network module 73. The outputs or inputs of the respective network interfaces 85 are connected to the network ports 63 of the network device 50, which are designed as SFP transceivers.

[0093] Video module 71 has two identically configured combined video input / output interfaces 83, which are connected to multiplexer 61 and demultiplexer 62 of network device 50, respectively. Combined video input / output interfaces 83 enable simultaneous forwarding of input and output video signals in the corresponding directions. Input video signals are forwarded to DisplayPort connection matrix input interface 74 or HDMI connection matrix input interface 75, depending on the standards they are based on. Output video signals are received via connection matrix 93 at DisplayPort connection matrix output interface 76 or HDMI connection matrix output interface 77, defined by the component addresses of the addressing scheme, depending on the standards they are based on. These signals are then forwarded to the corresponding demultiplexer 62 of network device 50 via the connected combined video input / output interfaces 83.

[0094] The integrated circuit 70 further includes a frame buffer control device 87 and a frame buffer interface 86. The frame buffer control device 87 controls access to the frame buffer 51 of the network device 50 via the frame buffer interface 86, so that video data V1, V2, V3, V4, and V0 from multiple data streams are written to different layers L1 and L2 of the frame buffer 51.

[0095] To this end, the data streams of video data V1, V2, and V4 are each assigned a position in the second layer L2 of the frame buffer 51 by means of the frame buffer control device 87, so that the arrangement of the video data of the corresponding data stream is also defined for generating the combined frame VC. Here, the frame buffer control device 87—particularly after its configuration has been set up accordingly according to user preferences—also controls the position of the frames of the respective original video signals V1, V2, and V4 in the generated combined video frame VC by means of the corresponding positions at which the frames are stored in the frame buffer 51.

[0096] To read or generate the composite frame VC, it is first determined in the first layer L1 at which locations or pixels a defined color value occurs. In particular, it is determined whether the defined color value occurs at multiple, i.e., at least two, consecutive pixels in a row. At these pixels, i.e., in the first image region B1, the video data V1, V2, V4, and V0 of the second layer L2 are used to generate the composite frame VC. At the remaining pixels, i.e., in the second image region B2, the video data V3 of the first layer L1 is used. The composite frame VC thus composed of the video data V1, V2, V3, V4, and V0 is read from the frame buffer 51 using the frame buffer interface 86.

[0097] The composite frame VC includes video data V3 in the upper second image area B2, which includes a menu bar M0 as UI data. Below this, in the composite frame VC, video signals V1, V2, and V4, including external video data, are arranged as equal-sized rectangles in the first image area B1. When the composite frame VC is read, the remaining rectangle in the lower right corner is filled with a background color or background pattern selected by default, since no video data exists in this area in the second layer L2.

[0098] exist Figure 4 FIG. 5 shows an exemplary embodiment of a frame buffer 51 of a network device 50 according to the present invention, wherein another set of input video data V3' is written into the first layer L1. In this case, the video data V3' is written in addition to the menu bar M0 (see FIG. Figure 1 ), also includes a drop-down menu M1, which is arranged as a rectangle in the upper right corner below the menu bar M0. In addition, the video data V3' includes a pop-up menu M2, which is arranged as a rectangle in the center or vertically and horizontally centered in the first layer L1.

[0099] If the user moves on the activated user interface using an input device such as a mouse or keyboard, clicks on the user interface, etc., additional menus M1 and M2 are included, for example, in the video data V3'. The menus can change from frame to frame and have any complex shape, making it difficult to change their shape and arrangement by configuring the frame buffer control device 87.

[0100] The menus M0, M1, M2 are recognized as UI data by the software 27 of the computer unit 25, are assigned to the second image area B2 and are therefore not masked with a defined color value. However, according to the invention, the first image area B1 is masked with a defined color value.

[0101] As described above, a combined frame VC' is generated from the first layer L1 and the second layer L2. Figure 1 Unlike the composite frame VC in , the composite frame VC' additionally contains further menus M1, M2. In the corresponding image area, the video data V1, V2, V4, V0 originating from the second layer L2 are therefore not completely incorporated into the composite frame VC'.

[0102] Furthermore, the integrated circuit arrangement 70 has a window control unit 88 which resets the vacated position when the position of the data stream of the video data V1 , V2 , V4 , V0 in the frame buffer 51 is shifted.

[0103] Window control unit 88 thus ensures that only current information is contained in the combined video signal. This can be done, for example, by setting the corresponding position to a background value or by setting the alpha value of a previously saved video signal to zero. This is possible because frame buffer 51 is designed as a multi-layer frame buffer 51. When the alpha value of a layer is set to zero, the underlying layer is visible or displayed.

[0104] exist Figure 5 FIG. 4 schematically shows a flow chart of an embodiment of a method for image processing according to the present invention.

[0105] In a first preliminary step, video data V3 are generated by computer unit 25 using software 27, which includes UI data M0, M1, M2 in second image region B2. In a first image region B1, which is different from second image region B2, video data V3 are filled or masked with defined color values ​​using software 27.

[0106] In a second step II, software-generated video data V3 and video data V1 , V2 , V4 from other video sources are received by means of the video interface 83 .

[0107] In the third step, the video data V3 generated by the software is written into the first layer L1 of the frame buffer 51 via the frame buffer interface 86 by means of the frame buffer control device 87. Furthermore, the other video data V1, V2, and V4 are written into the second layer L2 of the frame buffer 51 via the frame buffer interface 86 at the positions assigned thereto by means of the configuration of the frame buffer control device 87. Furthermore, if the second layer L2 of the frame buffer 51 is not already filled with the video data V1, V2, and V4, a default color value or a default pattern is written into the second layer as video data V0.

[0108] In a fourth step IV, it is determined in the first layer L1 of the frame buffer 51 at which positions or pixels a defined color value occurs. In particular, it is determined whether the defined color value occurs at a plurality of pixels, i.e., at least two pixels that are consecutive in a row. These pixels form the first image region B1.

[0109] In a fifth step V, the video data V1, V2, V4, V0 of the second layer L2 are used to generate a combined frame VC in the first image region B1. At the remaining pixels, i.e., in the second image region B2, the video data V3 of the first layer L1 are used. The combined frame VC composed of the video data V1, V2, V3, V4, V0 in this manner is read from the frame buffer 51 by means of the frame buffer interface 86.

[0110] In an additional sixth step VI, the combined frame VC is packed into network data N by means of the network interface 63 of the network device 50 and sent via the network 20 .

[0111] In an additional seventh step VII, network data N are received from another network device 50. The combined frame VC is unpacked and displayed via a suitable output device 23.

[0112] Alternatively, the combined frame VC can also be displayed directly via a suitable output device 23 .

[0113] Finally, it should be pointed out again that the apparatus and method described in detail above are only embodiments and can be modified in various ways by a skilled person without departing from the scope of the present invention. For example, the frame buffer can be extended with other layers using the described functions.

[0114] Furthermore, the frame buffer has previously been described only as an asynchronous frame buffer. Similarly, a synchronous frame buffer can also be used, in which each layer is implemented using areas to be written, read, and cleared. Pointers for the accesses to be performed are then stored in the frame buffer control. A frame is only read when it has been completely written to the frame buffer. A synchronous frame buffer can be advantageous in order to avoid conflicting read or write accesses, and thus also in order to avoid display artifacts, since a complete and consistent frame is always read.

[0115] Furthermore, the use of the indefinite article "a" or "an" does not exclude the possibility that the feature in question may be present multiple times. Similarly, the term "unit" does not exclude the possibility that the unit is composed of multiple components, which—unless otherwise specified—may also be spatially distributed. However, a network device explicitly refers to an integral unit that includes all of the specified components in a structural unit.

Claims

1. An integrated circuit device (70) for processing video data, the integrated circuit device comprising: - a plurality of video interfaces (83, 85) for receiving and / or sending video data from a plurality of data streams, - a frame buffer control device (87) and a frame buffer interface (86), wherein the frame buffer control device (87) controls access to a frame buffer (51) having a plurality of layers (L1, L2) by means of the frame buffer interface (86), - causing video data from a plurality of data streams to be written into different layers (L1, L2) of the frame buffer (51), wherein the video data of the first layer (L1) has defined color values ​​in a first image region (B1) that changes from frame to frame, - the first image region (B1) is determined as a plurality of pixels that follow one another line by line and have defined color values, and - causing a combined frame (VC) of video data to be read from said frame buffer (51), in - in said first image area (B1), said combined frame (VC) is formed by video data of a second layer (L2), and - forming said combined frame (VC) in a second image area (B2) using the video data of said first layer (L1). 2 . The integrated circuit arrangement according to claim 1 , wherein the video data of the first layer comprises software generated data in the second image area ( B2 ). 3 . The integrated circuit arrangement according to claim 2 , wherein the software generated data is UI data ( M0 , M1 , M2 ). 4 . The integrated circuit arrangement according to claim 1 , wherein the first image region ( B1 ) comprises at least four pixels of a defined color value that follow one another line by line.

5. An integrated circuit arrangement according to any one of claims 1 to 3, wherein the frame buffer (51) has more than two layers (L1, L2, . . . ), and the higher-level layers each have a first image area (B1) with defined color values, in which the combined frame is formed from the video data of the lower-level layers.

6. The integrated circuit arrangement according to any one of claims 1 to 3, wherein the video interface (83, 85) comprises a network interface (85) that receives the video data from a separate network device (50). 7 . The integrated circuit arrangement according to claim 5 , wherein the combination of the video data of the low-level layers in the second image area ( B2 ) is implemented as a linear combination.

8. The integrated circuit device according to any one of claims 1 to 3, comprising a window control unit (89) for resetting a vacated position when the position of the data stream of video data in the frame buffer (51) is shifted.

9. The integrated circuit device of claim 1, wherein the integrated circuit device (70) is a FPGA or an ASIC.

10. A network device (50), comprising an integrated circuit arrangement (70) according to any one of claims 1 to 9 and a physical interface, the physical interface being connected to a corresponding interface (83, 85) of the integrated circuit arrangement (70), and comprising a frame buffer (51) with a plurality of layers (L1, L2), the frame buffer (51) being connected to the frame buffer interface (86) and being controlled via the frame buffer control device (87).

11. A computer unit (25) configured to generate video data of a first layer (L1) for transmission to an integrated circuit arrangement (70) according to any one of claims 1 to 9, wherein the video data of the first layer (L1) have defined color values ​​in a first image region (B1) that can be changed from frame to frame and include software-generated data in a second image region (B2).

12. The computer unit (25) according to claim 11, wherein the software generated data are UI data (M0, M1, M2).

13. The computer unit (25) according to claim 12, wherein the UI data comprises video data of a mouse pointer.

14. A network (20) comprising a plurality of network devices (50) according to claim 10.

15. The network (20) according to claim 14, wherein the network (20) comprises at least one computer unit (25) according to any one of claims 11 to 13.

16. A method for processing video data by means of an integrated circuit arrangement (70), the method comprising the following steps: - receiving (II) video data from multiple data streams, - writing (III) video data from a plurality of data streams into different layers (L1, L2) of a frame buffer (51), wherein the video data of a first layer (L1) has defined color values ​​in a first image area (B1) that can vary from frame to frame, - determining (IV) the first image region (B1) as a plurality of pixels that follow one another line by line and have defined color values, - reading a combined frame (VC) of video data from said frame buffer (51), in - in said first image area (B1), said combined frame (VC) is formed by video data of a second layer (L2), and - In the remaining image area (B2), forming the combined frame (VC) using the video data of the first layer (L1).

17. The method of claim 16, wherein the integrated circuit device (70) is a FPGA or an ASIC.

18. A computer program product comprising a computer program which can be directly loaded into an integrated circuit arrangement (70), the computer program comprising program sections for executing all steps of the method according to claim 16 or 17 when the integrated circuit arrangement (70) is configured by means of the computer program.

19. A computer-readable medium having stored thereon a program segment capable of configuring an integrated circuit device (70), wherein when the integrated circuit device (70) is configured by means of the program segment at runtime, all steps of the method according to claim 16 or 17 are executed.

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