Methods for wafer cleaving and chip failure analysis

Abstract

This application relates to a method for wafer dicing and chip failure analysis. The method includes providing a wafer sample, the wafer sample including a first surface having a target point and a second surface opposite to the first surface; forming a first crack and a second crack at the edge of the wafer sample, wherein the orthographic projections of the first crack and the second crack on the first surface are on the same straight line as the target point along a preset direction; forming a dicing groove along the preset direction on the second surface, the bottom of the dicing groove being at a preset distance from the first surface, and the orthographic projections of the first crack and the second crack on the second surface being on the same straight line as the dicing groove; dicing the wafer sample along the dicing groove to break the wafer sample along the preset direction, obtaining a cross-section of the target point along the preset direction. This method can accurately obtain the cross-section of the target point along the preset direction, unaffected by the angle between the wafer crystal orientation and the preset direction.

Description

Technical Field

[0001] This application relates to the field of integrated circuit manufacturing, and in particular to a method for wafer dicing and a method for chip failure analysis. Background Technology

[0002] In semiconductor process development or semiconductor device failure analysis, analyzing the cross-sectional morphology of specific patterns on a wafer is a very common method. Wafers are single-crystal structures with neatly arranged atoms. A typical cleaving method involves using a diamond tungsten steel pen to gently scratch the surface of the silicon wafer near the target area, then tearing it directly by hand. The fracture surface naturally and neatly breaks along the lattice direction, which is the preferred direction for wafer fracture. The wafer notch is perpendicular or parallel to the product lines on the wafer. Typically, the product lines are parallel or perpendicular to the wafer lattice direction. The fracture surface obtained from natural cleaving is parallel or perpendicular to the preferred direction for wafer fracture, and direct observation of this fracture surface allows for microscopic analysis of the wafer's physical properties.

[0003] Due to performance requirements, some wafers have a preset angle between the product line direction and the wafer lattice direction (preferred direction for wafer fracture) that is greater than 0 degrees and less than 90 degrees. The fracture surface obtained by natural cleaving also has a preset angle with the wafer lattice direction. In this case, it is impossible to perform microscopic analysis of the wafer's physical properties by directly observing the fracture surface. How to ensure that the direction of the fracture surface after cleaving is always perpendicular or parallel to the product line direction on the wafer has become an urgent problem to be solved. Summary of the Invention

[0004] This application provides a method for wafer cleaving and a method for chip failure analysis, which can optimize the influence of the wafer lattice orientation on the direction of the fracture surface after cleaving, so that the direction of the fracture surface after cleaving is always perpendicular or parallel to the product line direction on the wafer.

[0005] A method for wafer dicing includes:

[0006] A wafer sample is provided, the wafer sample including a first surface having a target point and a second surface disposed opposite to the first surface;

[0007] A first crack and a second crack are formed at the edge of the wafer sample, and the orthographic projections of the first crack and the second crack on the first surface are on the same straight line as the target point along a preset direction.

[0008] A cutting groove is formed on the second surface along a preset direction. The bottom of the cutting groove and the first surface are at a preset distance. The orthographic projections of the first crack and the second crack on the second surface are on the same straight line as the cutting groove.

[0009] The wafer sample is cleaved along the cutting groove so that the wafer sample is cleaved in a preset direction to obtain a cross section of the target point along the preset direction.

[0010] In one embodiment, forming a first crack and a second crack at the edge of the wafer sample includes:

[0011] A first crack and a second crack extending toward a target point are formed on the first surface, and the first crack and the second crack at least partially penetrate the wafer sample.

[0012] In one embodiment, the step of forming a first crack and a second crack extending toward a target point on the first surface includes:

[0013] Using the first cutting device, a first slit and a second slit are formed on opposite sides of the target point along a preset direction;

[0014] The step of forming a cutting groove along a predetermined direction on the second surface includes:

[0015] Using the first and second cracks as endpoints, a cutting groove is formed on the second surface by a second cutting device.

[0016] In one embodiment, both the first cutting device and the second cutting device are laser cutting devices.

[0017] In one embodiment, the lengths of the first rift and the second rift in the preset direction are a first preset length and a second preset length, respectively.

[0018] In one embodiment, both the first preset length and the second preset length are preset values.

[0019] In one embodiment, in a preset direction, the distance between the target point and the first crack is equal to the distance between the target point and the second crack.

[0020] In one embodiment, the ratio of the preset distance to the wafer sample thickness is less than 1 and not less than 0.1.

[0021] In one embodiment, the angle between the preset direction and the lattice direction of the wafer sample is greater than 0 degrees and less than 90 degrees.

[0022] In one embodiment, the step of dicing the wafer sample along the dicing groove includes:

[0023] Provide a thimble;

[0024] Place the ejector pin in the cutting groove, and there is a certain distance between the ejector pin and the orthographic projection of the target point in the cutting groove;

[0025] Force is applied to the wafer sample and the ejector pin to cause the wafer sample to crack along the dicing groove.

[0026] In one embodiment, the step of providing a wafer sample includes:

[0027] Provide wafers with target points;

[0028] The wafer is shredded to obtain a wafer sample including the target point.

[0029] In one embodiment, the length of the target point is not less than 10 micrometers.

[0030] A method for chip failure analysis includes:

[0031] Using the abnormal chip region as the target point, the wafer dicing method described in any of the above methods is used to obtain the cross-section of the abnormal chip region along a preset direction.

[0032] Failure analysis was performed on the cross-section of the abnormal chip area.

[0033] The aforementioned wafer dicing method and chip failure analysis method include providing a wafer sample, the wafer sample comprising a first surface having a target point and a second surface disposed opposite to the first surface; forming a first crack and a second crack at the edge of the wafer sample, wherein the orthographic projections of the first crack and the second crack on the first surface are on the same straight line as the target point along a preset direction; forming a dicing groove along the preset direction on the second surface, the bottom of the dicing groove being at a preset distance from the first surface, and the orthographic projections of the first crack and the second crack on the second surface being on the same straight line as the dicing groove; dicing the wafer sample along the dicing groove to split the wafer sample along the preset direction, thereby obtaining a cross-section of the target point along the preset direction. This method can accurately obtain the cross-section of the target point along the preset direction, unaffected by the angle between the wafer crystal orientation and the preset direction. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic flowchart of a wafer dicing method in one embodiment;

[0036] Figure 2 This is a schematic diagram of the process for providing a wafer sample in one embodiment;

[0037] Figure 3 This is a top view schematic diagram of a wafer with target points in one embodiment;

[0038] Figure 4 for Figure 3 A top view of a wafer sample in one corresponding embodiment;

[0039] Figure 5 This is a top view of a wafer sample after the formation of the first and second cracks in one embodiment.

[0040] Figure 6 for Figure 5 A cross-sectional view of the wafer sample along the AA direction after the dicing groove is formed in one of the corresponding embodiments;

[0041] Figure 7 This is a schematic diagram of the process of dicing a wafer sample along a dicing groove in one embodiment;

[0042] Figure 8 This is a flowchart illustrating a chip failure analysis method in one embodiment.

[0043] Explanation of reference numerals in the attached figures:

[0044] 100. Wafer; 102. Target point; 104. Silicon wafer alignment notch; 106. First fracture direction; 108. Second fracture direction; 110. First marking line; 112. Second marking line; 114. Third marking line; 116. Fourth marking line; 200. Wafer sample; 202. First edge; 204. Second edge; 206. Third edge; 208. Fourth edge; 302. First adhesive film; 304. First crack; 306. Second crack; 308. Second adhesive film; 310. Cutting groove. Detailed Implementation

[0045] To facilitate understanding of the embodiments of this application, a more comprehensive description of the embodiments of this application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the embodiments of this application. However, the embodiments of this application can be implemented in many different forms and are not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the embodiments of this application more thorough and complete.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of this application belong. The terminology used herein in the description of embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0047] In the description of the embodiments of this application, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the method or positional relationship shown in the drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0048] It is understood that the terms "first," "second," etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first crack may be referred to as a second crack, and similarly, a second crack may be referred to as a first crack. Both the first crack and the second crack are cracks formed on the wafer sample, but they are not the same crack.

[0049] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. In the description of this application, "several" means at least one, such as one, two, etc., unless otherwise explicitly specified.

[0050] A wafer with a wafer notch perpendicular or parallel to the wafer lattice direction is called a Type I wafer. A wafer with a wafer notch at other angles to the wafer lattice direction is called a Type II wafer. For a Type I wafer, the product lines on the wafer are parallel or perpendicular to the wafer lattice direction. In this case, the wafer lattice direction is the preferred wafer direction. Using a diamond tungsten steel pen, gently scratch the surface of the wafer near the target edge. Then, tear the wafer directly with both hands. The fracture surface is neatly broken along the preferred wafer direction (100°), i.e., the wafer direction. The wafer's physical properties can be directly analyzed using microscopic methods through the fracture surface. For a Type II wafer, the product lines on the wafer have a preset angle greater than 0 degrees and less than 90 degrees to the wafer lattice direction. Although the fracture surface is neatly broken along the preferred wafer direction, it has a preset angle with the product lines. Therefore, the wafer's physical properties cannot be directly analyzed using microscopic methods through the fracture surface. Taking a preset angle of 45 degrees as an example, the silicon wafer is first rotated by 45 degrees and then the wafer notch is defined to obtain a wafer with the preferred direction of (110). At this time, the product line direction and the preferred direction of the wafer have a 45-degree angle. The natural fracture surface obtained by wafer dicing will have a 45-degree angle with the product line direction, and it is impossible to directly perform physical property microscopic analysis on the product line at the fracture surface position through the fracture surface.

[0051] Figure 1 This is a schematic flowchart of a wafer dicing method in one embodiment. Figure 1 As shown, in this application, the method for wafer dicing includes:

[0052] S102, a wafer sample is provided, the wafer sample including a first surface having a target point and a second surface disposed opposite to the first surface.

[0053] Specifically, the wafer sample consists of a substrate and a device layer formed on the substrate. The surface of the substrate on which the device layer is formed is the first surface of the wafer sample, and the other surface of the substrate opposite to the first surface is the second surface. The target point is a pattern on the wafer that needs to be subjected to cross-sectional analysis, such as a pattern to be analyzed for failure. The target point can be any pattern used for fabricating semiconductor devices, such as a circle, rectangle, or triangle. The substrate can be undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. As an example, in this embodiment, the substrate material is selected as single-crystal silicon.

[0054] S104, forming a first crack and a second crack at the edge of the wafer sample, respectively.

[0055] First, locate the target point on the wafer sample. Then, form a first crack and a second crack on the edge of the wafer sample. The orthographic projection of the first crack and the second crack on the first surface is on the same straight line as the target point along a preset direction. The preset direction refers to the preset cross-sectional direction of the target point to be observed, that is, the direction of the wafer sample to be cleaved. For example, the preset direction is the same as the product line direction where the target point is located.

[0056] S106, a cutting groove along a preset direction is formed on the second surface.

[0057] Using the first and second cracks as alignment points, a cutting groove is formed on the second surface of the wafer along a preset direction. There is a preset distance between the bottom of the cutting groove and the first surface, that is, the depth of the cutting groove is less than the thickness of the wafer sample. The preset distance refers to the cutting depth of the wafer sample along the cutting groove without affecting the cross-section of the target point. The orthographic projection of the first and second cracks on the second surface is on the same straight line as the cutting groove.

[0058] S108, the wafer sample is cleaved along the cutting groove to obtain a cross-section of the target point along a preset direction.

[0059] Specifically, the wafer sample is cleaved along the dicing groove on the second surface to create a cross-section at the target point along the predetermined direction. This avoids the influence of the substrate's lattice orientation on the cleaving direction.

[0060] The aforementioned wafer dicing method includes providing a wafer sample, the wafer sample comprising a first surface having a target point and a second surface disposed opposite to the first surface; forming a first cleavage and a second cleavage at the edge of the wafer sample, wherein the orthographic projections of the first cleavage and the second cleavage on the first surface are on the same straight line as the target point along a preset direction; forming a dicing groove along the preset direction on the second surface, the bottom of the dicing groove being at a preset distance from the first surface, and the orthographic projections of the first cleavage and the second cleavage on the second surface being on the same straight line as the dicing groove; and dicing the wafer sample along the dicing groove to split the wafer sample along the preset direction, thereby obtaining a cross-section of the target point along the preset direction. This method can accurately obtain the cross-section of the target point along the preset direction, unaffected by the angle between the wafer crystal orientation and the preset direction.

[0061] Figure 2 This is a schematic diagram of the process for providing a wafer sample in one embodiment. Figure 3 This is a top view of a wafer with a target point in one embodiment. Figure 4 for Figure 3 A top view of a wafer sample in one corresponding embodiment. (See attached diagram.) Figure 2 , Figure 3 , Figure 4As shown, in one embodiment, the step of providing a wafer sample includes:

[0062] S202 provides wafers with target points.

[0063] like Figure 3 As shown, a wafer 100 with a target point 102 is provided. The silicon alignment notch 104 of the wafer 100 has a certain angle with the lattice direction of the wafer 100. The silicon alignment notch 104 extends along the Y direction. The preset direction of the target point is the X direction, which is perpendicular to the Y direction. The preferred fracture direction of the wafer 100 includes a first fracture direction 106 perpendicular to the lattice direction and a second fracture direction 108 parallel to the lattice direction. The angle between the direction of the silicon alignment notch 104 and the first fracture direction 106 is β, and the angle between the direction of the silicon alignment notch 104 and the second fracture direction 108 is α, where α + β = 90 degrees.

[0064] In one embodiment, the angle between the preset direction and the lattice direction of the wafer sample is greater than 0 degrees and less than 90 degrees, that is, β is greater than 0 degrees and less than 90 degrees, such as 30 degrees, 45 degrees, 60 degrees, etc.

[0065] S204, the wafer is broken to obtain a wafer sample including the target point.

[0066] refer to Figure 3 , Figure 4Before dicing the wafer, the wafer 100 is first placed under an optical microscope to determine the location of the target point 102 on the wafer 100, and the location of the target point 102 is marked on the wafer 100. A marker can be used to draw a circle around the target point 102 to quickly locate the target point 102 in subsequent steps. Next, lines are drawn around the target point 102 along the first fracture direction 106 and the second fracture direction 108, respectively, to obtain a first marking line 110, a second marking line 112, a third marking line 114, and a fourth marking line 116. The first marking line 110 and the third marking line 114 are parallel to the first fracture direction 106, and the second marking line 112 and the fourth marking line 116 are parallel to the second fracture direction 108. Then, a diamond tungsten carbide pen is used to break the wafer 100 along the first marking line 110, the second marking line 112, the third marking line 114, and the fourth marking line 116 to obtain a larger sample including the target point 102, which serves as the wafer sample 200. The first side 202 of the wafer sample 200 is obtained along the first marking line 110, the second side 204 along the second marking line 112, the third side 206 along the third marking line 114, and the fourth side 208 along the fourth marking line 116. To facilitate subsequent dicing of the wafer sample 200 along the dicing groove, in the X direction, the distance L1 between the target point 102 and the first side 202 is equal to the distance L2 between the target point 102 and the third side 206.

[0067] In one embodiment, forming a first cleavage and a second cleavage at the edge of the wafer sample 200 includes forming a first cleavage and a second cleavage extending toward a target point on a first surface, wherein the first cleavage and the second cleavage at least partially penetrate the wafer sample 200. The first cleavage and the second cleavage that at least partially penetrate the wafer sample 200 can serve as alignment points for subsequently forming a dicing groove on a second surface, thereby improving the accuracy of dicing.

[0068] In one embodiment, the first and second cracks completely penetrate the wafer sample 200.

[0069] In one embodiment, the step of forming a first rift and a second rift extending toward a target point on a first surface includes: forming a first rift and a second rift along a preset direction on opposite sides of the target point using a first cutting device; the step of forming a cutting groove along a preset direction on a second surface includes: forming a cutting groove on the second surface using a second cutting device with the first rift and the second rift as endpoints.

[0070] Figure 5 This is a top view of a wafer sample after the formation of the first and second cracks in one embodiment. Figure 6 for Figure 5A cross-sectional view of the wafer sample along the AA direction after the dicing groove is formed in one corresponding embodiment. First, as... Figure 5 As shown, the second surface of the wafer sample 200 is attached to the first adhesive film 302 corresponding to the first dicing device. Then, taking advantage of the first dicing device's ability to precisely control the dicing position and depth, a first slit 304 is formed at the edge of the wafer sample 200 by cutting along the first adhesive film 302 near the wafer sample 200 towards the first side 202 of the target point 102 in a preset direction. A second slit 306 is formed at the edge of the wafer sample 200 by cutting along the first adhesive film 302 near the wafer sample 200 towards the third side 206 of the target point 102. Next, as... Figure 6 As shown, the first adhesive film 302 on the second surface of the wafer sample 200 is removed, and then the first surface of the wafer sample 200 is attached to the second adhesive film 308 corresponding to the second dicing device. Taking the first crack 304 and the second crack 306 as reference points, the second surface of the wafer sample 200 is diced by utilizing the characteristic that the second dicing device can precisely control the dicing position and dicing depth, forming a dicing groove 310 along a preset direction. There is a preset distance D1 between the bottom of the dicing groove 310 and the first surface. Without affecting the cross-section of the target point, the smaller the preset distance D1, the better the dicing effect and the easier it is to obtain a high-precision cross-section.

[0071] In one embodiment, along the Y direction, the width of the cutting groove 310 is smaller than the width of the first crack 304, and the width of the cutting groove 310 is smaller than the width of the second crack 306. The accuracy of the obtained cross-section can be controlled by the accuracy of the cutting groove 310.

[0072] In one embodiment, along the Y direction, the width of the cutting groove 310 is greater than the width of the first rift 304, and the width of the cutting groove 310 is greater than the width of the second rift 306. The accuracy of the obtained cross-section can be controlled by the accuracy of the first rift 304 and the second rift 306.

[0073] In one embodiment, the first crack 304 is the initial cracking direction along the Y direction. The width of the first crack 304 is smaller than the width of the second crack 306, which can shrink the splitting direction of the fragment and obtain a cross-section with higher accuracy.

[0074] In one embodiment, the thickness of the first adhesive film 302 is 100 micrometers. In other embodiments, the thickness of the first adhesive film 302 can be selected as needed, as long as the thickness of the first adhesive film 302 does not affect the performance of the first crack 304 and the second crack 306.

[0075] In one embodiment, the thickness of the second adhesive film 308 is 100 micrometers. In other embodiments, the thickness of the second adhesive film 308 can be selected as needed, as long as the thickness of the second adhesive film 308 does not affect the formation of the cutting groove.

[0076] In one embodiment, the second adhesive film 308 and the first adhesive film 302 are the same adhesive film. In another embodiment, the second adhesive film 308 and the first adhesive film 302 are different adhesive films.

[0077] In one embodiment, the length L3 of the first rift 304 in the preset direction is a first preset length, and the length L4 of the second rift 306 in the preset direction is a second preset length.

[0078] In one embodiment, both the first preset length and the second preset length are preset values, such as 1 mm or 2 mm. If the first crack 304 and the second crack 306 do not affect the cross-section of the target point 102 along the preset direction, the values ​​of the first preset length and the second preset length can be set according to actual needs.

[0079] In one embodiment, in a preset direction, the distance between the target point 102 and the first crack 304 is equal to the distance between the target point 102 and the second crack 306. This setting can improve the cracking accuracy.

[0080] In one embodiment, both the first cutting device and the second cutting device are laser cutting devices. The wafer sample 200, with the side without adhesive film facing upwards, is placed on the laser cutting device, and the parameters of the laser cutting device are set. These parameters may include the depth of the dots, energy, and the wavelength of the laser. For example, when forming the first crack 304 and the second crack 306, after locating the target point 102 using a high-powered microscope on the laser cutting device, the width and horizontality of each dot can be adjusted. Each dot is perpendicular to the edge of the wafer sample, resulting in the first crack 304 and the second crack 306 along a preset direction. For example, multiple dots are made from near the target point 102 toward the edge of the wafer sample 200 to form a first crack 304 and a second crack 306. The width of the first crack 304 and the second crack 306 along the Y direction gradually increases from the target point 102 to the edge of the wafer sample 200 to ensure that the first crack 304 and the second crack 306 can serve as calibration points when forming the dicing groove, making the dicing position more accurate and ensuring that the wafer sample can be diced along the straight line where the first crack 304 and the second crack 306 are located during dicing.

[0081] In one embodiment, the ratio of the preset distance to the wafer sample thickness is less than 1 and not less than 0.1, such as 0.2, 0.3, 0.4, 0.5, 0.7, 0.9, etc. For example, the wafer sample 200 has a thickness of 780 micrometers and a dicing groove depth of 680 micrometers, meaning the preset distance is 100 micrometers. In this case, after removing the wafer sample from the second adhesive film 308, a small amount of external force can cause the wafer sample 200 to fracture along the dicing groove 310 on the second surface, resulting in a fracture surface with the fracture direction along the preset direction, unaffected by the wafer sample's lattice orientation. Compared to traditional methods of obtaining a cross-section of the target point 102 along the preset direction through grinding or ion beam cutting, the method of obtaining the fracture surface of the target point in this application is characterized by low cost and short time.

[0082] Figure 7 This is a schematic diagram of the process of dicing a wafer sample along a dicing groove in one embodiment, as shown below. Figure 7 As shown, in one embodiment, the step of dicing the wafer sample along the dicing groove includes:

[0083] S302, provides ejector pins.

[0084] S304, the ejector pin is placed in the cutting groove, and there is a certain distance between the ejector pin and the orthographic projection of the target point in the cutting groove.

[0085] S306 applies force to the wafer sample and the ejector pin to cause the wafer sample to crack along the dicing groove.

[0086] Specifically, a shim is provided, which can be placed vertically under an optical microscope. Then, a wafer sample 200 is placed above the shim, with the surface containing the target point 102 facing upwards. The shim is positioned close to the target point and aligned with the dicing groove 310, with a certain distance between the shim and the target point's orthographic projection within the dicing groove. Preferably, the shim is aligned with the dicing groove 310 near the edge of the wafer sample 200. Because the dicing groove 310 is quite deep, it is easier for the shim to apply force, thus improving the dicing effect.

[0087] In one embodiment, the length of the target point 102 is not less than 10 micrometers and not more than 1 millimeter, that is, the target point 102 is at the micrometer level.

[0088] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0089] Figure 8 This is a flowchart illustrating a chip failure analysis method in one embodiment, as shown below. Figure 8 As shown, this application also provides a method for chip failure analysis, including:

[0090] S402, using the abnormal chip region as the target point, the wafer dicing method described in any of the above methods is used to obtain the cross-section of the abnormal chip region along a preset direction.

[0091] S404 performs failure analysis on the cross-section of the abnormal chip area.

[0092] The aforementioned chip failure analysis method includes providing a wafer sample, the wafer sample comprising a first surface having an abnormal chip region and a second surface disposed opposite to the first surface; forming a first crack and a second crack at the edge of the wafer sample, wherein the orthographic projections of the first crack and the second crack on the first surface are on the same straight line as the abnormal chip region along a preset direction; forming a dicing groove along the preset direction on the second surface, the bottom of the dicing groove being at a preset distance from the first surface, and the orthographic projections of the first crack and the second crack on the second surface being on the same straight line as the dicing groove; and dicing the wafer sample along the dicing groove to split the wafer sample along the preset direction, thereby obtaining a cross-section of the abnormal chip region along the preset direction. This method can accurately obtain the cross-section of the abnormal chip region along the preset direction, unaffected by the angle between the wafer crystal orientation and the preset direction.

[0093] This application also provides a computer device including a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the steps of the wafer dicing method as described in any of the preceding claims.

[0094] This application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the chip failure analysis method described above.

[0095] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0096] The above-described embodiments are merely illustrative of several implementation methods of the embodiments of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the embodiments of this application, and these all fall within the protection scope of the embodiments of this application. Therefore, the protection scope of the patent for the embodiments of this application should be determined by the appended claims.

Claims

1. A method for wafer dicing, characterized in that, include: A wafer sample is provided, the wafer sample including a first surface having a target point and a second surface disposed opposite to the first surface; A first crack and a second crack are formed at the edge of the wafer sample, and the orthographic projections of the first crack and the second crack onto the first surface are on the same straight line as the target point along a preset direction. A cutting groove is formed on the second surface along the preset direction, the bottom of the cutting groove and the first surface are at a preset distance, and the orthographic projections of the first crack and the second crack on the second surface are on the same straight line as the cutting groove. The wafer sample is cleaved along the cutting groove so that the wafer sample is cleaved along the preset direction to obtain a cross section of the target point along the preset direction; The angle between the preset direction and the lattice direction of the wafer sample is greater than 0 degrees and less than 90 degrees.

2. The method according to claim 1, characterized in that, The step of forming a first crack and a second crack at the edge of the wafer sample includes: A first crack and a second crack extending toward a target point are formed on the first surface, and the first crack and the second crack at least partially penetrate the wafer sample.

3. The method according to claim 2, characterized in that, The step of forming the first crack and the second crack extending toward the target point on the first surface includes: The first cutting device forms a first slit and a second slit along a preset direction on opposite sides of the target point; The step of forming a cutting groove along the preset direction on the second surface includes: Using the first crack and the second crack as endpoints, a cutting groove is formed on the second surface by a second cutting device.

4. The method according to claim 3, characterized in that, Both the first cutting device and the second cutting device are laser cutting devices.

5. The method according to claim 1, characterized in that, The lengths of the first crack and the second crack in the preset direction are the first preset length and the second preset length, respectively.

6. The method according to claim 5, characterized in that, Both the first preset length and the second preset length are preset values.

7. The method according to claim 1, characterized in that, In a preset direction, the distance between the target point and the first crack is equal to the distance between the target point and the second crack.

8. The method according to claim 1, characterized in that, The ratio of the preset distance to the thickness of the wafer sample is less than 1 and not less than 0.

1.

9. The method according to claim 1, characterized in that, The step of cleaving the wafer sample along the dicing groove includes: Provide a thimble; The ejector pin is placed in the cutting groove, and there is a certain distance between the ejector pin and the orthographic projection of the target point in the cutting groove; Force is applied to the wafer sample and the ejector pin to cause the wafer sample to crack along the dicing groove.

10. The method according to claim 1, characterized in that, The step of providing wafer samples includes: Provide wafers with target points; The wafer is shredded to obtain a wafer sample including the target point.

11. The method according to claim 1, characterized in that, The length of the target point is not less than 10 micrometers.

12. A method for chip failure analysis, characterized in that, include: Using the abnormal chip region as the target point, the wafer dicing method as described in any one of claims 1-11 is used to obtain the cross-section of the abnormal chip region along a preset direction. Failure analysis was performed on the cross-section of the abnormal chip region.

Images