Method and system for accelerating verification of device attribute memory
By separately modeling the Forward and Merge features that can accelerate Device memory, and using the Forward and Merge models for verification, the problem of verification methods relying on microarchitecture familiarity in existing technologies is solved, achieving fast and accurate verification and improving debugging efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUANGDONG STARFIVE TECH LTD
- Filing Date
- 2022-11-28
- Publication Date
- 2026-05-15
AI Technical Summary
There is a lack of effective methods in the existing technology to verify the correctness of Forward and Merge operations that can accelerate Device memory, and the verification process needs to be tightly coupled with the microarchitecture, so only people who are very familiar with the microarchitecture can guarantee the correctness.
By separately modeling the Forward and Merge characteristics of Device address attributes, the Forward model monitors query information on the DUT pipeline, and the Merge model monitors write data requests. The address and size information of each unit in the DUT are captured and compared. If they are different, an error is reported, thus realizing the verification of accelerating Device memory access.
It can quickly and effectively determine whether the forward and merge logic of the DUT is correct, accurately report the erroneous logic and time point, greatly shorten the debugging time and improve the debugging efficiency.
Smart Images
Figure CN116089182B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of CPU technology, and specifically to a method and system for accelerating the verification of Device attribute memory. Background Technology
[0002] Current CPU architectures, including ARM and RISC-CV architectures, support memory types categorized as general-purpose memory and device memory. For programs accessing general-purpose memory, both the CPU and compiler can optimize performance using operations such as reorder, forward, and merge. However, device memory access typically cannot be reordered, forwarded, or merged. To improve the speed of accessing this type of memory, both ARM and RISC-CV architectures have subdivided device memory, one type being accelerated device memory. Access to this type of memory allows for forward and merge operations. This verification method verifies the correctness of the forward and merge operations for this type of access. Summary of the Invention
[0003] To address the shortcomings of existing technologies, this invention discloses a method and system for accelerating the verification of Device attribute memory. This method addresses the problem that there is currently no effective way to verify Forward and Merge operations that can accelerate Device memory access. Furthermore, this verification must be tightly coupled with the microarchitecture, requiring a thorough understanding of the microarchitecture to ensure its correctness.
[0004] This invention is achieved through the following technical solution:
[0005] In a first aspect, the present invention provides a method for accelerating the verification of Device attribute memory. The method models the Forward and Merge characteristics of Device address attributes separately. During verification, the Forward model monitors query information on the DUT pipeline, captures and compares the address and size information of each unit in the DUT, and reports an error if they are different. The Merge model monitors new write data requests in the DUT, captures and compares the address and size information of each unit in the DUT, and reports an error if they are different.
[0006] Furthermore, in the method, the Forward model monitors query information from access instructions on the DUT pipeline. At the same time, the Forward model captures the address and size information of each unit in the DUT, and determines whether the query information can be forwarded from a certain unit based on this unit information. Finally, the model query result is compared with the DUT query result. If they are different, an error is reported.
[0007] Furthermore, in the method, the Merge model monitors new write data requests in the DUT, and the address attribute of the request is an acceleration Device attribute. At the same time, the Merge model captures the address and size information of each cell in the DUT, and determines whether the new request hits a certain cell based on this cell information. If it hits, it means that the request can be merged into the original cell. Finally, the model query result is compared with the DUT query result. If they are different, an error is reported.
[0008] Furthermore, the specific implementation of the Forward model in the method includes the following steps:
[0009] Based on the write address and write data size of each cell in the DUT, the Forward model creates an array from the minimum write address to the maximum write address for each cell;
[0010] Query information for access commands on the DUT pipeline;
[0011] If the access address attribute of the current query information is an accelerated Device attribute, then the access instruction can forward data from the DUT. The forward model traverses all the cells in the model according to the read address and data size, compares the read address range with the write address range of each cell, and if there is an overlap, it means that the overlapping address part can be forwarded.
[0012] The forward result generated by each cell includes whether a forward can be made from the current cell, the forward data, and which bytes can be forwarded. This information is compared with the forward result of the DUT. If they are different, an error is reported.
[0013] Furthermore, in the method, if multiple units can be forwarded simultaneously, the forwarding model performs a priority judgment. Based on the principle that newer units have higher priority, the last data that can be forwarded is obtained, and this data is compared with the DUT data. If they are different, an error is reported.
[0014] Furthermore, in the method, the query information includes the read address, the read data size, and the access address attribute information.
[0015] Furthermore, in the method, the array from the minimum write address to the maximum write address represents the address range that the current unit needs to write, with the smallest unit being 1 Byte.
[0016] Furthermore, the specific process of the Merge model in the method includes the following steps:
[0017] Monitor new write transfer requests in the DUT and determine whether they are speed-upable Device attributes based on address attributes;
[0018] If it is not a speed-up Device property, the current process ends;
[0019] If the Device property can be accelerated, then based on the address of the current write transfer and the size of the write data, traverse each cell in the model. If there is a cell whose address range overlaps with the address range of the current write transfer and does not exceed 128 bits, it means that the current write transfer can be merged into that cell.
[0020] If the current cell can be merged, then the merge_vld value of that cell is set to 1; otherwise, it is set to 0.
[0021] Monitor the merge_vld information of the DUT and compare it with the merge_vld of the Merge model. If they are inconsistent, report an error.
[0022] Secondly, the present invention provides a verification system for accelerating Device attribute memory, the system being used to implement the verification method for accelerating Device attribute memory described in the first aspect, including a Device Under Test (DUT), a Forward model, a Merge model, and a comparator.
[0023] Furthermore, the DUT is a module that stores write transfers with memory attributes that can accelerate Device attributes. If a new write request with an accelerated Device attribute is found in a unit with the same address in the DUT, the new write request is merged into that unit. The DUT provides data for read requests with the same address, so that the read request does not need to read data from memory.
[0024] The beneficial effects of this invention are as follows:
[0025] This invention verifies the read and write transmission of Device address attributes that can be accelerated. These attributes have the characteristics of forwarding and merging. This invention models the characteristics of forwarding and merging separately, which can quickly and effectively determine whether the forwarding and merging logic of the DUT is correct, accurately report the logic and timing of errors, greatly shorten the debugging time, and improve the debugging efficiency. Attached Figure Description
[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0027] Figure 1 This is an overall structural diagram of the verification method according to an embodiment of the present invention;
[0028] Figure 2 This is a structural diagram of the Forward model according to an embodiment of the present invention;
[0029] Figure 3 This is a flowchart of the Merge model in an embodiment of the present invention. Detailed Implementation
[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0031] Example 1
[0032] Reference Figure 1 As shown, this embodiment provides a verification system for accelerating Device attribute memory, including a Device Under Test (DUT), a Forward model, a Merge model, and a comparator.
[0033] In this embodiment, the DUT refers to a module that stores write transfers with memory attributes that can accelerate Device attributes. Currently, it is designed to store 8 such write transfers simultaneously, and the data width of each unit is 128 bits.
[0034] In this embodiment, a new write request that can accelerate Device attribute write requests can be merged into a cell if a cell with the same address is found in the DUT.
[0035] In this embodiment, the DUT can provide data for read requests with the same address, so that the read request does not need to read data from memory. This operation is called Forward.
[0036] In this embodiment, the Forward model in the verification system monitors query information on the DUT pipeline, which originates from access commands. Simultaneously, the Forward model captures the address and size information of each cell in the DUT, determines whether the query information can be forwarded from a specific cell based on this information, and finally compares the model's query result with the DUT's query result. If they differ, an error is reported.
[0037] In this embodiment, the Merge model in the verification system monitors new write data requests in the DUT, and the address attribute of the request is an acceleration Device attribute. Simultaneously, the Merge model captures the address and size information of each cell in the DUT, and determines whether the new request hits a specific cell based on this information. If it does, it means the request can be merged into an existing cell. Finally, the model's query result is compared with the DUT's query result; if they differ, an error is reported.
[0038] Example 2
[0039] This embodiment provides a method for accelerating the verification of Device attribute memory. The method models the Forward and Merge characteristics of Device address attributes separately. During verification, the Forward model monitors query information on the DUT pipeline, captures and compares the address and size information of each unit in the DUT, and reports an error if they are different. The Merge model monitors new write data requests in the DUT, captures and compares the address and size information of each unit in the DUT, and reports an error if they are different.
[0040] When this embodiment is replaced, it can accelerate the read access of Device attributes. The read data can be compared after the CPU obtains the data. However, this method can only determine whether the data is correct, but cannot determine whether the data was forwarded from this DUT.
[0041] When this embodiment is replaced, write access to Device attributes can be accelerated. After the stimulus is completed, it is possible to compare whether the data DUT in the final memory is consistent with the memory model. However, at this time, it is impossible to determine which data was written after Merge.
[0042] This embodiment verifies the read and write transmission of the Device address attribute, which can accelerate the Device address attribute. The accelerated Device address attribute has the characteristics of forwarding and merging. This verification method models the characteristics of forwarding and merging separately, which can quickly and effectively determine whether the forwarding and merging logic of the DUT is correct.
[0043] Example 3
[0044] At the implementation level, this embodiment provides a specific implementation of the Forward model, such as... Figure 2 As shown:
[0045] In this embodiment, based on the write address and write data size of each cell in the DUT, the Forward model creates an array from the minimum write address to the maximum write address for each cell, representing the address range that the current cell needs to write, with the smallest unit being 1 byte.
[0046] This embodiment monitors query information for access commands on the DUT pipeline, including read address, read data size, access address attributes, and other information.
[0047] In this embodiment, if the access address attribute of the current query information is an acceleration Device attribute, the access instruction can forward data from the DUT. The forward model traverses all the units in the model according to the read address and the data size. Specifically, the traversal method is to compare the read address range with the write address range of each unit. If there is an overlap, it means that the overlapping address part can be forwarded.
[0048] In this embodiment, the forward result generated by each unit includes whether it is possible to forward from the current unit, the forward data, and which bytes can be forwarded. This information is compared with the forward result of the DUT. If they are different, an error is reported.
[0049] In this embodiment, if there are multiple units that can be forwarded, the forwarding model will determine the priority. Based on the principle that the newer the unit, the higher the priority, the final data that can be forwarded will be obtained and compared with the DUT data. If they are different, an error will be reported.
[0050] Example 4
[0051] At the implementation level, this embodiment provides a specific process for the Merge model, such as... Figure 3 As shown:
[0052] This embodiment monitors new write transfer requests in the DUT and determines whether they are speed-upable Device attributes based on address attributes.
[0053] In this embodiment, if it is not an accelerable Device attribute, the current process ends; if it is an accelerable Device attribute, then according to the address of the current write transfer and the size of the write data, each unit in the model is traversed. If there is a unit whose address range overlaps with the address range of the current write transfer and does not exceed 128 bits, it means that the current write transfer can be merged into that unit.
[0054] In this embodiment, if the current unit can be merged, the merge_vld of that unit is set to 1; otherwise, it is set to 0.
[0055] This embodiment monitors the merge_vld information of the DUT and compares it with the merge_vld of the Merge model. If they are inconsistent, an error is reported.
[0056] In summary, this invention verifies the read and write transmission of Device address attributes that can be accelerated. These attributes have both forward and merge capabilities. This invention models the forward and merge capabilities separately, enabling rapid and effective determination of the correctness of the DUT's forward and merge logic, accurately reporting the erroneous logic and timing, significantly shortening debugging time and improving debugging efficiency.
[0057] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for accelerating the verification of Device attribute memory, characterized in that, The method separately models the Forward and Merge characteristics of Device address attributes and verifies that it can accelerate the read and write transmission of Device address attributes. During verification, the Forward model monitors the query information on the DUT pipeline, captures the address and size information of each unit in the DUT, and compares them. If they are different, an error is reported. The Merge model monitors new write data requests in the DUT, captures the address and size information of each unit in the DUT, and compares them. If they are different, an error is reported. The forward model monitors query information from access instructions on the DUT pipeline. At the same time, the forward model captures the address and size information of each cell in the DUT and determines whether the query information can be forwarded from a certain cell based on this cell information. Finally, the model query result is compared with the DUT query result. If they are different, an error is reported. The Merge model monitors new write data requests in the DUT, and the request address attribute is an acceleration Device attribute. At the same time, the Merge model captures the address and size information of each cell in the DUT, and determines whether the new request hits a certain cell based on this cell information. If it hits, it means that the request can be merged into the original cell. Finally, the model query results are compared with the DUT query results. If they are different, an error is reported. The specific implementation of the Forward model includes the following steps: Based on the write address and write data size of each cell in the DUT, the Forward model creates an array from the minimum write address to the maximum write address for each cell; Query information for access commands on the DUT pipeline; If the access address attribute of the current query information is an accelerated Device attribute, then the access instruction can forward data from the DUT. The forward model traverses all cells in the model according to the read address and data size, compares the read address range with the write address range of each cell, and if there is an overlap, it means that the overlapping address part can be forwarded. The forward result generated by each cell includes whether a forward can be made from the current cell, the forward data, and which bytes can be forwarded. This information is compared with the forward result of the DUT. If they are different, an error is reported.
2. The method for accelerating Device attribute memory verification according to claim 1, characterized in that, In the method, if multiple units can be forwarded simultaneously, the forwarding model performs a priority judgment. Based on the principle that newer units have higher priority, the last data that can be forwarded is obtained, and this data is compared with the DUT data. If they are different, an error is reported.
3. The method for accelerating Device attribute memory verification according to claim 1, characterized in that, In the method, the query information includes the read address, the read data size, and the access address attribute information.
4. The method for accelerating Device attribute memory verification according to claim 2, characterized in that, In the method, the array from the minimum write address to the maximum write address represents the address range that the current unit needs to write, and the smallest unit is 1 Byte.
5. The method for accelerating Device attribute memory verification according to claim 1, characterized in that, The specific process of the Merge model in the method includes the following steps: Monitor new write transfer requests in the DUT and determine whether they are speed-upable Device attributes based on address attributes; If it is not a speed-up Device property, the current process ends; If the Device property can be accelerated, then based on the address of the current write transfer and the size of the write data, traverse each cell in the model. If there is a cell whose address range overlaps with the address range of the current write transfer and does not exceed 128 bits, it means that the current write transfer can be merged into that cell. If the current cell can be merged, then the merge_vld value of that cell is set to 1; otherwise, it is set to 0. Monitor the merge_vld information of the DUT and compare it with the merge_vld of the Merge model. If they are inconsistent, report an error.
6. A system for accelerating the verification of Device attribute memory, the system being used to implement the method for accelerating the verification of Device attribute memory as described in any one of claims 1-5, characterized in that, This includes the DUT, the forward model, the merge model, and the comparator.
7. The verification system for device attribute memory acceleration according to claim 6, characterized in that, The DUT is a module that stores memory attributes that can accelerate device write transfers. If a new write request with the accelerated device attribute is found in a unit with the same address in the DUT, the new write request is merged into that unit. The DUT provides data for read requests with the same address, so that the read request does not need to read data from memory.