A Deep Learning-Based Method for Predicting DC Characteristics of FINFET Devices

Abstract

A deep learning-based method for predicting the DC characteristics of FINFET devices is proposed. This method utilizes the ADS software and calls the BSIM-CMG module to construct a schematic diagram for testing the electrical characteristics of FINFET devices. The batch simulation module built into ADS extracts the electrical characteristics of FINFET devices of different sizes. The dimensions affecting device characteristics and the device's gate voltage (VGS) are used as input features, and the device's electrical characteristics are used as output results to construct a dataset. The constructed dataset is then proportionally divided into training, testing, and prediction sets. A device electrical characteristic prediction model based on a deep learning neural network is constructed. This model is trained using the dataset, and the trained model is used to predict the electrical characteristics of the devices. This invention solves the problems of high learning costs, long processing times, and low efficiency of simulation circuit simulator software; and significantly reduces the operational threshold through deep learning.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor simulation technology, and specifically relates to a method for predicting the DC characteristics of FINFET devices based on deep learning. Background Technology

[0002] When the channel length of a metal-oxide-semiconductor field-effect transistor (MOSFET) is shrunk to below 20 nanometers, many problems are encountered, especially as the channel length becomes smaller, the distance between the source and drain becomes closer, and the oxide under the gate becomes thinner, resulting in leakage current.

[0003] The introduction of FinFETs solved the problems of subthreshold leakage and poor short-channel electrostatic discharge performance. However, to better utilize FinFETs, their electrical characteristics need to be obtained. Traditional solutions rely on simulation circuit simulator software. Since simulator software is derived from actual test data from device manufacturers, it inherently contains errors, which fluctuate depending on the software chosen by the designer. Simulation circuit simulator software has a high learning curve, requiring designers to have a deep understanding of the internal structure of semiconductor devices. Furthermore, simulation circuit simulator software is typically large and complex, requiring designers to carefully evaluate the degree of matching between various parameters and actual devices. The variety and complexity of parameter settings create a high learning curve for designers. Finally, simulation using simulation circuit simulator software is time-consuming.

[0004] Overall, the acquisition of the electrical characteristics of FinFETs is currently mainly based on simulation using SPICE software, which is still relatively time-consuming compared to deep learning-based artificial intelligence solutions. It requires users to have a deep understanding of semiconductor device physics and its prerequisite knowledge, and may even require guidance from industry professionals. Summary of the Invention

[0005] To overcome the shortcomings of the prior art, the present invention aims to provide a deep learning-based method for predicting the DC characteristics of FINFET devices. This method constructs a high-speed deep learning neural network model by collecting data from simulation circuit simulator software in batches, thereby directly and quickly obtaining the circuit characteristics required by the designer. This solves the problems of high learning cost, long time consumption, and low efficiency of simulation circuit simulator software, and significantly reduces the operating threshold through deep learning.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A deep learning-based method for predicting the DC characteristics of FINFET devices includes the following steps:

[0008] Step 1: Using the BSIM-CMG module in ADS software, construct a schematic diagram for testing the electrical characteristics of FINFET devices. Use the batch simulation module built into ADS software to extract the electrical characteristics of FINFET devices of different sizes. Use the dimensions affecting the device characteristics and the gate voltage VGS of the device as input features, and the electrical characteristics of the device as the output results to complete the construction of the dataset. The device electrical characteristics refer to the curve of leakage current versus leakage voltage, i.e., the leakage current-leakage voltage curve.

[0009] Step 2: Divide the dataset constructed in Step 1 into training set, test set and prediction set according to the proportions;

[0010] Step 3: Construct a device electrical characteristic prediction model based on deep learning neural networks;

[0011] Step 4: Train the device electrical characteristic prediction model using the dataset, and use the trained device electrical characteristic prediction model to predict the device electrical characteristics.

[0012] In one embodiment, in step 1, the dimensions affecting device characteristics are the device gate oxide thickness t_tfin, the device channel length t_l, the device interpolation index t_nf, and the number of interpolation fins per finger t_nfin. By progressively changing the four variables t_tfin, t_l, t_nf, and t_nfin, leakage current-leakage voltage curves of devices of different sizes with gate voltage VGS at several different values ​​in the range of 0 to Vn are simulated. The horizontal axis of the curve is the leakage voltage, the vertical axis is the leakage current, and Vn is the set device gate voltage value.

[0013] In one embodiment, a batch simulation simulator component is invoked in ADS software, and five loops are used to sequentially change the following parameters from the inside out: device gate voltage VGS, number of interpolation fins per finger t_nfin, interpolation index t_nf, gate oxide thickness t_tfin, and channel length t_l; this is repeated N times in total. Each time, leakage current data of the device under a set of different leakage voltages is obtained, where the set of different leakage voltages is 0 to Vn, with a step size of m; based on the (Vn / m)+1 points obtained in each set, a plot is generated with leakage voltage as the x-axis and leakage current as the y-axis. The leakage current-leakage voltage curves are generated, and finally, the M points obtained from the simulation are divided into N groups of leakage current-leakage voltage relationships; where M=N×[(Vn / m)+1]; N=k1×k2×k3×k4×k5, k1 is the number of values ​​when the device gate voltage VGS changes, k2 is the number of values ​​when the number of interpolation fins t_nfin changes, k3 is the number of values ​​when the device interpolation index t_nf changes, k4 is the number of values ​​when the device gate oxide thickness t_tfin changes, and k5 is the number of values ​​when the device channel length t_l changes.

[0014] Each set of device gate voltage VGS, device interpolation fin number t_nfin, device interpolation index t_nf, device gate oxide thickness t_tfin, and device channel length t_l corresponds to a set of leakage current-leakage voltage relationships; that is, each set of device gate voltage VGS, device interpolation fin number t_nfin, device interpolation index t_nf, device gate oxide thickness t_tfin, and device channel length t_l is used as input, and each corresponding set of leakage current-leakage voltage relationships, i.e., (Vn / m) + 1 leakage voltage-leakage current points, is used as output.

[0015] In one embodiment, N = 15000, Vn = 1.5V, m = 0.05V; the gate voltage VGS changes in the range of 0V to 1.5V with a step size of 0.3V, i.e., k1 = 6; the number of interpolation fins t_nfin changes in the range of 1 to 5 with a step size of 1, i.e., k2 = 5; the device interpolation index t_nf changes in the range of 1 to 5 with a step size of 1, i.e., k3 = 5; the device gate oxide thickness t_tfin changes in the range of 1nm to 10nm with a step size of 1nm, i.e., k4 = 10; and the device channel length t_l changes in the range of 2nm to 20nm with a step size of 2nm, i.e., k5 = 10.

[0016] In one embodiment, the device electrical characteristic prediction model includes an upsampling module and a prediction module; the upsampling module includes a first transposed convolutional layer, a second transposed convolutional layer, a convolutional layer, a max pooling layer, and a single-kernel convolutional layer;

[0017] The input to the prediction module is the output of the upsampling network module, which consists of a dual-channel fully connected layer. The first fully connected layer outputs 0 to Vn with a step size of m, and (Vn / m)+1 significant digits of the current under the leakage voltage. The second fully connected layer is used as a classification layer, which is connected to the SOFTMAX function to classify and obtain the current order. The two are combined to obtain the final current prediction value.

[0018] In one embodiment, the parameters of the first transposed convolutional layer are (1, 256, 3, 3), the parameters of the second transposed convolutional layer are (256, 256, 3, 3), the parameters of the convolutional layer are (256, 256, 3, 1), and the parameters of the single-kernel convolutional layer are (256, 64, 1, 1); the upsampling module finally obtains a set of one-dimensional 1*1344 feature vectors.

[0019] In one embodiment, step 4 involves using L1 loss (mean absolute difference) as the loss function to backpropagate the loss and change the network weights.

[0020] In one embodiment, step 4 involves feeding the prediction set into the device electrical characteristic prediction model to obtain the predicted current value, plotting the predicted leakage current-leakage voltage curve, and comparing it with the actual leakage current-leakage voltage curve.

[0021] Compared with existing technologies, this invention can directly, quickly and accurately predict the DC characteristics of FINFET devices, solving the problem that traditional simulation circuit simulator software requires complicated parameter settings and cumbersome processes to predict the DC characteristics of FINFET devices. It also significantly reduces time costs and learning costs for using simulation circuit simulator software. Attached Figure Description

[0022] Figure 1 This is a schematic diagram for testing the electrical characteristics of a FINFET device.

[0023] Figure 2 This is a schematic diagram of an upsampling network module.

[0024] Figure 3 This is a schematic diagram of the prediction network module.

[0025] Figure 4 This is the network training loss monitoring graph.

[0026] Figure 5 This is the network training loss monitoring graph.

[0027] Figure 6 This is a diagram showing the network prediction results. Detailed Implementation

[0028] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings and examples.

[0029] This invention presents a deep learning-based method for predicting the DC characteristics, or key electrical characteristics, of FINFET devices. It extracts the electrical characteristics of FINFET devices of different sizes using ADS (Advanced Design System) software and uses these characteristics, along with the device dimensions, as a database to construct a deep learning model. The specific steps are as follows:

[0030] Step 1: Use the BSIM-CMG module in ADS software to construct a schematic diagram for testing the electrical characteristics of FINFET devices. Use the batch simulation module built into ADS software to extract the electrical characteristics of FINFET devices of different sizes. Use the size that affects the device characteristics and the gate voltage VGS of the device as input features, and the electrical characteristics of the device as output results to complete the construction of the dataset.

[0031] In this invention, the electrical characteristics of the device refer to the curve of leakage current versus leakage voltage, i.e., the leakage current-leakage voltage curve, which directly reflects the DC characteristics of the FINFET device.

[0032] In FINFET devices, the dimensions that primarily affect their characteristics are the gate oxide thickness t_tfin, the channel length t_l, the interpolation index t_nf, and the number of fins per interpolation finger t_nfin. The electrical characteristics of devices with different dimensions are extracted using the FINFET NMOS module built into the ADS software, such as... Figure 1 As shown, the BSIM-CMG version used is 106.1. The variables are set as follows: drain voltage VDS, gate voltage VGS, device gate oxide thickness t_tfin, device channel length t_l, device fin height t_hfin, device interpolation index t_nf, and number of interpolation fins per finger t_nfin, where the last five variables are input features. This embodiment of the invention simulates the drain current-drain voltage curves of devices of different sizes at several different values ​​of the gate voltage VGS within the range of 0 to Vn by progressively changing four variables t_tfin, t_l, t_nf, and t_nfin. The horizontal axis of the curve represents the drain voltage, and the vertical axis represents the drain current. Vn is the device gate voltage value set in this invention. Generally, a suitable value is 1.5V. When the step size is set to 0.3V, the corresponding values ​​are 0V, 0.3V, 0.6V, 0.9V, 1.2V, and 1.5V.

[0033] In this embodiment of the invention, the batch simulation simulator component of ADS software (ADS software has a built-in component that can extract multiple simulation results in one operation, enabling complex cyclic simulation operations) is used to perform a total of 5 cycles on the aforementioned dimensions and device gate voltage VGS. The step size is set and changed sequentially from the inside out: device gate voltage VGS, number of interpolation fins per device t_nfin, device interpolation index t_nf, device gate oxide layer thickness t_tfin, and device channel length t_l. This is repeated N times in total. Each cycle yields leakage current data for a set of different leakage voltages, where the set of different leakage voltages is 0 to Vn, with a step size of m, resulting in a total of (Vn / m)+1 values. Based on the (Vn / m)+1 points obtained in each set, a leakage current-leakage voltage curve can be plotted with leakage voltage as the abscissa and leakage current as the ordinate. Finally, the M points obtained from the simulation are grouped into N sets of leakage current-leakage voltage relationships.

[0034] Where M = N × [(Vn / m) + 1]; N = k1 × k2 × k3 × k4 × k5, k1 is the number of values ​​when the device gate voltage VGS changes, specifically, k1 = 6, that is, the device gate voltage VGS is changed in the range of 0V to 1.5V in steps of 0.3V. k2 is the number of values ​​when the number of interpolation fins t_nfin changes, specifically, k2 = 5, that is, the number of interpolation fins t_nfin changes in the range of 1 to 5 in steps of 1. k3 is the number of values ​​when the interpolation index t_nf changes, specifically, k3 = 5, that is, the interpolation index t_nf changes in the range of 1 to 5 in steps of 1. k4 is the number of values ​​when the device gate oxide thickness t_tfin changes, specifically, k4 = 10, that is, the device gate oxide thickness t_tfin changes in the range of 1nm to 10nm in steps of 1nm. k5 represents the number of values ​​that can be taken when the device channel length t_l changes. Specifically, k5 = 10, meaning the device channel length t_l changes within the range of 2nm to 20nm, in 2nm increments. Therefore, N = 6 × 5 × 5 × 10 × 10 = 15000. Taking Vn = 1.5V and m = 0.05V, then M = 465000.

[0035] In the above manner, each set of device gate voltage VGS, device interpolation fin number t_nfin, device interpolation index t_nf, device gate oxide thickness t_tfin, and device channel length t_l corresponds to a set of leakage current-leakage voltage relationships; that is, each set of device gate voltage VGS, device interpolation fin number t_nfin, device interpolation index t_nf, device gate oxide thickness t_tfin, and device channel length t_l is used as input, and each set of leakage current-leakage voltage relationships corresponding to it, i.e., (Vn / m)+1 leakage voltage-leakage current points, is used as output.

[0036] Step 2: Divide the dataset constructed in Step 1 into training set, test set and prediction set according to the proportion.

[0037] In this invention, the ratio of division is 7:2:1.

[0038] Step 3: Construct a device electrical characteristic prediction model based on a deep learning neural network. This invention combines deep learning with EDA software, significantly lowering the barrier to entry for circuit design using FINFET devices.

[0039] In embodiments of the present invention, the device electrical characteristic prediction model includes an upsampling module and a prediction module.

[0040] refer to Figure 2The upsampling module includes a first transposed convolutional layer, a second transposed convolutional layer, a convolutional layer, a max pooling layer, a single-kernel convolutional layer, and a batch normalization operation. A batch normalization operation is added after each computational layer to prevent the network from overfitting.

[0041] Two transposed convolutional layers are used at the beginning, their main function being to capture more information from the input features and feed it into the subsequent networks. The single-kernel convolutional layer has a 1x1 kernel and a stride of 1. The max-pooling layer increases the network's robustness, and the batch normalization layer prevents overfitting.

[0042] Figure 2 The values ​​marked in the figure represent the number of feature values ​​after each layer. For example, the parameters of the first transposed convolutional layer are (1, 256, 3, 3), the parameters of the second transposed convolutional layer are (256, 256, 3, 3), the parameters of the convolutional layer are (256, 256, 3, 1), and the parameters of the single-kernel convolutional layer are (256, 64, 1, 1). The upsampling module ultimately obtains a set of one-dimensional 1*1344 feature vectors. For example, for a 1*5 input feature vector, after the first transposed convolutional layer it becomes 256*15, after the second transposed convolutional layer it becomes 256*45, after the convolutional layer it becomes 256*43, after the pooling layer it becomes 256*21, after the single-kernel convolutional layer it becomes 64*21, and finally flattened into a one-dimensional feature vector of 1*1344 (64*21 = 1344).

[0043] refer to Figure 3 The prediction module consists of a dual-channel fully connected layer. The first fully connected layer outputs 0 to Vn with a step size of m, representing the significant figures of the current at the leakage voltage (Vn / m) + 1. The second fully connected layer acts as a classification layer, using the SOFTMAX function to classify the current order. The two are then combined to obtain the final predicted current value. This dual-channel prediction module employs a prediction method combining significant figures and order, leveraging the characteristic of deep learning where classification is more accurate than linear regression, significantly reducing the error in the prediction results. The input to the prediction module is the output of the upsampling network module.

[0044] In this embodiment, a network result consisting of an upsampling module and a dual-channel prediction module is used to reduce the error of the prediction result.

[0045] Step 4: Use the obtained dataset to train a prediction model for the electrical characteristics of the device.

[0046] Specifically, this invention preprocesses the divided training set and feeds it into the network for training. The network model weights are optimized through backpropagation, and the network model and its hyperparameters are iteratively modified repeatedly to obtain a final model that can be used for prediction after training is complete. The test set is then fed into the network for testing to evaluate its performance metrics and generalization ability.

[0047] In this embodiment of the invention, L1 loss (mean absolute difference) is used as the loss function for backpropagation loss adjustment of network weights. After the training set is fed into the network, the third-party Wandb component is used to detect the network training results, so as to update the network hyperparameters in a timely manner to optimize the network structure. The Wandb component can upload the train_loss and test_loss during training to the network in real time and plot them in real time for detection. When an abnormal loss is detected, training can be stopped at any time, and the hyperparameters can be changed to optimize the network. After repeated iterations, the learning rate finally adopted in this invention is 0.00025, and the learning rate is reduced to 0.1 times the current learning rate every 20 training epochs. After 440 training epochs, the prediction effect is good and very stable. Figure 4 , Figure 5 As shown, the test_loss value in this invention successfully converged to 0.007306 and is significantly lower than the train_loss value of 0.01227. The data indicates that the predictive network weight model of this invention has good generalization performance and does not exhibit overfitting.

[0048] In this embodiment, the Wandb component is introduced to dynamically monitor the training results, which greatly improves the network training efficiency.

[0049] Step 5: Input the predicted set into the device electrical characteristic prediction model to obtain the predicted current value, plot the predicted leakage current-leakage voltage curve, and compare it with the actual leakage current-leakage voltage curve. For example... Figure 6 As shown in the figures, curve a represents the predicted DC characteristics of a device with a length of 8 nm, a gate oxide thickness of 10 nm, an interpolation index of 3, 1 fin per interpolation finger, and a gate voltage of 1.5 V; curve b represents the predicted DC characteristics of a device with a length of 20 nm, a gate oxide thickness of 8 nm, an interpolation index of 4, 3 fins per interpolation finger, and a gate voltage of 0.6 V; curve c represents the predicted DC characteristics of a device with a length of 14 nm, a gate oxide thickness of 5 nm, an interpolation index of 3, 5 fins per interpolation finger, and a gate voltage of 0.9 V; and curve d represents the predicted DC characteristics of a device with a length of 2 nm, a gate oxide thickness of 5 nm, an interpolation index of 3, 4 fins per interpolation finger, and a gate voltage of 1.5 V. These figures demonstrate that, for various device sizes and gate voltage nodes, the network predicted values ​​are very close to the actual current values, and the curve trends show good fit, indicating that the predicted network weight model of this invention has excellent prediction accuracy.

Claims

1. A method for predicting the DC characteristics of a FINFET device based on deep learning, characterized in that, Comprising the following steps: Step 1, calling BSIM-CMG module through ADS software, constructing FINFET device electrical characteristic test schematic, using the batch simulation module built-in ADS software to extract the electrical characteristics of different size FINFET devices, taking the size affecting the device characteristics and the gate voltage VGS of the device as input characteristics, and the electrical characteristics of the device as output results, completing the construction of the data set; the device electrical characteristics refer to the curve of drain current changing with drain voltage, that is, the drain current-drain voltage curve; the size affecting the device characteristics is the device gate oxide layer thickness t_tfin, the device channel length t_l, the device insertion index t_nf and the device number of fins t_nfin; gradually changing the four variables t_tfin, t_l, t_nf and t_nfin, simulating the drain current-drain voltage curve of the device gate voltage VGS of different sizes in the range of 0~Vn at several different values, wherein the horizontal axis of the curve is the drain voltage, the vertical axis is the drain current, and Vn is the set device gate voltage value; In the ADS software, the batch simulation simulator component is used to change the device gate voltage VGS, the number of fins t_nfin of the device, the device insertion index t_nf, the device gate oxide layer thickness t_tfin and the device channel length t_l in turn from inside to outside with 5 cycles; a total of N cycles, each time obtaining the drain current data of the device under a group of different drain voltages, the group of different drain voltages is 0~Vn, and the step is m; according to the obtained (Vn / m)+1 points of each group, the drain current-drain voltage curve is drawn with the drain voltage as the horizontal coordinate and the drain current as the vertical coordinate, and finally M points obtained by simulation are grouped into N groups of drain current-drain voltage relationships; wherein M=N×[(Vn / m)+1]; N=k1×k2×k3×k4×k5, k1 is the number of values when the device gate voltage VGS changes, k2 is the number of values when the number of fins t_nfin of the device changes, k3 is the number of values when the device insertion index t_nf changes, k4 is the number of values when the device gate oxide layer thickness t_tfin changes, and k5 is the number of values when the device channel length t_l changes; Each group of device gate voltage VGS, number of fins t_nfin of the device, device insertion index t_nf, device gate oxide layer thickness t_tfin and device channel length t_l corresponds to a group of drain current-drain voltage relationships; that is, each group of device gate voltage VGS, number of fins t_nfin of the device, device insertion index t_nf, device gate oxide layer thickness t_tfin and device channel length t_l as input, and each group of drain current-drain voltage relationship corresponding thereto as output, that is, (Vn / m)+1 drain voltage-drain current points; Step 2, dividing the data set constructed in step 1 into training set, test set and prediction set according to the proportion; Step 3, constructing a device electrical characteristic prediction model based on deep learning neural network; Step 4, training the device electrical characteristic prediction model using the data set, and predicting the device electrical characteristics using the device electrical characteristic prediction model obtained after training. 2.The deep learning based DC characteristic prediction method for FINFET devices according to claim 1, wherein, The N = 15000, Vn = 1.5V, m = 0.05V; the change of the gate voltage VGS is in the range of 0V to 1.5V, with a step of 0.3V, that is, k1 = 6; the change of the number of each finger fin t_nfin is in the range of 1 to 5, with a step of 1, that is, k2 = 5; the change of the device insertion index t_nf is in the range of 1 to 5, with a step of 1, that is, k3 = 5; the change of the device gate oxide layer thickness t_tfin is in the range of 1nm to 10nm, with a step of 1nm, that is, k4 = 10; the change of the device channel length t_l is in the range of 2nm to 20nm, with a step of 2nm, that is, k5 = 10. 3.The deep learning based DC characteristic prediction method of a FINFET device according to claim 1, wherein, The device electrical property prediction model comprises an upsampling module and a prediction module; the upsampling module comprises a first transpose convolution layer, a second transpose convolution layer, a convolution layer, a max pooling layer, a single-core convolution layer and a batch normalization layer; The input of the prediction module is the output of the upsampling network module, which is composed of a double-channel fully connected layer, the first fully connected layer outputs 0~Vn, with a step of m, and the effective number of current under (Vn / m) +1 leakage voltage; the second fully connected layer is a classification layer, which is classified by a SOFTMAX function to obtain the current order; and the two are combined to obtain the final current prediction value. 4.The method of claim 3, wherein, The first transpose convolution layer parameter is (1, 256, 3, 3), the second transpose convolution layer parameter is (256, 256, 3, 3), the convolution layer parameter is (256, 256, 3, 1), and the single-core convolution layer parameter is (256, 64, 1, 1); the upsampling module finally obtains a group of one-dimensional 1*1344 feature vectors. 5.The deep learning based DC characteristic prediction method for FINFET devices of claim 1, wherein, In step 4, L1loss, that is, the average absolute difference, is used as the loss function to propagate the loss and change the network weight. 6.The deep learning based DC characteristic prediction method of a FINFET device according to claim 1, wherein, In step 4, the prediction set is sent into the device electrical property prediction model to obtain the predicted current value, the predicted drain current-drain voltage curve is drawn and compared with the actual drain current-drain voltage curve.

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