Display device and driving circuit

Abstract

A display device and a driving circuit are disclosed. The display device includes: a display panel including a light-emitting element, a driving transistor for providing a driving current to the light-emitting element using a high-potential driving voltage, and a plurality of switching transistors for controlling the operation of the driving transistor; a gate driving circuit for providing a plurality of scanning signals to the display panel; a data driving circuit for generating a data voltage or a bias voltage using a feedback high-potential driving voltage transmitted via a high-potential driving voltage feedback line; and a timing controller for controlling the gate driving circuit and the data driving circuit so that the data voltage is provided to the display panel during a first period of a low-speed mode and the bias voltage is provided to the display panel during a second period of the low-speed mode, wherein the low-speed mode is driven at a predetermined driving frequency lower than that of the high-speed mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2021-0152339 filed on November 8, 2021, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present invention relates to a display device, a driving circuit and a display driving method, which can reduce image quality defects occurring on a display panel during a process of changing a driving frequency. Background Art

[0004] With the development of the information society, the demand for various types of image display devices is increasing. In this regard, a series of display devices such as liquid crystal display devices and organic light emitting display devices have been widely used recently.

[0005] Among these display devices, organic light emitting display devices have excellent characteristics such as fast response speed, high contrast, high luminous efficiency, high brightness, and wide viewing angle because they use self-luminous organic light emitting diodes as light emitting elements.

[0006] Such an organic light emitting display device may include organic light emitting diodes (OLEDs) in a plurality of sub-pixels arranged in a display panel, and may control the organic light emitting diodes to emit light by controlling a voltage flowing through the OLEDs, thereby displaying an image while controlling the brightness of the sub-pixels.

[0007] In this case, the image data provided to the display device may be a still image or a moving image that changes at a constant speed, and even in the case of a moving image, there may be various types of images such as motion pictures, movies, or game images.

[0008] Furthermore, the display device may be switched to various operation modes according to a user's input or operation status.

[0009] On the other hand, the display device may change the driving frequency according to the type of input image data or the operation mode. During operation at a low driving frequency, image distortion or quality degradation such as flicker may occur. Summary of the Invention

[0010] Therefore, this document describes a display device, a driving circuit, and a display driving method that can reduce image quality defects that occur during operation at a low driving frequency.

[0011] Embodiments of the present invention provide a display device, a driving circuit, and a display driving method capable of reducing image quality defects such as flickering caused by image data patterns during a period of operation at a low driving frequency.

[0012] Embodiments of the present invention provide a display device, a driving circuit, and a display driving method capable of reducing image quality defects such as flicker by determining a bias voltage based on a driving voltage variation due to an image data pattern during a period of operation at a low driving frequency.

[0013] Problems solved by the embodiments of the present invention described below are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0014] According to an embodiment of the present invention, a display device includes: a display panel, the display panel including a light-emitting element, a driving transistor for providing a driving current to the light-emitting element using a high-potential driving voltage, and a plurality of switching transistors for controlling the operation of the driving transistor; a gate driving circuit for providing a plurality of scanning signals to the display panel; a data driving circuit for generating a data voltage or a bias voltage using a feedback high-potential driving voltage transmitted via a high-potential driving voltage feedback line; and a timing controller for controlling the gate driving circuit and the data driving circuit so that the data voltage is provided to the display panel in a first period of a low-speed mode in which the display panel is driven at a low-speed driving frequency, and the bias voltage is provided to the display panel in a second period of the low-speed mode, wherein the low-speed mode is driven at a predetermined driving frequency lower than the frequency of the high-speed mode.

[0015] In the display device according to an embodiment of the present invention, the plurality of switching transistors include: a first switching transistor, wherein a first scanning signal is supplied to a gate of the first switching transistor, a drain of the first switching transistor is connected to the gate of the driving transistor, and a source of the first switching transistor is connected to the source of the driving transistor; a second switching transistor, wherein a second scanning signal is supplied to a gate of the second switching transistor, the data voltage or the bias voltage is supplied to a drain of the second switching transistor, and the source of the second switching transistor is connected to the drain of the driving transistor; a third switching transistor, wherein a light emitting signal is supplied to a gate of the third switching transistor, a high potential driving voltage is supplied to a drain of the third switching transistor, and a a first switching transistor, wherein the light emitting signal is supplied to the gate of the fourth switching transistor, the drain of the fourth switching transistor is connected to the source of the driving transistor, and the source of the fourth switching transistor is connected to the anode of the light emitting element; a second switching transistor, wherein the third scanning signal is supplied to the gate of the fifth switching transistor, the stabilization voltage is supplied to the drain of the fifth switching transistor, and the source of the fifth switching transistor is connected to the gate of the driving transistor and the storage capacitor; and a third switching transistor, wherein the fourth scanning signal is supplied to the gate of the sixth switching transistor, the reset voltage is supplied to the drain of the sixth switching transistor, and the source of the sixth switching transistor is connected to the anode of the light emitting element.

[0016] In the display device according to an embodiment of the present invention, the plurality of switching transistors include: a first switching transistor, wherein a first scanning signal is supplied to a gate of the first switching transistor, a drain of the first switching transistor is connected to a gate of the driving transistor, and a source of the first switching transistor is connected to a source of the driving transistor; a second switching transistor, wherein a second scanning signal is supplied to a gate of the second switching transistor, the data voltage is supplied to a drain of the second switching transistor, and a source of the second switching transistor is connected to a drain of the driving transistor; a third switching transistor, wherein a light emitting signal is supplied to a gate of the third switching transistor, a high potential driving voltage is supplied to a drain of the third switching transistor, and a source of the third switching transistor is connected to a drain of the driving transistor; and a fourth switching transistor, wherein the light emitting signal is supplied to the fourth switching transistor the gate of the fourth switching transistor, the drain of the fourth switching transistor is connected to the source of the driving transistor, and the source of the fourth switching transistor is connected to the anode of the light-emitting element; a fifth switching transistor, wherein the third scanning signal is supplied to the gate of the fifth switching transistor, the stabilization voltage is supplied to the drain of the fifth switching transistor, and the source of the fifth switching transistor is connected to the gate of the driving transistor and the storage capacitor; a sixth switching transistor, wherein the fourth scanning signal is supplied to the gate of the sixth switching transistor, the reset voltage is supplied to the drain of the sixth switching transistor, and the source of the sixth switching transistor is connected to the anode of the light-emitting element; and a seventh switching transistor, wherein the fifth scanning signal is supplied to the gate of the seventh switching transistor, the bias voltage is supplied to the drain of the seventh switching transistor, and the source of the seventh switching transistor is connected to the drain of the driving transistor.

[0017] In the display device according to the embodiment of the present invention, the high potential driving voltage feedback line extends from one end of the driving voltage line arranged outside the display panel and is electrically connected to the data driving circuit.

[0018] In a display device according to an embodiment of the present invention, the data driving circuit includes: a gamma voltage generating circuit, which generates a reference gamma voltage by using the feedback high-potential driving voltage as a reference voltage; a bias voltage generating circuit, which generates the bias voltage by using the feedback high-potential driving voltage as a reference voltage; a plurality of resistor strings that generate the data voltage by dividing the reference gamma voltage; and a multiplexer, which is used to transmit the data voltage or the bias voltage to the display panel in response to a selection signal.

[0019] In a display device according to an embodiment of the present invention, the gamma voltage generating circuit includes: a first reference gamma voltage output circuit, which generates a first reference gamma voltage with a low grayscale by using the feedback high-potential driving voltage as a reference voltage; and a second reference gamma voltage output circuit, which generates a second reference gamma voltage with a high grayscale by using the feedback high-potential driving voltage as a reference voltage.

[0020] In the display device according to the embodiment of the present invention, the first reference gamma voltage output circuit, the second reference gamma voltage output circuit, and the bias voltage generating circuit are low voltage drop output circuits for converting the feedback high potential driving voltage into a specific output voltage.

[0021] In the display device according to the embodiment of the present invention, the first period is a refresh frame period for providing a data voltage for driving the light emitting element.

[0022] In the display device according to the embodiment of the present invention, the second period is a frame skip period in which the data voltage is not supplied and the bias voltage is supplied.

[0023] In the display device according to the embodiment of the present invention, the data voltage and the bias voltage change by the same amount.

[0024] In the display device according to the embodiment of the present invention, the third scan signal and the fourth scan signal are separate signals from each other.

[0025] In the display device according to the embodiment of the present invention, the bias voltage changes with the same amount as the first reference gamma voltage and the second reference gamma voltage.

[0026] According to an embodiment of the present invention, there is provided a driving circuit, comprising: a gamma voltage generating circuit, which generates a reference gamma voltage by using a feedback high-potential driving voltage as a reference voltage; a bias voltage generating circuit, which generates a bias voltage by using the feedback high-potential driving voltage as a reference voltage; a plurality of resistor strings that generate data voltages by dividing the reference gamma voltage; and a multiplexer for transmitting the data voltage or the bias voltage to a display panel in response to a selection signal.

[0027] In a display device according to an embodiment of the present invention, the gamma voltage generating circuit includes: a first reference gamma voltage output circuit, which generates a first reference gamma voltage with a low grayscale by using the feedback high-potential driving voltage as a reference voltage; and a second reference gamma voltage output circuit, which generates a second reference gamma voltage with a high grayscale by using the feedback high-potential driving voltage as a reference voltage.

[0028] In the display device according to an embodiment of the present invention, the first reference gamma voltage output circuit, the second reference gamma voltage output circuit and the bias voltage generating circuit are low voltage drop output circuits for converting the feedback high potential driving voltage into a specific output voltage.

[0029] In the display device according to the embodiment of the present invention, the data voltage and the bias voltage change by the same amount.

[0030] In a display device according to an embodiment of the present invention, the data voltage is transmitted to the display panel during a first period of the low-speed mode of the display panel, and the bias voltage is transmitted to the display panel during a second period of the low-speed mode of the display panel, wherein the display panel is driven in the low-speed mode at a predetermined driving frequency lower than that in the high-speed mode.

[0031] In the display device according to the embodiment of the present invention, the first period is a refresh frame period in which the data voltage is supplied.

[0032] In the display device according to the embodiment of the present invention, the second period is a frame skip period in which the data voltage is not supplied and the bias voltage is supplied.

[0033] In the display device according to the embodiment of the present invention, the bias voltage changes with the same amount as the first reference gamma voltage and the second reference gamma voltage.

[0034] According to an embodiment of the present invention, a display driving method for driving a display panel is provided, wherein the display panel includes a light-emitting element, a driving transistor for providing a driving current to the light-emitting element using a high-potential driving voltage, and a plurality of switching transistors for controlling the operation of the driving transistor. The display driving method includes: receiving a feedback high-potential driving voltage via a high-potential driving voltage feedback line; generating a reference gamma voltage by using the feedback high-potential driving voltage; generating a bias voltage by using the feedback high-potential driving voltage; providing a data voltage by using the reference gamma voltage in a first period of a low-speed mode, wherein the display panel is driven at a predetermined driving frequency lower than that in a high-speed mode in the low-speed mode; and providing the bias voltage in a second period of the low-speed mode.

[0035] According to the embodiments of the present invention, a display device, a driving circuit, and a display driving method can be provided, which can reduce defects in image quality that occur during operation at a low driving frequency.

[0036] Furthermore, according to the embodiments of the present invention, a display device, a driving circuit, and a display driving method can be provided that can reduce image quality defects such as flickering caused by an image data pattern during a period of operation at a low driving frequency.

[0037] In addition, according to an embodiment of the present invention, a display device, a driving circuit, and a display driving method can be provided, which can reduce image quality defects such as flicker by determining a bias voltage based on a driving voltage change caused by an image data pattern during a period of operation at a low driving frequency.

[0038] The effects of the embodiments disclosed in the present invention are not limited to the above-mentioned effects. In addition, those skilled in the art will clearly understand from the following description that the embodiments disclosed in the present invention can achieve other effects not mentioned above. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In the attached figure:

[0040] Figure 1 A schematic diagram showing a display device according to an embodiment of the present invention is shown.

[0041] Figure 2 A system diagram of a display device according to an embodiment of the present invention is shown.

[0042] Figure 3 FIG. 1 is a schematic diagram showing a data driving circuit for generating data voltages in a display device according to an embodiment of the present invention.

[0043] Figure 4FIG. 1 shows a structural diagram of a gamma voltage generating circuit in a display device according to an embodiment of the present invention.

[0044] Figure 5 A sub-pixel circuit diagram of a display device according to an embodiment of the present invention is shown.

[0045] Figure 6 FIG. 1 is a schematic diagram showing a driving mode based on frequency variation in a display device according to an embodiment of the present invention.

[0046] Figure 7 1 shows a driving timing in the second mode of driving at a low-speed driving frequency in the display device according to the embodiment of the present invention.

[0047] Figure 8 A diagram illustrating a change in a mode of image data displayed via a display panel in a display device according to an embodiment of the present invention.

[0048] Figure 9 A conceptual diagram illustrating a phenomenon in which a deviation occurs in a reference gamma voltage according to a change in an image data pattern in a display device according to an embodiment of the present invention.

[0049] Figure 10 A structure for generating a reference gamma voltage and a bias voltage by using a feedback high potential driving voltage detected through a high potential driving voltage feedback line in a display device according to an embodiment of the present invention is shown.

[0050] Figure 11 A view showing a transmission path of a high-potential driving voltage in a display device according to an embodiment of the present invention.

[0051] Figure 12 FIG. 1 shows a structural diagram of a gamma voltage generating circuit and a bias voltage generating circuit in a display device according to an embodiment of the present invention.

[0052] Figure 13 A diagram illustrating a situation in which a deviation between a data voltage and a bias voltage is kept constant even if an on-pixel ratio (OPR) is changed in a display device according to an embodiment of the present invention.

[0053] Figure 14 A conceptual diagram illustrating a phenomenon in which a reference gamma voltage and a bias voltage have the same amount of change according to a change in an image data pattern in a display device according to an embodiment of the present invention.

[0054] Figure 15 FIG. 1 is a flow chart of a display driving method according to an embodiment of the present invention.

[0055] Figure 16Another sub-pixel circuit diagram in a display device according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0056] The advantages and features of the present invention and methods for achieving these advantages and features will become apparent through reference to the accompanying drawings and detailed description of the embodiments. The present invention should not be construed as limited to the embodiments described herein, but rather may be implemented in a variety of different forms. These embodiments are provided to make the disclosure of the present invention thorough and complete and to fully convey the scope of the present invention to those skilled in the art. The scope of the present invention is defined by the appended claims.

[0057] The shapes, sizes, proportions, angles, quantities, etc. shown in the accompanying drawings for the purpose of describing exemplary embodiments are merely examples, and the present invention is not limited to the embodiments shown in the drawings. The same reference numerals and symbols will be used throughout the application to refer to the same or similar components. In the following description of the present invention, detailed descriptions of known functions and components involved in the present invention will be omitted to avoid unnecessarily obscuring the subject matter of the present invention. It will be understood that the terms "including", "having" and "comprising" used herein and any variations thereof are intended to cover non-exclusive "including" unless otherwise expressly stated.

[0058] When analyzing an element, it should be understood that the element is interpreted as including a range of error even if not explicitly stated.

[0059] When spatially relative terms such as "on," "above," "below," "under," and "to the side of" are used to describe the relationship between one element or component and another element or component, one or more intervening elements or components may be present between the one element or component and the other element or component unless terms such as "directly" are used.

[0060] When time-relative terms such as "after," "subsequently," "following," and "before" are used to define a temporal relationship, discontinuous situations may be included unless the terms "immediately" or "directly" are used.

[0061] When describing signal transmission such as "a signal is sent from node A to node B," the signal may be sent from node A to node B via another node unless the term "immediately" or "directly" is used.

[0062] Furthermore, terms such as "first" and "second" may be used herein to describe various components. However, it should be understood that these components are not limited by these terms. These terms are merely used to distinguish one element or component from other elements or components. Therefore, within the spirit of the present invention, the first component mentioned below may also be the second component.

[0063] The features of the exemplary embodiments of the present invention may be combined or combined with each other in part or in whole, and may cooperate with each other or operate in various technical ways. In addition, each exemplary embodiment may be implemented independently of each other, or implemented in conjunction with other embodiments.

[0064] Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings.

[0065] Figure 1 A schematic diagram showing a display device according to an embodiment of the present invention is shown.

[0066] Reference Figure 1 According to an embodiment of the present invention, a display device 100 may include: a display panel 110 connected to a plurality of gate lines GL and a plurality of data lines DL, in which a plurality of sub-pixels SP are arranged in rows and columns; a gate driving circuit 120 for supplying scan signals to the plurality of gate lines GL and a data driving circuit 130 for supplying data voltages to the plurality of data lines DL; a timing controller 140 for controlling the gate driving circuit 120 and the data driving circuit 130; and a power management circuit 150.

[0067] The display panel 110 displays an image based on scan signals supplied from the gate driving circuit 120 via the plurality of gate lines GL and data voltages supplied from the data driving circuit 130 via the plurality of data lines DL.

[0068] In the case of a liquid crystal display, the display panel 110 includes a liquid crystal layer formed between two substrates and can operate in any known mode such as a TN (twisted nematic) mode, a VA (vertical alignment) mode, an IPS (in-plane switching) mode, or an FFS (fringe field switching) mode. In the case of an organic light-emitting display device, the display panel 110 can be implemented in a top emission method, a bottom emission method, or a bi-directional emission method.

[0069] In the display panel 110, a plurality of pixels may be arranged in a matrix. Each pixel may be composed of sub-pixels SP of different colors, such as a white sub-pixel, a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Each sub-pixel SP may be defined by a plurality of data lines DL and a plurality of gate lines GL.

[0070] The subpixel SP may include a thin film transistor (TFT) disposed in a region where the data line DL and the gate line GL cross each other, a light emitting element such as a light emitting diode that emits light according to a data voltage, and a storage capacitor for maintaining the data voltage by being electrically connected to the light emitting element.

[0071] For example, when the display device 100 having a resolution of 2160×3840 includes four sub-pixels SP of white W, red R, green G, and blue B, 3840×4=15360 data lines DL may be provided by 2160 gate lines GL and 3840 data lines DL connected to the four sub-pixels WRGB, respectively. Each of the plurality of sub-pixels SP may be disposed in an area where a plurality of gate lines GL and a plurality of data lines DL overlap with each other.

[0072] The gate driving circuit 120 is controlled by the timing controller 140 , and controls the driving timing of the plurality of sub-pixels SP by sequentially supplying scan signals to the plurality of gate lines GL located in the display panel 110 .

[0073] In the display device 100 having a resolution of 2160×3840, the operation of sequentially supplying scan signals to 2160 gate lines from the first gate line GL1 to the 2160th gate line GL2160 may be referred to as a 2160-phase drive operation. On the other hand, the operation of sequentially supplying scan signals to every four gate lines GL, such as the case where the scan signal is sequentially supplied from the first gate line GL1 to the fourth gate line GL4 and then sequentially supplied from the fifth gate line GL5 to the eighth gate line GL8, may be referred to as a 4-phase drive operation. As described above, the operation of sequentially supplying scan signals to every N gate lines may be referred to as an N-phase drive operation.

[0074] The gate driver circuit 120 may include one or more gate driver integrated circuits (GDICs), which may be provided on one or both sides of the display panel 110 depending on the driving method. Alternatively, the gate driver circuit 120 may be implemented as a gate-in-panel (GIP) structure built into the bezel area of ​​the display panel 110.

[0075] The data driving circuit 130 receives digital image data DATA from the timing controller 140 and converts the received digital image data DATA into an analog data voltage. Then, the data driving circuit 130 supplies the analog data voltage to each data line DL at a time when a scan signal is supplied via the gate line GL, thereby causing each sub-pixel SP connected to the data line DL to emit light at a corresponding brightness corresponding to the analog data voltage.

[0076] Similarly, the data driver circuit 130 may include one or more source driver integrated circuits (SDICs). Each source driver integrated circuit (SDIC) may be connected to a bonding pad of the display panel 110 via tape automated bonding (TAB) or chip on glass (COG), or may be directly mounted on the display panel 110.

[0077] In some cases, each source driver integrated circuit (SDIC) may be integrated with the display panel 110. In addition, each source driver integrated circuit (SDIC) may be implemented using a chip on film (COF) structure. In this case, the source driver integrated circuit (SDIC) may be mounted on a circuit film to be electrically connected to the data line DL in the display panel 110 via the circuit film.

[0078] The timing controller 140 provides various control signals to the gate driving circuit 120 and the data driving circuit 130, and controls the operations of the gate driving circuit 120 and the data driving circuit 130. That is, the timing controller 140 controls the gate driving circuit 120 to provide a scan signal in response to the timing achieved by the corresponding frame; on the other hand, the timing controller 140 transmits image data DATA from an external source to the data driving circuit 130.

[0079] Here, the timing controller 140 receives various timing signals including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a main clock MCLK from the external host system 200 .

[0080] The host system 200 may be any one of a TV (television) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, and a wearable device.

[0081] Therefore, the timing controller 140 generates control signals using various timing signals received from an external source and provides the control signals to the gate driving circuit 120 and the data driving circuit 130 .

[0082] For example, the timing controller 140 generates various gate control signals including a gate start pulse GSP, a gate clock GCLK, and a gate output enable signal GOE to control the gate driver circuit 120. Here, the gate start pulse GSP is used to control the start timing of one or more gate driver integrated circuits (GDICs) of the gate driver circuit 120. In addition, the gate clock GCLK is a clock signal commonly provided to one or more gate driver integrated circuits (GDICs) to control the shift timing of the scan signal. The gate output enable signal GOE specifies the timing information of one or more gate driver integrated circuits (GDICs).

[0083] In addition, the timing controller 140 generates various data control signals, including a source start pulse SSP, a source sampling clock SCLK, and a source output enable signal SOE, to control the data driver circuit 130. The source start pulse SSP is used to control the start timing of data sampling for one or more source driver integrated circuits (SDICs) in the data driver circuit 130. The source sampling clock SCLK is a clock signal used to control the data sampling timing in each source driver integrated circuit (SDIC). The source output enable signal SOE controls the output timing of the data driver circuit 130.

[0084] The display device 100 may further include a power management circuit 150 for providing or controlling various voltages or currents for the display panel 110 , the gate driving circuit 120 , and the data driving circuit 130 .

[0085] The power management circuit 150 generates necessary power required to drive the display panel 110 , the gate driving circuit 120 , and the data driving circuit 130 by controlling a direct current (DC) input voltage Vin provided from the host system 200 .

[0086] The sub-pixel SP is located at a point where the gate line GL and the data line DL intersect each other, and a light-emitting element may be located in each sub-pixel SP. For example, an organic light-emitting display device may include a light-emitting element such as a light-emitting diode located in each sub-pixel SP, and may display an image by controlling a current flowing through the light-emitting element in response to a data voltage.

[0087] The display device 100 may be various devices such as a liquid crystal display, an organic light emitting display, and a plasma display panel.

[0088] Figure 2 A system diagram of a display device according to an embodiment of the present invention is shown.

[0089] As an example, Figure 2 It is shown that in the display device 100 according to the embodiment of the present invention, each source driver integrated circuit SDIC of the data driver circuit 130 and each gate driver integrated circuit GDIC of the gate driver circuit 120 are implemented using a COF type among various structures such as TAB, COG and COF.

[0090] One or more gate driver integrated circuits GDIC included in the gate driver circuit 120 may be mounted on the gate film GF, respectively, and one side of the gate film GF may be electrically connected to the display panel 110. In addition, wires may be provided on the gate film GF to electrically connect the gate driver integrated circuits GDIC and the display panel 110.

[0091] Similarly, the data driving circuit 130 may include one or more source driver integrated circuits SDIC that may be mounted on the source film SF, respectively. A portion of the source film SF may be electrically connected to the display panel 110. In addition, wires may be provided on the source film SF to electrically connect the source driver integrated circuits SDIC and the display panel 110.

[0092] The display device 100 may include at least one source printed circuit board (SPCB) for connecting a plurality of source driver integrated circuits (SDIC) to other devices through circuits, and a control printed circuit board (CPCB) for mounting various control components and electrical elements.

[0093] The other portion of the source film SF on which the source driver integrated circuit SDIC is mounted may be connected to at least one source printed circuit board SPCB. That is, one portion of the source film SF on which the source driver integrated circuit SDIC is mounted may be electrically connected to the display panel 110, and the other portion of the source film SF may be electrically connected to the source printed circuit board SPCB.

[0094] The timing controller 140 and the power management circuit 150 may be mounted on the control printed circuit board (CPCB). The timing controller 140 may control the operation of the data driving circuit 130 and the gate driving circuit 120. The power management circuit 150 may provide a driving voltage and a driving current, or control the voltage and current for the data driving circuit 130 and the gate driving circuit 120.

[0095] The at least one source printed circuit board (SPCB) and the control printed circuit board (CPCB) may be circuit-connected via at least one connecting member. For example, the connecting member may be a flexible printed circuit (FPC), a flexible flat cable (FFC), or the like. In this case, the connecting member used to connect the at least one source printed circuit board (SPCB) and the control printed circuit board (CPCB) may vary depending on the size and type of the display device 100. The at least one source printed circuit board (SPCB) and the control printed circuit board (CPCB) may be integrated into a single printed circuit board.

[0096] In the display device 100 having the above configuration, the power management circuit 150 supplies the driving voltage required for display driving operation or characteristic value sensing operation to the source printed circuit board SPCB via the flexible printed circuit (FPC) or the flexible flat cable (FFC). The driving voltage supplied to the source printed circuit board SPCB is transmitted within the display panel 110 via the source driver integrated circuit (SDIC) to cause a specific sub-pixel SP to emit light or sense a specific sub-pixel SP.

[0097] Each sub-pixel SP arranged in the display panel 110 of the display device 100 may include an organic light emitting diode as a light emitting element and circuit elements such as a driving transistor for driving the light emitting element.

[0098] The type and number of circuit elements constituting each sub-pixel SP may be variously determined according to function, design, and the like.

[0099] In this case, the data driving circuit 130 may convert the image data DATA transmitted from the timing controller 140 into data voltages corresponding to the gray levels using gamma voltages corresponding to specific gray levels.

[0100] Figure 3 FIG. 1 is a schematic diagram showing a data driving circuit for generating data voltages in a display device according to an embodiment of the present invention.

[0101] Reference Figure 3 According to an embodiment of the present invention, the data driving circuit 130 of the display device 100 may include: a data voltage output circuit 160 that provides a data voltage Vdata corresponding to the image data DATA received from the timing controller 140; and a gamma voltage generating circuit 170 that generates a gamma voltage and transmits the gamma voltage to the data voltage output circuit 160.

[0102] The data voltage output circuit 160 receives the digital image data DATA from the timing controller 140 and converts the received image data DATA into an analog data voltage Vdata to display a grayscale of the image data DATA.

[0103] At this time, the data voltage output circuit 160 provides a data voltage Vdata corresponding to each gray level using the gamma voltage transmitted from the gamma voltage generating circuit 170 .

[0104] The gamma voltage generating circuit 170 receives a reference voltage for generating a gamma voltage from the outside, and generates a gamma voltage corresponding to a specific grayscale using the received reference voltage.

[0105] For example, to display 256 gray levels, the gamma voltage generating circuit 170 may generate gamma voltages corresponding to gray level 0 (G0), gray level 1 (G1), gray level 3 (G3), gray level 15 (G15), gray level 31 (G31), gray level 63 (G63), gray level 127 (G127), gray level 191 (G191), and gray level 255 (G255).

[0106] The data voltage output circuit 160 receives a gamma voltage corresponding to a specific gray level transmitted from the gamma voltage generating circuit 170 and generates a data voltage corresponding to the gray level of the image data DATA using the received gamma voltage.

[0107] That is, when the data voltage output circuit 160 generates the data voltage Vdata corresponding to the gray level 255 (G255), the gamma voltage corresponding to the gray level 255 (G255) may be used. In addition, when generating the data voltage Vdata between the gray level 191 (G191) and the gray level 255 (G255), the gamma voltage corresponding to the gray level 191 (G191) and the gamma voltage corresponding to the gray level 255 (G255) may be used.

[0108] Figure 4 FIG. 1 shows a structural diagram of a gamma voltage generating circuit in a display device according to an embodiment of the present invention.

[0109] Reference Figure 4 According to an embodiment of the present invention, the gamma voltage generating circuit 170 of the display device 100 may include: a first reference gamma voltage output circuit 172 that generates a first reference gamma voltage VREG1 using a circuit driving voltage DDVDH; a second reference gamma voltage output circuit 174 that generates a second reference gamma voltage VREG2 using the circuit driving voltage DDVDH; and a plurality of resistor strings R for dividing the first reference gamma voltage VREG1 and the second reference gamma voltage VREG2.

[0110] The first reference gamma voltage output circuit 172 and the second reference gamma voltage output circuit 174 can be configured as a low dropout (LDO) circuit that converts an input voltage into a desired specific output voltage. Such an LDO circuit can be used to stably generate an output voltage when the difference between the input voltage and the output voltage is small.

[0111] For example, the first reference gamma voltage output circuit 172 may be implemented by an LDO circuit that receives the reference voltage Vref and stably generates the first reference gamma voltage VREG1 by applying the first offset voltage VDC1 to the reference voltage Vref.

[0112] In addition, the second reference gamma voltage output circuit 174 may be implemented by an LDO circuit that receives the reference voltage Vref and stably generates the second reference gamma voltage VREG2 by applying the second offset voltage VDC2 to the reference voltage Vref.

[0113] At this time, the reference voltage Vref provided to the first reference gamma voltage output circuit 172 and the second reference gamma voltage output circuit 174 for generating the reference gamma voltages VREG1 and VREG2 may be a DC voltage having a specific level. Alternatively, it may be a feedback voltage of the high-potential driving voltage VDD to apply a change to the high-potential driving voltage VDD provided to the display panel 110.

[0114] The first reference gamma voltage VREG1 may be a gamma voltage of 0 gray level G0 supplied to an upper end of the resistor string, and the second reference gamma voltage VREG2 may be a gamma voltage of 255 gray level G255 supplied to a lower end of the resistor string.

[0115] Therefore, the gamma voltage generating circuit 170 can generate gamma voltages corresponding to multiple gray levels (for example, 0 gray level G0, 1 gray level G1, 3 gray level G3, 15 gray level G15, 31 gray level G31, 63 gray level G63, 127 gray level G127, 191 gray level G191 and 255 gray level G255) by dividing the first reference gamma voltage VREG1 and the second reference gamma voltage VREG2 through a resistor string.

[0116] The gamma voltage generating circuit 170 may generate gamma voltages corresponding to low gray levels at narrow intervals in order to improve resolution at low gray levels.

[0117] Figure 5 A sub-pixel circuit diagram of a display device according to an embodiment of the present invention is shown.

[0118] Reference Figure 5 , the sub-pixel SP of the display device 100 according to the embodiment of the present invention includes first to sixth switching transistors T1 - T6 , a driving transistor DRT, a storage capacitor Cst, and a light emitting element ED.

[0119] Here, the light-emitting element ED may be, for example, a self-luminous element capable of emitting light by itself, such as an organic light-emitting diode OLED.

[0120] In the subpixel SP according to the embodiment of the present invention, the second to fourth switching transistors T2 - T4 , the sixth switching transistor T6 and the driving transistor DRT may be P-type transistors, and the first switching transistor T1 and the fifth switching transistor T5 may be N-type transistors.

[0121] P-type transistors are relatively more reliable than N-type transistors. P-type transistors have the advantage that, because their drains are fixed to a high-potential drive voltage VDD, the current flowing through the light-emitting element ED does not fluctuate due to the storage capacitor Cst. Therefore, current can be stably supplied.

[0122] For example, a P-type transistor may be connected to the anode of the light-emitting element ED. In this case, when the switching transistors T4 and T6 connected to the light-emitting element ED operate in the saturation region, a constant current can flow regardless of changes in the current and threshold voltage of the light-emitting element ED. Therefore, reliability is relatively high.

[0123] In this sub-pixel SP structure, the N-type transistors T1 and T5 can be oxide transistors formed using semiconductor oxides (for example, transistors having a channel formed by a semiconductor oxide such as indium, gallium, zinc oxide or IGZO), and the other P-type transistors DRT, T2-T4, and T6 can be silicon transistors formed by a semiconductor such as silicon (for example, transistors having a polysilicon channel formed by a low-temperature process such as LTPS or low-temperature polysilicon).

[0124] Oxide transistors have relatively low leakage current compared to silicon transistors. Therefore, when implemented using oxide transistors, leakage current from the gate of the drive transistor DRT is reduced, which has the effect of reducing image quality defects such as flicker.

[0125] Meanwhile, the remaining P-type transistors DRT, T2 - T4 , and T6 excluding the first and fifth switching transistors T1 and T5 corresponding to N-type transistors may be formed of low-temperature polysilicon.

[0126] The first scan signal SCAN1 is provided to the gate of the first switch transistor T1. The drain of the first switch transistor T1 is connected to the gate of the drive transistor DRT.

[0127] The source of the first switching transistor T1 is connected to the source of the driving transistor DRT.

[0128] The first switching transistor T1 is turned on by the first scan signal SCAN1 and controls the operation of the driving transistor DRT using the high potential driving voltage VDD stored in the storage capacitor Cst.

[0129] The first switch transistor T1 may be formed by an N-type MOS transistor to constitute an oxide transistor. Since the N-type MOS transistor uses electrons as carriers, it has higher mobility and faster switching speed than the P-type MOS transistor.

[0130] The second scan signal SCAN2 is provided to the gate of the second switch transistor T2. The data voltage Vdata or the bias voltage VOBS may be provided to the drain of the second switch transistor T2. The source of the second switch transistor T2 is connected to the drain of the drive transistor DRT.

[0131] The second switching transistor T2 is turned on by the second scan signal SCAN2 to provide the data voltage Vdata to the drain of the driving transistor DRT.

[0132] The light emitting signal EM is supplied to the gate of the third switch transistor T3, the high potential driving voltage VDD is supplied to the drain of the third switch transistor T3, and the source of the third switch transistor T3 is connected to the drain of the driving transistor DRT.

[0133] The third switch transistor T3 is turned on by the light emitting signal EM to provide the high potential driving voltage VDD to the drain of the driving transistor DRT.

[0134] The emission signal EM is provided to the gate of the fourth switch transistor T4. The drain of the fourth switch transistor T4 is connected to the source of the drive transistor DRT. The source of the fourth switch transistor T4 is connected to the anode of the light emitting element ED.

[0135] The fourth switching transistor T4 is turned on by the light emitting signal EM to provide a driving current to the anode of the light emitting element ED.

[0136] The third scan signal SCAN3 is provided to the gate of the fifth switching transistor T5.

[0137] Here, the third scan signal SCAN3 may be the first scan signal SCAN1 provided to the sub-pixel SP located at another position. For example, when the first scan signal SCAN1 is provided to the nth gate line, the third scan signal SCAN3 may be the first scan signal SCAN1 provided to the (n-9)th gate line. That is, depending on the driving phase of the display panel 110, the third scan signal SCAN3 may serve as the first scan signal SCAN1 at another gate line GL.

[0138] A stabilization voltage Vini is supplied to the drain of the fifth switching transistor T5. A source of the fifth switching transistor T5 is connected to the gate of the driving transistor DRT and the storage capacitor Cst.

[0139] The fifth switch transistor T5 is turned on by the third scan signal SCAN3 to provide the stabilized voltage Vini to the gate of the driving transistor DRT.

[0140] The fourth scan signal SCAN4 is provided to the gate of the sixth switching transistor T6.

[0141] Here, the fourth scan signal SCAN4 may be the second scan signal SCAN2 provided to the sub-pixel SP located at another position. For example, when the second scan signal SCAN2 is provided to the n-th gate line, the fourth scan signal SCAN4 may be the second scan signal SCAN2 provided to the (n-1)-th gate line. That is, depending on the driving phase of the display panel 110, the fourth scan signal SCAN4 may be used as the second scan signal SCAN2 at another gate line GL.

[0142] The reset voltage VAR is supplied to the drain of the sixth switch transistor T6. The source of the sixth switch transistor T6 is connected to the anode of the light emitting element ED.

[0143] The sixth switching transistor T6 is turned on by the fourth scan signal SCAN4 to provide the reset voltage VAR to the anode of the light emitting element ED.

[0144] The gate of the driving transistor DRT is connected to the drain of the first switching transistor T1 , the drain of the driving transistor DRT is connected to the source of the second switching transistor T2 , and the source of the driving transistor DRT is connected to the source of the first switching transistor T1 .

[0145] The driving transistor DRT is turned on by the voltage difference between the source and the drain of the first switching transistor T1 to supply the driving current to the light emitting element ED.

[0146] The high potential driving voltage VDD is supplied to one end of the storage capacitor Cst, and the other end of the storage capacitor Cst is connected to the gate of the driving transistor DRT. The storage capacitor Cst stores the voltage of the gate of the driving transistor DRT.

[0147] The anode of the light emitting element ED is connected to the source of the fourth switching transistor T4 and the source of the sixth switching transistor T6. The low potential driving voltage VSS is supplied to the cathode of the light emitting element ED.

[0148] The light emitting element ED emits light with predetermined brightness according to a driving current controlled by the driving transistor DRT.

[0149] At this time, the stabilization voltage Vini is supplied to stabilize the change in capacitance formed at the gate of the driving transistor DRT, and the reset voltage VAR is supplied to reset the anode of the light emitting element ED.

[0150] When the reset voltage VAR is supplied to the anode of the light emitting element ED in a state in which the fourth switching transistor T4 is turned off, the anode of the light emitting element ED may be reset.

[0151] The sixth switching transistor T6 for providing the reset voltage VAR is connected to the anode of the light emitting element ED.

[0152] In order to separately perform the driving operation of the driving transistor DRT and the resetting operation of the anode of the light emitting element ED, the third scan signal SCAN3 for driving or resetting the driving transistor DRT and the fourth scan signal SCAN4 for controlling the supply of the reset voltage VAR to the anode of the light emitting element ED are separated from each other.

[0153] When the switching transistors T5 and T6 for providing the stabilization voltage Vini and the reset voltage VAR are turned on, the fourth switching transistor T4, which connects the source of the driving transistor DRT to the anode of the light-emitting element ED, can be turned off. As a result, the driving current of the driving transistor DRT is blocked from flowing to the anode of the light-emitting element ED, so that the anode is not affected by voltages other than the reset voltage VAR.

[0154] As described above, the sub-pixel SP including the seven transistors DRT, T1, T2, T3, T4, T5, and T6 and one capacitor Cst may be referred to as a 7T1C structure.

[0155] Here, a 7T1C structure is shown as an example of various types of sub-pixel SP circuits. The structure and number of transistors and capacitors constituting the sub-pixel SP may vary. At the same time, each of the plurality of sub-pixels SP may have the same structure, or some of the plurality of sub-pixels SP may have different structures.

[0156] Figure 6 FIG. 1 is a schematic diagram showing a driving mode based on frequency variation in a display device according to an embodiment of the present invention.

[0157] Reference Figure 6 According to an embodiment of the present invention, the display device 100 (or the display panel 110) may include: a first mode Mode1, in which moving image data is displayed at a high-speed first frequency; and a second mode Mode2, in which still image data or low-speed image data is displayed at a low-speed second frequency (or a predetermined driving frequency) lower than the high-speed first frequency.

[0158] For example, in the first mode Mode1, moving image data may be displayed in full color at a frequency of 120 Hz corresponding to the first frequency on the display panel 110. While the display device 100 operates in the first mode Mode1, the subpixels SP of the display panel 110 display moving image data transmitted from the timing controller 140 every 120 frame periods.

[0159] As described above, the period of continuously displaying image data on the display panel 110 at a high-speed driving frequency may be referred to as a refresh frame. For example, when the driving frequency is 120 Hz, all 120 frames within 1 second in the first mode Mode1 will be refresh frames for displaying image data.

[0160] Meanwhile, when the display device 100 operates in the second mode Mode2 for displaying still image data or low-speed image data, the display device 100 may display specified image data on the display panel 110 during an initial period of the second mode Mode2, and may not display image data on the display panel 110 during the remaining periods.

[0161] For example, when entering the second mode Mode2, the display device 100 may change the driving frequency from the first frequency of 120 Hz to the second frequency of 1 Hz. In this case, the image data displayed in the last period of the first mode Mode1 may be displayed on the display panel 110 in the second mode Mode2 with the frequency changed to 1 Hz.

[0162] For example, in the second mode Mode2 driven at 1 Hz, the display device 100 may display the image data displayed in the last frame of the first mode Mode1 on the display panel 110 once, and may not display the image data during the remaining time.

[0163] In this case, the subpixel SP may display image data once in the second mode Mode2, but may maintain the voltage stored in the storage capacitor Cst for the rest of the time. As described above, the period during which the voltage stored in the storage capacitor Cst is maintained and image data is not transmitted to the display panel 110 may be referred to as a skip frame. For example, when the driving frequency is 120 Hz, the first frame of the second mode Mode2 will be a refresh frame for displaying image data, and the remaining frames will be skip frames in which image data is not transmitted.

[0164] As described above, by not transmitting the image data DATA during a specific period (eg, frame skipping) in the second mode Mode2 driven at a low-speed driving frequency lower than the high-speed driving frequency, power consumption can be reduced.

[0165] However, in the process of switching from the first mode Mode 1 driven at a high speed driving frequency to the second mode Mode 2 driven at a low speed driving frequency, a flicker phenomenon may occur due to brightness deviation.

[0166] Figure 7 1 shows a driving timing in the second mode of driving at a low-speed driving frequency in the display device according to the embodiment of the present invention.

[0167] Reference Figure 7 In the display device 100 according to the embodiment of the present invention, the second mode Mode2 driven at a low speed driving frequency may include a first period and a second period divided from one frame period based on the synchronization signal SYNC.

[0168] The first period may be a refresh frame for displaying the image data DATA, and the second period may be a skip frame for not transmitting the image data DATA.

[0169] The data voltage Vdata, the stabilization voltage Vini, and the reset voltage VAR for driving the sub-pixel SP may be provided during the refresh frame.

[0170] The refresh frame is a period for initializing the voltage charged or retained in the storage capacitor Cst and the drive transistor DRT. The refresh frame can be partially set within the start period of each frame in the low-speed second mode Mode2. The effects of the data voltage Vdata and the drive voltage stored in the subpixel SP in the high-speed first mode Mode1 can be removed in the refresh frame.

[0171] After the refresh operation is completed within the refresh frame, the light emitting element ED may emit light according to the data voltage Vdata supplied to the sub-pixel SP.

[0172] Meanwhile, a sampling process Sampling for compensating a characteristic value (threshold voltage or mobility) of the driving transistor DRT may be performed within the refresh frame.

[0173] For example, when the first switching transistor T1 is turned on by the first scan signal SCAN1 to electrically connect the gate and source of the driving transistor DRT, the gate and source of the driving transistor DRT have substantially equal potentials. At this point, when the second switching transistor T2 is turned on by the second scan signal SCAN2 to provide the data voltage Vdata, a current path is formed until the voltage difference Vgs between the gate and source of the driving transistor DRT reaches the threshold voltage of the driving transistor DRT. As a result, the gate and source voltages of the driving transistor DRT are charged.

[0174] That is, when the data voltage Vdata is supplied to the drain of the driving transistor DRT, the voltages of the gate and source of the driving transistor DRT rise to the voltage difference between the data voltage and the threshold voltage, thereby compensating for the threshold voltage of the driving transistor DRT.

[0175] As described above, the process of compensating the characteristic value of the driving transistor DRT through the sampling process may correspond to internal compensation.

[0176] The frame skipping is a period for charging or setting the data voltage Vdata and the driving voltage of each frame, and the frame skipping continues until the refresh frame of the next frame starts after the refresh frame of each frame is completed.

[0177] In the frame skipping, the driving transistor DRT and the light emitting element ED are driven according to the scan signal SCAN and the light emitting signal EM. That is, the initialization operation and supply of the data voltage Vdata can be performed in the refresh frame period of one frame cycle, and the light emitting element ED can emit light in the frame skipping period.

[0178] In the frame skipping, the anode of the light emitting element ED is reset to the reset voltage VAR. In this case, the anode of the light emitting element ED can be reset to a predetermined voltage to improve flicker generated while the frame skipping is continued by the low-speed driving operation in the frame skipping.

[0179] Specifically, the data voltage Vdata in the skip frame maintains a low logic level L. Meanwhile, in order to reduce a hysteresis effect that may occur in the driving transistor DRT and improve response characteristics, a bias voltage VOBS may be provided in the skip frame.

[0180] For example, the driving transistor DRT may be in an on-bias state, in which a large current flows between the drain and source of the driving transistor DRT by supplying a peak white grayscale voltage to the gate of the driving transistor DRT.

[0181] On the other hand, the driving transistor DRT may be in an off-bias state in which no current flows between the drain and source of the driving transistor DRT by supplying the peak black grayscale voltage to the gate of the driving transistor DRT.

[0182] The peak white grayscale voltage refers to the voltage supplied to the gate of the driving transistor DRT so that the light-emitting element ED emits light at the peak white grayscale, and the peak black grayscale voltage refers to the voltage supplied to the gate of the driving transistor DRT so that the light-emitting element ED emits light at the peak black grayscale. For example, when the grayscale values ​​are expressed as 8-bit digital values, the peak black grayscale may represent the minimum value "0" and the peak white grayscale may represent the maximum value "255".

[0183] At this time, since sweep curves of the on-bias state and the off-bias state in the P-type driving transistor DRT are different, currents flowing between the drain and the source of the driving transistor DRT may be different at the same gray level.

[0184] At this time, during grayscale expression, due to the voltage deviation between the gate and source of the driving transistor DRT, the current characteristics flowing between the drain and source of the driving transistor DRT change between the on-bias state and the off-bias state. This phenomenon is called hysteresis, which can cause afterimages.

[0185] In addition, the driving current difference flowing through the drain and source of the driving transistor DRT makes the driving characteristics of the light emitting element ED unstable, which may cause brightness deviation.

[0186] In particular, when the operation mode of the display device 100 changes from the first mode Mode1 driven at a high-speed driving frequency to the second mode Mode2 driven at a low-speed driving frequency lower than the high-speed driving frequency, afterimages due to the hysteresis phenomenon can be easily recognized.

[0187] Therefore, while the display device 100 is operating in the second mode Mode2 driven at a low speed driving frequency, on-bias processing OBS1 and OBS2 for setting the driving transistor DRT to an on-bias state can be performed before the light-emitting period starts due to the light-emitting signal EM of the low logic level L, so as to reduce the afterimage recognized due to the hysteresis phenomenon.

[0188] To achieve the above purpose, the driving transistor DRT may be placed in an on-bias state by supplying a bias voltage VOBS to the drain or source of the driving transistor DRT before the light emitting period begins.

[0189] For example, in the frame skipping of the second mode Mode2 driven at a low speed driving frequency, the bias voltage VOBS may be supplied to the drain of the driving transistor DRT through the data line DL before the light emitting period begins.

[0190] Alternatively, in the frame skipping of the second mode Mode2 driven at a low speed driving frequency, the bias voltage VOBS may be supplied to the source of the driving transistor DRT through a separate bias voltage supply line before the light emitting period starts.

[0191] Here, as an example, a case is shown where the bias voltage VOBS is supplied to the drain of the driving transistor DRT through the data line DL before the light emitting period starts in the frame skipping of the second mode Mode2 driven at a low speed driving frequency.

[0192] During the frame skipping, the first scan signal SCAN1 and the third scan signal SCAN3 maintain a low logic level L, and the second scan signal SCAN2 and the fourth scan signal SCAN4 maintain a high logic level H.

[0193] Therefore, the data voltage Vdata is not provided during the frame skipping. In addition, the first switching transistor T1 and the fourth switching transistor T4 remain in the off state during the frame skipping.

[0194] The second and fourth scan signals SCAN2 and SCAN4 may be supplied to odd and even gate lines with a phase difference, and may maintain a low logic level L during a portion of the skip frame and a high logic level H during the remaining period.

[0195] The second switching transistor T2 is turned on during a period when the second scan signal SCAN2 maintains a low logic level L, and the sixth switching transistor T6 is turned on during a period when the fourth scan signal SCAN4 maintains a low logic level L.

[0196] During the frame skip period, the second switching transistor T2 in the on state provides the bias voltage VOBS to the driving transistor DRT, and the sixth switching transistor T6 in the on state provides the reset voltage VAR to the anode of the light emitting element ED.

[0197] The emission signal EM maintains a high logic level H during the skip frame. The third switching transistor T3 and the fourth switching transistor T4 are turned on during a period in which the emission signal EM maintains a low logic level L.

[0198] Since the luminescence signal EM maintains a high logic level H during the frame skipping, the third and fourth switching transistors T3 and T4 are turned off, so that the current of the driving transistor DRT can be cut off while the anode of the luminescence element ED is reset.

[0199] Figure 8 A diagram illustrating a change in a mode of image data displayed via a display panel in a display device according to an embodiment of the present invention.

[0200] Reference Figure 8 , when the image data DATA provided to the display panel 110 is a moving image, in the display device 100 according to the embodiment of the present invention, a pattern of the image data DATA displayed via the display panel 110 changes over time.

[0201] Therefore, as the pattern of the image data DATA changes, an on-pixel ratio (OPR) of the sub-pixels SP emitting light via the display panel 110 during one frame changes, and the grayscale of the display panel 110 during one frame changes.

[0202] When the display panel 110 has an on-pixel ratio (OPR) of a low grayscale level close to black during one frame, since the number of sub-pixels SP provided with the high-potential driving voltage VDD is small, the magnitude of the voltage drop (IR drop) of the high-potential driving voltage VDD transmitted through the display panel 110 is reduced.

[0203] On the other hand, when the display panel 110 has an on-pixel ratio (OPR) with a high grayscale level close to white during one frame, since the number of sub-pixels SP provided with the high-potential driving voltage VDD is large, the magnitude of the voltage drop (IR drop) of the high-potential driving voltage VDD transmitted through the display panel 110 increases.

[0204] As described above, since the voltage drop of the high potential driving voltage VDD supplied to the display panel 110 changes as the pattern of the image data DATA changes, deviation occurs in the reference gamma voltages VREG1 and VREG2 generated by the gamma voltage generating circuit 170 using the high potential driving voltage VDD as a reference voltage.

[0205] Figure 9 A conceptual diagram illustrating a phenomenon in which a deviation occurs in a reference gamma voltage according to a change in an image data pattern in a display device according to an embodiment of the present invention.

[0206] Reference Figure 9 In the gamma voltage generating circuit 170 of the display device 100 according to an embodiment of the present invention, the first reference gamma voltage output circuit 172 generating the first reference gamma voltage VREG1 and the second reference gamma voltage output circuit 174 generating the second reference gamma voltage VREG2 may use the high potential driving voltage VDD as the reference voltage Vref.

[0207] In this case, since the on-pixel ratio (OPR) of the display panel 110 changes according to the mode change of the input image data DATA, the level of the high-potential driving voltage VDD transmitted through the display panel 110 may change. Therefore, the first reference gamma voltage VREG1 generated from the first reference gamma voltage output circuit 172 and the second reference gamma voltage VREG2 generated from the second reference gamma voltage output circuit 174 may change.

[0208] As a result, the data voltage Vdata supplied to the display panel 110 in the refresh frame period varies according to the pattern of the image data DATA, while the bias voltage VOBS supplied to the display panel 110 has a constant value in the frame skip period (see FIG. 1 ). Figure 9 Therefore, the large brightness deviation between the refresh frame period and the frame skip period can be recognized as flicker from the user's perspective.

[0209] In order to reduce the defects of image quality, the display device 100 of the present invention controls the reference gamma voltages VREG1, VREG2 and the bias voltage VOBS together based on the high-potential driving voltage VDD, thereby reducing the brightness deviation between the refresh frame period and the frame skipping period and improving the image quality degradation caused by flicker.

[0210] To achieve the above objectives, the display device 100 of the present invention may include a high-potential driving voltage feedback line for detecting the high-potential driving voltage VDD provided to the display panel 110 .

[0211] Figure 10 A structure for generating a reference gamma voltage and a bias voltage by using a feedback high potential driving voltage detected through a high potential driving voltage feedback line in a display device according to an embodiment of the present invention is shown.

[0212] Reference Figure 10According to an embodiment of the present invention, a display device 100 may include: a display panel 110, in which a driving voltage line DVL for providing a high-potential driving voltage VDD and a high-potential driving voltage feedback line VDD_FL for providing a feedback high-potential driving voltage VDD_FB are provided; a power management circuit 150 for providing the high-potential driving voltage VDD to the display panel 110; and a data driving circuit 130 for generating a reference gamma voltage VREG and a bias voltage VOBS using the feedback high-potential driving voltage VDD_FB.

[0213] The bias voltage generating circuit (not shown) for generating the bias voltage VOBS to reduce the hysteresis of the driving transistor DRT may be located in the power management circuit 150 or in the data driving circuit 130. Here, it is shown as being located in the data driving circuit 130.

[0214] The data driving circuit 130 may receive a feedback high potential driving voltage VDD_FB transmitted through a high potential driving voltage feedback line VDD_FL disposed on the display panel 110 and generate a reference gamma voltage VREG corresponding to a variation value of the high potential driving voltage VDD.

[0215] In addition, the data driving circuit 130 may include a bias voltage generating circuit that receives the feedback high potential driving voltage VDD_FB transmitted via the high potential driving voltage feedback line VDD_FL arranged on the display panel 110 and generates a bias voltage VOBS corresponding to the change value of the high potential driving voltage VDD.

[0216] Levels and output timings of the bias voltage VOBS and the data voltage Vdata of the data driving circuit 130 may be controlled by the timing controller 140 .

[0217] The high potential driving voltage VDD may be transmitted through driving voltage lines DVL, which extend through the data driving circuit 130 and are arranged in horizontal and vertical directions on the display panel 110 .

[0218] At this time, the high-potential driving voltage feedback line VDD_FL may be connected to the ends of the driving voltage line DVL arranged on the left and right sides of the display panel 110, respectively. The high-potential driving voltage feedback line VDD_FL may extend from one end of the driving voltage line DVL arranged outside the display panel 110 and be electrically connected to the data driving circuit 130. The feedback high-potential driving voltage VDD_FB transmitted via the high-potential driving voltage feedback line VDD_FL is provided to the data driving circuit 130.

[0219] At this time, the high potential driving voltage feedback line VDD_FL for transmitting the feedback high potential driving voltage VDD_FB may be arranged on the side of the display panel 110, or may be arranged in a loop along a non-display area surrounding the display area of ​​the display panel 110. The high potential driving voltage feedback line VDD_FL may be arranged in various shapes in the display panel 110.

[0220] Figure 11 A view showing a transmission path of a high-potential driving voltage in a display device according to an embodiment of the present invention.

[0221] Here, Figure 2 Part A shown in Figure 11 Shown in.

[0222] Reference Figure 11 In the display device 100 according to the embodiment of the present invention, a plurality of sub-pixels SP defined by a plurality of data lines DL and a plurality of gate lines GL crossing each other are provided on the display panel 110 .

[0223] In this case, each sub-pixel SP receives a high-potential driving voltage VDD through a plurality of driving voltage lines DVL arranged in parallel with a plurality of data lines DL.

[0224] The plurality of driving voltage lines DVL may be respectively arranged between and in parallel with the plurality of data lines DL, or may be arranged to be shared between two adjacent left and right sub-pixels SP.

[0225] The plurality of driving voltage lines DVL may be commonly connected to a common driving voltage line 135 disposed in an upper bezel region of the display panel 110 .

[0226] The high potential driving voltage VDD transmitted from the power management circuit 150 may be provided to the common driving voltage line 135 via the plurality of data driving circuits 130 .

[0227] In order to transmit the high potential driving voltage VDD to the plurality of driving voltage lines DVL, a first driving voltage supply line 131 , a second driving voltage supply line 132 , a third driving voltage supply line 133 , and a fourth driving voltage supply line 134 may be provided.

[0228] The first driving voltage supply line 131 , the second driving voltage supply line 132 , and the third driving voltage supply line 133 may be electrically connected to one another in the source printed circuit board SPCB.

[0229] The fourth driving voltage supply line 134 may be arranged to branch to both sides or one side of the source driving integrated circuit SDIC in the data driving circuit 130 .

[0230] The third driving voltage supply line 133 may be disposed in a region adjacent to the source film SP and electrically connected to the fourth driving voltage supply line 134 disposed in the data driving circuit 130 .

[0231] Since the first driving voltage supply line 131 is a portion where the high potential driving voltage VDD transmitted from the power management circuit 150 is densely supplied, the first driving voltage supply line 131 may have a relatively larger area than that of the third driving voltage supply line 133 .

[0232] The second driving voltage supply line 132 branches from the first driving voltage supply line 131 and may be arranged to have a constant interval. In addition, the second driving voltage supply line 132 is connected to the third driving voltage supply line 133.

[0233] At this time, since the second driving voltage supply line 132 is arranged at the front end of the area where the high-potential driving voltage VDD branches through the multiple driving voltage lines DVL, the second driving voltage supply line 132 can have a relatively higher current density than the current density of the fourth driving voltage supply line 134 and the current density of the driving voltage line DVL.

[0234] Therefore, since the temperature of the second driving voltage supply line 132 increases due to the high-density current, the possibility of failure increases.

[0235] Meanwhile, the high potential driving voltage VDD may be provided by arranging several source driving integrated circuits SDIC in units of groups, so the data driving circuit 130 may be formed into groups.

[0236] Figure 12 FIG. 1 shows a structural diagram of a gamma voltage generating circuit and a bias voltage generating circuit in a display device according to an embodiment of the present invention.

[0237] Reference Figure 12 According to an embodiment of the present invention, the data driving circuit 130 of the display device 100 may include a gamma voltage generating circuit 170 and a bias voltage generating circuit 180 using the feedback high potential driving voltage VDD_FB as a reference voltage, and a multiplexer MUX for selectively transmitting the data voltage Vdata or the bias voltage VOBS to the display panel 110 through the selection signal SEL.

[0238] The gamma voltage generating circuit 170 may include: a first reference gamma voltage output circuit 172 that generates a first reference gamma voltage VREG1 using a circuit driving voltage DDVDH; a second reference gamma voltage output circuit 174 that generates a second reference gamma voltage VREG2 using the circuit driving voltage DDVDH; and a plurality of resistor strings R for dividing the first reference gamma voltage VREG1 and the second reference gamma voltage VREG2.

[0239] The first reference gamma voltage output circuit 172 and the second reference gamma voltage output circuit 174 can be configured as a low dropout (LDO) circuit that converts the feedback high potential driving voltage VDD_FB into a desired specific output voltage. Such an LDO circuit can be used to stably generate an output voltage when the difference between the input voltage and the output voltage is not large.

[0240] The first reference gamma voltage output circuit 172 may receive the feedback high potential driving voltage VDD_FB and stably generate the first reference gamma voltage VREG1 by applying the first offset voltage VDC1 to the feedback high potential driving voltage VDD_FB.

[0241] In addition, the second reference gamma voltage output circuit 174 may receive the feedback high potential driving voltage VDD_FB and stably generate the second reference gamma voltage VREG2 by applying the second offset voltage VDC2 to the feedback high potential driving voltage VDD_FB.

[0242] The first reference gamma voltage VREG1 may be a gamma voltage of 0 gray level G0 supplied to an upper end of the resistor string, and the second reference gamma voltage VREG2 may be a gamma voltage of 255 gray level G255 supplied to a lower end of the resistor string.

[0243] Therefore, the gamma voltage generating circuit 170 can generate gamma voltages corresponding to multiple gray levels (for example, 0 gray level G0, 1 gray level G1, 3 gray level G3, 15 gray level G15, 31 gray level G31, 63 gray level G63, 127 gray level G127, 191 gray level G191 and 255 gray level G255) by dividing the first reference gamma voltage VREG1 and the second reference gamma voltage VREG2 according to the change of the high-potential driving voltage VDD provided to the display panel 110.

[0244] The bias voltage generating circuit 180 may receive the feedback high potential driving voltage VDD_FB and stably generate the bias voltage VOBS by applying the third offset voltage VDC3 to the feedback high potential driving voltage VDD_FB.

[0245] The bias voltage generating circuit 180 may be formed of a low dropout output (LDO) circuit for converting the feedback high potential driving voltage VDD_FB into a desired specific output voltage.

[0246] As a result, the gamma voltage generation circuit 170 generates the reference gamma voltages VREG1 and VREG2 by applying a variation to the feedback high-potential driving voltage VDD_FB, and the bias voltage generation circuit 180 generates the bias voltage VOBS by applying a variation to the feedback high-potential driving voltage VDD_FB. Therefore, even if the pattern of the image data DATA changes, the deviation between the data voltage Vdata provided during the refresh frame period and the bias voltage VOBS provided during the frame skip period can be reduced, and flicker can be improved.

[0247] According to the selection signal SEL provided from the timing controller 140 , the multiplexer MUX may provide the data voltage Vdata through the data line DL in the refresh frame period and provide the bias voltage VOBS through the data line DL in the skip frame period.

[0248] Figure 13 A diagram illustrating a situation in which a deviation between a data voltage and a bias voltage is kept constant even if an on-pixel ratio (OPR) is changed in a display device according to an embodiment of the present invention.

[0249] Reference Figure 13 , in the display device 100 according to the embodiment of the present invention, when the image data DATA provided to the display panel 110 is moving image data, a pattern of the image data DATA displayed via the display panel 110 may change over time.

[0250] Therefore, as the pattern of the image data DATA changes, the on-pixel ratio (OPR) of the sub-pixels SP emitting light via the display panel 110 changes at each frame, and the grayscale of the display panel 110 changes over time within one frame period.

[0251] For example, the mode of the image data DATA displayed via the display panel 110 may be changed from a low on-pixel ratio (OPR) of a low grayscale to a high on-pixel ratio (OPR) of a high grayscale.

[0252] When the display panel 110 has a low grayscale on-pixel ratio (OPR) close to black during one frame, the high potential driving voltage VDD is supplied to a smaller number of sub-pixels SP. Therefore, the voltage drop (IR drop) of the high potential driving voltage VDD transmitted through the display panel 110 is reduced.

[0253] On the other hand, when the display panel 110 has a high grayscale on-pixel ratio (OPR) close to white during one frame, the high potential driving voltage VDD is supplied to a larger number of sub-pixels SP. Therefore, the voltage drop (IR drop) of the high potential driving voltage VDD transmitted through the display panel 110 increases.

[0254] As a result, since the voltage drop degree of the high-potential driving voltage VDD provided to the display panel 110 changes as the mode of the image data DATA changes, a brightness deviation may occur between the refresh frame period and the frame skip period due to the gamma voltage generating circuit 170 that uses the feedback high-potential driving voltage VDD_FB to generate the reference gamma voltages VREG1 and VREG2.

[0255] However, since the display device 100 of the present invention generates the bias voltage VOBS by using the feedback high potential driving voltage VDD_FB in the bias voltage generating circuit 180, the bias voltage VOBS having the same variation as the variation of the reference gamma voltages VREG1 and VREG2 can be generated (see FIG. Figure 13 The gap between VOBS and VREG1 Gap1 and the gap between VOBS and VREG Gap2).

[0256] As a result, the potential difference between the data voltage Vdata formed in the refresh frame period and the bias voltage VOBS in the frame skip period can be maintained at the same level, so the flicker between the refresh frame period and the frame skip period can be reduced.

[0257] Figure 14 A conceptual diagram illustrating a phenomenon in which a reference gamma voltage and a bias voltage have the same amount of change according to a change in an image data pattern in a display device according to an embodiment of the present invention.

[0258] Reference Figure 14 According to an embodiment of the present invention, the gamma voltage generating circuit 170 in the display device 100 may include a first reference gamma voltage output circuit 172 for generating a first reference gamma voltage VREG1 and a second reference gamma voltage output circuit 174 for generating a second reference gamma voltage VREG2. The first reference gamma voltage output circuit 172 and the second reference gamma voltage output circuit 174 may each use the feedback high potential driving voltage VDD_FB as a reference voltage Vref.

[0259] In this case, the on-pixel ratio (OPR) of the display panel 110 changes according to the mode change of the input image data DATA. As a result, the level of the feedback high-potential driving voltage VDD_FB transmitted through the display panel 110 may change, and the first reference gamma voltage VREG1 generated from the first reference gamma voltage output circuit 172 and the second reference gamma voltage VREG2 generated from the second reference gamma voltage output circuit 174 may change.

[0260] However, since the bias voltage generating circuit 180 also generates the bias voltage VOBS by using the feedback high potential driving voltage VDD_FB as a reference voltage, the bias voltage VOBS has the same variation as that of the reference gamma voltages VREG1 , VREG2 .

[0261] As a result, even if the data voltage Vdata changes according to the pattern of the image data DATA, that is, the level of the high-potential driving voltage VDD, the bias voltage VOBS supplied to the display panel 110 during the frame skip period also changes by the same amount according to the level of the high-potential driving voltage VDD. Therefore, the deviation (or gap) between the data voltage Vdata during the refresh frame period and the bias voltage VOBS during the frame skip period is also maintained at the same level (the data voltage Vdata and the bias voltage VOBS change by the same amount).

[0262] As described above, the display device 100 of the present invention can reduce the luminance deviation between the refresh frame period and the frame skip period by associating the reference gamma voltages VREG1 and VREG2 and the bias voltage VOBS with the high potential driving voltage VDD, and can improve image quality degradation caused by flicker.

[0263] Figure 15 FIG. 1 is a flow chart of a display driving method according to an embodiment of the present invention.

[0264] Reference Figure 15 , a display driving method according to an embodiment of the present invention may include: step S100, receiving a feedback high potential driving voltage VDD_FB via a high potential driving voltage feedback line VDD_FL; step S200, generating a reference gamma voltage VREG by using the feedback high potential driving voltage VDD_FB; step S300, generating a bias voltage VOBS by using the feedback high potential driving voltage VDD_FB; step S400, providing a data voltage Vdata using the reference gamma voltage VREG in a refresh frame period; and step S500, providing the bias voltage VOBS in a frame skip period.

[0265] The step S100 of receiving the feedback high potential driving voltage VDD_FB through the high potential driving voltage feedback line VDD_FL is a process of receiving the feedback high potential driving voltage VDD_FB transmitted through the high potential driving voltage feedback line VDD_FL disposed on the display panel 110 .

[0266] The step S200 of generating the reference gamma voltages VREG by using the feedback high potential driving voltage VDD_FB is a process of generating the first and second reference gamma voltages VREG1 and VREG2 using the feedback high potential driving voltage VDD_FB in the gamma voltage generating circuit 170 .

[0267] The first and second reference gamma voltages VREG1 and VREG2 are used to generate the data voltage Vdata via the resistor string.

[0268] The step S300 of generating the bias voltage VOBS by using the feedback high potential driving voltage VDD_FB is a process of generating the bias voltage VOBS associated with the variation amount of the reference gamma voltage using the feedback high potential driving voltage VDD_FB in the bias voltage generating circuit 180 .

[0269] The step S400 of providing the data voltage Vdata using the reference gamma voltage VREG in the refresh frame period is a process of providing the data voltage Vdata to the display panel 110 during the refresh frame period through the selection signal SEL of the timing controller 140 .

[0270] The step S500 of providing the bias voltage VOBS in the frame skip period is a process of providing the bias voltage VOBS to the display panel 110 in the frame skip period through the selection signal SEL of the timing controller 140 .

[0271] Through the above display driving method, the display device 100 of the present invention can reduce the brightness deviation between the refresh frame period and the frame skipping period by associating the reference gamma voltages VREG1, VREG2 and the bias voltage VOBS with the high potential driving voltage VDD, and improve the image quality degradation caused by flicker.

[0272] Figure 16 Another sub-pixel circuit diagram in a display device according to an embodiment of the present invention is shown.

[0273] Reference Figure 16 , the sub-pixel SP of the display device 100 according to the embodiment of the present invention includes first to seventh switching transistors T1 - T7 , a driving transistor DRT, a storage capacitor Cst, and a light emitting element ED.

[0274] Here, the light-emitting element ED may be, for example, a self-luminous element capable of emitting light by itself, such as an organic light-emitting diode OLED.

[0275] In the subpixel SP according to the embodiment of the present invention, the second to fourth switching transistors T2-T4, the sixth switching transistor T6, the seventh switching transistor T7 and the driving transistor DRT may be P-type transistors. In addition, the first switching transistor T1 and the fifth switching transistor T5 may be N-type transistors.

[0276] P-type transistors are relatively more reliable than N-type transistors. P-type transistors have the advantage that, because their drains are fixed to a high-potential drive voltage VDD, the current flowing through the light-emitting element ED does not fluctuate due to the storage capacitor Cst. Therefore, current can be stably supplied.

[0277] For example, a P-type transistor may be connected to the anode of the light-emitting element ED. In this case, when the transistors T4 and T6 connected to the light-emitting element ED operate in the saturation region, a constant current can flow regardless of changes in the current and threshold voltage of the light-emitting element ED. Therefore, reliability is relatively high.

[0278] In this sub-pixel SP structure, the N-type transistors T1 and T5 can be oxide transistors formed using semiconductor oxides (for example, transistors having a channel formed by a semiconductor oxide such as indium, gallium, zinc oxide or IGZO), and the other P-type transistors DRT, T2-T4, T6, and T7 can be silicon transistors formed by a semiconductor such as silicon (for example, transistors having a polysilicon channel formed by a low-temperature process such as LTPS or low-temperature polysilicon).

[0279] Oxide transistors have relatively low leakage current compared to silicon transistors. Therefore, when implemented using oxide transistors, leakage current from the gate of the drive transistor DRT is reduced, which has the effect of reducing image quality defects such as flicker.

[0280] Meanwhile, the remaining P-type transistors DRT, T2 - T4 , T6 , and T7 excluding the first and fifth switching transistors T1 and T5 corresponding to N-type transistors may be formed of low-temperature polysilicon.

[0281] The first scan signal SCAN1 is provided to the gate of the first switch transistor T1. The drain of the first switch transistor T1 is connected to the gate of the drive transistor DRT. The source of the first switch transistor T1 is connected to the source of the drive transistor DRT.

[0282] The first switching transistor T1 is turned on by the first scan signal SCAN1 and controls the operation of the driving transistor DRT using the high potential driving voltage VDD stored in the storage capacitor Cst.

[0283] The first switch transistor T1 may be formed by an N-type MOS transistor to constitute an oxide transistor. Since the N-type MOS transistor uses electrons as carriers, it has higher mobility and faster switching speed than the P-type MOS transistor.

[0284] The second scan signal SCAN2 is provided to the gate of the second switching transistor T2. The data voltage Vdata is provided to the drain of the second switching transistor T2. The source of the second switching transistor T2 is connected to the drain of the driving transistor DRT.

[0285] The second switching transistor T2 is turned on by the second scan signal SCAN2 to provide the data voltage Vdata to the drain of the driving transistor DRT.

[0286] The light emitting signal EM is supplied to the gate of the third switch transistor T3, the high potential driving voltage VDD is supplied to the drain of the third switch transistor T3, and the source of the third switch transistor T3 is connected to the drain of the driving transistor DRT.

[0287] The third switch transistor T3 is turned on by the light emitting signal EM to provide the high potential driving voltage VDD to the drain of the driving transistor DRT.

[0288] The emission signal EM is provided to the gate of the fourth switch transistor T4. The drain of the fourth switch transistor T4 is connected to the source of the drive transistor DRT. The source of the fourth switch transistor T4 is connected to the anode of the light emitting element ED.

[0289] The fourth switching transistor T4 is turned on by the light emitting signal EM to provide a driving current to the anode of the light emitting element ED.

[0290] The third scan signal SCAN3 is provided to the gate of the fifth switching transistor T5.

[0291] Here, the third scan signal SCAN3 may be the first scan signal SCAN1 provided to the sub-pixel SP located at another position. For example, when the first scan signal SCAN1 is provided to the nth gate line, the third scan signal SCAN3 may be the first scan signal SCAN1 provided to the (n-9)th gate line. That is, depending on the driving phase of the display panel 110, the third scan signal SCAN3 may serve as the first scan signal SCAN1 at another gate line GL.

[0292] The stabilized voltage Vini is supplied to the drain of the fifth switch transistor T5. The source of the fifth switch transistor T5 is connected to the gate of the drive transistor DRT and the storage capacitor Cst.

[0293] The fifth switch transistor T5 is turned on by the third scan signal SCAN3 to provide the stabilized voltage Vini to the gate of the driving transistor DRT.

[0294] The fourth scan signal SCAN4 is provided to the gate of the sixth switching transistor T6.

[0295] The reset voltage VAR is supplied to the drain of the sixth switch transistor T6. The source of the sixth switch transistor T6 is connected to the anode of the light emitting element ED.

[0296] The sixth switching transistor T6 is turned on by the fourth scan signal SCAN4 to provide the reset voltage VAR to the anode of the light emitting element ED.

[0297] The fifth scan signal SCAN5 is provided to the gate of the seventh switching transistor T7.

[0298] The bias voltage VOBS is provided to the drain of the seventh switch transistor T7. The source of the seventh switch transistor T7 is connected to the drain of the driving transistor DRT.

[0299] Here, the fifth scan signal SCAN5 may be the fourth scan signal SCAN4 having a different phase provided to a sub-pixel SP located at another position. For example, when the fourth scan signal SCAN4 is provided to the nth gate line, the fifth scan signal SCAN5 may be the fourth scan signal SCAN4 provided to the (n-1)th gate line. That is, depending on the driving phase of the display panel 110, the fifth scan signal SCAN5 may serve as the fourth scan signal SCAN4 at another gate line GL.

[0300] Meanwhile, since the fifth scan signal SCAN5 is a signal for providing the bias voltage VOBS to the driving transistor DRT, it may be different from the second scan signal SCAN2 for providing the data voltage Vdata.

[0301] The gate of the driving transistor DRT is connected to the drain of the first switching transistor T1 , the drain of the driving transistor DRT is connected to the source of the second switching transistor T2 , and the source of the driving transistor DRT is connected to the source of the first switching transistor T1 .

[0302] The driving transistor DRT is turned on by the voltage difference between the source and the drain of the first switching transistor T1 to supply the driving current to the light emitting element ED.

[0303] The high potential driving voltage VDD is supplied to one end of the storage capacitor Cst, and the other end of the storage capacitor Cst is connected to the gate of the driving transistor DRT. The storage capacitor Cst stores the voltage of the gate of the driving transistor DRT.

[0304] The anode of the light emitting element ED is connected to the source of the fourth switching transistor T4 and the source of the sixth switching transistor T6. The low potential driving voltage VSS is supplied to the cathode of the light emitting element ED.

[0305] The light emitting element ED emits light with predetermined brightness according to a driving current controlled by the driving transistor DRT.

[0306] At this time, the stabilization voltage Vini is supplied to stabilize the change in capacitance formed at the gate of the driving transistor DRT, and the reset voltage VAR is supplied to reset the anode of the light emitting element ED.

[0307] When the reset voltage VAR is supplied to the anode of the light emitting element ED in a state in which the fourth switching transistor T4 is turned off, the anode of the light emitting element ED may be reset.

[0308] The sixth switching transistor T6 for providing the reset voltage VAR is connected to the anode of the light emitting element ED.

[0309] In order to separately perform the driving operation of the driving transistor DRT and the resetting operation of the anode of the light emitting element ED, the third scan signal SCAN3 for driving or stabilizing the driving transistor DRT and the fourth scan signal SCAN4 for controlling the supply of the reset voltage VAR to the anode of the light emitting element ED are separated from each other.

[0310] When the switching transistors T5 and T6 for providing the stabilization voltage Vini and the reset voltage VAR are turned on, the fourth switching transistor T4, which connects the source of the driving transistor DRT to the anode of the light-emitting element ED, can be turned off. As a result, the driving current of the driving transistor DRT is blocked from flowing to the anode of the light-emitting element ED, so that the anode is not affected by voltages other than the reset voltage VAR.

[0311] As described above, the sub-pixel SP including the eight transistors DRT, T1, T2, T3, T4, T5, T6, and T7 and one capacitor Cst may be referred to as an 8T1C structure.

[0312] As previously described, an 8T1C structure is shown as an example of various types of sub-pixel SP circuits. The structure and number of transistors and capacitors constituting the sub-pixel SP may vary. At the same time, each of the plurality of sub-pixels SP may have the same structure, or some of the plurality of sub-pixels SP may have different structures.

[0313] The above description and the accompanying drawings provide examples of the technical concepts of the present invention for the purpose of illustration only. Those skilled in the art of the present invention will recognize that various modifications and changes in form, such as combinations, separations, substitutions, and changes in structure, are possible without departing from the essential features of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate the scope of the technical concepts of the present invention, and the scope of the present invention is not limited to these embodiments. The scope of the present invention should be interpreted based on the appended claims as all technical concepts included in the scope equivalent to the claims belong to the present invention.

Claims

1. A display device comprising: a display panel including a light emitting element, a driving transistor configured to supply a driving current to the light emitting element using a high potential driving voltage, and a plurality of switching transistors configured to control an operation of the driving transistor; a gate driving circuit configured to provide a plurality of scanning signals to the display panel; a data driving circuit configured to generate a data voltage or a bias voltage using a feedback high-potential driving voltage transmitted via a high-potential driving voltage feedback line; as well as a timing controller configured to control the gate driving circuit and the data driving circuit so that the data voltage is provided to the display panel in a first period of a low-speed mode and the bias voltage is provided to the display panel in a second period of the low-speed mode, The low-speed mode is driven at a predetermined driving frequency lower than the frequency of the high-speed mode.

2. The display device according to claim 1 , wherein the plurality of switching transistors comprises: a first switching transistor, wherein a first scanning signal is supplied to a gate of the first switching transistor, a drain of the first switching transistor is connected to the gate of the driving transistor, and a source of the first switching transistor is connected to the source of the driving transistor; a second switching transistor, wherein a second scan signal is supplied to a gate of the second switching transistor, the data voltage or the bias voltage is supplied to a drain of the second switching transistor, and a source of the second switching transistor is connected to a drain of the driving transistor; a third switch transistor, wherein a light emitting signal is supplied to a gate of the third switch transistor, a high potential driving voltage is supplied to a drain of the third switch transistor, and a source of the third switch transistor is connected to the drain of the driving transistor; a fourth switching transistor, wherein the light emitting signal is provided to a gate of the fourth switching transistor, a drain of the fourth switching transistor is connected to a source of the driving transistor, and a source of the fourth switching transistor is connected to an anode of the light emitting element; a fifth switching transistor, wherein a third scan signal is supplied to a gate of the fifth switching transistor, a stabilization voltage is supplied to a drain of the fifth switching transistor, and a source of the fifth switching transistor is connected to the gate of the driving transistor and a storage capacitor; as well as a sixth switching transistor, wherein the fourth scan signal is supplied to a gate of the sixth switching transistor, a reset voltage is supplied to a drain of the sixth switching transistor, and a source of the sixth switching transistor is connected to the anode of the light emitting element.

3. The display device according to claim 1 , wherein the plurality of switching transistors comprises: a first switching transistor, wherein a first scanning signal is supplied to a gate of the first switching transistor, a drain of the first switching transistor is connected to the gate of the driving transistor, and a source of the first switching transistor is connected to the source of the driving transistor; a second switching transistor, wherein the second scan signal is supplied to a gate of the second switching transistor, the data voltage is supplied to a drain of the second switching transistor, and a source of the second switching transistor is connected to the drain of the driving transistor; a third switch transistor, wherein a light emitting signal is supplied to a gate of the third switch transistor, a high potential driving voltage is supplied to a drain of the third switch transistor, and a source of the third switch transistor is connected to the drain of the driving transistor; a fourth switching transistor, wherein the light emitting signal is provided to a gate of the fourth switching transistor, a drain of the fourth switching transistor is connected to a source of the driving transistor, and a source of the fourth switching transistor is connected to an anode of the light emitting element; a fifth switching transistor, wherein a third scan signal is supplied to a gate of the fifth switching transistor, a stabilization voltage is supplied to a drain of the fifth switching transistor, and a source of the fifth switching transistor is connected to the gate of the driving transistor and a storage capacitor; a sixth switching transistor, wherein a fourth scan signal is supplied to a gate of the sixth switching transistor, a reset voltage is supplied to a drain of the sixth switching transistor, and a source of the sixth switching transistor is connected to an anode of the light emitting element; as well as a seventh switching transistor, wherein the fifth scan signal is supplied to a gate of the seventh switching transistor, the bias voltage is supplied to a drain of the seventh switching transistor, and a source of the seventh switching transistor is connected to the drain of the driving transistor. 4 . The display device according to claim 1 , wherein the high potential driving voltage feedback line extends from one end of a driving voltage line arranged outside the display panel and is electrically connected to the data driving circuit.

5. The display device according to claim 1 , wherein the data driving circuit comprises: a gamma voltage generating circuit configured to generate a reference gamma voltage by using the feedback high potential driving voltage as a reference voltage of the gamma voltage generating circuit; a bias voltage generating circuit configured to generate the bias voltage by using the feedback high-potential driving voltage as a reference voltage of the bias voltage generating circuit; a plurality of resistor strings configured to generate the data voltages by dividing the reference gamma voltage; as well as A multiplexer is configured to transmit the data voltage or the bias voltage to the display panel in response to a selection signal.

6. The display device according to claim 5, wherein the gamma voltage generating circuit comprises: a first reference gamma voltage output circuit configured to generate a first reference gamma voltage having a low grayscale by using the feedback high potential driving voltage as a reference voltage of the first reference gamma voltage output circuit; as well as a second reference gamma voltage output circuit configured to generate a second reference gamma voltage having a high grayscale by using the feedback high potential driving voltage as a reference voltage of the second reference gamma voltage output circuit.

7. The display device according to claim 6, wherein the first reference gamma voltage output circuit, the second reference gamma voltage output circuit, and the bias voltage generating circuit are low voltage drop output circuits configured to convert the feedback high potential driving voltage into a specific output voltage. 8 . The display device according to claim 1 , wherein the first period is a refresh frame period in which a data voltage for driving the light emitting element is supplied. 9 . The display device according to claim 1 , wherein the second period is a frame skip period in which the bias voltage is supplied but the data voltage is not supplied.

10. The display device of claim 1, wherein the data voltage and the bias voltage change by the same amount. 11 . The display device of claim 4 , wherein the driving voltage line extends through the data driving circuit and is arranged in horizontal and vertical directions on the display panel.

12. The display device according to claim 2, wherein the high potential driving voltage is supplied to one end of the storage capacitor, and the other end of the storage capacitor is connected to the gate electrode of the driving crystal. 13 . The display device according to claim 2 , wherein each of the first and fifth switching transistors comprises an oxide transistor, and each of the driving transistor, the second, third, fourth, and sixth switching transistors comprises a silicon transistor.

14. The display device according to claim 3, wherein each of the first switching transistor and the fifth switching transistor comprises an oxide transistor, and each of the driving transistor, the second switching transistor, the third switching transistor, the fourth switching transistor, the sixth switching transistor, and the seventh switching transistor comprises a silicon transistor. 15 . The display device according to claim 2 , wherein the third scan signal and the fourth scan signal are separate signals from each other. 16 . The display device of claim 6 , wherein the bias voltage changes with the same amount of change as the first and second reference gamma voltages.

17. A driving circuit comprising: a gamma voltage generating circuit configured to generate a reference gamma voltage by using a feedback high potential driving voltage as a reference voltage of the gamma voltage generating circuit; a bias voltage generating circuit configured to generate a bias voltage by using the feedback high-potential driving voltage as a reference voltage of the bias voltage generating circuit; a plurality of resistor strings configured to generate data voltages by dividing the reference gamma voltage; as well as A multiplexer is configured to transmit the data voltage or the bias voltage to a display panel in response to a selection signal.

18. The driving circuit according to claim 17, wherein the gamma voltage generating circuit comprises: a first reference gamma voltage output circuit that generates a first reference gamma voltage having a low grayscale by using the feedback high-potential driving voltage as a reference voltage; as well as a second reference gamma voltage output circuit that generates second reference gamma voltages having a high grayscale by using the feedback high potential driving voltage as a reference voltage.

19. The driving circuit according to claim 18, wherein the first reference gamma voltage output circuit, the second reference gamma voltage output circuit, and the bias voltage generating circuit are low voltage drop output circuits for converting the feedback high potential driving voltage into a specific output voltage.

20. The driving circuit of claim 17, wherein the data voltage and the bias voltage change by the same amount.

21. The driving circuit according to claim 17, wherein the data voltage is transmitted to the display panel during a first period of a low-speed mode of the display panel, and the bias voltage is transmitted to the display panel during a second period of the low-speed mode of the display panel, wherein the display panel is driven in the low-speed mode at a predetermined driving frequency lower than that in the high-speed mode.

22. The driving circuit according to claim 21, wherein the first period is a refresh frame period in which the data voltage is supplied. 23 . The driving circuit according to claim 21 , wherein the second period is a frame skip period in which the data voltage is not supplied and the bias voltage is supplied. 24 . The driving circuit of claim 18 , wherein the bias voltage changes with the same amount of change as the first and second reference gamma voltages.

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