A sealing ring, a stacked structure and a manufacturing method of the sealing ring

Abstract

Embodiments of the present disclosure provide a sealing ring, a stacked structure and a manufacturing method of the sealing ring. Among them, the sealing ring is disposed around the chip device area; the sealing ring includes an inner ring structure, a middle ring structure and an outer ring structure; the middle ring structure is connected to the device area through a doped well; the doped well is located in a partial substrate corresponding to the inner ring structure and the middle ring structure, and the doped well is isolated from the inner ring structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and relates to, but is not limited to, a sealing ring, a stacked structure, and a method for manufacturing a sealing ring. Background Art

[0002] A sealing ring is usually formed between the scribe line of each chip on a wafer and the peripheral area of an integrated circuit. When performing a wafer dicing process along the scribe line, the sealing ring can block the stress caused by the above-mentioned wafer dicing process from the scribe line to the integrated circuit. In addition, the sealing ring can also block the intrusion of impurity particles, water vapor, etc. into the internal devices of the chip.

[0003] In the related art, by setting the sealing ring structure into a double-layer structure to resist more serious intrusion into the chip. However, the resistance performance of the double-layer structure sealing ring is still limited, and the related art cannot detect the integrity of the sealing ring. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a sealing ring, a stacked structure, and a method for manufacturing a sealing ring.

[0005] In a first aspect, embodiments of the present disclosure provide a sealing ring, which is disposed around a chip device area, and the sealing ring includes: an inner ring structure, a middle ring structure, and an outer ring structure;

[0006] Wherein, the middle ring structure is connected to the device area through a doped well; the doped well is located in a part of the substrate corresponding to the inner ring structure and the middle ring structure, and the doped well is isolated from the inner ring structure.

[0007] In some embodiments, a test circuit is provided in the device area;

[0008] The middle ring structure is electrically connected to the test circuit through the doped well.

[0009] In some embodiments, the substrate includes a first surface and a second surface disposed opposite to each other, and the doped well is located in the first surface; the middle ring structure includes a first middle ring structure and a second middle ring structure;

[0010] Wherein, the first middle ring structure is disposed in a first dielectric layer on the first surface of the substrate;

[0011] The second middle ring structure is disposed in a second dielectric layer on the second surface of the substrate.

[0012] In some embodiments, the sealing ring is disposed in a stacked structure, and the stacked structure includes at least a first chip and a second chip stacked in sequence;

[0013] The first middle ring structure of the second chip is electrically connected to the test circuit through the doped well.

[0014] In some embodiments, the second middle ring structure of the first chip is connected to the first middle ring structure of the second chip.

[0015] In some embodiments, the first middle ring structure includes a plurality of metal layers, vias connecting the metal layers, and metal plugs connecting the substrate and the metal layers.

[0016] In some embodiments, the first surface of the substrate further includes a plurality of spaced-apart isolation regions and active regions;

[0017] The metal plugs of the first middle ring structure include a first metal plug and a second metal plug; wherein, the first metal plug is used to connect the active region to the first metal layer among the plurality of metal layers, and the second metal plug is used to connect the doped well to the second metal layer among the plurality of metal layers.

[0018] In some embodiments, the first metal layer of the first middle ring structure is not connected to the second metal layer of the first middle ring structure.

[0019] In some embodiments, the inner ring structure includes a first inner ring structure disposed in the first dielectric layer and a second inner ring structure disposed in the second dielectric layer;

[0020] The outer ring structure includes a first outer ring structure disposed in the first dielectric layer and a second outer ring structure disposed in the second dielectric layer.

[0021] In some embodiments, the first inner ring structure has the same structure as the first outer ring structure;

[0022] Wherein, the first inner ring structure includes a plurality of metal layers, vias connecting the metal layers, and metal plugs connecting the substrate and the third metal layer among the plurality of metal layers.

[0023] In some embodiments, the metal plugs of the first inner ring structure are disposed in the isolation region, and the metal plugs of the first outer ring structure are disposed in the active region.

[0024] In some embodiments, the second inner ring structure, the second middle ring structure, and the second outer ring structure all have the same structure;

[0025] Wherein, the second inner ring structure includes at least two metal layers and vias connecting adjacent metal layers.

[0026] In some embodiments, through-silicon vias are further provided in the device region;

[0027] The test circuit is connected to the surface of the topmost chip in the stacked structure through the through-silicon via.

[0028] In a second aspect, an embodiment of the present disclosure provides a stacked structure, which includes a plurality of the chips bonded face to back in sequence, and each of the chips includes at least the above-mentioned sealing ring.

[0029] In a third aspect, an embodiment of the present disclosure provides a method for manufacturing a sealing ring, where the sealing ring is disposed around a chip device area; the method includes:

[0030] Forming a doped well in the chip substrate;

[0031] Forming an inner ring structure, a middle ring structure, and an outer ring structure around the device area on the surface of the substrate;

[0032] Wherein, the inner ring structure, the middle ring structure, and the outer ring structure constitute the sealing ring; the middle ring structure is connected to the device area through the doped well; the doped well is located in a part of the substrate corresponding to the inner ring structure and the middle ring structure, and the doped well is isolated from the inner ring structure.

[0033] In some embodiments, forming the inner ring structure, the middle ring structure, and the outer ring structure around the device area on the surface of the substrate includes:

[0034] Respectively forming the inner ring structure, the middle ring structure, and the outer ring structure around the device area on a first surface and a second surface of the substrate; wherein, the first surface and the second surface are oppositely arranged, and the doped well is located in the first surface.

[0035] In some embodiments, before or after forming the doped well, forming a plurality of spaced-apart isolation regions and active regions in the first surface of the substrate;

[0036] The doped well is isolated from the inner ring structure through the isolation region.

[0037] In some embodiments, the inner ring structure at least includes a first inner ring structure located on the first surface of the substrate; the middle ring structure at least includes a first middle ring structure located on the first surface of the substrate; the outer ring structure at least includes a first outer ring structure located on the first surface of the substrate;

[0038] Forming the inner ring structure, the middle ring structure, and the outer ring structure in the first surface of the substrate includes:

[0039] Forming a first dielectric layer on the first surface of the substrate;

[0040] The first inner ring structure, the first middle ring structure, and the first outer ring structure are formed in the first dielectric layer.

[0041] In some embodiments, the inner ring structure further includes a second inner ring structure located on the second surface of the substrate; the middle ring structure further includes a second middle ring structure located on the second surface of the substrate; the outer ring structure further includes a second outer ring structure located on the second surface of the substrate;

[0042] A second dielectric layer is formed on the second surface of the substrate;

[0043] The second inner ring structure, the second middle ring structure, and the second outer ring structure are formed in the second dielectric layer.

[0044] In some embodiments, forming the first inner ring structure, the first middle ring structure, and the first outer ring structure in the first dielectric layer includes:

[0045] Etch the first dielectric layer to form a plurality of first etch holes; wherein, the first etch holes of the first inner ring structure expose the surface of the isolation region, the first etch holes of the first middle ring structure expose the surfaces of the active region and the doped well respectively, and the first etch holes of the first outer ring structure expose the surface of the active region;

[0046] Fill a first metal material in each of the first etch holes to form metal plugs;

[0047] Form a plurality of metal layers and vias connecting the metal layers on the surface of each of the metal plugs.

[0048] In some embodiments, the method includes:

[0049] Form a test circuit in the first dielectric layer on the surface of the device region;

[0050] Wherein, the first middle ring structure is electrically connected to the test circuit through the doped well.

[0051] In some embodiments, the sealing ring is disposed in a stacked structure, and the stacked structure includes a plurality of chips stacked in sequence; the method includes:

[0052] Form a through-silicon via structure in the device region;

[0053] The test circuit is connected to the surface of the topmost chip in the stacked structure through the through-silicon via.

[0054] In some embodiments, forming the second inner ring structure, the second middle ring structure, and the second outer ring structure in the second dielectric layer includes:

[0055] Etch the second dielectric layer to form a plurality of second etch holes;

[0056] Fill a second metal material in each of the second etch holes to respectively form a first metal layer of the second inner ring structure, the second middle ring structure, and the second outer ring structure;

[0057] Form at least one second metal layer on the surface of the first metal layer and through holes connecting the first metal layer and the second metal layer.

[0058] The sealing ring, stacked structure, and manufacturing method of the sealing ring provided by the embodiments of the present disclosure, wherein the sealing ring includes an inner ring structure, a middle ring structure, and an outer ring structure; the middle ring structure is connected to the device region through a doped well; the doped well is located in a part of the substrate corresponding to the inner ring structure and the middle ring structure, and the doped well is isolated from the inner ring structure. Since the sealing ring includes a middle ring structure, the chip strength can be further improved, and the reliability of the devices inside the chip can be protected; in addition, since the middle ring structure can be connected to the device region through a doped well, in this way, the integrity of the sealing ring can be detected by setting a specific test circuit in the device region. Description of the Drawings

[0059] In the drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The drawings generally illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0060] Figure 1a is a schematic structural diagram of a sealing ring in the related art;

[0061] Figure 1b is a schematic structural diagram of a stacked chip in the related art;

[0062] Figure 2 is a schematic structural diagram of a sealing ring provided by an embodiment of the present disclosure;

[0063] Figure 3a is a top view of a sealing ring provided by an embodiment of the present disclosure;

[0064] Figures 3b to 3f provided by an embodiment of the present disclosure Figure 3a Cross-sectional views of the sealing ring in different directions;

[0065] Figure 4 is a schematic structural diagram of a stacked structure provided by an embodiment of the present disclosure;

[0066] Figure 5 is a schematic flow chart of a manufacturing method of a sealing ring provided by an embodiment of the present disclosure;

[0067] Figures 6a to 6e Structural schematic diagram of the sealing ring forming process provided by the embodiments of the present disclosure. Detailed implementation manners

[0068] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific implementation manners set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully communicated to those skilled in the art.

[0069] In the following description, numerous specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some well-known technical features are not described; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0070] In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. The same reference numerals represent the same elements throughout.

[0071] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part. And when discussing the second element, component, region, layer, or part, it does not mean that the present disclosure necessarily has a first element, component, region, layer, or part.

[0072] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0073] Currently, a seal ring region for forming a seal ring structure is provided around the chip. The seal ring structure extends from the substrate surface to the top metal layer, which is used to improve the strength of the chip and protect the internal devices of the chip from external stress, impurity particles, or moisture.

[0074] Before detailing the seal ring provided by the embodiments of the present disclosure, the seal ring in the related art will be introduced first.

[0075] Figure 1a For the structural schematic diagram of the seal ring in the related art, as Figure 1a shown, the seal ring 10 in the related art includes a first seal ring structure 101 and a second seal ring structure 102 located in the seal ring region a. The double-layer structure of the first seal ring structure 101 and the second seal ring structure 102 is used to protect the device region b from external stress, impurity particles, moisture, etc. Figure 1b For the structural schematic diagram of the stacked chips in the related art, as Figure 1b shown, the seal ring 10 in the related art is only located on one side of the chip. For the back-to-back bonded stacked chips, due to the absence of the seal ring on the other side of the chip and the influence of the bonding process, the bonding interface I between the chips becomes a weak link affecting the reliability of the chips. In addition, the related art cannot detect the integrity of the seal ring.

[0076] Based on the problems existing in the related art, the embodiments of the present disclosure provide a seal ring, a stacked structure, and a method for manufacturing the seal ring. The seal ring includes an inner ring structure, a middle ring structure, and an outer ring structure. The middle ring structure is connected to the device region through a doped well. The doped well is located in the corresponding part of the substrate between the inner ring structure and the middle ring structure, and the doped well is isolated from the inner ring structure. Since the seal ring includes a middle ring structure, the strength of the chip can be further improved, and the reliability of the internal devices of the chip can be protected. In addition, since the middle ring structure can be connected to the device region through a doped well, the integrity of the seal ring can be detected by setting a specific functional circuit in the device region.

[0077] The embodiments of the present disclosure provide a seal ring, Figure 2The structural schematic diagram of the sealing ring provided by the embodiments of the present disclosure is as follows Figure 2 As shown, the sealing ring 20 includes: an inner ring structure 201, a middle ring structure 202, and an outer ring structure 203.

[0078] In the embodiments of the present disclosure, the sealing ring is disposed in a sealing ring area S surrounding the chip device area D. Among them, the middle ring structure 202 is connected to the device area D of the chip through a doped well 204; the doped well 204 is located in a partial substrate 200 corresponding to the inner ring structure 201 and the middle ring structure 202, and the doped well 204 is isolated from the inner ring structure 201.

[0079] In the embodiments of the present disclosure, the substrate of the chip can be a silicon substrate, or the substrate of the chip can also include other semiconductor elements, such as: germanium (Ge), or include semiconductor compounds, such as: silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or include other semiconductor alloys, such as: silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or a combination thereof.

[0080] In the embodiments of the present disclosure, isolation regions 2001 and active regions 2002 are also disposed in the substrate 200 at intervals, and the inner ring structure 201 is isolated from the doped well 204 through the isolation region 2001.

[0081] In some embodiments, a test circuit 205 is disposed in the device area D, and the middle ring structure 202 is connected to the test circuit 205 through the doped well 204 to test the integrity of the middle ring structure 202 through the test circuit 205.

[0082] It should be noted that in the embodiments of the present disclosure, both the inner ring structure and the outer ring structure can include a plurality of sub-sealing ring structures. Here, the number of sub-rings of the inner ring structure and the outer ring structure is not limited.

[0083] The sealing ring provided by the embodiments of the present disclosure can further improve the chip strength and protect the reliability of the devices inside the chip due to including the middle ring structure; in addition, since the middle ring structure can be connected to the device area through the doped well, in this way, the integrity of the sealing ring can be detected by setting a specific test circuit in the device area.

[0084] Figure 3a The top view of the sealing ring provided by the embodiments of the present disclosure Figures 3b to 3f provided by the embodiments of the present disclosure Figure 3a The cross-sectional views of the sealing ring in Figures 3a to 3f, it can be seen that in the embodiments of the present disclosure, the sealing ring 30 includes: an inner ring structure 301, a middle ring structure 302, and an outer ring structure 303. The middle ring structure 302 includes a first middle ring structure 3021 and a second middle ring structure 3022; wherein, the first middle ring structure 3021 is disposed in the first dielectric layer 306 on the first surface A of the substrate 300; the second middle ring structure 3022 is disposed in the second dielectric layer 307 on the second surface B of the substrate 300; the first surface A and the second surface B are two surfaces oppositely disposed along the thickness direction of the substrate.

[0085] In the embodiments of the present disclosure, the middle ring structure 302 is connected to the test circuit 305 in the device region D through the doped well 304 to test the integrity of the middle ring structure through the test circuit 305. The doped well 304 straddles the inner ring structure and the middle ring structure, and the doped well 304 is isolated from the inner ring structure.

[0086] Please continue to refer to Figure 3b , 3c and 3e, the first middle ring structure 3021 includes a plurality of metal layers (only three metal layers are shown in the figure), vias 310 connecting the metal layers, and metal plugs connecting the substrate 300 and the metal layers. The second middle ring structure 3022 includes at least two metal layers 309 (only two metal layers are shown in the figure) and vias 310 connecting adjacent metal layers.

[0087] In the embodiments of the present disclosure, the metal layer can be composed of any one metal, for example, copper or tungsten. Any one metal material can also be filled in the vias, for example, copper. The metal plug can be a tungsten plug.

[0088] Please continue to refer to Figure 3b , 3c and 3e, the doped well 304 is located in the first surface A of the substrate 300, and the first surface A of the substrate 300 further includes a plurality of spaced isolation regions 3001 and active regions 3002. The metal plugs of the first middle ring structure 3021 include a first metal plug 308a and a second metal plug 308b; wherein, the first metal plug 308a is used to connect the active region 3002 and the first metal layer 309a among the plurality of metal layers, and the second metal plug 308b is used to connect the doped well 304 and the second metal layer 309b among the plurality of metal layers.

[0089] In the embodiments of the present disclosure, the first metal layer can be the bottom metal layer among the plurality of metal layers; the second metal layer can be the sub-bottom metal layer among the plurality of metal layers or the bottom metal layer different from the first metal layer.

[0090] The first metal layer 309a of the first middle ring structure 3021 is not connected to the second metal layer 309b of the first middle ring structure 3021.

[0091] Please continue to refer to Figures 3b to 3f, the inner ring structure 301 includes a first inner ring structure 3011 disposed in the first dielectric layer 306 and a second inner ring structure 3012 disposed in the second dielectric layer 307. The outer ring structure 303 includes a first outer ring structure 3031 disposed in the first dielectric layer 306 and a second outer ring structure 3032 disposed in the second dielectric layer 307.

[0092] In some embodiments, the inner ring structure and the outer ring structure of the sealing ring are exactly the same. That is, the structure of the first inner ring structure 3011 is the same as that of the first outer ring structure 3031, the structure of the second inner ring structure 3012 is the same as that of the second outer ring structure 3032, and in the embodiments of the present disclosure, the structure of the second middle ring structure 3022 is also the same as that of the second inner ring structure 3012.

[0093] Please continue to refer to Figure 3b 、 3c 、3d and 3f, both the first inner ring structure 3011 and the first outer ring structure 3031 include a plurality of metal layers 309, through holes 310 connecting the metal layers, and metal plugs 308 connecting the substrate 300 to the third metal layer among the plurality of metal layers. Among them, the third metal layer may be the bottom metal layer among the plurality of metal layers. Both the second inner ring structure 3012 and the second outer ring structure 3032 include at least two metal layers 309 (only two metal layers are shown in the figure) and through holes 310 connecting adjacent metal layers. In the embodiments of the present disclosure, the metal plugs 310 of the first inner ring structure 3011 are disposed in the isolation region 3001, and the metal plugs 310 of the first outer ring structure 3031 are disposed in the active region 3002.

[0094] In the embodiments of the present disclosure, the metal plugs of the first inner ring structure are disposed on the isolation region. In this way, the extraction of the first middle ring structure does not damage the integrity of the metal plugs of the inner ring structure. In addition, for the sealing ring provided in the embodiments of the present disclosure, the inner ring is close to the device region, the outer ring structure is far from the device region, and the middle ring structure with a complex structure is disposed between the inner ring structure and the outer ring structure, which improves the sealing performance of the sealing ring without damaging the inner ring structure and the outer ring structure.

[0095] In some embodiments, the sealing ring is disposed in a stacked structure, and the stacked structure includes at least a first chip and a second chip stacked in sequence; the first middle ring structure of the second chip is electrically connected to the test circuit through the doped well.

[0096] In some embodiments, the second middle ring structure of the first chip is connected to the first middle ring structure of the second chip, and the first middle ring structure of the second chip is electrically connected to the test circuit through the doped well. Through silicon vias are further disposed in the device regions of each chip in the stacked structure, and the test circuit is connected to the surface of the topmost chip in the stacked structure through the through silicon vias.

[0097] An embodiment of the present disclosure provides a stacked structure, which includes a plurality of chips bonded face-to-back in sequence, and each chip includes at least the sealing ring in the above embodiment. Figure 4 It is a schematic structural diagram of the stacked structure provided by an embodiment of the present disclosure, as Figure 4 shown, the stacked structure 40 includes three chips bonded face-to-back in sequence, namely chip 401, chip 402, and chip 403. Among them, the first middle ring structure 4011 of chip 401 is connected to the test circuit in the device area D through the doped well 4013 of chip 401, so as to detect the structural integrity of the first middle ring structure 4011 through the test point T1 at the top of the test circuit. The first middle ring structure 4021 of chip 402 is connected to the second middle ring structure 4012 of chip 401, and the first middle ring structure 4021 of chip 402 is connected to the test circuit of chip 402 through the doped well 4023 of chip 402. The test circuit of chip 402 is connected to the surface of the topmost chip (i.e., chip 401) in the stacked structure 40 through the through-silicon via 4014 of chip 401, so as to test whether the bonding interface between chip 402 and chip 401 fails through the test point T2. In the embodiment of the present disclosure, the test points on the surface of the topmost chip (i.e., chip 401) and the number of test points are not limited.

[0098] It should be noted that in other embodiments, the number of chips in the stacked structure may also be 2, 4, or 6. In the embodiment of the present disclosure, the number of chips in the stacked structure is not limited.

[0099] The sealing ring structure provided by the embodiment of the present disclosure can prevent the bonding failure of the chip caused by stress during processes such as cutting and packaging, and at the same time can detect the structural integrity of the chip and locate the failure layer of the stacked chips.

[0100] In addition, an embodiment of the present disclosure also provides a method for manufacturing a sealing ring, and the sealing ring is arranged around the device area of the chip. Figure 5 It is a schematic flow diagram of the method for manufacturing a sealing ring provided by an embodiment of the present disclosure, Figures 6a to 6e It is a schematic structural diagram of the formation process of the sealing ring provided by an embodiment of the present disclosure, as Figure 5 shown, the method for manufacturing the sealing ring includes the following steps:

[0101] Step S501, forming a doped well in the chip substrate.

[0102] In the embodiment of the present disclosure, the doped well can be formed by doping the substrate with N-type ions or P-type ions. The doped well is formed in the first surface of the substrate, and the first surface can be any surface in the thickness direction of the substrate.

[0103] In the embodiments of the present disclosure, the substrate of the chip may be a silicon substrate, and the substrate of the chip may also include other semiconductor elements, such as germanium (Ge), or include semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or include other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or a combination thereof.

[0104] In some embodiments, the method for manufacturing the sealing ring further includes the following steps:

[0105] Step S10: Form a plurality of spaced-apart isolation regions and active regions in the first surface of the substrate.

[0106] In some embodiments, by etching the first surface of the substrate, a plurality of spaced-apart etching grooves are formed, and an insulating material is filled in the etching grooves to form the isolation regions.

[0107] As Figure 6a shown, a doped well 601, and a plurality of spaced-apart isolation regions 6001 and active regions 6002 are formed in the first surface A of the substrate 600.

[0108] In the embodiments of the present disclosure, the doped well 601 and the inner ring structure are isolated from each other by the isolation region 6001.

[0109] It should be noted that in the embodiments of the present disclosure, there is no strict sequential relationship in the formation process of the isolation region and the doped well. The isolation region may be formed first and then the doped well, or the doped well may be formed first and then the isolation region. There is an inversion layer between the doped well and the substrate to isolate the doped well from the substrate.

[0110] Step S502: Form an inner ring structure, a middle ring structure, and an outer ring structure around the device region on the surface of the substrate, wherein the inner ring structure, the middle ring structure, and the outer ring structure form the sealing ring; the middle ring structure is connected to the device region through the doped well; the doped well is located in the corresponding part of the substrate of the inner ring structure and the middle ring structure, and the doped well is isolated from the inner ring structure.

[0111] In some embodiments, step S502 may include the following steps:

[0112] Form an inner ring structure, a middle ring structure, and an outer ring structure around the device region on the first surface and the second surface of the substrate respectively; wherein the first surface and the second surface are oppositely arranged.

[0113] In the embodiments of the present disclosure, the inner ring structure at least includes a first inner ring structure located on the first surface of the substrate; the middle ring structure at least includes a first middle ring structure located on the first surface of the substrate; the outer ring structure at least includes a first outer ring structure located on the first surface of the substrate; forming the inner ring structure, the middle ring structure and the outer ring structure on the first surface of the substrate includes the following steps:

[0114] Step S5021: Form a first dielectric layer on the first surface of the substrate.

[0115] Here, the first dielectric layer may be a silicon oxide layer or other material layer. In the embodiments of the present disclosure, the first dielectric layer can be formed by any suitable deposition process, for example, Chemical Vapor Deposition (CVD) process, Physical Vapor Deposition (PVD) process, Atomic Layer Deposition (ALD) process, spin coating process or coating process.

[0116] Please continue to refer to Figure 6a and it can be seen that a first dielectric layer 603 is formed on the first surface A of the substrate 600.

[0117] Step S5022: Form the first inner ring structure, the first middle ring structure and the first outer ring structure in the first dielectric layer.

[0118] In some embodiments, step S5022 can be formed by the following steps:

[0119] Etch the first dielectric layer to form a plurality of first etch holes; wherein, the first etch holes of the first inner ring structure expose the surface of the isolation region, the first etch holes of the first middle ring structure respectively expose the surfaces of the active region and the doped well, and the first etch holes of the first outer ring structure expose the surface of the active region.

[0120] In the embodiments of the present disclosure, the first dielectric layer can be etched by a dry etching process to form the first etch holes, for example, plasma etching process, reactive ion etching process or ion milling process.

[0121] Fill a first metal material in each first etch hole to form a metal plug.

[0122] The first metal material can be any metal material, for example, tungsten or copper.

[0123] Form a plurality of metal layers and vias connecting the metal layers on the surface of each metal plug.

[0124] As Figures 6a to 6cAs shown, three metal layers 605 are formed on the surface of the metal plug 604 and vias 606 connecting two adjacent metal layers are formed, thereby forming a first inner ring structure 6071, a first middle ring structure 6081, and a first outer ring structure 6091.

[0125] In some embodiments, please continue to refer to Figures 6a to 6c , while forming the first inner ring structure 6071, the first middle ring structure 6081, and the first outer ring structure 6091, a test circuit 607 is formed in the first dielectric layer 603 on the surface of the device region D; wherein, the first middle ring structure 6081 is electrically connected to the test circuit 607 through a doped well 601. While forming the metal plug 604, a silicon blind via structure 610 located in the device region D is also formed.

[0126] It should be noted that in the embodiments of the present disclosure, the first metal layer and the second metal layer of the first middle ring structure 6081 are not connected. Among them, the first metal layer of the first middle ring structure is the bottom metal layer among the multiple metal layers of the first middle ring structure, and the second metal layer of the first middle ring structure is the sub-bottom metal layer among the multiple metal layers of the first middle ring structure or a bottom metal layer different from the first metal layer.

[0127] Step S5023: Form a second dielectric layer on the second surface of the substrate.

[0128] Here, the second dielectric layer may be a silicon oxide layer or other material layer. In the embodiments of the present disclosure, the first dielectric layer and the second dielectric layer are the same or different.

[0129] Such as Figure 6d shown, a second dielectric layer 611 is formed on the second surface B of the substrate 600.

[0130] In some embodiments, before forming the second dielectric layer 611, the method for forming the sealing ring further includes the following steps:

[0131] Thin the second surface of the substrate until a silicon blind via structure with a preset height is exposed to form a silicon through hole; wherein, the test circuit is connected to the surface of the topmost chip in the stacked structure through the silicon through hole.

[0132] Please continue to refer to Figure 6d , it can be seen that the second surface B of the substrate 600 is thinned to form a silicon through hole 610'. When stacking chips subsequently, the test circuit is connected to the surface of the topmost chip in the stacked structure through the silicon through hole. In the embodiments of the present disclosure, the second surface of the substrate can be thinned by processes such as Chemical Mechanical Polishing (CMP) or etching.

[0133] Step S5024: Form a second inner ring structure, a second middle ring structure, and a second outer ring structure in the second dielectric layer.

[0134] In some embodiments, step S5024 can be formed through the following steps:

[0135] Etch the second dielectric layer to form a plurality of second etch holes.

[0136] Here, the second dielectric layer can be etched through a dry etching process to form second etch holes. For example, a plasma etching process, a reactive ion etching process, or an ion milling process.

[0137] Fill a second metal material in each second etch hole to respectively form the first metal layer of the second inner ring structure, the second middle ring structure, and the second outer ring structure.

[0138] The second metal material can be any metal material. For example, tungsten or copper. In the embodiments of the present disclosure, the first metal material and the second metal material can be the same or different.

[0139] Please continue to refer to Figure 6d , it can be seen that the first metal layer 605 is formed in the second dielectric layer 611.

[0140] Form at least one second metal layer and a through hole connecting the first metal layer and the second metal layer on the surface of the first metal layer.

[0141] As Figure 6e shown, a second metal layer 605 and a through hole 606 connecting the first metal layer and the second metal layer are formed on the surface of the first metal layer 605, thereby forming the second inner ring structure 6072, the second middle ring structure 6082, and the second outer ring structure 6092.

[0142] The sealing ring structure provided by the embodiments of the present disclosure has a sealing ring structure on both surfaces of the chip. Thus, the strength of the bonding layer is strengthened during chip stacking, realizing the protection of the chip. In addition, a middle ring structure and a test circuit are added to the sealing ring structure, which can detect the bonding performance of the bonding layer in the sealing ring area in real time and discover failure phenomena in time.

[0143] The manufacturing method of the sealing ring provided by the embodiments of the present disclosure is similar to the sealing ring in the above embodiments. For the technical features not detailedly disclosed in the embodiments of the present disclosure, please refer to the above embodiments for understanding, and will not be elaborated here.

[0144] The manufacturing method of the sealing ring provided by the embodiments of the present disclosure forms the middle ring structure located between the inner ring structure and the outer ring structure and the test circuit located in the device area while forming the inner ring structure and the outer ring structure. By doping the well to lead out the middle ring structure and the test circuit, the integrity of the sealing ring can be detected. In addition, the existence of the middle ring structure can further improve the chip strength and protect the reliability of the devices inside the chip. Thus, a high-performance sealing ring structure is manufactured without increasing the process complexity.

[0145] In several embodiments provided by the present disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-targeted manner. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the couplings between the various components shown or discussed are either direct couplings or indirect couplings.

[0146] The units described as separate components above may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0147] The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0148] The above is only some embodiments of the embodiments of the present disclosure, but the protection scope of the embodiments of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the embodiments of the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the embodiments of the present disclosure. Therefore, the protection scope of the embodiments of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A sealing ring, characterized in that, The sealing ring is disposed around the chip device area, and the sealing ring includes: an inner ring structure, a middle ring structure, and an outer ring structure; Wherein, the middle ring structure is connected to the device area through a doped well; the doped well is located in a part of the substrate corresponding to the inner ring structure and the middle ring structure, and the doped well is isolated from the inner ring structure; A test circuit is provided in the device area, and the middle ring structure is electrically connected to the test circuit through the doped well; The substrate includes a first surface and a second surface arranged opposite to each other, and the doped well is located in the first surface; the middle ring structure includes a first middle ring structure and a second middle ring structure; Wherein, the first middle ring structure is disposed in a first dielectric layer on the first surface of the substrate; The second middle ring structure is disposed in a second dielectric layer on the second surface of the substrate.

2. The sealing ring according to claim 1, wherein The sealing ring is disposed in a stacked structure, and the stacked structure at least includes a first chip and a second chip stacked in sequence; The first middle ring structure of the second chip is electrically connected to the test circuit through the doped well.

3. The sealing ring according to claim 2, characterized in that, The second middle ring structure of the first chip is connected to the first middle ring structure of the second chip.

4. The sealing ring according to claim 1, wherein The first middle ring structure includes a plurality of metal layers, vias connecting the metal layers, and metal plugs connecting the substrate and the metal layers.

5. The sealing ring according to claim 4, characterized in that, The first surface of the substrate further includes a plurality of spaced-apart isolation regions and active regions; The metal plugs of the first middle ring structure include a first metal plug and a second metal plug; wherein, the first metal plug is used to connect the active region to the first metal layer among the plurality of metal layers, and the second metal plug is used to connect the doped well to the second metal layer among the plurality of metal layers.

6. The sealing ring according to claim 5, characterized in that, The first metal layer of the first middle ring structure is not connected to the second metal layer of the first middle ring structure.

7. The sealing ring according to claim 5, characterized in that, The inner ring structure includes a first inner ring structure disposed in the first dielectric layer and a second inner ring structure disposed in the second dielectric layer; The outer ring structure includes a first outer ring structure disposed in the first dielectric layer and a second outer ring structure disposed in the second dielectric layer.

8. The sealing ring according to claim 7, characterized in that, The first inner ring structure has the same structure as the first outer ring structure; Wherein, the first inner ring structure includes a plurality of metal layers, vias connecting the metal layers, and metal plugs connecting the substrate and the third metal layer among the plurality of metal layers.

9. The sealing ring according to claim 8, characterized in that, The metal plugs of the first inner ring structure are disposed in the isolation region, and the metal plugs of the first outer ring structure are disposed in the active region.

10. The sealing ring according to any one of claims 7 to 9, characterized in that, The structures of the second inner ring structure, the second middle ring structure, and the second outer ring structure are all the same; Wherein, the second inner ring structure includes at least two metal layers and vias connecting adjacent metal layers.

11. The sealing ring according to claim 2, wherein, A through-silicon via is further provided in the device area; The test circuit is connected to the surface of the topmost chip in the stacked structure through the through-silicon via.

12. A stacked structure, characterized in that, The stacked structure includes a plurality of the chips bonded back-to-back in sequence, and each of the chips at least includes the sealing ring according to any one of claims 1 to 11.

13. A manufacturing method of a sealing ring, characterized in that, The sealing ring is disposed around the chip device area; the method includes: Forming a doped well in the chip substrate; An inner ring structure, a middle ring structure, and an outer ring structure are formed around the device region on the surface of the substrate; Wherein, the inner ring structure, the middle ring structure, and the outer ring structure constitute the sealing ring; the middle ring structure is connected to the device region through the doped well; the doped well is located in the corresponding part of the substrate of the inner ring structure and the middle ring structure, and the doped well is isolated from the inner ring structure; Wherein, the forming of the inner ring structure, the middle ring structure, and the outer ring structure around the device region on the surface of the substrate includes: The inner ring structure, the middle ring structure, and the outer ring structure are respectively formed around the device region on the first surface and the second surface of the substrate; wherein, the first surface and the second surface are oppositely arranged, and the doped well is located in the first surface; Wherein, before or after forming the doped well, a plurality of spaced-apart isolation regions and active regions are formed in the first surface of the substrate; the doped well is isolated from the inner ring structure through the isolation regions; Wherein, the inner ring structure includes a first inner ring structure located on the first surface of the substrate and a second inner ring structure located on the second surface of the substrate; the middle ring structure includes a first middle ring structure located on the first surface of the substrate and a second middle ring structure located on the second surface of the substrate; the outer ring structure at least includes a first outer ring structure located on the first surface of the substrate and a second outer ring structure located on the second surface of the substrate; The forming of the inner ring structure, the middle ring structure, and the outer ring structure around the device region on the first surface and the second surface of the substrate respectively includes: Form a first dielectric layer on the first surface of the substrate; Form the first inner ring structure, the first middle ring structure, and the first outer ring structure in the first dielectric layer; Form a second dielectric layer on the second surface of the substrate; Form the second inner ring structure, the second middle ring structure, and the second outer ring structure in the second dielectric layer.

14. The method according to claim 13, wherein The forming of the first inner ring structure, the first middle ring structure, and the first outer ring structure in the first dielectric layer includes: Etch the first dielectric layer to form a plurality of first etch holes; wherein, the first etch holes of the first inner ring structure expose the surface of the isolation region, the first etch holes of the first middle ring structure respectively expose the surfaces of the active region and the doped well, and the first etch holes of the first outer ring structure expose the surface of the active region; Fill a first metal material in each of the first etch holes to form metal plugs; Form a plurality of metal layers and vias connecting the metal layers on the surface of each of the metal plugs.

15. The method according to claim 14, wherein The method includes: Form a test circuit in the first dielectric layer on the surface of the device region; Wherein, the first middle ring structure is electrically connected to the test circuit through the doped well.

16. The method according to claim 15, characterized in that, The sealing ring is arranged in a stacked structure, and the stacked structure includes a plurality of chips stacked in sequence; the method includes: Form a through-silicon via structure in the device region; The test circuit is connected to the surface of the topmost chip in the stacked structure through the through-silicon via.

17. The method according to any one of claims 13 to 16, characterized in that Forming the second inner ring structure, the second middle ring structure, and the second outer ring structure in the second dielectric layer includes: Etching the second dielectric layer to form a plurality of second etching holes; Filling a second metal material into each of the second etching holes to respectively form a first metal layer of the second inner ring structure, the second middle ring structure, and the second outer ring structure; Forming at least one second metal layer on the surface of the first metal layer and a through hole connecting the first metal layer and the second metal layer.

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