Display substrate, preparation method thereof and display device

By setting a composite insulating layer with non-smooth edges in the bending area of ​​the display substrate, the signal short circuit problem caused by metal layer residue is solved, improving the yield and reliability of the display substrate.

CN116096174BActive Publication Date: 2026-05-15BOE TECHNOLOGY GROUP CO LTD +1
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
BOE TECHNOLOGY GROUP CO LTD
Filing Date
2023-02-24
Publication Date
2026-05-15

AI Technical Summary

Technical Problem

In the bending area of ​​the display substrate, the etching process of the insulating layer can easily lead to metal layer residue, causing signal short circuits and affecting the yield of the display substrate.

Method used

A composite insulating layer with non-smooth edges is provided in the bending area of ​​the display substrate. By designing multiple serrated sections at intervals along the edge, the edge shape is reduced, the process boundary is increased, and metal residue is avoided.

Benefits of technology

It effectively improves the problem of metal residue in the bending area, increases the yield of display substrates, avoids signal short circuits, and improves the reliability of the manufacturing process.

✦ Generated by Eureka AI based on patent content.

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Abstract

A display substrate includes a substrate, a first composite insulating layer and a metal conductive layer sequentially arranged on the substrate. The substrate includes a display area and a first bezel area located at least one side of the display area along a first direction. The first bezel area has a first bending area. The first composite insulating layer includes a first groove located at least the first bending area, and the first groove includes oppositely arranged first and second edges. At least one of the first and second edges is a non-smooth edge. Part of the metal conductive layer is located in the first bending area.
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Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and its preparation method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate, a method for preparing the same, and a display device.

[0005] In one aspect, embodiments of this disclosure provide a display substrate, comprising: a substrate, a first composite insulating layer and a metal conductive layer sequentially disposed on the substrate. The substrate includes a display area and a first border area located on at least one side of the display area along a first direction; the first border area has a first bending region. The first composite insulating layer includes a first groove located at least in the first bending region, the first groove including a first edge and a second edge disposed opposite to each other; at least one of the first edge and the second edge is a non-smooth edge. A portion of the metal conductive layer is located in the first bending region.

[0006] In some exemplary embodiments, the display substrate may further include: a second composite insulating layer, the second composite insulating layer being located on the side of the first composite insulating layer away from the substrate and on the side of the metal conductive layer close to the substrate. The second composite insulating layer includes: a second groove, the second groove being at least located in the first bending region, the second groove including a third edge and a fourth edge disposed opposite to each other, at least one of the third edge and the fourth edge being a non-smooth edge. The first edge is located on the side of the second edge close to the display area, the third edge is located on the side of the first edge close to the display area, and the fourth edge is located on the side of the second edge away from the display area.

[0007] In some exemplary embodiments, the substrate further includes: a second border region, the second border region and the first border region being located on opposite sides of the display area along the first direction; the second border region having a second bending region. The first composite insulating layer further includes: a third groove, the third groove being at least located in the second bending region, the third groove including a fifth edge and a sixth edge disposed opposite to each other, at least one of the fifth edge and the sixth edge being a non-smooth edge.

[0008] In some exemplary embodiments, the display substrate further includes a second composite insulating layer, located on the side of the first composite insulating layer away from the substrate and on the side of the metal conductive layer near the substrate. The second composite insulating layer includes a fourth groove, at least located in the second bending region, the fourth groove including a seventh edge and an eighth edge disposed opposite to each other. A fifth edge is located on the side of the sixth edge near the display area, the seventh edge is located on the side of the fifth edge near the display area, and the eighth edge is located on the side of the sixth edge away from the display area.

[0009] In some exemplary embodiments, at least one of the seventh and eighth edges is a non-smooth edge.

[0010] In some exemplary embodiments, the non-smooth edge has a plurality of serrated portions spaced apart.

[0011] In some exemplary embodiments, the slope angle of the non-smooth edge is less than 40 degrees.

[0012] In some exemplary embodiments, the metal conductive layer includes at least: a first power trace; the first frame region includes a first bonding region located on the side of the first bend region away from the display area, and the second frame region includes a second bonding region located on the side of the second bend region away from the display area; the first bonding region is provided with a first bonding pin, and the second bonding region is provided with a second bonding pin; the first power trace is electrically connected to the first bonding pin in the first bonding region and to the second bonding pin in the second bonding region.

[0013] On the other hand, embodiments of this disclosure provide a display device including a display substrate as described above.

[0014] On the other hand, this disclosure provides a method for fabricating a display substrate, for fabricating the display substrate as described above. The method includes: forming a first composite insulating layer on a substrate and forming a metal conductive layer on the side of the first composite insulating layer away from the substrate. The substrate includes a display area and a first border area located on at least one side of the display area along a first direction; the first border area has a first bending area; the first insulating layer includes a first groove located at least in the first bending area, the first groove including a first edge and a second edge disposed opposite to each other; at least one of the first edge and the second edge is a non-smooth edge. The metal conductive layer is partially located in the first bending area.

[0015] In some exemplary embodiments, forming the first composite insulating layer on the substrate includes: patterning the first composite insulating layer using a first mask to form a first edge and a second edge of the first composite insulating layer in the first border area, wherein the first mask employs a grayscale mask design in the first border area.

[0016] In some exemplary embodiments, the substrate further includes: a second border region, the second border region and the first border region being located on opposite sides of the display area along the first direction; the second border region having a second bending region. Forming the first composite insulating layer on the substrate further includes: patterning the first composite insulating layer using the first mask to form a fifth edge and a sixth edge of the first composite insulating layer in the second border region, wherein the first mask employs a grayscale mask design in the second border region.

[0017] In some exemplary embodiments, forming the first composite insulating layer on the substrate further includes: while forming a first groove of the first composite insulating layer in the first border area, forming a plurality of first connection holes on the first composite insulating layer in the display area using the first mask.

[0018] In some exemplary embodiments, the fabrication method further includes: forming a second composite insulating layer on the side of the first composite insulating layer away from the substrate before forming the metal conductive layer; wherein the second composite insulating layer includes a second groove at least located in the first bending region, the second groove includes a third edge and a fourth edge disposed opposite to each other, at least one of the third edge and the fourth edge being a non-smooth edge; the first edge is located on the side of the second edge close to the display area, the third edge is located on the side of the first edge close to the display area, and the fourth edge is located on the side of the second edge away from the display area.

[0019] In some exemplary embodiments, forming a second composite insulating layer on the side of the first composite insulating layer away from the substrate includes: patterning the second composite insulating layer using a second mask, forming a third edge and a fourth edge of the second composite insulating layer in the first border area, wherein the second mask employs a grayscale mask design in the first border area.

[0020] In some exemplary embodiments, the substrate further includes: a second border region, the second border region and the first border region being located on opposite sides of the display area along the first direction; the second border region having a second bending region. Forming a second composite insulating layer on the side of the first composite insulating layer away from the substrate further includes: patterning the second composite insulating layer using a second mask, forming the seventh and eighth edges of the fourth groove of the second composite insulating layer in the second border region, the second mask employing a grayscale mask design in the second border region.

[0021] In some exemplary embodiments, forming a second composite insulating layer on the side of the first composite insulating layer away from the substrate further includes: forming a second groove of the second composite insulating layer in the first border area while using a second mask to form a plurality of second connection holes on the second composite insulating layer in the display area.

[0022] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0023] The accompanying drawings are provided to illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of one or more components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0024] Figure 1 This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0025] Figure 2 This is a partial schematic diagram of the first border region of at least one embodiment of the present disclosure;

[0026] Figure 3 for Figure 2 A partial cross-sectional view along the R-R' direction;

[0027] Figure 4 This is a partial top view of the first bending region according to at least one embodiment of the present disclosure;

[0028] Figure 5 This is another partial top view of the first bending region according to at least one embodiment of the present disclosure;

[0029] Figure 6 This is another partial top view of the first bending region according to at least one embodiment of the present disclosure;

[0030] Figure 7 for Figure 2 Another partial cross-sectional view along the R-R' direction;

[0031] Figure 8 for Figure 2 Another partial cross-sectional view along the R-R' direction;

[0032] Figure 9 This is a partial schematic diagram of the first bending region according to at least one embodiment of the present disclosure;

[0033] Figure 10 This is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0034] Figure 11 This is a partial schematic diagram of the second bending region according to at least one embodiment of the present disclosure;

[0035] Figure 12 for Figure 11 A partial cross-sectional view along the Q-Q' direction;

[0036] Figure 13 This is a partial schematic diagram of the second bending region according to at least one embodiment of the present disclosure;

[0037] Figure 14 for Figure 11 Another partial cross-sectional view along the Q-Q' direction;

[0038] Figure 15 This is another partial schematic diagram of the second bending region according to at least one embodiment of the present disclosure;

[0039] Figure 16 for Figure 11 Another partial cross-sectional view along the Q-Q' direction;

[0040] Figure 17 This is another partial schematic diagram of the second bending region according to at least one embodiment of the present disclosure;

[0041] Figure 18 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0042] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be changed to one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0043] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0044] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure can include two or more quantities.

[0045] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which the constituent elements are described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0046] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0047] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on the "elements that have a certain electrical function," as long as they enable the transmission of electrical signals between the connected components. Examples of "elements that have a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with one or more functions.

[0048] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain terminal, drain region, or drain) and the source electrode (source terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0049] In this specification, to distinguish the two terminals of a transistor other than the gate electrode, one electrode is referred to as the first terminal and the other as the second terminal. The first terminal can be either the source or the drain, and the second terminal can be either the drain or the source. Additionally, the gate of the transistor can be referred to as the control terminal. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged.

[0050] In this specification, "parallel" refers to a state in which two straight lines form an angle of -10° or more and less than 10°, and therefore can include a state in which the angle is -5° or more and less than 5°. Similarly, "perpendicular" refers to a state in which two straight lines form an angle of 80° or more and less than 100°, and therefore can include a state in which the angle is 85° or more and less than 95°.

[0051] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0052] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0053] In this specification, "approximately" and "roughly" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this specification, "same" can mean values ​​differing by less than 10%, or similarity greater than or equal to 90%.

[0054] In this specification, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this specification, "A extends along direction B" refers to "the main part of A extends along direction B".

[0055] The "patterning process" and "patterning treatment" mentioned in the embodiments of this disclosure, for metallic materials, inorganic materials, or transparent conductive materials, include processes such as coating with photoresist, mask exposure, development, etching, and photoresist stripping; for organic materials, they include processes such as coating with organic materials, mask exposure, and development. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be any one or more of spraying, spin coating, and inkjet printing; etching can be any one or more of dry etching and wet etching, and this disclosure does not limit the methods. A "thin film" refers to a thin film of a certain material fabricated on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. A "layer" after the patterning process contains at least one "pattern." The "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In this specification, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0056] In this specification, "slope angle" refers to the angle between the slope of the film layer and the plane of the substrate.

[0057] In some implementations, the display substrate may include a display area and a bezel area surrounding the display area. To achieve a narrow bezel display substrate, the bezel area may include a bent region, such that the portion of the bent region away from the display area can be bent to the back of the display area. To improve the bending effect of the bent region, the insulating layer of the bent region needs to be etched or thinned. However, after the etching process of the insulating layer in the bent region, during subsequent metal layer fabrication, metal residue can easily remain at the etching boundary of the insulating layer, potentially causing signal short circuits.

[0058] This embodiment provides a display substrate, including: a substrate, a first composite insulating layer disposed on the substrate, and a metal conductive layer. The substrate includes a display area and a first border area located on at least one side of the display area along a first direction, the first border area having a first bending region. The first composite insulating layer includes a first groove located at least in the first bending region, the first groove including a first edge and a second edge disposed opposite to each other. At least one of the first edge and the second edge is a non-smooth edge. The metal conductive layer is located on the side of the first composite insulating layer away from the substrate and is partially located in the first bending region. For example, either the first edge or the second edge is a non-smooth edge, or both the first edge and the second edge are non-smooth edges.

[0059] The display substrate provided in this embodiment, by setting at least a portion of the edges of the first composite insulating layer in the first bending region to be non-smooth edges, can reduce the edge morphology of the first composite insulating layer in the first bending region and increase the process boundary. This can improve the situation where metal residue is generated in the first bending region due to the edge morphology of the insulating layer during the fabrication of the display substrate, thereby avoiding signal short circuits caused by metal residue in the first bending region and improving the yield of the display substrate.

[0060] In some exemplary embodiments, the display substrate may further include a second composite insulating layer, which is located on the side of the first composite insulating layer away from the substrate and on the side of the metal conductive layer close to the substrate. The second composite insulating layer may include a second groove at least located in the first bending region. The second groove may include a third edge and a fourth edge disposed opposite to each other. At least one of the third edge and the fourth edge may be a non-smooth edge. For example, the third edge or the fourth edge is a non-smooth edge, or both the third edge and the fourth edge are non-smooth edges. The first edge may be located on the side of the second edge close to the display area, the third edge may be located on the side of the first edge close to the display area, and the fourth edge may be located on the side of the second edge away from the display area. This example, by setting at least a portion of the edges of the second composite insulating layer in the first bending region to be non-smooth edges, can reduce the edge morphology of the second composite insulating layer in the first bending region, increase the process boundary, and improve the situation where signal short circuits are caused by metal residue in the first bending region.

[0061] In some exemplary embodiments, the substrate may further include a second border region. The second border region and the first border region may be located on opposite sides of the display area along a first direction. The second border region may have a second bend region. The first composite insulating layer may further include a third groove at least located in the second bend region. The third groove may include a fifth edge and a sixth edge disposed opposite to each other, at least one of the fifth edge and the sixth edge being a non-smooth edge. For example, the fifth edge or the sixth edge is a non-smooth edge, or both the fifth edge and the sixth edge are non-smooth edges. This example, by setting at least a portion of the edges of the first composite insulating layer in the second bend region to be non-smooth edges, can reduce the edge morphology of the first composite insulating layer in the second bend region, increase the process boundary, and improve the situation where signal short circuits are caused by metal residues in the second bend region.

[0062] In some exemplary embodiments, the second composite insulating layer may include a fourth groove at least located in the second bending region. The fourth groove may include a seventh edge and an eighth edge disposed opposite to each other. The fifth edge may be located on the side of the sixth edge closer to the display area, the seventh edge may be located on the side of the fifth edge closer to the display area, and the eighth edge may be located on the side of the sixth edge farther from the display area. In some examples, at least one of the seventh and eighth edges may be a non-smooth edge. For example, the seventh edge or the eighth edge may be a non-smooth edge, or both the seventh and eighth edges may be non-smooth edges. This example, by setting at least a portion of the edges of the second composite insulating layer in the second bending region to be non-smooth edges, can reduce the edge morphology of the second composite insulating layer in the second bending region, increase the process boundary, and improve the situation where signal short circuits are caused by metal residue in the second bending region.

[0063] In some exemplary embodiments, the non-smooth edge may have multiple serrated portions spaced apart. In some examples, the slope angle of the non-smooth edge may be less than 40 degrees. For example, the non-smooth edge may be formed using a mask with a graytone design, thereby reducing the edge profile of the insulating layer, increasing the process margin, and avoiding metal residue during subsequent metal layer fabrication that could cause signal short circuits. However, this embodiment is not limited to this. In other examples, the non-smooth edge may be formed using a mask with a halftone design.

[0064] The display substrate of this embodiment will be illustrated below with some examples. In the following exemplary embodiments, an OLED display substrate will be used as an example for illustration.

[0065] Figure 1This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, the display substrate of this example may include a display area AA and a border area surrounding the display area AA. The display substrate may have a generally rectangular shape. For example, the display substrate may include a pair of long sides parallel to a first direction Y and a pair of short sides parallel to a second direction X, that is, the length of the display substrate in the first direction Y may be greater than the length in the second direction X. The first direction Y and the second direction X may intersect each other, for example, the first direction Y may be perpendicular to the second direction X. However, this embodiment is not limited in this respect. In other examples, the display substrate may be a closed polygon including linear sides, a circle or ellipse including curved sides, or a semicircle or semi-ellipse including linear sides and curved sides, etc. In some examples, when the display substrate has linear sides, at least some corners of the display substrate may be curves. When the display substrate has a rectangular shape, the portion where adjacent linear sides intersect each other may be replaced by a curve with a predetermined curvature. The curvature may be set according to the position of the curve. For example, the curvature may be changed according to the starting position of the curve, the length of the curve, etc.

[0066] In some examples, such as Figure 1 As shown, the display area AA may include at least: multiple sub-pixels PX, multiple gate lines GL, and multiple data lines DL. The multiple gate lines GL may extend along a second direction X and be arranged sequentially along a first direction Y; the multiple data lines DL may extend along the first direction Y and be arranged sequentially along the second direction X. The orthogonal projections of the multiple gate lines GL and the multiple data lines DL on the substrate may intersect to form multiple sub-pixel regions, and each sub-pixel region may contain one sub-pixel PX. The multiple data lines DL are electrically connected to the multiple sub-pixels PX, and the multiple data lines DL can be configured to provide data voltages to the multiple sub-pixels PX. The multiple gate lines GL are electrically connected to the multiple sub-pixels PX, and the multiple gate lines GL can be configured to provide gate control signals to the multiple sub-pixels PX. However, this embodiment is not limited in this respect.

[0067] In some examples, a pixel unit may include three sub-pixels, which may be red, green, and blue sub-pixels, respectively. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, which may be red, green, blue, and white sub-pixels, respectively.

[0068] In some examples, at least one sub-pixel may include a pixel circuit and a light-emitting element. The pixel circuit may be configured to drive the connected light-emitting element. For example, the pixel circuit may be configured to provide a drive current to drive the light-emitting element to emit light. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C structure, an 8T1C structure, a 7T1C structure, or a 5T1C structure. Here, in the above circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0069] In some examples, the multiple transistors in the pixel circuit can be either P-type or N-type transistors. Using the same type of transistors in the pixel circuit simplifies the manufacturing process, reduces the complexity of the display substrate manufacturing, and improves product yield. In other examples, the multiple transistors in the pixel circuit can include both P-type and N-type transistors.

[0070] In some examples, the multiple transistors in the pixel circuit can be low-temperature polysilicon (LTPS) thin-film transistors (TFTs), oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polysilicon (LTPS), while the active layer of the OPT TFT is made of oxide. LTPS TFTs offer advantages such as high mobility and fast charging, while OPTs offer advantages such as low leakage current. Integrating LTPS and OPTs onto a single display substrate—an LTPS+Oxide (LTPO) display substrate—leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0071] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0072] In some examples, the shape of the light-emitting element can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0073] In some examples, such as Figure 1 As shown, the border area may include: a first border area B1 and a second border area B2 located on opposite sides of the display area AA along the first direction Y, and a third border area B3 and a fourth border area B4 located on opposite sides of the display area AA along the second direction X. In this example, the first border area B1 may be the bottom border, the second border area B2 may be the top border, the third border area B3 may be the left border, and the fourth border area B4 may be the right border. For example, the third border area B3 and the fourth border area B4 may be provided with gate driving circuits that provide gate control signals to multiple sub-pixels PX of the display area AA. In some examples, the sizes of the first border area B1 and the second border area B2 are different; for example, the size of the first border area B1 may be larger than the size of the second border area B2.

[0074] Figure 2 This is a partial schematic diagram of the first border region according to at least one embodiment of the present disclosure. In some examples, such as... Figure 1 and Figure 2As shown, the first border area B1 may include: a first trace area B12, a first bend area B10, a first circuit area B13, and a first bonding area B11 arranged sequentially along a direction away from the display area AA. The first trace area B12 may be connected to the display area AA, the third border area B3, and the fourth border area B4. The first trace area B12 may have multiple data leads, which may be configured to connect multiple data lines DL of the display area AA in a fan-out routing manner. The first bend area B10 may be configured to bend the first circuit area B13 and the first bonding area B11 to the back of the display area AA. The first bend area B10 may include at least multiple data connection lines, which may be configured to connect the multiple data leads in the first trace area B12 to the integrated circuit (IC) 31 in the first circuit area B13. For example, the first circuit area B13 may have four integrated circuits 31. The first circuit area B13 may also include an anti-static circuit, which can be configured to prevent electrostatic damage to the display substrate by eliminating static electricity. The first bonding area B11 may include a plurality of bonding pins, which can be configured to bond to an external flexible printed circuit (FPC). However, this embodiment is not limited in this respect.

[0075] Figure 3 for Figure 2 A partial cross-sectional view along the R-R' direction. In some examples, such as... Figure 3 As shown, the display substrate can be an LTPS display substrate. Figure 3 The illustration uses a first transistor 21a and a capacitor 22a from a pixel circuit in display area AA as an example. For instance, the first transistor 21a can be a low-temperature polycrystalline silicon thin-film transistor. Figure 3As shown, in a direction perpendicular to the display substrate, the display area AA may include: a substrate 100 and a first semiconductor layer, a first insulating layer 101, a first gate metal layer, a second insulating layer 102, a second gate metal layer, a third insulating layer 103, a first source / drain metal layer, and a first planarization layer 106 sequentially disposed on the substrate 100. The first semiconductor layer may include the active layer of the first transistor 21a; the first gate metal layer may include the gate of the first transistor 21a and the first electrode of the capacitor 22a; the second gate metal layer may include the second electrode of the capacitor 22a; and the first source / drain metal layer may include the source and drain of the first transistor 21a. The orthographic projection of the second electrode of the capacitor 22a onto the substrate may overlap with the orthographic projection of the first electrode of the capacitor 22a onto the substrate. The source and drain of the first transistor 21a may be electrically connected to the two ends of the active layer through first pixel vias formed in the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101, respectively. In some examples, the first insulating layer 101 to the third insulating layer 103 may be inorganic insulating layers, and the first planarization layer 106 may be made of an organic material. However, this embodiment is not limited to this. In other examples, an inorganic insulating layer may also be disposed between the first planarization layer 106 and the first source / drain metal layer. In this example, the first composite insulating layer 11 may include: the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103. The first source / drain metal layer is the aforementioned metal conductive layer.

[0076] In some examples, such as Figure 3 As shown, the first composite insulating layer 11 may include a first groove at least located in the first bending region B10. The first groove may include a first edge 111 and a second edge 112 disposed opposite to each other. The first edge 111 may be located on the side of the second edge 112 closer to the display area AA. The first planarization layer 106 may cover the first groove of the first bending region B10. In some examples, at least one of the first edge 111 and the second edge 112 may be a non-smooth edge. For example, the slope angle α of the first edge 111 and the slope angle b of the second edge 112 may be approximately the same, for example, both may be less than 40 degrees, such as approximately 35 degrees. In other examples, the slope angle α of the first edge 111 and the slope angle b of the second edge 112 may both be less than 40 degrees and are not the same. In some examples, the first source / drain metal layer may include at least a first power trace, which may cross the first groove of the first bending region B10 and be electrically connected to a first bonding pin of the first bonding region.

[0077] In some examples, before fabricating the first source / drain metal layer, the first composite insulating layer 11 can be patterned using a first mask to form a first groove with a first edge 111 and a second edge 112 in the first bending region B10, and to form a plurality of first connection holes in the display region AA. For example, the plurality of first connection holes may include: vias exposing a portion of the surface of the first semiconductor layer in the display region (e.g., including the aforementioned plurality of first pixel vias), vias exposing a portion of the surface of the first gate metal layer, and vias exposing a portion of the surface of the second gate metal layer. In this example, the process of opening the first composite insulating layer in the display region (i.e., forming a plurality of first connection holes) and the process of trenching in the first bending region (e.g., forming a first groove in the first bending region) can be performed using the same first mask, achieved through a single patterning process, thereby saving costs and increasing production capacity.

[0078] Figure 4 This is a partial top view of the first bending region according to at least one embodiment of the present disclosure. In some examples, such as... Figure 4 As shown, the first edge 111 and the second edge 112 of the first groove 21 in the first bending region B10 of the first composite insulating layer 11 can both be non-smooth edges. The first edge 111 may include a first edge portion 1110 and a plurality of first serrated portions 1111 extending from the first edge portion 1110 toward the side away from the display area. The plurality of first serrated portions 1111 can be spaced apart on the side of the first edge portion 1110 away from the display area. The second edge 112 may include a second edge portion 1120 and a plurality of second serrated portions 1121 extending from the second edge portion 1120 toward the side near the display area. The plurality of second serrated portions 1121 can be spaced apart on the side of the second edge portion 1120 near the display area. The orthographic projection shapes of the first serrated portions 1111 and the second serrated portions 1121 on the substrate can be substantially the same. For example, the orthographic projections of a single first serrated portion 1111 and a single second serrated portion 1121 on the substrate can both be trapezoidal. However, this embodiment is not limited to this. In other examples, the orthographic projection shapes of the first and second serrated portions onto the substrate can be different, for example, they can be rectangular, triangular, or semi-circular. This example, by setting the first and second edges of the first composite insulating layer in the first bending region to be non-smooth edges, can reduce the etching slope angle of the first composite insulating layer boundary, thereby reducing the risk of metal residue at the edge of the first composite insulating layer due to the grooves in the bending region.

[0079] In some examples, such as Figure 4As shown, the dimensions of the plurality of first serrated portions 1111 and the plurality of second serrated portions 1121 can be substantially the same. For example, the length H1 of the first serrated portion 1111 along the first direction Y and the length H2 of the second serrated portion 1121 along the first direction Y can be substantially the same, for example, approximately 5 micrometers to 7 micrometers, or approximately 6 micrometers. In the second direction X, the dimensions of the first serrated portions 1111 and the spacing between adjacent first serrated portions 1111 can be substantially the same, and the dimensions of the second serrated portions 1121 and the spacing between adjacent second serrated portions 1121 can be substantially the same. The dimensions of the first serrated portions 1111 along the second direction X and the dimensions of the second serrated portions 1121 along the second direction X can be substantially the same. In some examples, in the second direction X, the dimensions of the first serrated portions 1111 (e.g., the average length along the second direction X) can be approximately 0.8 micrometers to 1.2 micrometers, for example, approximately 1 micrometer. In the second direction X, the spacing between adjacent first serrated portions 111a can be approximately 0.8 micrometers to 1.2 micrometers, for example, approximately 1 micrometer. However, this embodiment is not limited in this respect. The size and shape of the first edge and the second edge of the first composite insulating layer in the first bending region of this example are beneficial to reducing the edge profile, increasing the process boundary, and improving the metal residue situation.

[0080] In some examples, such as Figure 4 As shown, the plurality of first serrated portions 1111 of the first edge 111 and the plurality of second serrated portions 1121 of the second edge 112 can be aligned in the first direction Y. However, this embodiment is not limited to this. For example, the plurality of first serrated portions 1111 and the plurality of second serrated portions 1121 may be misaligned in the first direction Y.

[0081] In some examples, the first mask may employ a grayscale mask design in the first border area. The grayscale mask design, through the grating effect, allows for different intensities of light transmitted through different areas of the first mask in the first border area, thereby enabling selective exposure and development of the photoresist. Using a grayscale mask design in this example can save costs. However, this embodiment is not limited to this. In other examples, the first mask may employ a halftone mask design in the first border area.

[0082] In some examples, taking a grayscale mask design as an example, the first mask may include transparent areas, opaque areas, and semi-transparent areas. The transparent areas may correspond at least to the opening areas of the display area and the groove areas of the first bending area. The semi-transparent areas may correspond at least to at least a portion of the first edge and the second edge of the first composite insulating layer. The opaque areas may correspond to the remaining areas of the display substrate. For example, before fabricating the first source / drain metal layer, photoresist can be coated on the third insulating layer. After exposing and developing the photoresist using the first mask, a photoresist fully retained area, a photoresist partially retained area, and a photoresist completely removed area can be formed. The photoresist fully retained area corresponds to the opaque area of ​​the first mask, the photoresist partially retained area corresponds to the semi-transparent area of ​​the first mask, and the photoresist completely removed area corresponds to the transparent area of ​​the first mask. Subsequently, etching processes can be performed sequentially in the photoresist completely removed area and the photoresist partially retained area to form the first connection hole of the display area and the first groove of the first bending area. This example demonstrates how a single patterning process can simultaneously achieve the opening of the display area and the trenching of the first bending area, reducing process steps, complexity, and cost. Furthermore, the first mask, designed using a grayscale mask, can meet the different etching load requirements of different areas of the display substrate. For example, the etching requirement for the display area is that it cannot penetrate the first semiconductor layer, and the slope angle of the inorganic insulating layer can be approximately 75 degrees, while the slope angle of the insulating layer in the first bending area needs to be less than 40 degrees. The grayscale mask design used in this example can meet the etching requirements of the first border area and reduce the edge profile of the first composite insulating layer in the first bending area, increasing the process boundary and preventing metal residue from subsequent metal layer etching that could cause signal short circuits, thereby improving product yield.

[0083] Figure 5 This is another partial top view of the first bending region according to at least one embodiment of the present disclosure. In some examples, such as Figure 5 As shown, the first edge 111 of the first composite insulating layer 11 in the first groove 21 of the first bending region B10 can be a non-smooth edge, and the second edge 112 can be a smooth edge. The first edge 111 may include a first edge portion 1110 and a plurality of first serrated portions 1111 extending from the first edge portion 1110 toward the side away from the display area, and the second edge 112 facing the plurality of first serrated portions 1111 can be a smooth edge. The structure of the first edge 111 can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0084] In this example, the morphology of the first and second edges of the first composite insulating layer in the first bending region can adapt to the etching load of different areas of the first frame region, and is beneficial for reducing the edge profile of the first bending region, increasing the process boundary, and improving metal residue. However, this embodiment is not limited in this respect. In other examples, the first edge of the first composite insulating layer can be a smooth edge, and the second edge can be a non-smooth edge. Further descriptions of this embodiment can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0085] Figure 6 This is another partial top view of the first bending region according to at least one embodiment of the present disclosure. Figure 7 for Figure 2 Another partial cross-sectional view along the R-R' direction. In some examples, such as... Figure 6 and Figure 7 As shown, the first composite insulating layer 11 may include: a first insulating layer 101, a second insulating layer 102, and a third insulating layer 103 stacked together. The orthographic projections of the first insulating layer 101 and the second insulating layer 102 at the first edge 111 and the second edge 112 onto the substrate may coincide, and the orthographic projections of the third insulating layer 103 at the first edge 111 and the second edge 112 onto the substrate may be located within the orthographic projection range of the second insulating layer 102 onto the substrate. Figure 7 As shown, at the first edge 111, the edge of the third insulating layer 103 can be located on the side of the edge of the second insulating layer 102 closer to the display area, and the edges of the third insulating layer 103 and the second insulating layer 102 can be designed in a stepped shape; at the second edge 112, the edge of the third insulating layer 103 can be located on the side of the edge of the second insulating layer 102 away from the display area, and the edges of the third insulating layer 103 and the second insulating layer 102 can be designed in a stepped shape. At the first edge 111, the first insulating layer 101 and the second insulating layer 102 can have multiple first sub-serrations 1111a, and the third insulating layer 103 can have multiple first sub-serrations 1111b. The first sub-serrations 1111a and 1111b can be aligned in the first direction Y or can be misaligned. The size of the first sub-serration 1111a can be greater than or equal to the size of the first sub-serration 1111b. At the second edge 112, the first insulating layer 101 and the second insulating layer 102 may have a plurality of second sub-serrations 1121a, and the third insulating layer 103 may have a plurality of second sub-serrations 1121b. The second sub-serrations 1121a and 1121b may be aligned or misaligned in the first direction Y. The size of the second sub-serration 1121a may be greater than or equal to the size of the second sub-serration 1121b. However, this embodiment is not limited in this respect.

[0086] This example demonstrates a differentiated design (e.g., a stepped design) for the edges of different insulating layers in the first composite insulating layer at the first bending region. This design allows the edge morphology of the first composite insulating layer at the first bending region to reduce the edge profile of the first bending region, increase the process boundary, and improve metal residue. In other examples, at the first and second edges, the first, second, and third insulating layers can be sequentially designed in a stepped shape, and each of the first, second, and third insulating layers can form sub-serrations of approximately the same size. In still other examples, the edges of the first and second insulating layers can be designed in a stepped shape, and the edges of the second and third insulating layers can overlap. Further details regarding this embodiment can be found in the description of the foregoing embodiments and will not be repeated here.

[0087] Figure 8 for Figure 2 Another partial cross-sectional view along the R-R' direction. In some examples, such as... Figure 8 As shown, the display substrate can be an LTPO display substrate. Figure 8 The diagram illustrates a first transistor 21b, a second transistor 23, and a capacitor 22b in a pixel circuit of display area AA. For example, the first transistor 21b can be a low-temperature polycrystalline silicon thin-film transistor, and the second transistor 23 can be an oxide thin-film transistor.

[0088] In some examples, such as Figure 8 As shown, in a direction perpendicular to the display substrate, the display area AA may include: a substrate 100, and a first semiconductor layer, a first insulating layer 101, a first gate metal layer, a second insulating layer 102, a second gate metal layer, a third insulating layer 103, a second semiconductor layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source / drain metal layer, and a first planarization layer 106 sequentially disposed on the substrate 100. In some examples, the first insulating layers 101 to 105 may be inorganic insulating layers, and the first planarization layer 106 may be an organic insulating layer. For example, the first composite insulating layer 11 may include at least one inorganic insulating layer on the side of the second semiconductor layer near the substrate, and the second composite insulating layer may include at least one inorganic insulating layer on the side of the second semiconductor layer away from the substrate. In this example, the first composite insulating layer 11 may include the first insulating layers 101 to 103, and the second composite insulating layer 12 may include the fourth insulating layer 104 and the fifth insulating layer 105. The first source / drain metal layer in this example is the aforementioned metal conductive layer.

[0089] In some examples, such as Figure 8As shown, the first composite insulating layer 11 may include a first groove at least located in the first bending region B10. The first groove may include a first edge 111 and a second edge 112 disposed opposite to each other. The first edge 111 may be located on the side of the second edge 112 closer to the display area AA. The second composite insulating layer 12 may include a second groove at least located in the first bending region B10. The second groove may include a third edge 121 and a fourth edge 122 disposed opposite to each other. The third edge 121 may be located on the side of the fourth edge 122 closer to the display area AA. The first flattening layer 106 may cover the first groove and the second groove of the first bending region B10. In some examples, the slope angles of the first edge 111 and the second edge 112, the third edge 121 and the fourth edge 122 may be approximately the same, for example, all may be less than 40 degrees, such as approximately 35 degrees. In other examples, the slope angles of the first edge 111 and the second edge 112, the third edge 121 and the fourth edge 122 may be partially the same or all different. In some examples, the first source-drain metal layer may include at least a first power trace, which may be electrically connected to a first bonding pin of the first bonding region across the first recess and the second recess of the first bend region B10.

[0090] The structure of a display substrate is illustrated below using an example of the fabrication process. In some examples, the fabrication process of a display substrate may include the following operations.

[0091] (1) Providing a substrate. In some examples, the substrate may be a flexible substrate. For example, the flexible substrate may include, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In some examples, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si). This embodiment is not limited in this respect.

[0092] (2) Forming a first semiconductor layer. In some examples, a first semiconductor thin film is sequentially deposited on a substrate, and the first semiconductor thin film is patterned by a patterning process to form a first semiconductor layer disposed on the substrate. In some examples, the material of the first semiconductor layer may be amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc. For example, the first semiconductor layer may include at least the active layer of the first transistor 21b.

[0093] (3) Forming a first gate metal layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate on which the aforementioned structure is formed. The first conductive film is patterned using a patterning process to form a first insulating layer and a first gate metal layer disposed on the first insulating layer. For example, the first gate metal layer may include at least: the gate of the first transistor 21b and the first electrode of the first capacitor 22b. After this process, the first bending region may include the first insulating layer disposed on the substrate.

[0094] (4) Forming a second gate metal layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate on which the aforementioned structure is formed. The second conductive film is patterned using a patterning process to form a second insulating layer and a second gate metal layer disposed on the second insulating layer. For example, the second gate metal layer may include at least the second electrode of the first capacitor 22b. After this process, the first bending region may include the first insulating layer and the second insulating layer disposed on the substrate.

[0095] (5) Forming a second semiconductor layer. In some examples, a third insulating film and a second semiconductor layer film are sequentially deposited on the substrate on which the aforementioned structure is formed. The second semiconductor film is patterned using a patterning process to form a third insulating layer and a second semiconductor layer disposed on the third insulating layer. In some examples, the material of the second semiconductor layer may include indium gallium zinc oxide (IGZO). For example, the second semiconductor layer may include at least the active layer of the second transistor 23. After this process, the first bending region may include the first insulating layer, the second insulating layer, and the third insulating layer disposed on the substrate.

[0096] (6) Forming a third gate metal layer. In some examples, a fourth insulating film and a third conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed. The third conductive film is patterned using a patterning process to form a fourth insulating layer and a third conductive layer disposed on the fourth insulating layer. For example, the third gate metal layer may include at least the gate of the second transistor 23. After this process, the first bending region may include the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer disposed on the substrate.

[0097] (7) Forming the fifth insulating layer. In some examples, a fifth insulating film is deposited on the substrate on which the aforementioned pattern is formed, and the fifth insulating film is patterned through two patterning processes to form the fifth insulating layer. In some examples, a first patterning process is performed using a first mask to pattern the first composite insulating layer 11, forming a plurality of first connection holes in the display area (e.g., vias exposing a portion of the surface of the first semiconductor layer, vias exposing a portion of the surface of the first gate metal layer, and vias exposing a portion of the surface of the second gate metal layer), and a groove is cut in the first bending region to form a first edge and a second edge located on both sides of the first groove. The first mask may employ a grayscale mask design in the first border region.

[0098] In some examples, a second patterning process is performed using a second mask to pattern the second composite insulating layer 12, forming multiple second connection holes (e.g., vias exposing a portion of the surface of the second semiconductor layer and vias exposing a portion of the surface of the third gate metal layer) in the display area. A groove is cut in the second composite insulating layer 12 in the first bending region to form a third edge and a fourth edge located on both sides of the second groove. The second mask may employ a grayscale mask design in the first border area. This embodiment is not limited to this. The grayscale mask design can be referred to the description in the foregoing embodiments, and therefore will not be repeated here.

[0099] Figure 9 This is a partial schematic diagram of the first bending region according to at least one embodiment of the present disclosure. In some examples, such as... Figure 8 and Figure 9 As shown, the first edge 111 and the second edge 112 of the first groove 21 in the first bending region B10 of the first composite insulating layer 11 can be non-smooth edges. The first edge 111 may include a plurality of first serrated portions 1111, and the second edge 112 may include a plurality of second serrated portions 1121. The morphology of the first edge 111 and the second edge 112 can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0100] In some examples, such as Figure 8 and Figure 9As shown, the third edge 121 and the fourth edge 122 of the second groove 22 in the first bending region B10 of the second composite insulating layer 12 can be non-smooth edges. The orthogonal projection of the second groove 22 onto the substrate can cover the orthogonal projection of the first groove 21 onto the substrate. The third edge 121 can be located on the side of the first edge 111 closer to the display area, and the fourth edge 122 can be located on the side of the second edge 112 away from the display area. The third edge 121 can include a plurality of third serrated portions 1211, and the fourth edge 122 can include a plurality of fourth serrated portions 1221. The arrangement and size of the third serrated portions 1211 and the fourth serrated portions 1221 can be substantially the same as the arrangement and size of the first serrated portions 1111 and the second serrated portions 1121. The description of the third serrated portions 1211 and the fourth serrated portions 1222 can be referred to the description of the first serrated portions 1111 and the second serrated portions 1121 in the foregoing embodiments, and therefore will not be repeated here. However, this embodiment is not limited in this respect. In other examples, at least one of the third edge 121 and the fourth edge 122 can be a smooth edge, for example, with Figure 5 The second edge 112 shown has a similar shape. In other examples, the fourth insulating layer 104 and the fifth insulating layer 105 of the second composite insulating layer 12 may not overlap at the edges of the first bending region; for example, they may be arranged as follows: Figure 6 The stepped design shown.

[0101] (8) Forming a first source / drain metal layer. In some examples, a fourth conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the fourth conductive film is patterned by a patterning process to form the first source / drain metal layer on the fifth insulating layer. For example, the first source / drain metal layer may include: the source and drain of the first transistor 21b, the source and drain of the second transistor 23, and a first power line. The first power line may extend across the first bend region to the first bonding region.

[0102] (9) Forming a first planarization layer. In some examples, a sixth insulating film is coated on the substrate on which the aforementioned pattern is formed, and the sixth insulating film is patterned by a patterning process to form a first planarization layer. The first planarization layer may cover the first and second grooves in the first bending region and planarize the first bending region. In some examples, a second source / drain metal layer, a second planarization layer, and a light-emitting structure layer may also be formed on the side of the first planarization layer away from the substrate; or, a light-emitting structure layer may be formed directly. An encapsulation structure layer may be formed on the side of the light-emitting structure layer away from the substrate. This embodiment is not limited in this respect.

[0103] In some examples, an anode thin film can be deposited on the substrate forming the aforementioned structure, and the anode thin film can be patterned using a patterning process to form an anode layer. A pixel definition thin film is coated on the substrate with the aforementioned pattern, and a pixel definition layer is formed using a masking, exposure, and development process. The pixel definition layer of the display area has multiple pixel openings. An organic light-emitting layer is formed within the pixel openings, and the organic light-emitting layer is connected to the anode. Subsequently, a cathode thin film is deposited, and the cathode thin film is patterned using a patterning process to form a cathode layer, which can be electrically connected to the organic light-emitting layer. Subsequently, an encapsulation structure layer is formed on the cathode layer, and the encapsulation structure layer may include a stacked structure of inorganic / organic / inorganic materials.

[0104] In some exemplary embodiments, the first gate metal layer, the second gate metal layer, the third gate metal layer, and the first source / drain metal layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first to fifth insulating layers can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first planarization layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The anode layer can be made of reflective materials such as metal, and the cathode layer can be made of transparent conductive materials. However, this embodiment is not limited in this respect.

[0105] The structure and fabrication process of the display substrate in this embodiment are merely illustrative. In some exemplary embodiments, the corresponding structure and patterning processes can be modified and added or reduced according to actual needs. The fabrication process of this exemplary embodiment can be implemented using currently mature fabrication equipment, is well compatible with existing fabrication processes, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0106] In this example, the process of creating holes in the first composite insulating layer in the display area and the process of creating grooves in the first bending area can be performed using the same first mask, achieved through a single patterning process. Similarly, the process of creating holes in the second composite insulating layer in the display area and the process of creating grooves and vias in the first bending area can be performed using the same second mask, achieved through a single patterning process, thereby saving costs and increasing production capacity. Furthermore, the display substrate in this example uses a grayscale mask design for both the first and second masks, which can meet the etching requirements at different locations in the first bezel area. This also reduces the edge profile of the first composite insulating layer in the first bending area, increasing the process boundary and preventing metal residue from subsequent metal layer etching that could cause signal short circuits, thus improving product yield.

[0107] Figure 10 This is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, such as... Figure 10 As shown, the display substrate of this example may include a display area AA and a border area surrounding the display area AA. The border area may include a first border area B1 and a second border area B2 located on opposite sides of the display area AA along a first direction Y, and a third border area B3 and a fourth border area B4 located on opposite sides of the display area AA along a second direction X. The display substrate may have a generally rectangular shape. For example, the display substrate may include a pair of short sides parallel to the first direction Y and a pair of long sides parallel to the second direction X, that is, the length of the display substrate in the first direction Y may be less than the length in the second direction X. The first direction Y and the second direction X may intersect each other; for example, the first direction Y may be perpendicular to the second direction X. However, this embodiment is not limited in this respect. The description of the display area, the first border area, the third border area, and the fourth border area of ​​this example can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0108] Figure 11 This is a partial schematic diagram of the second border region according to at least one embodiment of the present disclosure. In some examples, such as... Figure 10 and Figure 11 As shown, the second border area B2 may include: a second trace area B22, a second bend area B20, and a second bonding area B21, sequentially arranged along a direction away from the display area AA. The second trace area B22 may communicate with the display area AA, the third border area B3, and the fourth border area B4. The second bend area B20 may be configured to bend the second bonding area B21 to the back of the display area AA. The second bonding area B21 may include multiple bonding pins, which may be configured to bond with an external FPC.

[0109] In some examples, such as Figures 10 to 11As shown, a first power trace (e.g., a low-potential power line) may be provided in the peripheral area of ​​the display substrate. The first power trace may include a first sub-trace PLA, a second sub-trace PLb, and a third sub-trace PLc. The first sub-trace PLA may be located within the third frame area B3 and extend to the first bonding area B11 of the first frame area B1 to electrically connect with a first bonding pin within the first bonding area B11; the first sub-trace PLA may also extend to the second bonding area B21 of the second frame area B2 to electrically connect with a second bonding pin within the second bonding area B21. The third sub-trace PLc may be located within the fourth frame area B4 and extend to the first bonding area B11 of the first frame area B1 to electrically connect with another first bonding pin within the first bonding area B11; the third sub-trace PLc may also extend to the second bonding area B21 of the second frame area B2 to electrically connect with another second bonding pin within the second bonding area B21. The second sub-trace PLb can be located within the second trace area B22 of the second bezel area B2, and both ends can extend into the second bonding area B21, and be electrically connected to the second bonding pin within the second bonding area B21. In this example, the first power trace can be arranged around three sides of the display area using the first sub-trace PLA, the second sub-trace PLb, and the third sub-trace Plc. In this example, by bonding the first power trace to the FPC in the first bezel area B1 and the second bezel area B2, the signal voltage drop of the first power trace can be reduced, mitigating the impact of the increased size of the display substrate on the voltage drop of the first power trace surrounding the display area. In this example, the second bend area B20 in the second bezel area B2 not only facilitates the narrow bezel design of the display substrate but also helps to mitigate the impact of the increased size of the display substrate on the trace voltage drop.

[0110] Figure 12 for Figure 11 A partial cross-sectional view along the Q-Q' direction. Figure 13 This is a partial schematic diagram of the second bending region according to at least one embodiment of the present disclosure. In some examples, the display substrate may be an LTPS display substrate. For example... Figure 12 and Figure 13As shown, the first composite insulating layer 11 may include at least a third groove 23 located in the second bending region B20. The third groove 23 may include a fifth edge 115 and a sixth edge 116 disposed opposite to each other. The fifth edge 115 may be located on the side of the sixth edge 116 closer to the display area AA. The first planarization layer 106 may, for example, cover the third groove 23 of the second bending region B20. The fifth edge 115 and the sixth edge 116 of the first composite insulating layer 11 in the second bending region B20 may both be non-smooth edges. The fifth edge 115 may include a plurality of fifth serrated portions 1151, and the sixth edge 116 may include a plurality of sixth serrated portions 1161. The shapes and sizes of the fifth serrated portions 1151 and the sixth serrated portions 1161 may be substantially the same. The length H3 of the fifth serrated portion 1151 along the first direction Y and the length H4 of the sixth serrated portion 1161 along the first direction Y may be substantially the same. For example, the length H3 of the fifth serrated portion 1151 along the first direction Y may be less than the length H1 of the first serrated portion along the first direction Y. This allows for adaptation to different etching loads in the first and second border regions. However, this embodiment is not limited in this respect. The dimensions and morphology of the fifth and sixth edges of the first composite insulating layer in the second bending region in this example can refer to the edge morphology of the first composite insulating layer in the first bending region, and therefore will not be repeated here. The edge morphology of the first composite insulating layer in the second bending region in this example can help reduce the edge profile, increase the process boundary, and improve metal residue. In other examples, the fifth edge 115 or the sixth edge 116 can be a non-smooth edge.

[0111] Figure 14 for Figure 11 Another partial cross-sectional view along the Q-Q' direction. Figure 15 This is another partial schematic diagram of the second bending region according to at least one embodiment of the present disclosure. In some examples, such as... Figure 14 and Figure 15 As shown, the display substrate can be an LTPO display substrate. The first composite insulating layer 11 may include at least a third groove 23 located in the second bending region B20. The third groove 23 may include a fifth edge 115 and a sixth edge 116 disposed opposite to each other. The fifth edge 115 may be located on the side of the sixth edge 116 closer to the display area AA. The second composite insulating layer 12 may include at least a fourth groove 24 located in the second bending region B20. The fourth groove 24 may include a seventh edge 127 and an eighth edge 128 disposed opposite to each other. The seventh edge 127 may be located on the side of the eighth edge 128 closer to the display area AA. The seventh edge 127 is located on the side of the fifth edge 115 closer to the display area AA, and the eighth edge 128 is located on the side of the sixth edge 116 away from the display area AA. The first planarization layer 106 may, for example, cover the third groove 23 and the fourth groove 24 of the second bending region B20.

[0112] In some examples, such as Figure 14 and Figure 15 As shown, the fifth edge 115 and the sixth edge 116 of the first composite insulating layer 11 can both be non-smooth edges, and the seventh edge 127 and the eighth edge 128 of the second composite insulating layer 12 can both be non-smooth edges. The slope angle of the non-smooth edges can be less than 40 degrees. The slope angles of the fifth edge 115, the sixth edge 116, the seventh edge 127, and the eighth edge 128 can be approximately the same, for example, approximately 35 degrees, or they can be partially the same. This embodiment is not limited in this respect. In other examples, the fifth edge 115 or the sixth edge 116 can be a non-smooth edge, and the seventh edge 127 or the eighth edge 128 can be a non-smooth edge.

[0113] In some examples, such as Figure 15 As shown, the fifth edge 115 of the first composite insulating layer 11 may include a plurality of fifth serrated portions 1151, and the sixth edge 116 may include a plurality of sixth serrated portions 1161; the seventh edge 127 of the second composite insulating layer 12 may include a plurality of seventh serrated portions 1271, and the eighth edge 128 may include a plurality of eighth serrated portions 1281. The plurality of fifth serrated portions 1151 and the plurality of seventh serrated portions 1271 may be aligned in the first direction Y, or they may be misaligned; the plurality of sixth serrated portions 1161 and the plurality of eighth serrated portions 1281 may be aligned in the first direction Y, or they may be misaligned. The dimensions of the sixth serrated portions 1161 and the eighth serrated portions 1281 of the second composite insulating layer 12 may be approximately the same, and may be smaller than the dimensions of the third serrated portions 1211 and the fourth serrated portions 1221 of the second composite insulating layer 12 in the first bending region. This is to accommodate different etching loads in the first and second border regions. The description of the remaining edge morphology of the first and second composite insulating layers in the second bending region in this example can refer to the description of the edge morphology of the first bending region, and therefore will not be repeated here. The edge morphology of the first and second composite insulating layers in the first bending region can be as described in the foregoing embodiments.

[0114] In some examples, the first mask used to fabricate the first composite insulating layer can employ a grayscale mask design in both the first and second border regions, thereby simultaneously forming the first and second edges in the first bending region, and the fifth and sixth edges in the second bending region. Similarly, the second mask used to fabricate the second composite insulating layer can employ a grayscale mask design in both the first and second border regions, thereby simultaneously forming the third and fourth edges in the first bending region, and the seventh and eighth edges in the second bending region. In this example, the display substrate can utilize a first and second mask with a grayscale mask design to meet the etching requirements of the first and second border regions. This reduces the edge profiles of the first and second composite insulating layers in the first and second bending regions, increases the process boundary, and avoids metal residue from subsequent metal layer etching that could cause signal short circuits, thus improving product yield.

[0115] Figure 16 for Figure 11 Another partial cross-sectional view along the Q-Q' direction. Figure 17 This is another partial schematic diagram of the second bending region according to at least one embodiment of the present disclosure. In some examples, the display substrate may be an LTPO display substrate. Figure 16 and Figure 11 As shown, the first composite insulating layer 11 may include a third groove 23 located at least in the second bending region B20. The third groove 23 may include a fifth edge 115 and a sixth edge 116 disposed opposite to each other. The fifth edge 115 may be located on the side of the sixth edge 116 closer to the display area AA. Both the fifth edge 115 and the sixth edge 116 may be non-smooth edges. The fifth edge 115 may include a plurality of fifth serrated portions 1151, and the sixth edge 116 may include a plurality of sixth serrated portions 1161. A description of the fifth edge 115 and the sixth edge 116 can be found in the description of the foregoing embodiments, and therefore will not be repeated here.

[0116] In some examples, such as Figure 16 and Figure 17 As shown, the second composite insulating layer 12 may include at least a fourth groove 24 located in the second bending region B20. The fourth groove 24 may include a seventh edge 127 and an eighth edge 128 disposed opposite to each other. The seventh edge 127 may be located on the side of the eighth edge 128 closer to the display area AA. In this example, the seventh edge 127 and the eighth edge 128 may be smooth edges. The slope angles of the seventh edge 127 and the eighth edge 128 may be approximately the same. The slope angles of the seventh edge 127 and the eighth edge 128 may be greater than the slope angles of the fifth edge 115 and the sixth edge 116.

[0117] In some examples, the edge morphology of the first composite insulating layer 11 and the second composite insulating layer 12 in the first bending region can be as follows: Figure 9 As shown. The edge morphology of the first composite insulating layer 11 and the second composite insulating layer 12 in the second bending region can be as follows. Figure 17 As shown. In this example, the morphology of the seventh and eighth edges of the second composite insulating layer 12 in the second bending region may differ from that of the third and fourth edges in the first bending region. In some examples, the first composite insulating layer 11 may utilize the grayscale mask design of the first mask to form the first and second edges in the first bending region, while simultaneously forming the fifth and sixth edges in the second bending region. The second composite insulating layer 12 may utilize the grayscale mask design of the second mask to form the third and fourth edges in the first bending region, while simultaneously forming the seventh and eighth edges in the second bending region without utilizing the grayscale mask design. The slope angle of the seventh and eighth edges may be greater than that of the third or fourth edges.

[0118] The edge morphology of the first composite insulating layer and the second composite insulating layer in the first bending region can be as described in the foregoing embodiment. The remaining structure of the display substrate of this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0119] In this example, the display substrate has different sizes for the first and second border areas, resulting in different etching loads in their bending areas. Therefore, the first and second masks with grayscale mask design can meet the different etching requirements of the first and second border areas. Furthermore, it can reduce the edge profile of the first composite insulating layer in the bending area, increase the process boundary, and avoid the situation where metal residue caused by subsequent metal layer etching leads to signal short circuits, thereby improving product yield.

[0120] In other examples, the above embodiments can be combined with each other. For example, the first composite insulating layer may have a smooth edge at the first or second edge of the first bending region, and the second composite insulating layer may have a smooth edge at the seventh or eighth edge of the second bending region; or, the first composite insulating layer may have a smooth edge at the fifth or sixth edge of the second bending region, and the second composite insulating layer may have a smooth edge at the third or fourth edge of the first bending region. This embodiment is not limited in this respect.

[0121] This embodiment also provides a method for fabricating a display substrate, for fabricating the display substrate as described above, comprising: forming a first composite insulating layer on a substrate; and forming a metal conductive layer on the side of the first composite insulating layer away from the substrate. The substrate includes a display area and a first border area located on at least one side of the display area along a first direction; the first border area has a first bending region; the first insulating layer includes a first groove located at least in the first bending region, the first groove including a first edge and a second edge disposed opposite to each other; at least one of the first edge and the second edge is a non-smooth edge. The metal conductive layer is partially located in the first bending region.

[0122] In some exemplary embodiments, forming a first composite insulating layer on a substrate may include: patterning the first composite insulating layer using a first mask to form a first edge and a second edge of the first composite insulating layer in a first border region, wherein the first mask employs a grayscale mask design in the first border region. This example, by employing a grayscale mask design for the first mask, can help reduce the slope angle of the edge of the first composite insulating layer in the first bending region and can save costs. However, this embodiment is not limited to this. For example, the first mask may employ a halftone mask design in the first border region.

[0123] In some exemplary embodiments, the substrate may further include: a second border region, the second border region and the first border region being located on opposite sides of the display area along a first direction; the second border region may have a second bend region. Forming the first composite insulating layer on the substrate may further include: patterning the first composite insulating layer using a first mask to form a fifth edge and a sixth edge of the first composite insulating layer in the second border region, wherein the first mask employs a grayscale mask design in the second border region. This example, by employing a first mask with a grayscale mask design, can advantageously reduce the slope angle of the first composite insulating layer at the edge of the second bend region and can save costs.

[0124] In some exemplary embodiments, forming the first composite insulating layer on the substrate may further include: simultaneously forming a first groove of the first composite insulating layer in the first border region, and using a first mask to form a plurality of first connection holes on the first composite insulating layer in the display area. This example uses the same mask to form the vias in the display area and the insulating layer grooves in the bending area, which helps to save process steps and reduce costs.

[0125] In some exemplary embodiments, the fabrication method of this example may further include: forming a second composite insulating layer on the side of the first composite insulating layer away from the substrate before forming the metal conductive layer. The second composite insulating layer includes a second groove located at least in the first bending region, and the second groove includes a third edge and a fourth edge disposed opposite to each other, at least one of the third edge and the fourth edge being a non-smooth edge. The first edge may be located on the side of the second edge closer to the display area, the third edge may be located on the side of the first edge closer to the display area, and the fourth edge may be located on the side of the second edge away from the display area.

[0126] In some exemplary embodiments, forming a second composite insulating layer on the side of the first composite insulating layer away from the substrate may include: patterning the second composite insulating layer using a second mask to form a third and fourth edge of the second composite insulating layer in a first border region, wherein the second mask employs a grayscale mask design in the first border region. This example, by using a second mask with a grayscale mask design, helps to reduce the slope angle of the edge of the second composite insulating layer in the first bending region and can save costs.

[0127] In some exemplary embodiments, the substrate may further include: a second border region, the second border region and the first border region being located on opposite sides of the display area along a first direction; the second border region having a second bend region. Forming the second composite insulating layer on the side of the first composite insulating layer away from the substrate may further include: patterning the second composite insulating layer using a second mask to form the seventh and eighth edges of the fourth groove of the second composite insulating layer in the second border region, wherein the second mask employs a grayscale mask design in the second border region. This example, by employing a grayscale mask design in the second mask, helps to reduce the slope angle of the second composite insulating layer at the edge of the second bend region and can save costs. In other examples, the second mask employs a grayscale mask design in the first border region, while a grayscale mask design may not be used in the second border region. This, considering the difference in etching load between the first and second border regions, can help to reduce the slope angle of the second composite insulating layer at the edge of the first bend region and can save costs.

[0128] In some exemplary embodiments, forming a second composite insulating layer on the side of the first composite insulating layer away from the substrate may further include: simultaneously forming a second groove of the second composite insulating layer in the first border region, and using a second mask to form a plurality of second connection holes on the second composite insulating layer in the display area. This example uses the same mask to form the vias in the display area and the insulating layer grooves in the bending area, which can help save process steps and reduce costs.

[0129] The remaining descriptions of the method for preparing the display substrate in this embodiment can be found in the descriptions of the foregoing embodiments, and therefore will not be repeated here.

[0130] Figure 18 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some examples, such as... Figure 18As shown, this embodiment provides a display device 91, including the display substrate 910 of the aforementioned embodiment. In some examples, the display substrate 910 can be an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device 91 can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. However, this embodiment is not limited to this.

[0131] The accompanying drawings in this disclosure only illustrate the structures involved in this disclosure; other structures can be referred to with common design. Unless otherwise specified, the embodiments and features described in these embodiments can be combined to obtain new embodiments. Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this disclosure without departing from the spirit and scope of this disclosure, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.

Claims

1. A display substrate, characterized in that, include: The substrate includes a display area and a first border area located on at least one side of the display area along a first direction, the first border area having a first bending area; A first composite insulating layer includes a first groove extending along a second direction, the first groove being at least located in the first bending region, the first groove including a first edge and a second edge disposed opposite to each other along the first direction, and at least one of the first edge and the second edge being a non-smooth edge; A metallic conductive layer is located on the side of the first composite insulating layer away from the substrate, and is partially located in the first bending region; The non-smooth edge has a plurality of serrated portions spaced apart along the second direction in the orthographic projection onto the substrate, the second direction intersecting the first direction.

2. The display substrate according to claim 1, characterized in that, The display substrate further includes: a second composite insulating layer located on the side of the first composite insulating layer away from the substrate and on the side of the metal conductive layer close to the substrate; the second composite insulating layer includes: a second groove, the second groove being at least located in the first bending region; the second groove includes a third edge and a fourth edge disposed opposite to each other, at least one of the third edge and the fourth edge being a non-smooth edge; the first edge is located on the side of the second edge close to the display area, the third edge is located on the side of the first edge close to the display area, and the fourth edge is located on the side of the second edge away from the display area.

3. The display substrate according to claim 1, characterized in that, The substrate further includes: a second border region, wherein the second border region and the first border region are located on opposite sides of the display area along the first direction; the second border region has a second bending region; The first composite insulating layer further includes a third groove, the third groove being at least located in the second bending region, the third groove including a fifth edge and a sixth edge disposed opposite to each other, at least one of the fifth edge and the sixth edge being a non-smooth edge.

4. The display substrate according to claim 3, characterized in that, The display substrate further includes: a second composite insulating layer located on the side of the first composite insulating layer away from the substrate and on the side of the metal conductive layer close to the substrate; the second composite insulating layer includes: a fourth groove, the fourth groove being at least located in the second bending region; the fourth groove including a seventh edge and an eighth edge disposed opposite to each other; a fifth edge located on the side of the sixth edge close to the display area; the seventh edge located on the side of the fifth edge close to the display area; and the eighth edge located on the side of the sixth edge away from the display area.

5. The display substrate according to claim 4, characterized in that, At least one of the seventh and eighth edges is a non-smooth edge.

6. The display substrate according to any one of claims 1 to 5, characterized in that, The slope angle of the non-smooth edge is less than 40 degrees.

7. The display substrate according to claim 3, characterized in that, The metal conductive layer includes at least: a first power trace; the first frame area includes a first bonding area located on the side of the first bend area away from the display area, and the second frame area includes a second bonding area located on the side of the second bend area away from the display area; the first bonding area is provided with a first bonding pin, and the second bonding area is provided with a second bonding pin; the first power trace is electrically connected to the first bonding pin in the first bonding area and to the second bonding pin in the second bonding area.

8. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 7.

9. A method for preparing a display substrate, characterized in that, The method for preparing a display substrate as described in any one of claims 1 to 7 comprises: A first composite insulating layer is formed on a substrate; wherein the substrate includes a display area and a first border area located on at least one side of the display area along a first direction; the first border area has a first bending area; the first composite insulating layer includes a first groove located at least in the first bending area and extending along a second direction, the first groove including a first edge and a second edge disposed opposite to each other along the first direction; at least one of the first edge and the second edge is a non-smooth edge; the non-smooth edge has a plurality of serrated portions spaced apart along the second direction in its orthographic projection on the substrate, the second direction intersecting the first direction; A metallic conductive layer is formed on the side of the first composite insulating layer away from the substrate; the portion of the metallic conductive layer is located in the first bending region.

10. The preparation method according to claim 9, characterized in that, The formation of the first composite insulating layer on the substrate includes: The first composite insulating layer is patterned using a first mask to form the first edge and the second edge of the first composite insulating layer in the first border area. The first mask adopts a grayscale mask design in the first border area.

11. The preparation method according to claim 10, characterized in that, The substrate further includes: a second border region, wherein the second border region and the first border region are located on opposite sides of the display area along the first direction; the second border region has a second bending region; The step of forming the first composite insulating layer on the substrate further includes: using the first mask to pattern the first composite insulating layer to form the fifth and sixth edges of the first composite insulating layer in the second border area, wherein the first mask adopts a grayscale mask design in the second border area.

12. The preparation method according to claim 10 or 11, characterized in that, The step of forming a first composite insulating layer on the substrate further includes: while forming a first groove of the first composite insulating layer in the first border area, forming a plurality of first connection holes on the first composite insulating layer in the display area using the first mask.

13. The preparation method according to claim 9, characterized in that, The preparation method further includes: forming a second composite insulating layer on the side of the first composite insulating layer away from the substrate before forming the metal conductive layer; wherein the second composite insulating layer includes a second groove at least located in the first bending region, the second groove includes a third edge and a fourth edge disposed opposite to each other, at least one of the third edge and the fourth edge being a non-smooth edge; the first edge is located on the side of the second edge close to the display area, the third edge is located on the side of the first edge close to the display area, and the fourth edge is located on the side of the second edge away from the display area.

14. The preparation method according to claim 13, characterized in that, A second composite insulating layer is formed on the side of the first composite insulating layer away from the substrate, comprising: The second composite insulating layer is patterned using a second mask, forming the third and fourth edges of the second composite insulating layer in the first border area. The second mask adopts a grayscale mask design in the first border area.

15. The preparation method according to claim 14, characterized in that, The substrate further includes: a second border region, wherein the second border region and the first border region are located on opposite sides of the display area along the first direction; the second border region has a second bending region; A second composite insulating layer is formed on the side of the first composite insulating layer away from the substrate, and further includes: The second composite insulating layer is patterned using a second mask, forming the seventh and eighth edges of the fourth groove of the second composite insulating layer in the second border area. The second mask adopts a grayscale mask design in the second border area.

16. The preparation method according to claim 13, characterized in that, The method of forming a second composite insulating layer on the side of the first composite insulating layer away from the substrate further includes: while forming a second groove of the second composite insulating layer in the first border area, forming a plurality of second connection holes on the second composite insulating layer in the display area using a second mask.