Array substrate, display panel and display device

Abstract

The present invention discloses an array substrate, a display panel and a display device. Each pixel unit of the array substrate includes a first thin film transistor and a second thin film transistor, wherein the first thin film transistor includes a first gate, a first active layer arranged on one side of the first gate, and a first source and a first drain arranged on the side of the first active layer away from the first gate; the second thin film transistor includes a second gate, a second active layer arranged on one side of the second gate, and a second source and a second drain arranged on the side of the second active layer away from the second gate; the first source and the second source are both connected to the pixel electrode; the ratio of the dimension of the first active layer in the width direction to the spacing from the first source to the first drain is greater than the ratio of the dimension of the second active layer in the width direction to the spacing from the second source to the second drain, and the first gate and the second gate are both connected to the same scanning line. The technical solution of the present invention can adapt to different scenarios, reduce energy consumption, and improve the aperture ratio.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate, a display panel using the array substrate, and a display device using the display panel. Background Art

[0002] As display devices become more and more popular, users have higher and higher requirements for display devices. High refresh rate display devices are produced under market demand. However, traditional display devices usually only have high refresh rates or low refresh rates, so it is difficult to choose a suitable refresh rate according to different scenarios. For example, in some situations where high refresh is not required, such as reading news and novels, we need to choose a low refresh rate mode to reduce energy consumption. If the display device only has a high refresh rate mode, the power consumption may increase in this case. Summary of the invention

[0003] The main purpose of the present invention is to provide an array substrate, aiming to improve the problem that traditional display devices cannot select a suitable refresh rate mode according to different scenes.

[0004] To achieve the above-mentioned purpose, the array substrate proposed in the present invention includes a substrate, on which a plurality of pixel units arranged in an array are provided, each of the pixel units includes a pixel electrode, a first thin film transistor and a second thin film transistor, the first thin film transistor includes a first gate, a first active layer, a first drain and a first source, the first gate is provided on one side of the substrate, the first active layer is provided on a side of the first gate away from the substrate, the first source and the first drain are provided at intervals on a side of the first active layer away from the first gate; the spacing between the first source and the first drain is L1; the direction perpendicular to the line between the first source and the first drain and parallel to the substrate is defined as the width direction, and the size of the first active layer in the width direction is W1; the second thin film transistor includes a second gate, a second active layer, a second drain and a second source, the second gate is provided on one side of the substrate side, the second active layer is arranged on the side of the second gate away from the substrate, the second source and the second drain are arranged at intervals on the side of the second active layer away from the second gate; and the first source and the second source are connected to the pixel electrode in parallel; the spacing between the second source and the second drain is L2, the direction perpendicular to the connection line between the second source and the second drain and parallel to the substrate is defined as the width direction, the size of the second active layer in the width direction is W2, and W1 / L1﹥W2 / L2; the array substrate also includes a first data line, a second data line and a scan line, the first data line and the second data line are both perpendicular to the scan line; the first drain and the second drain in the same pixel unit are respectively connected to the first data line and the second data line; and the first gate and the second gate in the same pixel unit are both connected to the same scan line.

[0005] In one embodiment, the first gate and the second gate are formed from the same metal layer.

[0006] In one embodiment, the first active layer and the second active layer are arranged at intervals along an extension direction parallel to the scan line.

[0007] In one embodiment, the first source electrode and the second source electrode are close to each other and spaced apart in a direction parallel to the scan line.

[0008] In one embodiment, the array substrate further includes a metal connection line having three connection ends, and the three connection ends are respectively connected to the pixel electrode, the first source electrode, and the second source electrode.

[0009] In one embodiment, the first active layer and the second active layer are made of the same material; or, the first active layer is a polysilicon layer or an amorphous silicon layer, and the second active layer is a metal oxide layer.

[0010] In one embodiment, a first insulating layer is disposed between the first gate and the first active layer; and a second insulating layer is disposed between the second gate and the second active layer.

[0011] In one embodiment, the array substrate further includes a first light shielding layer and a second light shielding layer, wherein the first light shielding layer is disposed between the first active layer and the first gate electrode; the second light shielding layer is connected to the first light shielding layer and together wraps the first active layer, the first drain electrode and the first source electrode;

[0012] And / or, the array substrate also includes a third light-shielding layer and a fourth light-shielding layer, the third light-shielding layer is arranged between the second active layer and the second gate; the fourth light-shielding layer is connected to the third light-shielding layer and together wraps the second active layer, the second drain and the second source.

[0013] The present invention further provides a display panel, comprising an opposing substrate, liquid crystal and the above-mentioned array substrate, wherein the opposing substrate and the array substrate are arranged opposite to each other, and the liquid crystal is arranged between the opposing substrate and the array substrate.

[0014] The present invention further provides a display device, characterized in that it comprises a backlight module and the above-mentioned display panel, wherein the backlight module is arranged on a side of the array substrate away from the opposing substrate.

[0015] The technical solution of the present invention is to set a first thin film transistor and a second thin film transistor in each pixel unit, the spacing between the first source and the first drain in the first thin film transistor is L1, the spacing between the second source and the second drain in the second thin film transistor is L2, the size of the first active layer of the first thin film transistor in the width direction is W1, the size of the second active layer of the second thin film transistor in the width direction is W2, and W1 / L1>W2 / L2, so that the size of the first thin film transistor is larger than that of the second thin film transistor, so that the first thin film transistor can carry a larger driving current and adapt to the scene of high refresh rate; the second thin film transistor can be used in the scene of low refresh rate, thereby reducing electric energy and improving the endurance of the display device. The array substrate of the present invention can select a suitable refresh rate mode according to different scenes to improve the flexibility and service life of the display device. And by connecting the first gate and the second gate to the same scan line, the number of scan lines is reduced and the aperture ratio of the pixel unit is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0017] Figure 1 A top view of an embodiment of a pixel unit in an array substrate according to an embodiment of the present invention;

[0018] Figure 2 is a partial cross-sectional view of an array substrate according to a first embodiment of the present invention;

[0019] Figure 3 This is a schematic diagram of the structure of a display panel according to a second embodiment of the present invention;

[0020] Figure 4 FIG. 4 is a schematic diagram of the structure of a display device according to Embodiment 3 of the present invention.

[0021] Description of Figure Numbers:

[0022]

[0023]

[0024] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0027] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0028] Embodiment 1:

[0029] The present invention provides an array substrate 100 .

[0030] In the embodiments of the present invention, please refer to Figure 1 and Figure 2The array substrate 100 includes a substrate 110, on which a plurality of pixel units 120 arranged in an array are disposed, each pixel unit 120 includes a pixel electrode 121, a first thin film transistor 122 and a second thin film transistor 123, the first thin film transistor 122 includes a first gate electrode 1221, a first active layer 1222, a first drain electrode 1223 and a first source electrode 1224, the first gate electrode 1221 is disposed on one side of the substrate 110, the first active layer 1222 is disposed on a side of the first gate electrode 1221 away from the substrate 110, the first source electrode 1224 and the first drain electrode 1223 are disposed at intervals on a side of the first active layer 1222 away from the first gate electrode 1221; the spacing between the first source electrode 1224 and the first drain electrode 1223 is L1, the direction perpendicular to the line between the first source electrode 1224 and the first drain electrode 1223 and parallel to the substrate 110 is defined as the width direction, the first active layer 1222 is disposed on the side of the first gate electrode 1221 away from the substrate 110, and the first drain electrode 1223 is disposed on the side of the first active layer 1222 away from the first gate electrode 1221. The dimension of the second thin film transistor 123 in the width direction is W1; the second thin film transistor 123 includes a second gate 1231, a second active layer 1232, a second drain 1233 and a second source 1234, the second gate 1231 is arranged on one side of the substrate 110, the second active layer 1232 is arranged on the side of the second gate 1231 away from the substrate 110, the second source 1234 and the second drain 1233 are arranged at intervals on the side of the second active layer 1232 away from the second gate 1231; and the first source 1224 and the second source 1234 are connected in parallel to the pixel electrode 121; the spacing between the second source 1234 and the second drain 1233 is L2, and the direction perpendicular to the line between the second source 1234 and the second drain 1233 and parallel to the substrate 110 is defined as the width direction, and the dimension of the second active layer 1232 in the width direction is W2; wherein W1 / L1 is greater than W2 / L2. The array substrate 100 also includes a first data line 124, a second data line 125 and a scan line, the first data line 124 and the second data line 125 are both perpendicular to the scan line; the first drain 1223 and the second drain 1233 in the same pixel unit 120 are respectively connected to the first data line 124 and the second data line 125; and the first gate 1221 and the second gate 1231 in the same pixel unit 120 are both connected to the same scan line.

[0031] In order to achieve the effect of controlling the first thin film transistor 122 and the second thin film transistor 123 to be turned on respectively, each pixel unit 120 in the present invention is provided with a corresponding scan line and at least two data lines, wherein the two data lines are connected to the first drain electrode 1223 and the second drain electrode 1233 respectively, and the first gate electrode 1221 of the first thin film transistor 122 and the second gate electrode 1231 of the second thin film transistor 123 can be the same metal layer, that is, the first gate electrode 1221 of the first thin film transistor 122 is also the second gate electrode 1231 of the second thin film transistor 123, and the first gate electrode 1221 and the second gate electrode 1231 can be connected to the same scan line. Alternatively, the first gate electrode 1221 of the first thin film transistor 122 and the second gate electrode 1231 of the second thin film transistor 123 can be two metal layers isolated from each other, and the two metal layers can be connected to the same scan line at the same time, thereby reducing the number of scan lines and improving the aperture ratio of the pixel unit 120.

[0032] A first active layer 1222 is provided between the first gate 1221 and the first drain 1223, a second active layer 1232 is provided between the second gate 1231 and the second drain 1233, the first drain 1223 and the first source 1224 are both provided on the side of the first active layer 1222 away from the first gate 1221, the first drain 1223 and the first source 1224 are spaced apart, the spacing between the first drain 1223 and the first source 1224 is defined as L1, and the projection of the first active layer 1222 on the substrate 110 in the direction perpendicular to the line connecting the first drain 1223 and the first source 1224 is W1; similarly, the second drain 1233 and the second source The electrodes 1234 are all arranged on the side of the second active layer 1232 away from the second gate electrode 1231, and the second drain electrode 1233 and the second source electrode 1234 are arranged at intervals, and the spacing between the second drain electrode 1233 and the second source electrode 1234 is defined as L2, and the projection of the second active layer 1232 on the substrate 110 in the direction perpendicular to the connection line between the second drain electrode 1233 and the second source electrode 1234 is W2; by setting W1 / L1>W2 / L2, the size of the first thin film transistor 122 and the size of the second thin film transistor 123 are large, so that the first thin film transistor 122 can withstand a larger driving current when turned on, and then can adapt to the high refresh rate mode. When it is necessary to switch to the low refresh rate mode, the first thin film transistor 122 can be turned off, and the second thin film transistor 123 can be turned on, so that the leakage current can be reduced, thereby reducing energy consumption. Since the size of the projection of the active layer on the substrate 110 in the direction perpendicular to the line connecting the drain and the source (i.e., the size of the active layer in the width direction) and the ratio of the distance between the drain and the source determine the size of the thin film transistor, in order to make the size of the first thin film transistor 122 larger, it can be achieved by setting the spacing between the first drain 1223 and the first source 1224 in the first thin film transistor 122 to be smaller than the spacing between the second drain 1233 and the second source 1234 in the second thin film transistor 123. Alternatively, it can also be achieved by making the size of the first active layer 1222 in the width direction larger than the size of the second active layer 1232 in the width direction. Combined with the above-mentioned solution that each pixel unit 120 corresponds to at least two data lines, the two data lines are respectively connected to the first drain 1223 and the second drain 1233, so that the first drain 1223 or the second drain 1233 can be controlled to be turned on through each data line, that is, the first thin film transistor 122 is controlled to be turned on or the second thin film transistor 123 is controlled to be turned on.

[0033] Furthermore, by connecting the first drain 1223 and the second drain 1233 in the same pixel unit 120 to the first data line 124 and the second data line 125 respectively, and connecting the first gate 1221 and the second gate 1231 in the same pixel unit 120 to the same scan line, the first thin film transistor 122 and the second thin film transistor 123 can be independently turned on under the drive of the first data line 124 and the second data line 125 respectively, satisfying two different usage scenarios of high refresh rate and low refresh rate; and the first thin film transistor 122 and the second thin film transistor 123 can share a scan line, reducing the number of scan lines, thereby greatly improving the aperture ratio of the pixel unit 120, and reducing the occupied area of ​​the pixel unit 120, so that a larger number of pixel units 120 can be arranged on the substrate 110, thereby improving the resolution of the array substrate 100.

[0034] The technical solution of the present invention is to set a first thin film transistor 122 and a second thin film transistor 123 in each pixel unit 120, the spacing between the first source 1224 and the first drain 1223 in the first thin film transistor 122 is L1, the spacing between the second source 1234 and the second drain 1233 in the second thin film transistor 123 is L2, the size of the first active layer 1222 of the first thin film transistor 122 in the width direction is W1, the size of the second active layer 1232 in the second thin film transistor 123 in the width direction is W2, and W1 / L1>W2 / L2, so that the size of the first thin film transistor 122 is larger than the size of the second thin film transistor 123, so that the first thin film transistor 122 can carry a larger driving current and adapt to the scene of high refresh rate; the second thin film transistor 123 can be used in the scene of low refresh rate, so as to reduce electric energy and improve the endurance of the display device. The array substrate 100 of the present invention can select a suitable refresh rate mode according to different scenes to improve the flexibility and service life of the display device. Furthermore, by connecting the first gate 1221 and the second gate 1231 to the same scan line, the number of scan lines is reduced, and the aperture ratio of the pixel unit 120 is improved.

[0035] Furthermore, if Figure 1 or Figure 2 As shown, in this example, the first gate 1221 and the second gate 1231 are the same metal layer.

[0036] By setting the first gate 1221 and the second gate 1231 as the same metal layer, the first gate 1221 is the second gate 1231, and the first active layer 1222 and the second active layer 1232 are both arranged above the metal layer, so that the projection of the first thin film transistor 122 and the second thin film transistor 123 on the substrate 110 only occupies the projection area of ​​one gate, thereby further improving the aperture ratio of the pixel electrode 121, so that the display device using the array substrate 100 has a higher brightness of the display screen.

[0037] Furthermore, if Figure 1 As shown, the first active layer 1222 and the second active layer 1232 are arranged at intervals along a direction parallel to the scan line.

[0038] By arranging the first active layer 1222 and the second active layer 1232 in a direction parallel to the scan line, the connection line between the first active layer 1222 and the second active layer 1232 is parallel to the scan line, thereby reducing the width of the first gate 1221 (or the second gate 1231), and improving the aperture ratio of the pixel unit 120. In addition, by arranging the first active layer 1222 and the second active layer 1232 in a direction parallel to the scan line, the first source electrode 1224 on the side of the first active layer 1222 away from the substrate 110 and the second source electrode 1234 on the side of the second active layer 1232 away from the substrate 110 are both arranged close to the pixel electrode 121, so that the connection paths when the first source electrode 1224 is connected to the pixel electrode 121 and when the second source electrode 1234 is connected to the pixel electrode 121 are both shorter, thereby saving costs and facilitating improving the aperture ratio of the pixel unit 120.

[0039] Furthermore, if Figure 1 or Figure 2 As shown, the first source electrode 1224 and the second source electrode 1234 are close to each other and spaced apart in a direction parallel to the scan line.

[0040] By arranging the first source electrode 1224 and the second source electrode 1234 close to each other, it can be understood that the first drain electrode 1223 and the second drain electrode 1233 are arranged far away from each other. Such arrangement facilitates, on the one hand, the first drain electrode 1223 and the second drain electrode 1233 to be connected to different data lines (i.e., the first data line 124 and the second data line 125, respectively), and on the other hand, the first source electrode 1224 and the second source electrode 1234 will not cross-connect with the first drain electrode 1223 and the second drain electrode 1233 when they are connected in parallel, thereby avoiding short circuits between the first source electrode 1224 and the first drain electrode 1223 or the second drain electrode 1233, and between the second source electrode 1234 and the first drain electrode 1223 or the second drain electrode 1233.

[0041] Furthermore, if Figure 1 As shown, the array substrate 100 further includes a metal connection line 126 . The metal connection line 126 has three connection ends, and the three connection ends are respectively connected to the pixel electrode 121 , the first source 1224 , and the second source 1234 .

[0042] By setting up a metal connecting line 126, the three connecting ends of the metal connecting line 126 are respectively connected to the pixel electrode 121, the first source 1224 and the second source 1234. When the first source 1224 is connected to the pixel electrode 121, and when the second source 1234 is connected to the pixel electrode 121, they can be connected through one connecting end of the metal connecting line 126, thereby avoiding the need to set up two connecting parts on the pixel electrode 121 for connecting the first source 1224 and the second source 1234, thereby simplifying the shape or structure of the pixel electrode 121.

[0043] In one example, the first active layer 1222 and the second active layer 1232 are made of the same material.

[0044] By using the same material for the first active layer 1222 and the second active layer 1232, the first active layer 1222 and the second active layer 1232 can be formed simultaneously in the same process step using the same photomask, thereby saving the number of photomasks, and further saving the cost and efficiency of the process. Specifically, the first active layer 1222 and the second active layer 1232 can both be made of metal oxide or both be made of polysilicon layers or amorphous silicon layers.

[0045] Of course, in other embodiments, the materials of the first active layer 1222 and the second active layer 1232 may also be different. Further, in order to ensure that the first thin film transistor 122 can adapt to the high refresh rate mode more stably, the first thin film transistor 122 is adapted to the low refresh rate mode, the first active layer 1222 may be a polysilicon layer or an amorphous silicon layer, and the second active layer 1232 may be a metal oxide layer. It is understood that the ion mobility of the crystalline silicon material is higher than that of the metal oxide, and therefore is more suitable for the high refresh rate mode. Based on the above-mentioned ratio of the width dimension W1 of the first active layer 1222 of the first thin film transistor 122 to the distance L1 from the first drain 1223 to the first source 1224 is greater than the ratio of the width dimension W2 of the second active layer 1232 of the second thin film transistor 123 to the distance L2 from the second drain 1233 to the second source 1234, so as to make the first thin film transistor 122 adapt to the high refresh rate mode, in this embodiment, the first active layer 1222 is further made of a polysilicon layer or an amorphous silicon layer, which further ensures that the first thin film transistor 122 can better adapt to the high refresh rate mode. Of course, by setting the second active layer 1232 to a metal oxide, due to its low ion mobility, the leakage current of the second thin film transistor 123 can be reduced, thereby achieving its adaptation to the low refresh rate mode, and having the effect of reducing energy consumption, increasing the battery life of the display device, and improving the service life.

[0046] Furthermore, if Figure 2 As shown, a first insulating layer 1225 is disposed between the first gate 1221 and the first active layer 1222 ; and a second insulating layer 1235 is disposed between the second gate 1231 and the second active layer 1232 .

[0047] In this example, by providing the first insulating layer 1225, the first gate 1221 and the first active layer 1222 in the first thin film transistor 122 can be isolated from each other, thereby avoiding the risk of short circuit between the first gate 1221 and the first active layer 1222. By providing the second insulating layer 1235, the second gate 1231 and the second active layer 1232 in the second thin film transistor 123 can be isolated from each other, thereby avoiding the risk of short circuit between the second gate 1231 and the second active layer 1232. The first insulating layer 1225 and the second insulating layer 1235 can be the same layer.

[0048] Furthermore, if Figure 2 As shown, the array substrate 100 also includes a first light-shielding layer 1226 and a second light-shielding layer 1227. The first light-shielding layer 1226 is arranged between the first active layer 1222 and the first gate 1221; the second light-shielding layer 1227 is connected to the first light-shielding layer 1226 and together wraps the first active layer 1222, the first drain 1223 and the first source 1224.

[0049] By arranging the first light shielding layer 1226 between the first active layer 1222 and the first gate electrode 1221, the first light shielding layer 1226 can block the backlight from the backlight module 400, thereby preventing the first active layer 1222 from being affected by the backlight and causing the resistance of the first thin film transistor 122 to decrease. By connecting the second light shielding layer 1227 to the first light shielding layer 1226 and wrapping the first active layer 1222, the first source electrode 1224 and the first drain electrode 1223 together, the second light shielding layer 1227 can block external light, thereby preventing the external light from affecting the first active layer 1222. In addition, by wrapping the first active layer 1222 with the second light shielding layer 1227 and the first light shielding layer 1226, the first active layer 1222 is completely enclosed in the space enclosed by the first light shielding layer 1226 and the second light shielding layer 1227, so that the diffraction phenomenon caused by the light of the backlight module 400 passing through the edge of the first gate 1221 can be avoided, and the diffracted light can be irradiated to the first active layer 1222, thereby avoiding the risk of the first active layer 1222 being affected by the light and causing the resistance of the first thin film transistor 122 to decrease, and further reducing the risk of the off-state current to increase. In addition, with such a configuration, it is not necessary to make the projection area of ​​the first light shielding layer 1226 and the second light shielding layer 1227 on the substrate 110 much larger than the projection area of ​​the first active layer 1222 in order to avoid the influence of the diffraction of light on the first active layer 1222 as much as possible.

[0050] Similarly, the array substrate 100 may further include a third light shielding layer 1236 and a fourth light shielding layer 1237. The third light shielding layer 1236 is disposed between the second active layer 1232 and the second gate electrode 1231. The fourth light shielding layer 1237 is connected to the third light shielding layer 1236 and together wraps the second active layer 1232, the second drain electrode 1233 and the second source electrode 1234. The third light shielding layer 1236 and the fourth light shielding layer 1237 may be in the same layer as the first light shielding layer 1226 and the second light shielding layer 1227, respectively.

[0051] Embodiment 2:

[0052] The present invention also provides a display panel, such as Figure 3 As shown, the display panel includes an opposing substrate 200, a liquid crystal 300 and an array substrate 100. The specific structure of the array substrate 100 refers to the above embodiment. Since the display panel adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here. Among them, the opposing substrate 200 is arranged opposite to the array substrate 100, and the liquid crystal 300 is arranged between the opposing substrate 200 and the array substrate 100.

[0053] The array substrate 100 includes a display area and a non-display area surrounding the display area. In order to enable the display panel to display images, the display area of ​​the array substrate 100 is provided with a plurality of pixel units 120 distributed in a matrix, and each pixel unit 120 has a pixel display area and a pixel non-display area. The first thin film transistor 122 and the second thin film transistor 123 are arranged in the pixel non-display area. A liquid crystal 300 is arranged between the position of the array substrate 100 corresponding to the pixel display area and the opposing substrate 200, so that the first thin film transistor 122 or the second thin film transistor 123 controls the steering of the liquid crystal 300 to achieve the effect that the display panel can display or not display images.

[0054] Embodiment three:

[0055] The present invention also provides a display device, such as Figure 4 As shown, the display device includes a backlight module 400 and a display panel. The specific structure of the display panel refers to the above embodiment. Since the display device adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here. Among them, the backlight module 400 is arranged on the side of the array substrate 100 away from the opposite substrate 200.

[0056] The backlight module 400 is used to provide light. By arranging the backlight module 400 on the side of the substrate 110 away from the opposing substrate 200, the light emitted by the backlight module 400 can irradiate the array substrate 100 and be emitted toward the opposing substrate 200 through the array substrate 100, thereby achieving the effect of emitting light from the light emitting surface of the opposing substrate 200 and displaying a picture.

[0057] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the inventive concept of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. An array substrate, comprising a substrate, on which a plurality of pixel units arranged in an array are provided, It is characterized in that Each of the pixel units comprises: Pixel electrode; a first thin film transistor, the first thin film transistor comprising a first gate, a first active layer, a first drain and a first source, the first gate being arranged on one side of the substrate, the first active layer being arranged on a side of the first gate away from the substrate, the first source and the first drain being arranged on a side of the first active layer away from the first gate; the spacing between the first source and the first drain being L1; a direction perpendicular to a line connecting the first source to the first drain and parallel to the substrate being defined as a width direction, and a dimension of the first active layer in the width direction being W1; and a second thin film transistor, the second thin film transistor comprising a second gate, a second active layer, a second drain and a second source, the second gate being arranged on one side of the substrate, the second active layer being arranged on a side of the second gate away from the substrate, the second source and the second drain being arranged at intervals on a side of the second active layer away from the second gate; and the first source and the second source being connected to the pixel electrode in parallel; the spacing between the second source and the second drain being L2, a direction perpendicular to a line connecting the second source to the second drain and parallel to the substrate being defined as a width direction, a dimension of the second active layer in the width direction being W2, and W1 / L1>W2 / L2; The array substrate also includes a first data line, a second data line and a scan line, the first data line and the second data line are both perpendicular to the scan line; the first drain and the second drain in the same pixel unit are respectively connected to the first data line and the second data line; and the first gate and the second gate in the same pixel unit are both connected to the same scan line.

2. The array substrate according to claim 1, It is characterized in that The first gate and the second gate are in the same metal layer.

3. The array substrate according to claim 2, It is characterized in that The first active layer and the second active layer are arranged at intervals along an extending direction parallel to the scanning line.

4. The array substrate according to claim 3, It is characterized in that The first source electrode and the second source electrode are arranged close to each other and spaced apart in a direction parallel to the scan line.

5. The array substrate according to claim 4, It is characterized in that The array substrate further includes a metal connection line having three connection ends, and the three connection ends are respectively connected to the pixel electrode, the first source electrode, and the second source electrode.

6. The array substrate according to claim 1, It is characterized in that The first active layer and the second active layer are made of the same material; or, the first active layer is a polysilicon layer or an amorphous silicon layer, and the second active layer is a metal oxide layer.

7. The array substrate according to claim 1, It is characterized in that A first insulating layer is disposed between the first gate and the first active layer; and a second insulating layer is disposed between the second gate and the second active layer.

8. The array substrate according to any one of claims 1 to 7, It is characterized in that The array substrate further includes a first light shielding layer and a second light shielding layer, wherein the first light shielding layer is disposed between the first active layer and the first gate electrode; the second light shielding layer is connected to the first light shielding layer and together wraps the first active layer, the first drain electrode and the first source electrode; And / or, the array substrate also includes a third light-shielding layer and a fourth light-shielding layer, the third light-shielding layer is arranged between the second active layer and the second gate; the fourth light-shielding layer is connected to the third light-shielding layer and together wraps the second active layer, the second drain and the second source.

9. A display panel, It is characterized in that It comprises an opposing substrate, liquid crystal and the array substrate according to any one of claims 1 to 8, wherein the opposing substrate is arranged opposite to the array substrate, and the liquid crystal is arranged between the opposing substrate and the array substrate.

10. A display device, It is characterized in that It comprises a backlight module and the display panel as claimed in claim 9, wherein the backlight module is arranged on a side of the array substrate away from the counter substrate.

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